From 496a87e4521bb14abb2c89db4ae2199775a75baa Mon Sep 17 00:00:00 2001 From: Robert Clipsham Date: Thu, 9 Dec 2010 22:27:14 +0000 Subject: [PATCH] Merged Iain Buclaw's AMD 3dNow! asm changes. --- gen/asm-x86-32.h | 23 +++++++++++++++++++++++ gen/asm-x86-64.h | 21 +++++++++++++++++++++ 2 files changed, 44 insertions(+) diff --git a/gen/asm-x86-32.h b/gen/asm-x86-32.h index 26af972f..19dedf7b 100644 --- a/gen/asm-x86-32.h +++ b/gen/asm-x86-32.h @@ -948,6 +948,7 @@ namespace AsmParserx8632 { "pand", Op_DstSrcMMX }, { "pandn", Op_DstSrcMMX }, { "pavgb", Op_DstSrcMMX }, + { "pavgusb", Op_DstSrcMMX }, // AMD 3dNow! { "pavgw", Op_DstSrcMMX }, { "pcmpeqb", Op_DstSrcMMX }, { "pcmpeqd", Op_DstSrcMMX }, @@ -956,6 +957,25 @@ namespace AsmParserx8632 { "pcmpgtd", Op_DstSrcMMX }, { "pcmpgtw", Op_DstSrcMMX }, { "pextrw", Op_DstSrcImmM }, // gpr32 dest + { "pf2id", Op_DstSrcMMX }, // %% AMD 3dNow! opcodes + { "pfacc", Op_DstSrcMMX }, + { "pfadd", Op_DstSrcMMX }, + { "pfcmpeq", Op_DstSrcMMX }, + { "pfcmpge", Op_DstSrcMMX }, + { "pfcmpgt", Op_DstSrcMMX }, + { "pfmax", Op_DstSrcMMX }, + { "pfmin", Op_DstSrcMMX }, + { "pfmul", Op_DstSrcMMX }, + { "pfnacc", Op_DstSrcMMX }, // 3dNow values are returned in MM0 register, + { "pfpnacc", Op_DstSrcMMX }, // so should be correct to use Op_DstSrcMMX. + { "pfrcp", Op_DstSrcMMX }, + { "pfrcpit1", Op_DstSrcMMX }, + { "pfrcpit2", Op_DstSrcMMX }, + { "pfrsqit1", Op_DstSrcMMX }, + { "pfrsqrt", Op_DstSrcMMX }, + { "pfsub", Op_DstSrcMMX }, + { "pfsubr", Op_DstSrcMMX }, + { "pi2fd", Op_DstSrcMMX }, // %% { "pinsrw", Op_DstSrcImmM }, // gpr32(16), mem16 src, sse too { "pmaddwd", Op_DstSrcMMX }, { "pmaxsw", Op_DstSrcMMX }, @@ -963,6 +983,8 @@ namespace AsmParserx8632 { "pminsw", Op_DstSrcMMX }, { "pminub", Op_DstSrcMMX }, { "pmovmskb", Op_DstSrcMMX }, + { "pmulhrw", Op_DstSrcMMX }, // AMD 3dNow! + { "pmulhuw", Op_DstSrcMMX }, { "pmulhw", Op_DstSrcMMX }, { "pmullw", Op_DstSrcMMX }, @@ -1000,6 +1022,7 @@ namespace AsmParserx8632 { "psubusb", Op_DstSrcMMX }, { "psubusw", Op_DstSrcMMX }, { "psubw", Op_DstSrcMMX }, + { "pswapd", Op_DstSrcMMX }, // AMD 3dNow! { "punpckhbw", Op_DstSrcMMX }, { "punpckhdq", Op_DstSrcMMX }, { "punpckhqdq",Op_DstSrcMMX }, diff --git a/gen/asm-x86-64.h b/gen/asm-x86-64.h index 391662ce..94926344 100644 --- a/gen/asm-x86-64.h +++ b/gen/asm-x86-64.h @@ -1058,6 +1058,7 @@ namespace AsmParserx8664 { "pandn", Op_DstSrcMMX }, { "pause", Op_DstSrcMMX }, { "pavgb", Op_DstSrcMMX }, + { "pavgusb", Op_DstSrcMMX }, // AMD 3dNow! { "pavgw", Op_DstSrcMMX }, { "pcmpeqb", Op_DstSrcMMX }, { "pcmpeqd", Op_DstSrcMMX }, @@ -1066,6 +1067,25 @@ namespace AsmParserx8664 { "pcmpgtd", Op_DstSrcMMX }, { "pcmpgtw", Op_DstSrcMMX }, { "pextrw", Op_DstSrcImmM }, // gpr32 dest + { "pf2id", Op_DstSrcMMX }, // %% AMD 3dNow! opcodes + { "pfacc", Op_DstSrcMMX }, + { "pfadd", Op_DstSrcMMX }, + { "pfcmpeq", Op_DstSrcMMX }, + { "pfcmpge", Op_DstSrcMMX }, + { "pfcmpgt", Op_DstSrcMMX }, + { "pfmax", Op_DstSrcMMX }, + { "pfmin", Op_DstSrcMMX }, + { "pfmul", Op_DstSrcMMX }, + { "pfnacc", Op_DstSrcMMX }, // 3dNow values are returned in MM0 register, + { "pfpnacc", Op_DstSrcMMX }, // so should be correct to use Op_DstSrcMMX. + { "pfrcp", Op_DstSrcMMX }, + { "pfrcpit1", Op_DstSrcMMX }, + { "pfrcpit2", Op_DstSrcMMX }, + { "pfrsqit1", Op_DstSrcMMX }, + { "pfrsqrt", Op_DstSrcMMX }, + { "pfsub", Op_DstSrcMMX }, + { "pfsubr", Op_DstSrcMMX }, + { "pi2fd", Op_DstSrcMMX }, // %% { "phaddd", Op_DstSrcSSE }, { "phaddsw", Op_DstSrcSSE }, { "phaddw", Op_DstSrcSSE }, @@ -1120,6 +1140,7 @@ namespace AsmParserx8664 { "psubusb", Op_DstSrcMMX }, { "psubusw", Op_DstSrcMMX }, { "psubw", Op_DstSrcMMX }, + { "pswapd", Op_DstSrcMMX }, // AMD 3dNow! { "punpckhbw", Op_DstSrcMMX }, { "punpckhdq", Op_DstSrcMMX }, { "punpckhqdq",Op_DstSrcMMX },