diff --git a/gen/toobj.cpp b/gen/toobj.cpp
index 585f030f..2ad877d0 100644
--- a/gen/toobj.cpp
+++ b/gen/toobj.cpp
@@ -14,9 +14,14 @@
 #include "gen/llvm.h"
 #include "llvm/Analysis/Verifier.h"
 #include "llvm/Bitcode/ReaderWriter.h"
+#include "llvm/Target/SubtargetFeature.h"
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Target/TargetMachineRegistry.h"
+#include "llvm/Module.h"
+#include "llvm/ModuleProvider.h"
+#include "llvm/PassManager.h"
 #include "llvm/System/Path.h"
+#include "llvm/Support/raw_ostream.h"
 
 #include "mars.h"
 #include "module.h"
@@ -190,6 +195,68 @@ void Module::genobjfile(int multiobj)
         ir.module->print(aos, NULL);
     }
 
+
+    //TODO: Move all of this into a helper function?
+    if(false)
+    {
+        using namespace llvm;
+
+    //FIXME: Proper out file name.
+        std::string Err;
+        raw_fd_ostream Out("test.s", Err);
+        if(!Err.empty()) {}
+
+        const TargetMachineRegistry::entry* MArch;
+        MArch = TargetMachineRegistry::getClosestStaticTargetForModule(*ir.module, Err);
+        if (MArch == 0) {
+            error("error auto-selecting target for module '%s'", Err.c_str());
+            fatal();
+        }
+ 
+        SubtargetFeatures Features;
+    //TODO: Features?
+    //    Features.setCPU(MCPU);
+    //    for (unsigned i = 0; i != MAttrs.size(); ++i)
+    //      Features.AddFeature(MAttrs[i]);
+
+    //TODO: Set PIC if shared (or just do it always?)
+    //  TargetMachine::setRelocationModel(...);
+
+        std::auto_ptr<TargetMachine> target(MArch->CtorFn(*ir.module, Features.getString()));
+        assert(target.get() && "Could not allocate target machine!");
+        TargetMachine &Target = *target.get();
+
+        // Build up all of the passes that we want to do to the module.
+        ExistingModuleProvider Provider(ir.module);
+        FunctionPassManager Passes(&Provider);
+    //FIXME does this TargetData match gTargetData?
+        Passes.add(new TargetData(*Target.getTargetData()));
+
+        // Ask the target to add backend passes as necessary.
+        MachineCodeEmitter *MCE = 0;
+
+    //TODO: May want to switch it on for -O0?
+        bool Fast = false;
+        FileModel::Model mod = Target.addPassesToEmitFile(Passes, Out, TargetMachine::AssemblyFile, Fast);
+        assert(mod == FileModel::AsmFile);
+
+        bool err = Target.addPassesToEmitFileFinish(Passes, MCE, Fast);
+        assert(!err);
+
+        Passes.doInitialization();
+
+        // Run our queue of passes all at once now, efficiently.
+        for (llvm::Module::iterator I = ir.module->begin(), E = ir.module->end(); I != E; ++I)
+        if (!I->isDeclaration())
+            Passes.run(*I);
+
+        Passes.doFinalization();
+
+        // release module from module provider so we can delete it ourselves
+        llvm::Module* rmod = Provider.releaseModule(&Err);
+        assert(rmod);
+    }
+
     delete ir.module;
     gTargetData = 0;
     gIR = NULL;
diff --git a/premake.lua b/premake.lua
index 2662b587..a8615638 100644
--- a/premake.lua
+++ b/premake.lua
@@ -55,7 +55,7 @@ package.excludes = { "dmd/idgen.c", "dmd/impcnvgen.c" }
 package.buildoptions = { "-x c++", "`llvm-config --cxxflags`" }
 package.linkoptions = {
     -- long but it's faster than just 'all'
-    "`llvm-config --libs bitwriter linker ipo instrumentation`",
+    "`llvm-config --libs bitwriter linker ipo instrumentation backend`",
     "`llvm-config --ldflags`",
 }
 package.defines = {