NetBSD re-synchronization of the source tree

This brings our tree to NetBSD 7.0, as found on -current on the
10-10-2015.

This updates:
 - LLVM to 3.6.1
 - GCC to GCC 5.1
 - Replace minix/commands/zdump with usr.bin/zdump
 - external/bsd/libelf has moved to /external/bsd/elftoolchain/
 - Import ctwm
 - Drop sprintf from libminc

Change-Id: I149836ac18e9326be9353958bab9b266efb056f0

sys/arch/Makefile

@@ -1,4 +1,4 @@
-#	$NetBSD: Makefile,v 1.42 2013/05/02 03:56:40 matt Exp $
+#	$NetBSD: Makefile,v 1.45 2014/09/03 19:27:53 matt Exp $
 
 # For now, we install the machine and arch includes, and symlink 'machine'
 # to the location of the machine includes (usually).
@@ -16,9 +16,15 @@ ARCHSUBDIR= mips
 ARCHSUBDIR= powerpc
 .endif
 
-.if ${MACHINE_CPU} == "arm"
+.if ${MACHINE_CPU} == "aarch64"
+SUBDIR= evbarm64
+.elif ${MACHINE_CPU} == "arm"
+.if defined(__MINIX)
 SUBDIR= evbarm
 .else
+SUBDIR= acorn26 acorn32 cats epoc32 evbarm hpcarm iyonix netwinder shark zaurus
+.endif # defined(__MINIX)
+.else
 SUBDIR=	${MACHINE}
 .endif
 
@@ -27,6 +33,9 @@ SUBDIR=	${MACHINE}
 SUBDIR+= ${ARCHSUBDIR}
 .endif
 .endif
+.if ${MACHINE_CPU} == "aarch64"
+SUBDIR+= arm
+.endif
 .if ${MACHINE} == sparc
 SUBDIR+= sparc64
 .endif
@@ -40,7 +49,7 @@ SUBDIR+= sun68k
 SUBDIR+= xen
 .endif
 
-#SUBDIR=acorn26 acorn32 algor alpha amiga amigappc arm arc atari \
+#SUBDIR=aarch64 acorn26 acorn32 algor alpha amiga amigappc arm arc atari \
 #	bebox \
 #	cats cesfic cobalt \
 #	dreamcast \
@@ -50,15 +59,15 @@ SUBDIR+= xen
 #	luna68k \
 #	m68k mac68k macppc mips mipsco mmeye mvme68k \
 #	netwinder news68k newsmips next68k \
-#	ofppc \
-#	pmax powerpc prep \
+#	ofppc or1k \
+#	playstation2 pmax powerpc prep \
 #	sandpoint sbmips sgimips sh3 shark sparc sparc64 sun2 sun3 sun68k \
 #	rs6000 \
 #	vax \
 #	x68k x86_64 xen \
 #	zaurus
 
-.if ${MACHINE_CPU} == arm
+.if ${MACHINE_CPU} == aarch64 || ${MACHINE_CPU} == "arm"
 INCSYMLINKS= ${MACHINE_CPU} /usr/include/machine
 .else
 INCSYMLINKS= ${MACHINE} /usr/include/machine

sys/arch/README

@@ -1,4 +1,4 @@
-$NetBSD: README,v 1.60 2013/05/02 12:09:40 kiyohara Exp $
+$NetBSD: README,v 1.62 2014/03/31 11:25:48 martin Exp $
 
 acorn26	arm	20000509	Acorn ARM2- and ARM3-based machines
 acorn32	arm	20011118	Acorn computers Ltd. ARM 6/7/SA based machines
@@ -22,7 +22,7 @@ evbppc	powerpc,powerpc64	20021209	PowerPC-based eval boards
 evbsh3	sh3eb,sh3el	20010206	Hitachi SuperH(TM) sh3 and sh4 eval boards
 ews4800mips	mipseb	20051229	NEC's MIPS based EWS4800 workstations
 hp300	m68k	19930512	Hewlett Packard 300- and 400-series machines
-hp700	hppa	20020606	Hewlett Packard 700-series machines
+hppa	hppa	20020606	Hewlett Packard 700-series machines
 hpcarm	arm	20010220	ARM based handheld PCs
 hpcmips	mipsel	19990925	MIPS based handheld PCs
 hpcsh	sh3el	20010117	Hitachi SuperH(TM) based handheld PCs
@@ -43,6 +43,7 @@ news68k	m68k	19991209	Sony's m68k based NET WORK STATION
 newsmips	mipseb	19980218	Sony's MIPS based NET WORK STATION
 next68k	m68k	19980609	NeXT Computer's cubes and slabs
 ofppc	powerpc,powerpc64	19980528	Open Firmware based PowerPC machines
+playstation2	mipsel	20011016	Sony PlayStation 2
 pmax	mipsel,mips64el	19931012	Digital Equipment Corp. MIPS based machines
 prep	powerpc	20000229	PowerPC Reference Platform machines
 rs6000	powerpc	20071217	MCA-based IBM RS/6000 wokstations

sys/arch/arm/include/Makefile

@@ -1,8 +1,8 @@
-#	$NetBSD: Makefile,v 1.47 2013/05/02 03:56:40 matt Exp $
+#	$NetBSD: Makefile,v 1.49 2014/07/23 18:19:43 alnsn Exp $
 
 INCSDIR= /usr/include/arm
 
-INCS=	aeabi.h ansi.h aout_machdep.h armreg.h asm.h atomic.h \
+INCS=	aeabi.h ansi.h aout_machdep.h apmvar.h armreg.h asm.h atomic.h \
 	bswap.h byte_swap.h \
 	cdefs.h cpu.h cpuconf.h \
 	disklabel.h \
@@ -10,14 +10,14 @@ INCS=	aeabi.h ansi.h aout_machdep.h armreg.h asm.h atomic.h \
 	fenv.h float.h frame.h \
 	ieee.h ieeefp.h \
 	int_const.h int_fmtio.h int_limits.h int_mwgwtypes.h int_types.h \
-	 \
+	joystick.h \
 	kcore.h \
 	limits.h lock.h \
 	math.h mcontext.h mutex.h \
 	param.h pcb.h pmc.h proc.h profile.h rwlock.h \
 	ptrace.h \
 	reg.h rwlock.h \
-	setjmp.h signal.h swi.h sysarch.h \
+	setjmp.h signal.h sljit_machdep.h swi.h sysarch.h \
 	trap.h types.h \
 	vfpreg.h vmparam.h \
 	wchar_limits.h

sys/arch/arm/include/Makefile.common

@@ -20,7 +20,7 @@ INCS+=	ansi.h aout_machdep.h asm.h \
 	wchar_limits.h
 .else
 INCS+=	disklabel.h \
-
+	intr.h
 .endif
 
 .include <bsd.kinc.mk>

sys/arch/arm/include/Makefile.inc

@@ -0,0 +1,5 @@
+# $NetBSD: Makefile.inc,v 1.2 2015/02/22 17:38:19 riastradh Exp $
+
+.if !defined(RUMPKERNEL)
+CFLAGS+=	 -mfloat-abi=soft
+.endif

sys/arch/arm/include/ansi.h

@@ -1,4 +1,4 @@
-/*	$NetBSD: ansi.h,v 1.15 2013/01/27 17:43:20 matt Exp $	*/
+/*	$NetBSD: ansi.h,v 1.17 2014/02/24 16:57:57 christos Exp $	*/
 
 /*
  * Copyright (c) 1990, 1993
@@ -31,8 +31,8 @@
  *	from: @(#)ansi.h	8.2 (Berkeley) 1/4/94
  */
 
-#ifndef	_ANSI_H_
-#define	_ANSI_H_
+#ifndef _ARM_ANSI_H_
+#define _ARM_ANSI_H_
 
 #include <sys/cdefs.h>
 
@@ -76,4 +76,4 @@
 #define	_BSD_WINT_T_		int		/* wint_t */
 #endif
 
-#endif	/* _ANSI_H_ */
+#endif	/* _ARM_ANSI_H_ */

sys/arch/arm/include/aout_machdep.h

@@ -1,4 +1,4 @@
-/*	$NetBSD: aout_machdep.h,v 1.5 2005/12/11 12:16:46 christos Exp $	*/
+/*	$NetBSD: aout_machdep.h,v 1.7 2014/02/24 16:57:57 christos Exp $	*/
 
 /*
  * Copyright (c) 1994-1996 Mark Brinicombe.
@@ -32,8 +32,8 @@
  * SUCH DAMAGE.
  */
 
-#ifndef	_ARM32_AOUT_MACHDEP_H_
-#define	_ARM32_AOUT_MACHDEP_H_
+#ifndef _ARM_AOUT_MACHDEP_H_
+#define _ARM_AOUT_MACHDEP_H_
 
 #define	AOUT_LDPGSZ	4096
 
@@ -56,4 +56,4 @@ struct relocation_info_arm6 {
 /* No special executable format */
 #define	cpu_exec_aout_makecmds(a, b)	ENOEXEC
 
-#endif	/* _ARM32_AOUT_MACHDEP_H_ */
+#endif	/* _ARM_AOUT_MACHDEP_H_ */

sys/arch/arm/include/apmvar.h

@@ -1,4 +1,4 @@
-/*	$NetBSD: apmvar.h,v 1.1 2013/05/02 03:56:40 matt Exp $	*/
+/*	$NetBSD: apmvar.h,v 1.2 2014/02/24 16:57:57 christos Exp $	*/
 
 /*-
  * Copyright (c) 1995 The NetBSD Foundation, Inc.
@@ -25,10 +25,10 @@
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
-#ifndef __ZAURUS_APMVAR_H__
-#define __ZAURUS_APMVAR_H__
+#ifndef _ARM_APMVAR_H_
+#define _ARM_APMVAR_H_
 
 #include <dev/apm/apmbios.h>
 #include <dev/apm/apmio.h>
 
-#endif /* __ZAURUS_APMVAR_H__ */
+#endif /* _ARM_APMVAR_H_ */

sys/arch/arm/include/arm32/Makefile

@@ -1,7 +1,7 @@
-#	$NetBSD: Makefile,v 1.9 2002/11/26 23:30:12 lukem Exp $
+#	$NetBSD: Makefile,v 1.10 2014/10/25 10:58:12 skrll Exp $
 
 INCSDIR= /usr/include/arm/arm32
 
-INCS=	frame.h katelib.h param.h pmap.h psl.h pte.h rtc.h types.h vmparam.h
+INCS=	frame.h param.h pmap.h psl.h pte.h rtc.h types.h vmparam.h
 
 .include <bsd.kinc.mk>

sys/arch/arm/include/arm32/db_machdep.h

@@ -1,4 +1,4 @@
-/* $NetBSD: db_machdep.h,v 1.7 2013/01/05 15:06:51 christos Exp $ */
+/* $NetBSD: db_machdep.h,v 1.9 2014/03/28 21:54:12 matt Exp $ */
 
 #ifndef _ARM32_DB_MACHDEP_H_
 #define _ARM32_DB_MACHDEP_H_
@@ -7,5 +7,11 @@
 
 void db_show_frame_cmd(db_expr_t, bool, db_expr_t, const char *);
 void db_show_fault_cmd(db_expr_t, bool, db_expr_t, const char *);
+#ifdef _KERNEL
+void db_show_tlb_cmd(db_expr_t, bool, db_expr_t, const char *);
+#endif
+#if defined(_KERNEL) && defined(MULTIPROCESSOR)
+void db_switch_cpu_cmd(db_expr_t, bool, db_expr_t, const char *);
+#endif
 
 #endif

sys/arch/arm/include/arm32/frame.h

@@ -1,4 +1,4 @@
-/*	$NetBSD: frame.h,v 1.36 2013/08/18 06:37:02 matt Exp $	*/
+/*	$NetBSD: frame.h,v 1.42 2015/04/17 17:28:33 matt Exp $	*/
 
 /*
  * Copyright (c) 1994-1997 Mark Brinicombe.
@@ -133,22 +133,6 @@ void validate_trapframe(trapframe_t *, int);
 #define	DO_PENDING_SOFTINTS		/* nothing */
 #endif
 
-#ifdef MULTIPROCESSOR
-#define	KERNEL_LOCK							\
-	mov	r0, #1							;\
-	mov	r1, #0							;\
-	bl	_C_LABEL(_kernel_lock)
-
-#define	KERNEL_UNLOCK							\
-	mov	r0, #1							;\
-	mov	r1, #0							;\
-	mov	r2, #0							;\
-	bl	_C_LABEL(_kernel_unlock)
-#else
-#define	KERNEL_LOCK			/* nothing */
-#define	KERNEL_UNLOCK			/* nothing */
-#endif
-
 #ifdef _ARM_ARCH_6
 #define	GET_CPSR(rb)			/* nothing */
 #define	CPSID_I(ra,rb)			cpsid	i
@@ -166,6 +150,28 @@ void validate_trapframe(trapframe_t *, int);
 	msr	cpsr_c, ra		/* Restore interrupts */
 #endif
 
+#ifdef __HAVE_PREEMPTION
+#define DO_CLEAR_ASTPENDING						\
+	mvn	r1, #1			/* complement of 1 */		;\
+	add	r0, r4, #CI_ASTPENDING	/* address of astpending */	;\
+	bl	_C_LABEL(atomic_and_uint) /* clear AST */
+#else
+#define DO_CLEAR_ASTPENDING						\
+	mov	r0, #0							;\
+	str	r0, [r4, #CI_ASTPENDING] /* clear AST */
+#endif
+
+#define DO_PENDING_AST(lbl)						;\
+1:	ldr	r1, [r4, #CI_ASTPENDING] /* Pending AST? */		;\
+	tst	r1, #0x00000001						;\
+	beq	lbl			/* Nope. Just bail */		;\
+	DO_CLEAR_ASTPENDING						;\
+	CPSIE_I(r5, r5)			/* Restore interrupts */	;\
+	mov	r0, sp							;\
+	bl	_C_LABEL(ast)		/* ast(frame) */		;\
+	CPSID_I(r0, r5)			/* Disable interrupts */	;\
+	b	1b			/* test again */
+
 /*
  * AST_ALIGNMENT_FAULT_LOCALS and ENABLE_ALIGNMENT_FAULTS
  * These are used in order to support dynamic enabling/disabling of
@@ -190,7 +196,7 @@ void validate_trapframe(trapframe_t *, int);
  */
 #define	ENABLE_ALIGNMENT_FAULTS						\
 	and	r7, r0, #(PSR_MODE)	/* Test for USR32 mode */	;\
-	teq	r7, #(PSR_USR32_MODE)					;\
+	cmp	r7, #(PSR_USR32_MODE)					;\
 	GET_CURCPU(r4)			/* r4 = cpuinfo */		;\
 	bne	1f			/* Not USR mode skip AFLT */	;\
 	ldr	r1, [r4, #CI_CURLWP]	/* get curlwp from cpu_info */	;\
@@ -201,7 +207,7 @@ void validate_trapframe(trapframe_t *, int);
 	ldr	r1, [r4, #CI_CTRL]	/* Fetch control register */	;\
 	mov	r0, #-1							;\
 	BL_CF_CONTROL(r2)		/* Enable alignment faults */	;\
-1:	KERNEL_LOCK
+1:	/* done */
 
 /*
  * This macro must be invoked just before PULLFRAMEFROMSVCANDEXIT or
@@ -213,12 +219,10 @@ void validate_trapframe(trapframe_t *, int);
 	DO_PENDING_SOFTINTS						;\
 	GET_CPSR(r5)			/* save CPSR */			;\
 	CPSID_I(r1, r5)			/* Disable interrupts */	;\
-	teq	r7, #(PSR_USR32_MODE)	/* Returning to USR mode? */	;\
+	cmp	r7, #(PSR_USR32_MODE)	/* Returning to USR mode? */	;\
 	bne	3f			/* Nope, get out now */		;\
-1:	ldr	r1, [r4, #CI_ASTPENDING] /* Pending AST? */		;\
-	teq	r1, #0x00000000						;\
-	bne	2f			/* Yup. Go deal with it */	;\
-	ldr	r1, [r4, #CI_CURLWP]	/* get curlwp from cpu_info */	;\
+	DO_PENDING_AST(2f)		/* Pending AST? */		;\
+2:	ldr	r1, [r4, #CI_CURLWP]	/* get curlwp from cpu_info */	;\
 	ldr	r0, [r1, #L_MD_FLAGS]	/* get md_flags from lwp */	;\
 	tst	r0, #MDLWP_NOALIGNFLT					;\
 	beq	3f			/* Keep AFLTs enabled */	;\
@@ -226,17 +230,8 @@ void validate_trapframe(trapframe_t *, int);
 	ldr	r2, .Laflt_cpufuncs					;\
 	mov	r0, #-1							;\
 	bic	r1, r1, #CPU_CONTROL_AFLT_ENABLE  /* Disable AFLTs */	;\
-	adr	lr, 3f							;\
-	B_CF_CONTROL(r2)		/* Set new CTRL reg value */	;\
-	/* NOTREACHED */						\
-2:	mov	r1, #0x00000000						;\
-	str	r1, [r4, #CI_ASTPENDING] /* Clear astpending */		;\
-	CPSIE_I(r5, r5)			/* Restore interrupts */	;\
-	mov	r0, sp							;\
-	bl	_C_LABEL(ast)		/* ast(frame) */		;\
-	CPSID_I(r0, r5)			/* Disable interrupts */	;\
-	b	1b			/* Back around again */		;\
-3:	KERNEL_UNLOCK
+	BL_CF_CONTROL(r2)		/* Set new CTRL reg value */	;\
+3:	/* done */
 
 #else	/* !EXEC_AOUT */
 
@@ -244,26 +239,17 @@ void validate_trapframe(trapframe_t *, int);
 
 #define	ENABLE_ALIGNMENT_FAULTS						\
 	and	r7, r0, #(PSR_MODE)	/* Test for USR32 mode */	;\
-	GET_CURCPU(r4)			/* r4 = cpuinfo */		;\
-	KERNEL_LOCK
+	GET_CURCPU(r4)			/* r4 = cpuinfo */
+	
 
 #define	DO_AST_AND_RESTORE_ALIGNMENT_FAULTS				\
 	DO_PENDING_SOFTINTS						;\
 	GET_CPSR(r5)			/* save CPSR */			;\
 	CPSID_I(r1, r5)			/* Disable interrupts */	;\
-	teq	r7, #(PSR_USR32_MODE)					;\
+	cmp	r7, #(PSR_USR32_MODE)					;\
 	bne	2f			/* Nope, get out now */		;\
-1:	ldr	r1, [r4, #CI_ASTPENDING] /* Pending AST? */		;\
-	teq	r1, #0x00000000						;\
-	beq	2f			/* Nope. Just bail */		;\
-	mov	r1, #0x00000000						;\
-	str	r1, [r4, #CI_ASTPENDING] /* Clear astpending */		;\
-	CPSIE_I(r5, r5)			/* Restore interrupts */	;\
-	mov	r0, sp							;\
-	bl	_C_LABEL(ast)		/* ast(frame) */		;\
-	CPSID_I(r0, r5)			/* Disable interrupts */	;\
-	b	1b							;\
-2:	KERNEL_UNLOCK			/* unlock the kernel */
+	DO_PENDING_AST(2f)		/* Pending AST? */		;\
+2:	/* done */
 #endif /* EXEC_AOUT */
 
 #ifndef _ARM_ARCH_6
@@ -304,7 +290,7 @@ LOCK_CAS_DEBUG_LOCALS
 #define	LOCK_CAS_CHECK							 \
 	ldr	r0, [sp]		/* get saved PSR */		;\
 	and	r0, r0, #(PSR_MODE)	/* check for SVC32 mode */	;\
-	teq	r0, #(PSR_SVC32_MODE)					;\
+	cmp	r0, #(PSR_SVC32_MODE)					;\
 	bne	99f			/* nope, get out now */		;\
 	ldr	r0, [sp, #(TF_PC)]					;\
 	ldr	r1, .L_lock_cas_end					;\
@@ -351,7 +337,7 @@ LOCK_CAS_DEBUG_LOCALS
 	sub	sp, sp, #(TF_PC-TF_R0);	/* Adjust the stack pointer */	   \
 	PUSHUSERREGS;			/* Push the user mode registers */ \
 	mov     r0, r0;                 /* NOP for previous instruction */ \
-	mrs	r0, spsr_all;		/* Get the SPSR */		   \
+	mrs	r0, spsr;		/* Get the SPSR */		   \
 	str	r0, [sp, #-TF_R0]!	/* Push the SPSR on the stack */
 
 /*
@@ -364,7 +350,7 @@ LOCK_CAS_DEBUG_LOCALS
 	str	lr, [sp, #-4]!;		/* save SVC32 lr */		   \
 	str	r6, [sp, #(TF_R6-TF_PC)]!; /* save callee-saved r6 */	   \
 	str	r4, [sp, #(TF_R4-TF_R6)]!; /* save callee-saved r4 */	   \
-	mrs	r0, cpsr_all;		/* Get the CPSR */		   \
+	mrs	r0, cpsr;		/* Get the CPSR */		   \
 	str	r0, [sp, #(-TF_R4)]!	/* Push the CPSR on the stack */
 
 /*
@@ -378,7 +364,7 @@ LOCK_CAS_DEBUG_LOCALS
 	str	ip, [sp, #TF_SVC_SP];					\
 	str	lr, [sp, #TF_SVC_LR];					\
 	str	lr, [sp, #TF_PC];					\
-	mrs	rX, cpsr_all;		/* Get the CPSR */		\
+	mrs	rX, cpsr;		/* Get the CPSR */		\
 	str	rX, [sp, #TF_SPSR]	/* save in trapframe */
 
 #define PUSHSWITCHFRAME1						   \
@@ -394,13 +380,13 @@ LOCK_CAS_DEBUG_LOCALS
 #define	PUSHSWITCHFRAME2						\
 	strd	r10, [sp, #TF_R10];	/* save r10 & r11 */		\
 	strd	r8, [sp, #TF_R8];	/* save r8 & r9 */		\
-	mrs	r0, cpsr_all;		/* Get the CPSR */		\
+	mrs	r0, cpsr;		/* Get the CPSR */		\
 	str	r0, [sp, #TF_SPSR]	/* save in trapframe */
 #else
 #define	PUSHSWITCHFRAME2						\
 	add	r0, sp, #TF_R8;		/* get ptr to r8 and above */	\
 	stmia	r0, {r8-r11};		/* save rest of registers */	\
-	mrs	r0, cpsr_all;		/* Get the CPSR */		\
+	mrs	r0, cpsr;		/* Get the CPSR */		\
 	str	r0, [sp, #TF_SPSR]	/* save in trapframe */
 #endif
 
@@ -411,7 +397,7 @@ LOCK_CAS_DEBUG_LOCALS
 
 #define PULLFRAME							   \
 	ldr     r0, [sp], #TF_R0;	/* Pop the SPSR from stack */	   \
-	msr     spsr_all, r0;						   \
+	msr     spsr_fsxc, r0;						   \
 	ldmia   sp, {r0-r14}^;		/* Restore registers (usr mode) */ \
 	mov     r0, r0;                 /* NOP for previous instruction */ \
 	add	sp, sp, #(TF_PC-TF_R0);	/* Adjust the stack pointer */	   \
@@ -464,12 +450,12 @@ LOCK_CAS_DEBUG_LOCALS
 	str	r0, [r2, #-4]!;		/* Push return address */	   \
 	stmdb	r2!, {sp, lr};		/* Push SVC sp, lr */		   \
 	mov	sp, r2;			/* Keep stack aligned */	   \
-	msr     spsr_all, r3;		/* Restore correct spsr */	   \
+	msr     spsr_fsxc, r3;		/* Restore correct spsr */	   \
 	ldmdb	r1, {r0-r3};		/* Restore 4 regs from xxx mode */ \
 	sub	sp, sp, #(TF_SVC_SP-TF_R0); /* Adjust the stack pointer */ \
 	PUSHUSERREGS;			/* Push the user mode registers */ \
 	mov     r0, r0;                 /* NOP for previous instruction */ \
-	mrs	r0, spsr_all;		/* Get the SPSR */		   \
+	mrs	r0, spsr;		/* Get the SPSR */		   \
 	str	r0, [sp, #-TF_R0]!	/* Push the SPSR onto the stack */
 
 /*
@@ -481,7 +467,7 @@ LOCK_CAS_DEBUG_LOCALS
 
 #define PULLFRAMEFROMSVCANDEXIT						   \
 	ldr     r0, [sp], #0x0008;	/* Pop the SPSR from stack */	   \
-	msr     spsr_all, r0;		/* restore SPSR */		   \
+	msr     spsr_fsxc, r0;		/* restore SPSR */		   \
 	ldmia   sp, {r0-r14}^;		/* Restore registers (usr mode) */ \
 	mov     r0, r0;	  		/* NOP for previous instruction */ \
 	add	sp, sp, #(TF_SVC_SP-TF_R0); /* Adjust the stack pointer */ \

sys/arch/arm/include/arm32/katelib.h

@@ -1,98 +0,0 @@
-/*	$NetBSD: katelib.h,v 1.3 2001/11/23 19:21:48 thorpej Exp $	*/
-
-/*
- * Copyright (c) 1994-1996 Mark Brinicombe.
- * Copyright (c) 1994 Brini.
- * All rights reserved.
- *
- * This code is derived from software written for Brini by Mark Brinicombe
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- *    must display the following acknowledgement:
- *	This product includes software developed by Brini.
- * 4. The name of the company nor the name of the author may be used to
- *    endorse or promote products derived from this software without specific
- *    prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
- * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * RiscBSD kernel project
- *
- * katelib.h
- *
- * Prototypes for machine specific functions. Most of these
- * could be inlined.
- *
- * This should not really be a separate header file. Eventually I will merge
- * this into other header files once I have decided where the declarations
- * should go. 
- *
- * Created      : 18/09/94
- *
- * Based on kate/katelib/prototypes.h
- */
-
-/*
- * USE OF THIS FILE IS DEPRECATED
- */
-
-#include <sys/types.h>
-#include <arm/cpufunc.h>
-
-#ifdef _KERNEL
-
-/* Assembly modules */
-
-/* In blockio.S */
-#include <arm/blockio.h>
-
-/* Macros for reading and writing words, shorts, bytes */
-
-#define WriteWord(a, b) \
-*((volatile unsigned int *)(a)) = (b)
-
-#define ReadWord(a) \
-(*((volatile unsigned int *)(a)))
-
-#define WriteShort(a, b) \
-*((volatile unsigned int *)(a)) = ((b) | ((b) << 16))
-
-#define ReadShort(a) \
-((*((volatile unsigned int *)(a))) & 0xffff)
-
-#define WriteByte(a, b) \
-*((volatile unsigned char *)(a)) = (b)
-
-#define ReadByte(a) \
-(*((volatile unsigned char *)(a)))
-
-/* Define in/out macros */
-
-#define inb(port)		ReadByte((port))
-#define outb(port, byte)	WriteByte((port), (byte))
-#define inw(port)		ReadShort((port))
-#define outw(port, word)	WriteShort((port), (word))
-#define inl(port)		ReadWord((port))
-#define outl(port, lword)	WriteWord((port), (lword))
-
-#endif
-
-/* End of katelib.h */

sys/arch/arm/include/arm32/machdep.h

@@ -1,4 +1,4 @@
-/* $NetBSD: machdep.h,v 1.17 2012/10/20 14:42:20 matt Exp $ */
+/* $NetBSD: machdep.h,v 1.18 2014/03/28 21:51:59 matt Exp $ */
 
 #ifndef _ARM32_BOOT_MACHDEP_H_
 #define _ARM32_BOOT_MACHDEP_H_
@@ -53,7 +53,7 @@ extern struct bootmem_info bootmem_info;
 extern char *booted_kernel;
 
 extern volatile uint32_t arm_cpu_hatched;
-extern uint32_t arm_cpu_mbox;
+extern volatile uint32_t arm_cpu_mbox;
 extern u_int arm_cpu_max;
 
 /* misc prototypes used by the many arm machdeps */

sys/arch/arm/include/arm32/param.h

@@ -1,4 +1,4 @@
-/*	$NetBSD: param.h,v 1.20 2013/05/29 23:29:44 rkujawa Exp $	*/
+/*	$NetBSD: param.h,v 1.24 2015/04/02 03:11:01 matt Exp $	*/
 
 /*
  * Copyright (c) 1994,1995 Mark Brinicombe.
@@ -35,8 +35,8 @@
 #ifndef	_ARM_ARM32_PARAM_H_
 #define	_ARM_ARM32_PARAM_H_
 
-#ifdef _KERNEL
-#  include <machine/cpu.h>
+#ifdef _KERNEL_OPT
+# include "opt_arm32_pmap.h"
 #endif
 
 /*
@@ -45,16 +45,26 @@
 /* These are defined in the Port File before it includes
  * this file. */
 
+#if defined(__minix)
+/* We do not support PAGE_SIZE != 4k */
 #define	PGSHIFT		12		/* LOG2(NBPG) */
+#endif /* defined(__minix) */
+#ifndef PGSHIFT
+#if defined(_ARM_ARCH_6)
+#define	PGSHIFT		13		/* LOG2(NBPG) */
+#else
+#define	PGSHIFT		12		/* LOG2(NBPG) */
+#endif
+#endif
 #define	NBPG		(1 << PGSHIFT)	/* bytes/page */
 #define	PGOFSET		(NBPG-1)	/* byte offset into page */
 #define	NPTEPG		(NBPG/(sizeof (pt_entry_t)))
 
 
-#define SSIZE           1               /* initial stack size/NBPG */
-#define SINCR           1               /* increment of stack/NBPG */
-#define UPAGES          2               /* pages of u-area */
-#define USPACE          (UPAGES * NBPG) /* total size of u-area */
+#define SSIZE		1		/* initial stack size/NBPG */
+#define SINCR		1		/* increment of stack/NBPG */
+#define USPACE		8192		/* total size of u-area */
+#define UPAGES		(USPACE / NBPG)	/* pages of u-area */
 
 #ifndef MSGBUFSIZE
 #define MSGBUFSIZE	16384	 	/* default message buffer size */

sys/arch/arm/include/arm32/pmap.h

@@ -1,4 +1,4 @@
-/*	$NetBSD: pmap.h,v 1.122 2013/08/18 05:01:47 matt Exp $	*/
+/*	$NetBSD: pmap.h,v 1.142 2015/09/09 07:37:36 skrll Exp $	*/
 
 /*
  * Copyright (c) 2002, 2003 Wasabi Systems, Inc.
@@ -75,11 +75,41 @@
 #ifndef _LOCORE
 #if defined(_KERNEL_OPT)
 #include "opt_arm32_pmap.h"
+#include "opt_multiprocessor.h"
 #endif
 #include <arm/cpufunc.h>
+#include <arm/locore.h>
 #include <uvm/uvm_object.h>
 #endif
 
+#ifdef ARM_MMU_EXTENDED
+#define PMAP_TLB_MAX			1
+#define PMAP_TLB_HWPAGEWALKER		1
+#if PMAP_TLB_MAX > 1
+#define PMAP_NEED_TLB_SHOOTDOWN		1
+#endif
+#define PMAP_TLB_FLUSH_ASID_ON_RESET	(arm_has_tlbiasid_p)
+#define PMAP_TLB_NUM_PIDS		256
+#define cpu_set_tlb_info(ci, ti)        ((void)((ci)->ci_tlb_info = (ti)))
+#if PMAP_TLB_MAX > 1
+#define cpu_tlb_info(ci)		((ci)->ci_tlb_info)
+#else
+#define cpu_tlb_info(ci)		(&pmap_tlb0_info)
+#endif
+#define pmap_md_tlb_asid_max()		(PMAP_TLB_NUM_PIDS - 1)
+#include <uvm/pmap/tlb.h>
+#include <uvm/pmap/pmap_tlb.h>
+
+/*
+ * If we have an EXTENDED MMU and the address space is split evenly between
+ * user and kernel, we can use the TTBR0/TTBR1 to have separate L1 tables for
+ * user and kernel address spaces.
+ */
+#if (KERNEL_BASE & 0x80000000) == 0
+#error ARMv6 or later systems must have a KERNEL_BASE >= 0x80000000
+#endif
+#endif  /* ARM_MMU_EXTENDED */
+
 /*
  * a pmap describes a processes' 4GB virtual address space.  this
  * virtual address space can be broken up into 4096 1MB regions which
@@ -111,6 +141,8 @@
  * space per l2_dtable. Most processes will, therefore, require only two or
  * three of these to map their whole working set.
  */
+#define	L2_BUCKET_XLOG2	(L1_S_SHIFT)
+#define L2_BUCKET_XSIZE	(1 << L2_BUCKET_XLOG2)
 #define	L2_BUCKET_LOG2	4
 #define	L2_BUCKET_SIZE	(1 << L2_BUCKET_LOG2)
 
@@ -119,7 +151,7 @@
  * of l2_dtable structures required to track all possible page descriptors
  * mappable by an L1 translation table is given by the following constants:
  */
-#define	L2_LOG2		((32 - L1_S_SHIFT) - L2_BUCKET_LOG2)
+#define	L2_LOG2		(32 - (L2_BUCKET_XLOG2 + L2_BUCKET_LOG2))
 #define	L2_SIZE		(1 << L2_LOG2)
 
 /*
@@ -134,6 +166,7 @@
 
 #ifndef _LOCORE
 
+#ifndef PMAP_MMU_EXTENDED
 struct l1_ttable;
 struct l2_dtable;
 
@@ -165,6 +198,7 @@ union pmap_cache_state {
  * Assigned to cs_all to force cacheops to work for a particular pmap
  */
 #define	PMAP_CACHE_STATE_ALL	0xffffffffu
+#endif /* !ARM_MMU_EXTENDED */
 
 /*
  * This structure is used by machine-dependent code to describe
@@ -182,21 +216,39 @@ struct pmap_devmap {
  * The pmap structure itself
  */
 struct pmap {
-	uint8_t			pm_domain;
-	bool			pm_remove_all;
-	bool			pm_activated;
-	struct l1_ttable	*pm_l1;
-#ifndef ARM_HAS_VBAR
-	pd_entry_t		*pm_pl1vec;
-#endif
-	pd_entry_t		pm_l1vec;
-	union pmap_cache_state	pm_cstate;
 	struct uvm_object	pm_obj;
 	kmutex_t		pm_obj_lock;
 #define	pm_lock pm_obj.vmobjlock
+#ifndef ARM_HAS_VBAR
+	pd_entry_t		*pm_pl1vec;
+	pd_entry_t		pm_l1vec;
+#endif
 	struct l2_dtable	*pm_l2[L2_SIZE];
 	struct pmap_statistics	pm_stats;
 	LIST_ENTRY(pmap)	pm_list;
+#ifdef ARM_MMU_EXTENDED
+	pd_entry_t		*pm_l1;
+	paddr_t			pm_l1_pa;
+	bool			pm_remove_all;
+#ifdef MULTIPROCESSOR
+	kcpuset_t		*pm_onproc;
+	kcpuset_t		*pm_active;
+#if PMAP_TLB_MAX > 1
+	u_int			pm_shootdown_pending;
+#endif
+#endif
+	struct pmap_asid_info	pm_pai[PMAP_TLB_MAX];
+#else
+	struct l1_ttable	*pm_l1;
+	union pmap_cache_state	pm_cstate;
+	uint8_t			pm_domain;
+	bool			pm_activated;
+	bool			pm_remove_all;
+#endif
+};
+
+struct pmap_kernel {
+	struct pmap		kernel_pmap;
 };
 
 /*
@@ -224,6 +276,10 @@ extern pv_addr_t idlestack;
 extern pv_addr_t systempage;
 extern pv_addr_t kernel_l1pt;
 
+#ifdef ARM_MMU_EXTENDED
+extern bool arm_has_tlbiasid_p;	/* also in <arm/locore.h> */
+#endif
+
 /*
  * Determine various modes for PTEs (user vs. kernel, cacheable
  * vs. non-cacheable).
@@ -290,9 +346,11 @@ extern int		arm_poolpage_vmfreelist;
 
 #define pmap_phys_address(ppn)		(arm_ptob((ppn)))
 u_int arm32_mmap_flags(paddr_t);
-#define ARM32_MMAP_WRITECOMBINE	0x40000000
+#define ARM32_MMAP_WRITECOMBINE		0x40000000
 #define ARM32_MMAP_CACHEABLE		0x20000000
-#define pmap_mmap_flags(ppn)			arm32_mmap_flags(ppn)
+#define pmap_mmap_flags(ppn)		arm32_mmap_flags(ppn)
+
+#define	PMAP_PTE			0x10000000 /* kenter_pa */
 
 /*
  * Functions that we need to export
@@ -322,6 +380,7 @@ void	pmap_bootstrap(vaddr_t, vaddr_t);
 
 void	pmap_do_remove(pmap_t, vaddr_t, vaddr_t, int);
 int	pmap_fault_fixup(pmap_t, vaddr_t, vm_prot_t, int);
+int	pmap_prefetchabt_fixup(void *);
 bool	pmap_get_pde_pte(pmap_t, vaddr_t, pd_entry_t **, pt_entry_t **);
 bool	pmap_get_pde(pmap_t, vaddr_t, pd_entry_t **);
 struct pcb;
@@ -344,11 +403,20 @@ void	pmap_devmap_bootstrap(vaddr_t, const struct pmap_devmap *);
 void	pmap_devmap_register(const struct pmap_devmap *);
 
 /*
- * Special page zero routine for use by the idle loop (no cache cleans). 
+ * Special page zero routine for use by the idle loop (no cache cleans).
  */
 bool	pmap_pageidlezero(paddr_t);
 #define PMAP_PAGEIDLEZERO(pa)	pmap_pageidlezero((pa))
 
+#ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS
+/*
+ * For the pmap, this is a more useful way to map a direct mapped page.
+ * It returns either the direct-mapped VA or the VA supplied if it can't
+ * be direct mapped.
+ */
+vaddr_t	pmap_direct_mapped_phys(paddr_t, bool *, vaddr_t);
+#endif
+
 /*
  * used by dumpsys to record the PA of the L1 table
  */
@@ -358,8 +426,15 @@ uint32_t pmap_kernel_L1_addr(void);
  */
 extern vaddr_t	pmap_curmaxkvaddr;
 
+#if defined(ARM_MMU_EXTENDED) && defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS)
 /*
- * Useful macros and constants 
+ * Ending VA of direct mapped memory (usually KERNEL_VM_BASE).
+ */
+extern vaddr_t pmap_directlimit;
+#endif
+
+/*
+ * Useful macros and constants
  */
 
 /* Virtual address to page table entry */
@@ -369,6 +444,8 @@ vtopte(vaddr_t va)
 	pd_entry_t *pdep;
 	pt_entry_t *ptep;
 
+	KASSERT(trunc_page(va) == va);
+
 	if (pmap_get_pde_pte(pmap_kernel(), va, &pdep, &ptep) == false)
 		return (NULL);
 	return (ptep);
@@ -406,7 +483,7 @@ extern int pmap_needs_pte_sync;
  * we need to do PTE syncs.  If only SA-1 is configured, then evaluate
  * this at compile time.
  */
-#if (ARM_MMU_SA1 + ARM_MMU_V6 != 0) && (ARM_NMMUS == 1) 
+#if (ARM_MMU_SA1 + ARM_MMU_V6 != 0) && (ARM_NMMUS == 1)
 #define	PMAP_INCLUDE_PTE_SYNC
 #if (ARM_MMU_V6 > 0)
 #define	PMAP_NEEDS_PTE_SYNC	1
@@ -428,50 +505,93 @@ extern int pmap_needs_pte_sync;
 static inline void
 pmap_ptesync(pt_entry_t *ptep, size_t cnt)
 {
-	if (PMAP_NEEDS_PTE_SYNC)
+	if (PMAP_NEEDS_PTE_SYNC) {
 		cpu_dcache_wb_range((vaddr_t)ptep, cnt * sizeof(pt_entry_t));
-#if ARM_MMU_V7 > 0
-	__asm("dsb");
+#ifdef SHEEVA_L2_CACHE
+		cpu_sdcache_wb_range((vaddr_t)ptep, -1,
+		    cnt * sizeof(pt_entry_t));
 #endif
+	}
+	arm_dsb();
 }
 
-#define	PTE_SYNC(ptep)			pmap_ptesync((ptep), 1)
+#define	PDE_SYNC(pdep)			pmap_ptesync((pdep), 1)
+#define	PDE_SYNC_RANGE(pdep, cnt)	pmap_ptesync((pdep), (cnt))
+#define	PTE_SYNC(ptep)			pmap_ptesync((ptep), PAGE_SIZE / L2_S_SIZE)
 #define	PTE_SYNC_RANGE(ptep, cnt)	pmap_ptesync((ptep), (cnt))
 
-#define	l1pte_valid(pde)	((pde) != 0)
-#define	l1pte_section_p(pde)	(((pde) & L1_TYPE_MASK) == L1_TYPE_S)
-#define	l1pte_supersection_p(pde) (l1pte_section_p(pde)	\
+#define l1pte_valid_p(pde)	((pde) != 0)
+#define l1pte_section_p(pde)	(((pde) & L1_TYPE_MASK) == L1_TYPE_S)
+#define l1pte_supersection_p(pde) (l1pte_section_p(pde)	\
 				&& ((pde) & L1_S_V6_SUPER) != 0)
-#define	l1pte_page_p(pde)	(((pde) & L1_TYPE_MASK) == L1_TYPE_C)
-#define	l1pte_fpage_p(pde)	(((pde) & L1_TYPE_MASK) == L1_TYPE_F)
+#define l1pte_page_p(pde)	(((pde) & L1_TYPE_MASK) == L1_TYPE_C)
+#define l1pte_fpage_p(pde)	(((pde) & L1_TYPE_MASK) == L1_TYPE_F)
+#define l1pte_pa(pde)		((pde) & L1_C_ADDR_MASK)
+#define l1pte_index(v)		((vaddr_t)(v) >> L1_S_SHIFT)
+#define l1pte_pgindex(v)	l1pte_index((v) & L1_ADDR_BITS \
+		& ~(PAGE_SIZE * PAGE_SIZE / sizeof(pt_entry_t) - 1))
 
-#define l2pte_index(v)		(((v) & L2_ADDR_BITS) >> L2_S_SHIFT)
-#define	l2pte_valid(pte)	(((pte) & L2_TYPE_MASK) != L2_TYPE_INV)
-#define	l2pte_pa(pte)		((pte) & L2_S_FRAME)
-#define l2pte_minidata(pte)	(((pte) & \
+static inline void
+l1pte_setone(pt_entry_t *pdep, pt_entry_t pde)
+{
+	*pdep = pde;
+}
+
+static inline void
+l1pte_set(pt_entry_t *pdep, pt_entry_t pde)
+{
+	*pdep = pde;
+	if (l1pte_page_p(pde)) {
+		KASSERTMSG((((uintptr_t)pdep / sizeof(pde)) & (PAGE_SIZE / L2_T_SIZE - 1)) == 0, "%p", pdep);
+		for (size_t k = 1; k < PAGE_SIZE / L2_T_SIZE; k++) {
+			pde += L2_T_SIZE;
+			pdep[k] = pde;
+		}
+	} else if (l1pte_supersection_p(pde)) {
+		KASSERTMSG((((uintptr_t)pdep / sizeof(pde)) & (L1_SS_SIZE / L1_S_SIZE - 1)) == 0, "%p", pdep);
+		for (size_t k = 1; k < L1_SS_SIZE / L1_S_SIZE; k++) {
+			pdep[k] = pde;
+		}
+	}
+}
+
+#define l2pte_index(v)		((((v) & L2_ADDR_BITS) >> PGSHIFT) << (PGSHIFT-L2_S_SHIFT))
+#define l2pte_valid_p(pte)	(((pte) & L2_TYPE_MASK) != L2_TYPE_INV)
+#define l2pte_pa(pte)		((pte) & L2_S_FRAME)
+#define l1pte_lpage_p(pte)	(((pte) & L2_TYPE_MASK) == L2_TYPE_L)
+#define l2pte_minidata_p(pte)	(((pte) & \
 				 (L2_B | L2_C | L2_XS_T_TEX(TEX_XSCALE_X)))\
 				 == (L2_C | L2_XS_T_TEX(TEX_XSCALE_X)))
 
 static inline void
 l2pte_set(pt_entry_t *ptep, pt_entry_t pte, pt_entry_t opte)
 {
-	KASSERT(*ptep == opte);
-	*ptep = pte;
-	for (vsize_t k = 1; k < PAGE_SIZE / L2_S_SIZE; k++) {
-		KASSERT(ptep[k] == opte ? opte + k * L2_S_SIZE : 0);
-		pte += L2_S_SIZE;
-		ptep[k] = pte;
+	if (l1pte_lpage_p(pte)) {
+		KASSERTMSG((((uintptr_t)ptep / sizeof(pte)) & (L2_L_SIZE / L2_S_SIZE - 1)) == 0, "%p", ptep);
+		for (size_t k = 0; k < L2_L_SIZE / L2_S_SIZE; k++) {
+			*ptep++ = pte;
+		}
+	} else {
+		KASSERTMSG((((uintptr_t)ptep / sizeof(pte)) & (PAGE_SIZE / L2_S_SIZE - 1)) == 0, "%p", ptep);
+		for (size_t k = 0; k < PAGE_SIZE / L2_S_SIZE; k++) {
+			KASSERTMSG(*ptep == opte, "%#x [*%p] != %#x", *ptep, ptep, opte);
+			*ptep++ = pte;
+			pte += L2_S_SIZE;
+			if (opte)
+				opte += L2_S_SIZE;
+		}
 	}
-}       
+}
 
 static inline void
 l2pte_reset(pt_entry_t *ptep)
 {
+	KASSERTMSG((((uintptr_t)ptep / sizeof(*ptep)) & (PAGE_SIZE / L2_S_SIZE - 1)) == 0, "%p", ptep);
 	*ptep = 0;
 	for (vsize_t k = 1; k < PAGE_SIZE / L2_S_SIZE; k++) {
 		ptep[k] = 0;
 	}
-}       
+}
 
 /* L1 and L2 page table macros */
 #define pmap_pde_v(pde)		l1pte_valid(*(pde))
@@ -480,7 +600,7 @@ l2pte_reset(pt_entry_t *ptep)
 #define pmap_pde_page(pde)	l1pte_page_p(*(pde))
 #define pmap_pde_fpage(pde)	l1pte_fpage_p(*(pde))
 
-#define	pmap_pte_v(pte)		l2pte_valid(*(pte))
+#define	pmap_pte_v(pte)		l2pte_valid_p(*(pte))
 #define	pmap_pte_pa(pte)	l2pte_pa(*(pte))
 
 /* Size of the kernel part of the L1 page table */
@@ -582,11 +702,16 @@ extern void (*pmap_zero_page_func)(paddr_t);
 
 /*****************************************************************************/
 
+#define	KERNEL_PID		0	/* The kernel uses ASID 0 */
+
 /*
  * Definitions for MMU domains
  */
 #define	PMAP_DOMAINS		15	/* 15 'user' domains (1-15) */
-#define	PMAP_DOMAIN_KERNEL	0	/* The kernel uses domain #0 */
+#define	PMAP_DOMAIN_KERNEL	0	/* The kernel pmap uses domain #0 */
+#ifdef ARM_MMU_EXTENDED
+#define	PMAP_DOMAIN_USER	1	/* User pmaps use domain #1 */
+#endif
 
 /*
  * These macros define the various bit masks in the PTE.
@@ -617,6 +742,7 @@ extern void (*pmap_zero_page_func)(paddr_t);
 #define	L1_S_CACHE_MASK_generic	(L1_S_B|L1_S_C)
 #define	L1_S_CACHE_MASK_xscale	(L1_S_B|L1_S_C|L1_S_XS_TEX(TEX_XSCALE_X))
 #define	L1_S_CACHE_MASK_armv6	(L1_S_B|L1_S_C|L1_S_XS_TEX(TEX_ARMV6_TEX))
+#define	L1_S_CACHE_MASK_armv6n	(L1_S_B|L1_S_C|L1_S_XS_TEX(TEX_ARMV6_TEX)|L1_S_V6_S)
 #define	L1_S_CACHE_MASK_armv7	(L1_S_B|L1_S_C|L1_S_XS_TEX(TEX_ARMV6_TEX)|L1_S_V6_S)
 
 #define	L2_L_PROT_U_generic	(L2_AP(AP_U))
@@ -642,6 +768,7 @@ extern void (*pmap_zero_page_func)(paddr_t);
 #define	L2_L_CACHE_MASK_generic	(L2_B|L2_C)
 #define	L2_L_CACHE_MASK_xscale	(L2_B|L2_C|L2_XS_L_TEX(TEX_XSCALE_X))
 #define	L2_L_CACHE_MASK_armv6	(L2_B|L2_C|L2_V6_L_TEX(TEX_ARMV6_TEX))
+#define	L2_L_CACHE_MASK_armv6n	(L2_B|L2_C|L2_V6_L_TEX(TEX_ARMV6_TEX)|L2_XS_S)
 #define	L2_L_CACHE_MASK_armv7	(L2_B|L2_C|L2_V6_L_TEX(TEX_ARMV6_TEX)|L2_XS_S)
 
 #define	L2_S_PROT_U_generic	(L2_AP(AP_U))
@@ -667,12 +794,12 @@ extern void (*pmap_zero_page_func)(paddr_t);
 #define	L2_S_CACHE_MASK_generic	(L2_B|L2_C)
 #define	L2_S_CACHE_MASK_xscale	(L2_B|L2_C|L2_XS_T_TEX(TEX_XSCALE_X))
 #define	L2_XS_CACHE_MASK_armv6	(L2_B|L2_C|L2_V6_XS_TEX(TEX_ARMV6_TEX))
-#define	L2_S_CACHE_MASK_armv6n	L2_XS_CACHE_MASK_armv6
 #ifdef	ARMV6_EXTENDED_SMALL_PAGE
 #define	L2_S_CACHE_MASK_armv6c	L2_XS_CACHE_MASK_armv6
 #else
 #define	L2_S_CACHE_MASK_armv6c	L2_S_CACHE_MASK_generic
 #endif
+#define	L2_S_CACHE_MASK_armv6n	(L2_B|L2_C|L2_V6_XS_TEX(TEX_ARMV6_TEX)|L2_XS_S)
 #define	L2_S_CACHE_MASK_armv7	(L2_B|L2_C|L2_V6_XS_TEX(TEX_ARMV6_TEX)|L2_XS_S)
 
 
@@ -700,8 +827,16 @@ extern void (*pmap_zero_page_func)(paddr_t);
 #else
 #define	L2_S_PROTO_armv6c	(L2_TYPE_S)	/* XP=0, subpage APs */
 #endif
+#ifdef ARM_MMU_EXTENDED
+#define	L2_S_PROTO_armv6n	(L2_TYPE_S|L2_XS_XN)
+#else
 #define	L2_S_PROTO_armv6n	(L2_TYPE_S)	/* with XP=1 */
+#endif
+#ifdef ARM_MMU_EXTENDED
+#define	L2_S_PROTO_armv7	(L2_TYPE_S|L2_XS_XN)
+#else
 #define	L2_S_PROTO_armv7	(L2_TYPE_S)
+#endif
 
 /*
  * User-visible names for the ones that vary with MMU class.
@@ -778,8 +913,8 @@ extern void (*pmap_zero_page_func)(paddr_t);
 #define	L2_L_PROT_RO		L2_L_PROT_RO_armv6n
 #define	L2_L_PROT_MASK		L2_L_PROT_MASK_armv6n
 
-#define	L1_S_CACHE_MASK		L1_S_CACHE_MASK_armv6
-#define	L2_L_CACHE_MASK		L2_L_CACHE_MASK_armv6
+#define	L1_S_CACHE_MASK		L1_S_CACHE_MASK_armv6n
+#define	L2_L_CACHE_MASK		L2_L_CACHE_MASK_armv6n
 #define	L2_S_CACHE_MASK		L2_S_CACHE_MASK_armv6n
 
 /* These prototypes make writeable mappings, while the other MMU types
@@ -811,7 +946,7 @@ extern void (*pmap_zero_page_func)(paddr_t);
 #define	L2_L_CACHE_MASK		L2_L_CACHE_MASK_generic
 #define	L2_S_CACHE_MASK		L2_S_CACHE_MASK_generic
 
-#define	L1_SS_PROTO		L1_SS_PROTO_generic
+#define	L1_SS_PROTO		L1_SS_PROTO_armv6
 #define	L1_S_PROTO		L1_S_PROTO_generic
 #define	L1_C_PROTO		L1_C_PROTO_generic
 #define	L2_S_PROTO		L2_S_PROTO_generic
@@ -925,10 +1060,10 @@ struct vm_page *arm_pmap_alloc_poolpage(int);
 #define	PMAP_ALLOC_POOLPAGE	arm_pmap_alloc_poolpage
 #endif
 #if defined(PMAP_NEED_ALLOC_POOLPAGE) || defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS)
-#define	PMAP_MAP_POOLPAGE(pa) \
-        ((vaddr_t)((paddr_t)(pa) - physical_start + KERNEL_BASE))
-#define PMAP_UNMAP_POOLPAGE(va) \
-        ((paddr_t)((vaddr_t)(va) - KERNEL_BASE + physical_start))
+vaddr_t	pmap_map_poolpage(paddr_t);
+paddr_t	pmap_unmap_poolpage(vaddr_t);
+#define	PMAP_MAP_POOLPAGE(pa)	pmap_map_poolpage(pa)
+#define PMAP_UNMAP_POOLPAGE(va)	pmap_unmap_poolpage(va)
 #endif
 
 /*
@@ -959,7 +1094,7 @@ struct vm_page_md {
 #define	VM_MDPAGE_PVH_ATTRS_INIT(pg) \
 	(pg)->mdpage.pvh_attrs = 0
 #endif
- 
+
 #define	VM_MDPAGE_INIT(pg)						\
 do {									\
 	SLIST_INIT(&(pg)->mdpage.pvh_list);				\

sys/arch/arm/include/arm32/psl.h

@@ -1,4 +1,4 @@
-/*	$NetBSD: psl.h,v 1.19 2012/07/27 05:36:09 matt Exp $	*/
+/*	$NetBSD: psl.h,v 1.20 2014/02/04 18:51:16 matt Exp $	*/
 
 /*
  * Copyright (c) 1995 Mark Brinicombe.
@@ -70,10 +70,6 @@ int raisespl	(int);
 int lowerspl	(int);
 void splx	(int);
 
-#ifdef __HAVE_FAST_SOFTINTS
-void _setsoftintr	(int si);
-#endif
-
 typedef uint8_t ipl_t;
 typedef struct {
 	uint8_t _ipl;

sys/arch/arm/include/arm32/pte.h

@@ -1,4 +1,4 @@
-/*	$NetBSD: pte.h,v 1.13 2012/09/11 15:28:14 matt Exp $	*/
+/*	$NetBSD: pte.h,v 1.19 2014/10/29 10:59:48 skrll Exp $	*/
 
 /*
  * Copyright (c) 2001, 2002 Wasabi Systems, Inc.
@@ -137,6 +137,7 @@ typedef uint32_t	pt_entry_t;	/* L2 table entry */
  * keep the old L2_TABLE_SIZE define lying around. Converted ports
  * should use L2_TABLE_SIZE_REAL until then.
  */
+#define	L1_TABLE_SIZE_REAL	0x4000	/* 16K */
 #define	L2_TABLE_SIZE_REAL	0x400	/* 1K */
 
 /*
@@ -201,13 +202,13 @@ typedef uint32_t	pt_entry_t;	/* L2 table entry */
 #define	L2_TYPE_T	0x03		/* Tiny Page (not armv7) */
 #define	L2_TYPE_MASK	0x03		/* mask of type bits */
 
-	/*
-	 * This L2 Descriptor type is available on XScale processors
-	 * when using a Coarse L1 Descriptor.  The Extended Small
-	 * Descriptor has the same format as the XScale Tiny Descriptor,
-	 * but describes a 4K page, rather than a 1K page.
-	 * For V6 MMU, this is used when XP bit is cleared.
-	 */
+/*
+ * This L2 Descriptor type is available on XScale processors
+ * when using a Coarse L1 Descriptor.  The Extended Small
+ * Descriptor has the same format as the XScale Tiny Descriptor,
+ * but describes a 4K page, rather than a 1K page.
+ * For V6 MMU, this is used when XP bit is cleared.
+ */
 #define	L2_TYPE_XS	0x03		/* XScale/ARMv6 Extended Small Page */
 
 #define	L2_B		0x00000004	/* Bufferable page */
@@ -226,6 +227,7 @@ typedef uint32_t	pt_entry_t;	/* L2 table entry */
 #define	L2_XS_nG	0x00000800	/* ARMv6 Not-Global */
 #define	L2_V6_L_TEX	L2_XS_L_TEX
 #define	L2_V6_XS_TEX	L2_XS_T_TEX
+#define	L2_XS_L_XN	0x00008000	/* ARMv6 eXecute Never */
 
 
 /*
@@ -238,7 +240,7 @@ typedef uint32_t	pt_entry_t;	/* L2 table entry */
  * Access Permissions for L1 and L2 of ARMv6 with XP=1 and ARMv7
  */
 #define	AP_R		0x01		/* readable */
-#define	AP_RO		0x20		/* read-only */
+#define	AP_RO		0x20		/* read-only (L2_XS_APX >> 4) */
 
 /*
  * Short-hand for common AP_* constants.
@@ -248,8 +250,8 @@ typedef uint32_t	pt_entry_t;	/* L2 table entry */
  */
 #define	AP_KR		0x00		/* kernel read */
 #define	AP_KRW		0x01		/* kernel read/write */
-#define	AP_KRWUR	0x02		/* kernel read/write usr read */
-#define	AP_KRWURW	0x03		/* kernel read/write usr read/write */
+#define	AP_KRWUR	0x02		/* kernel read/write user read */
+#define	AP_KRWURW	0x03		/* kernel read/write user read/write */
 
 /*
  * Note: These values assume the S (System) and the R (ROM) bits are clear and
@@ -267,9 +269,9 @@ typedef uint32_t	pt_entry_t;	/* L2 table entry */
  * Also used for ARMv6 with XP bit set.
  */
 #define	AP7_KR		0x21		/* kernel read */
-#define	AP7_KRUR	0x23		/* kernel read usr read */
+#define	AP7_KRUR	0x23		/* kernel read user read */
 #define	AP7_KRW		0x01		/* kernel read/write */
-#define	AP7_KRWURW	0x03		/* kernel read/write usr read/write */
+#define	AP7_KRWURW	0x03		/* kernel read/write user read/write */
 
 /*
  * Domain Types for the Domain Access Control Register.
@@ -302,34 +304,32 @@ typedef uint32_t	pt_entry_t;	/* L2 table entry */
 /*
  * Type Extension bits for ARM V6 and V7 MMU
  *
- * TEX C B                                    Shared
- * 000 0 0  Strong order                      yes
- * 000 0 1  Shared device                     yes
- * 000 1 0  write through, no write alloc     S-bit
- * 000 1 1  write back, no write alloc        S-bit
- * 001 0 0  non-cacheable                     S-bit
+ * TEX C B                                                    Shared
+ * 000 0 0  Strong order                                      yes
+ * 000 0 1  Shared device                                     yes
+ * 000 1 0  Outer and Inner write through, no write alloc     S-bit
+ * 000 1 1  Outer and Inner write back, no write alloc        S-bit
+ * 001 0 0  Outer and Inner non-cacheable                     S-bit
  * 001 0 1  reserved
  * 001 1 0  reserved
- * 001 1 1  write back, write alloc           S-bit
- * 010 0 0  Non-shared device                 no
+ * 001 1 1  Outer and Inner write back, write alloc           S-bit
+ * 010 0 0  Non-shared device                                 no
  * 010 0 1  reserved
  * 010 1 X  reserved
  * 011 X X  reserved
- * 1BB A A  BB for internal, AA for external  S-bit
+ * 1BB A A  BB for inner, AA for outer                        S-bit
  *
- *    BB    internal cache
- *    0 0   Non-cacheable non-buffered
- *    0 1   Write back, write alloc, buffered
- *    1 0   Write through, no write alloc, buffered
- *          (non-cacheable for MPCore)
- *    1 1   Write back, no write alloc, buffered
- *          (write back, write alloc for MPCore)
- *    
- *    AA    external cache 
- *    0 0   Non-cacheable non-buffered
- *    0 1   Write back, write alloc, buffered
- *    1 0   Write through, no write alloc, buffered
- *    1 1   Write back, no write alloc, buffered
+ *    BB    inner cache
+ *    0 0   Non-cacheable
+ *    0 1   Write back, write alloc
+ *    1 0   Write through, no write alloc
+ *    1 1   Write back, no write alloc
+ *
+ *    AA    outer cache
+ *    0 0   Non-cacheable
+ *    0 1   Write back, write alloc
+ *    1 0   Write through, no write alloc
+ *    1 1   Write back, no write alloc
  */
 
 #define	TEX_ARMV6_TEX	0x07		/* 3 bits in TEX */

sys/arch/arm/include/arm32/vmparam.h

@@ -1,4 +1,4 @@
-/*	$NetBSD: vmparam.h,v 1.29 2013/02/27 17:50:07 matt Exp $	*/
+/*	$NetBSD: vmparam.h,v 1.39 2015/06/20 07:13:25 skrll Exp $	*/
 
 /*
  * Copyright (c) 2001, 2002 Wasabi Systems, Inc.
@@ -44,29 +44,36 @@
  * Virtual Memory parameters common to all arm32 platforms.
  */
 
-#ifndef __ASSEMBLER__
-#include <sys/simplelock.h>	/* struct simplelock */ 
-#endif /* __ASSEMBLER__ */
+#include <arm/cpuconf.h>
 #include <arm/arm32/pte.h>	/* pt_entry_t */
 
+#define	__USE_TOPDOWN_VM 
 #define	USRSTACK	VM_MAXUSER_ADDRESS
 
+/*
+ * ARMv4 systems are normaly configured for 256MB KVA only, so restrict
+ * the size of the pager map to 4MB.
+ */
+#ifndef _ARM_ARCH_5
+#define PAGER_MAP_DEFAULT_SIZE          (4 * 1024 * 1024)
+#endif
+
 /*
  * Note that MAXTSIZ can't be larger than 32M, otherwise the compiler
  * would have to be changed to not generate "bl" instructions.
  */
-#define	MAXTSIZ		(64*1024*1024)		/* max text size */
+#define	MAXTSIZ		(128*1024*1024)		/* max text size */
 #ifndef	DFLDSIZ
-#define	DFLDSIZ		(128*1024*1024)		/* initial data size limit */
+#define	DFLDSIZ		(384*1024*1024)		/* initial data size limit */
 #endif
 #ifndef	MAXDSIZ
-#define	MAXDSIZ		(1024*1024*1024)	/* max data size */
+#define	MAXDSIZ		(1536*1024*1024)	/* max data size */
 #endif
 #ifndef	DFLSSIZ
-#define	DFLSSIZ		(2*1024*1024)		/* initial stack size limit */
+#define	DFLSSIZ		(4*1024*1024)		/* initial stack size limit */
 #endif
 #ifndef	MAXSSIZ
-#define	MAXSSIZ		(32*1024*1024)		/* max stack size */
+#define	MAXSSIZ		(64*1024*1024)		/* max stack size */
 #endif
 
 /*
@@ -80,13 +87,18 @@
 /*
  * Mach derived constants
  */
-#define	VM_MIN_ADDRESS		((vaddr_t) 0x00001000)
-#define	VM_MAXUSER_ADDRESS	((vaddr_t) KERNEL_BASE - 0x1000)
+#define	VM_MIN_ADDRESS		((vaddr_t) PAGE_SIZE)
+#ifdef ARM_MMU_EXTENDED
+#define	VM_MAXUSER_ADDRESS	((vaddr_t) 0x80000000 - PAGE_SIZE)
+#else
+#define	VM_MAXUSER_ADDRESS	((vaddr_t) KERNEL_BASE - PAGE_SIZE)
+#endif
 #define	VM_MAX_ADDRESS		VM_MAXUSER_ADDRESS
 
 #define	VM_MIN_KERNEL_ADDRESS	((vaddr_t) KERNEL_BASE)
-#define	VM_MAX_KERNEL_ADDRESS	((vaddr_t) 0xffffefff)
+#define	VM_MAX_KERNEL_ADDRESS	((vaddr_t) -(PAGE_SIZE+1))
 
+#if !defined(__minix)
 #ifndef __ASSEMBLER__
 /* XXX max. amount of KVM to be used by buffers. */
 #ifndef VM_MAX_KERNEL_BUF
@@ -97,6 +109,7 @@ extern vaddr_t virtual_end;
 	((virtual_end - virtual_avail) * 4 / 10)
 #endif
 #endif /* __ASSEMBLER__ */
+#endif /* !defined(__minix) */
 
 #endif /* _KERNEL || _KMEMUSER */
 

sys/arch/arm/include/armreg.h

@@ -1,4 +1,4 @@
-/*	$NetBSD: armreg.h,v 1.83 2013/09/07 00:32:33 matt Exp $	*/
+/*	$NetBSD: armreg.h,v 1.107 2015/06/09 08:08:14 skrll Exp $	*/
 
 /*
  * Copyright (c) 1998, 2001 Ben Harris
@@ -43,7 +43,7 @@
  * ARM Process Status Register
  *
  * The picture in the ARM manuals looks like this:
- *       3 3 2 2 2 2                            
+ *       3 3 2 2 2 2
  *       1 0 9 8 7 6                                   8 7 6 5 4       0
  *      +-+-+-+-+-+-------------------------------------+-+-+-+---------+
  *      |N|Z|C|V|Q|                reserved             |I|F|T|M M M M M|
@@ -58,19 +58,30 @@
 #define PSR_V_bit (1 << 28)	/* overflow */
 
 #define PSR_Q_bit (1 << 27)	/* saturation */
+#define PSR_IT1_bit (1 << 26)
+#define PSR_IT0_bit (1 << 25)
+#define PSR_J_bit (1 << 24)	/* Jazelle mode */
+#define PSR_GE_bits (15 << 16)	/* SIMD GE bits */
+#define PSR_IT7_bit (1 << 15)
+#define PSR_IT6_bit (1 << 14)
+#define PSR_IT5_bit (1 << 13)
+#define PSR_IT4_bit (1 << 12)
+#define PSR_IT3_bit (1 << 11)
+#define PSR_IT2_bit (1 << 10)
+#define PSR_E_BIT (1 << 9)	/* Endian state */
+#define PSR_A_BIT (1 << 8)	/* Async abort disable */
 
 #define I32_bit (1 << 7)	/* IRQ disable */
 #define F32_bit (1 << 6)	/* FIQ disable */
-#define	IF32_bits (3 << 6)	/* IRQ/FIQ disable */
+#define IF32_bits (3 << 6)	/* IRQ/FIQ disable */
 
 #define PSR_T_bit (1 << 5)	/* Thumb state */
-#define PSR_J_bit (1 << 24)	/* Java mode */
 
-#ifdef __minix
+#if defined(__minix)
 /* Minix uses these aliases */
 #define PSR_F F32_bit
 #define PSR_I I32_bit
-#endif
+#endif /* defined(__minix) */
 
 #define PSR_MODE	0x0000001f	/* mode mask */
 #define PSR_USR26_MODE	0x00000000
@@ -220,6 +231,7 @@
 #define CPU_ID_CORTEXA9R4	0x413fc090
 #define CPU_ID_CORTEXA15R2	0x412fc0f0
 #define CPU_ID_CORTEXA15R3	0x413fc0f0
+#define CPU_ID_CORTEXA17R1	0x411fc0e0
 #define CPU_ID_CORTEX_P(n)	((n & 0xff0ff000) == 0x410fc000)
 #define CPU_ID_CORTEX_A5_P(n)	((n & 0xff0ff0f0) == 0x410fc050)
 #define CPU_ID_CORTEX_A7_P(n)	((n & 0xff0ff0f0) == 0x410fc070)
@@ -264,6 +276,11 @@
 #define CPU_ID_ARM_88SV584X_V6	0x410fb020 /* Marvell Sheeva 88SV584x v6 Core */
 
 /* CPUID registers */
+#define ARM_ISA3_SYNCHPRIM_MASK	0x0000f000
+#define ARM_ISA4_SYNCHPRIM_MASK	0x00f00000
+#define ARM_ISA3_SYNCHPRIM_LDREX	0x10	// LDREX
+#define ARM_ISA3_SYNCHPRIM_LDREXPLUS	0x13	// +CLREX/LDREXB/LDREXH
+#define ARM_ISA3_SYNCHPRIM_LDREXD	0x20	// +LDREXD
 #define ARM_PFR0_THUMBEE_MASK	0x0000f000
 #define ARM_PFR1_GTIMER_MASK	0x000f0000
 #define ARM_PFR1_VIRT_MASK	0x0000f000
@@ -292,7 +309,7 @@
 #define ARM3_CP15_CONTROL	2
 #define ARM3_CP15_CACHEABLE	3
 #define ARM3_CP15_UPDATEABLE	4
-#define ARM3_CP15_DISRUPTIVE	5	
+#define ARM3_CP15_DISRUPTIVE	5
 
 /* ARM3 Control register bits */
 #define ARM3_CTL_CACHE_ON	0x00000001
@@ -353,6 +370,9 @@
 #define CPU_CONTROL_VECRELOC	0x00002000 /* V: Vector relocation */
 #define CPU_CONTROL_ROUNDROBIN	0x00004000 /* RR: Predictable replacement */
 #define CPU_CONTROL_V4COMPAT	0x00008000 /* L4: ARMv4 compat LDR R15 etc */
+#define CPU_CONTROL_HA_ENABLE	0x00020000 /* HA: Hardware Access flag enable */
+#define CPU_CONTROL_WXN_ENABLE	0x00080000 /* WXN: Write Execute Never */
+#define CPU_CONTROL_UWXN_ENABLE	0x00100000 /* UWXN: User Write eXecute Never */
 #define CPU_CONTROL_FI_ENABLE	0x00200000 /* FI: Low interrupt latency */
 #define CPU_CONTROL_UNAL_ENABLE	0x00400000 /* U: unaligned data access */
 #define CPU_CONTROL_XP_ENABLE	0x00800000 /* XP: extended page table */
@@ -374,6 +394,13 @@
 #define	CPACR_RESERVED		2
 #define	CPACR_ALL		3 /* Privileged and User mode access */
 
+/* ARMv6/ARMv7 Non-Secure Access Control Register (CP15, 0, c1, c1, 2) */
+#define NSACR_SMP		0x00040000 /* ACTRL.SMP is writeable (!A8) */
+#define NSACR_L2ERR		0x00020000 /* L2ECTRL is writeable (!A8) */
+#define NSACR_ASEDIS		0x00008000 /* Deny Advanced SIMD Ext. */
+#define NSACR_D32DIS		0x00004000 /* Deny VFP regs 15-31 */
+#define NSACR_CPn(n)		(1 << (n)) /* NonSecure access allowed */
+
 /* ARM11x6 Auxiliary Control Register (CP15 register 1, opcode2 1) */
 #define	ARM11X6_AUXCTL_RS	0x00000001 /* return stack */
 #define	ARM11X6_AUXCTL_DB	0x00000002 /* dynamic branch prediction */
@@ -391,22 +418,12 @@
 					    * in r0 steppings. See errata
 					    * 364296.
 					    */
-/* ARM1176 Auxiliary Control Register (CP15 register 1, opcode2 1) */   
+/* ARM1176 Auxiliary Control Register (CP15 register 1, opcode2 1) */
 #define	ARM1176_AUXCTL_PHD	0x10000000 /* inst. prefetch halting disable */
 #define	ARM1176_AUXCTL_BFD	0x20000000 /* branch folding disable */
 #define	ARM1176_AUXCTL_FSD	0x40000000 /* force speculative ops disable */
 #define	ARM1176_AUXCTL_FIO	0x80000000 /* low intr latency override */
 
-/* Cortex-A9 Auxiliary Control Register (CP15 register 1, opcode2 1) */   
-#define	CORTEXA9_AUXCTL_PARITY	0x00000200 /* Enable parity */
-#define	CORTEXA9_AUXCTL_1WAY	0x00000100 /* Alloc in one way only */
-#define	CORTEXA9_AUXCTL_EXCL	0x00000080 /* Exclusive cache */
-#define	CORTEXA9_AUXCTL_SMP	0x00000040 /* CPU is in SMP mode */
-#define	CORTEXA9_AUXCTL_WRZERO	0x00000008 /* Write full line of zeroes */
-#define	CORTEXA9_AUXCTL_L1PLD	0x00000004 /* L1 Dside prefetch */
-#define	CORTEXA9_AUXCTL_L2PLD	0x00000002 /* L2 Dside prefetch */
-#define	CORTEXA9_AUXCTL_FW	0x00000001 /* Forward Cache/TLB ops */
-
 /* XScale Auxiliary Control Register (CP15 register 1, opcode2 1) */
 #define	XSCALE_AUXCTL_K		0x00000001 /* dis. write buffer coalescing */
 #define	XSCALE_AUXCTL_P		0x00000002 /* ECC protect page table access */
@@ -423,13 +440,22 @@
 #define	MPCORE_AUXCTL_EX	0x00000010 /* exclusive L1/L2 cache */
 #define	MPCORE_AUXCTL_SA	0x00000020 /* SMP/AMP */
 
-/* Marvell PJ4B Auxillary Control Register */
-#define PJ4B_AUXCTL_SMPNAMP	0x00000040 /* SMP/AMP */
+/* Marvell PJ4B Auxillary Control Register (CP15.0.R1.c0.1) */
+#define PJ4B_AUXCTL_FW		__BIT(0)   /* Cache and TLB updates broadcast */
+#define PJ4B_AUXCTL_SMPNAMP	__BIT(6)   /* 0 = AMP, 1 = SMP */
+#define PJ4B_AUXCTL_L1PARITY	__BIT(9)   /* L1 parity checking */
+
+/* Marvell PJ4B Auxialiary Function Modes Control 0 (CP15.1.R15.c2.0) */
+#define PJ4B_AUXFMC0_L2EN	__BIT(0)  /* Tightly-Coupled L2 cache enable */
+#define PJ4B_AUXFMC0_SMPNAMP	__BIT(1)  /* 0 = AMP, 1 = SMP */
+#define PJ4B_AUXFMC0_L1PARITY	__BIT(2)  /* alias of PJ4B_AUXCTL_L1PARITY */
+#define PJ4B_AUXFMC0_DCSLFD	__BIT(2)  /* Disable DC Speculative linefill */
+#define PJ4B_AUXFMC0_FW		__BIT(8)  /* alias of PJ4B_AUXCTL_FW*/
 
 /* Cortex-A9 Auxiliary Control Register (CP15 register 1, opcode 1) */
 #define	CORTEXA9_AUXCTL_FW	0x00000001 /* Cache and TLB updates broadcast */
-#define	CORTEXA9_AUXCTL_L2_PLD	0x00000002 /* Prefetch hint enable */
-#define	CORTEXA9_AUXCTL_L1_PLD	0x00000004 /* Data prefetch hint enable */
+#define	CORTEXA9_AUXCTL_L2PE	0x00000002 /* Prefetch hint enable */
+#define	CORTEXA9_AUXCTL_L1PE	0x00000004 /* Data prefetch hint enable */
 #define	CORTEXA9_AUXCTL_WR_ZERO	0x00000008 /* Ena. write full line of 0s mode */
 #define	CORTEXA9_AUXCTL_SMP	0x00000040 /* Coherency is active */
 #define	CORTEXA9_AUXCTL_EXCL	0x00000080 /* Exclusive cache bit */
@@ -479,10 +505,10 @@
 #define	CPU_CT4_CWG(x)		(((x) >> 24) & 0xf)	/* Exclusive Resv. Granule */
 
 /* Cache size identifaction register definitions 1, Rd, c0, c0, 0 */
-#define	CPU_CSID_CTYPE_WT	0x80000000	/* write-through avail */ 
-#define	CPU_CSID_CTYPE_WB	0x40000000	/* write-back avail */ 
-#define	CPU_CSID_CTYPE_RA	0x20000000	/* read-allocation avail */ 
-#define	CPU_CSID_CTYPE_WA	0x10000000	/* write-allocation avail */ 
+#define	CPU_CSID_CTYPE_WT	0x80000000	/* write-through avail */
+#define	CPU_CSID_CTYPE_WB	0x40000000	/* write-back avail */
+#define	CPU_CSID_CTYPE_RA	0x20000000	/* read-allocation avail */
+#define	CPU_CSID_CTYPE_WA	0x10000000	/* write-allocation avail */
 #define	CPU_CSID_NUMSETS(x)	(((x) >> 13) & 0x7fff)
 #define	CPU_CSID_ASSOC(x)	(((x) >> 3) & 0x1ff)
 #define	CPU_CSID_LEN(x)		((x) & 0x07)
@@ -527,7 +553,11 @@
 #define FAULT_PERM_S    0x0d /* Permission -- Section */
 #define FAULT_PERM_P    0x0f /* Permission -- Page */
 
-#define	FAULT_IMPRECISE	0x400	/* Imprecise exception (XSCALE) */
+#define FAULT_LPAE	0x0200	/* (SW) used long descriptors */
+#define FAULT_IMPRECISE	0x0400	/* Imprecise exception (XSCALE) */
+#define FAULT_WRITE	0x0800	/* fault was due to write (ARMv6+) */
+#define FAULT_EXT	0x1000	/* fault was due to external abort (ARMv6+) */
+#define FAULT_CM	0x2000	/* fault was due to cache maintenance (ARMv7+) */
 
 /*
  * Address of the vector page, low and high versions.
@@ -538,7 +568,7 @@
 /*
  * ARM Instructions
  *
- *       3 3 2 2 2                              
+ *       3 3 2 2 2
  *       1 0 9 8 7                                                     0
  *      +-------+-------------------------------------------------------+
  *      | cond  |              instruction dependent                    |
@@ -548,7 +578,21 @@
 
 #define INSN_SIZE		4		/* Always 4 bytes */
 #define INSN_COND_MASK		0xf0000000	/* Condition mask */
-#define INSN_COND_AL		0xe0000000	/* Always condition */
+#define INSN_COND_EQ		0		/* Z == 1 */
+#define INSN_COND_NE		1		/* Z == 0 */
+#define INSN_COND_CS		2		/* C == 1 */
+#define INSN_COND_CC		3		/* C == 0 */
+#define INSN_COND_MI		4		/* N == 1 */
+#define INSN_COND_PL		5		/* N == 0 */
+#define INSN_COND_VS		6		/* V == 1 */
+#define INSN_COND_VC		7		/* V == 0 */
+#define INSN_COND_HI		8		/* C == 1 && Z == 0 */
+#define INSN_COND_LS		9		/* C == 0 || Z == 1 */
+#define INSN_COND_GE		10		/* N == V */
+#define INSN_COND_LT		11		/* N != V */
+#define INSN_COND_GT		12		/* Z == 0 && N == V */
+#define INSN_COND_LE		13		/* Z == 1 || N != V */
+#define INSN_COND_AL		14		/* Always condition */
 
 #define THUMB_INSN_SIZE		2		/* Some are 4 bytes.  */
 
@@ -603,6 +647,26 @@
 #define CORTEX_CNTENC_C __BIT(31)	/* Disables the cycle counter */
 #define CORTEX_CNTOFL_C __BIT(31)	/* Cycle counter overflow flag */
 
+/* Defines for ARM Cortex A7/A15 L2CTRL */
+#define L2CTRL_NUMCPU	__BITS(25,24)	// numcpus - 1
+#define L2CTRL_ICPRES	__BIT(23)	// Interrupt Controller is present
+
+/* Translation Table Base Register */
+#define	TTBR_C			__BIT(0)	/* without MPE */
+#define	TTBR_S			__BIT(1)
+#define	TTBR_IMP		__BIT(2)
+#define	TTBR_RGN_MASK		__BITS(4,3)
+#define	 TTBR_RGN_NC		__SHIFTIN(0, TTBR_RGN_MASK)
+#define	 TTBR_RGN_WBWA		__SHIFTIN(1, TTBR_RGN_MASK)
+#define	 TTBR_RGN_WT		__SHIFTIN(2, TTBR_RGN_MASK)
+#define	 TTBR_RGN_WBNWA		__SHIFTIN(3, TTBR_RGN_MASK)
+#define	TTBR_NOS		__BIT(5)
+#define	TTBR_IRGN_MASK		(__BIT(6) | __BIT(0))
+#define	 TTBR_IRGN_NC		0
+#define	 TTBR_IRGN_WBWA		__BIT(6)
+#define	 TTBR_IRGN_WT		__BIT(0)
+#define	 TTBR_IRGN_WBNWA	(__BIT(0) | __BIT(6))
+
 /* Translate Table Base Control Register */
 #define TTBCR_S_EAE	__BIT(31)	// Extended Address Extension
 #define TTBCR_S_PD1	__BIT(5)	// Don't use TTBR1
@@ -622,6 +686,43 @@
 #define TTBCR_L_EPD0	__BIT(7)	// Don't use TTBR0
 #define TTBCR_L_T0SZ	__BITS(2,0)	// TTBR0 size offset
 
+#define NRRR_ORn(n)	__BITS(17+2*(n),16+2*(n)) // Outer Cacheable mappings
+#define NRRR_IRn(n)	__BITS(1+2*(n),0+2*(n)) // Inner Cacheable mappings
+#define NRRR_NC		0		// non-cacheable
+#define NRRR_WB_WA	1		// write-back write-allocate
+#define NRRR_WT		2		// write-through
+#define NRRR_WB		3		// write-back
+#define PRRR_NOSn(n)	__BITS(24+2*(n))// Memory region is Inner Shareable
+#define PRRR_NS1	__BIT(19)	// Normal Shareable S=1 is Shareable
+#define PRRR_NS0	__BIT(18)	// Normal Shareable S=0 is Shareable
+#define PRRR_DS1	__BIT(17)	// Device Shareable S=1 is Shareable
+#define PRRR_DS0	__BIT(16)	// Device Shareable S=0 is Shareable
+#define PRRR_TRn(n)	__BITS(1+2*(n),0+2*(n))
+#define PRRR_TR_STRONG	0		// Strongly Ordered
+#define PRRR_TR_DEVICE	1		// Device
+#define PRRR_TR_NORMAL	2		// Normal Memory
+
+/* ARMv7 MPIDR, Multiprocessor Affinity Register generic format  */
+#define MPIDR_MP		__BIT(31)	/* 1 = Have MP Extention */
+#define MPIDR_U			__BIT(30)	/* 1 = Uni-Processor System */
+#define MPIDR_MT		__BIT(24)	/* 1 = SMT(AFF0 is logical) */
+#define MPIDR_AFF2		__BITS(23,16)	/* Affinity Level 2 */
+#define MPIDR_AFF1		__BITS(15,8)	/* Affinity Level 1 */
+#define MPIDR_AFF0		__BITS(7,0)	/* Affinity Level 0 */
+
+/* MPIDR implementation of ARM Cortex A9: SMT and AFF2 is not used */
+#define CORTEXA9_MPIDR_MP	MPIDR_MP
+#define CORTEXA9_MPIDR_U	MPIDR_U
+#define	CORTEXA9_MPIDR_CLID	__BITS(11,8)	/* AFF1 = cluster id */
+#define CORTEXA9_MPIDR_CPUID	__BITS(0,1)	/* AFF0 = phisycal core id */
+
+/* MPIDR implementation of Marvell PJ4B-MP: AFF2 is not used */
+#define PJ4B_MPIDR_MP		MPIDR_MP
+#define PJ4B_MPIDR_U		MPIDR_U
+#define PJ4B_MPIDR_MT		MPIDR_MT	/* 1 = SMT(AFF0 is logical) */
+#define PJ4B_MPIDR_CLID		__BITS(11,8)	/* AFF1 = cluster id */
+#define PJ4B_MPIDR_CPUID	__BITS(0,3)	/* AFF0 = core id */
+
 /* Defines for ARM Generic Timer */
 #define ARM_CNTCTL_ENABLE		__BIT(0) // Timer Enabled
 #define ARM_CNTCTL_IMASK		__BIT(1) // Mask Interrupt
@@ -641,6 +742,125 @@
 #define ARM_CNTHCTL_PL1PCTEN		__BIT(1)
 #define ARM_CNTHCTL_PL1VCTEN		__BIT(0)
 
+#define ARM_A5_TLBDATA_DOM		__BITS(62,59)
+#define ARM_A5_TLBDATA_AP		__BITS(58,56)
+#define ARM_A5_TLBDATA_NS_WALK		__BIT(55)
+#define ARM_A5_TLBDATA_NS_PAGE		__BIT(54)
+#define ARM_A5_TLBDATA_XN		__BIT(53)
+#define ARM_A5_TLBDATA_TEX		__BITS(52,50)
+#define ARM_A5_TLBDATA_B		__BIT(49)
+#define ARM_A5_TLBDATA_C		__BIT(48)
+#define ARM_A5_TLBDATA_S		__BIT(47)
+#define ARM_A5_TLBDATA_ASID		__BITS(46,39)
+#define ARM_A5_TLBDATA_SIZE		__BITS(38,37)
+#define ARM_A5_TLBDATA_SIZE_4KB		0
+#define ARM_A5_TLBDATA_SIZE_16KB	1
+#define ARM_A5_TLBDATA_SIZE_1MB		2
+#define ARM_A5_TLBDATA_SIZE_16MB	3
+#define ARM_A5_TLBDATA_VA		__BITS(36,22)
+#define ARM_A5_TLBDATA_PA		__BITS(21,2)
+#define ARM_A5_TLBDATA_nG		__BIT(1)
+#define ARM_A5_TLBDATA_VALID		__BIT(0)
+
+#define ARM_A7_TLBDATA2_S2_LEVEL	__BITS(85-64,84-64)
+#define ARM_A7_TLBDATA2_S1_SIZE		__BITS(83-64,82-64)
+#define ARM_A7_TLBDATA2_S1_SIZE_4KB	0
+#define ARM_A7_TLBDATA2_S1_SIZE_64KB	1
+#define ARM_A7_TLBDATA2_S1_SIZE_1MB	2
+#define ARM_A7_TLBDATA2_S1_SIZE_16MB	3
+#define ARM_A7_TLBDATA2_DOM		__BITS(81-64,78-64)
+#define ARM_A7_TLBDATA2_IS		__BITS(77-64,76-64)
+#define ARM_A7_TLBDATA2_IS_NC		0
+#define ARM_A7_TLBDATA2_IS_WB_WA	1
+#define ARM_A7_TLBDATA2_IS_WT		2
+#define ARM_A7_TLBDATA2_IS_DSO		3
+#define ARM_A7_TLBDATA2_S2OVR		__BIT(75-64)
+#define ARM_A7_TLBDATA2_SDO_MT		__BITS(74-64,72-64)
+#define ARM_A7_TLBDATA2_SDO_MT_D	2
+#define ARM_A7_TLBDATA2_SDO_MT_SO	6
+#define ARM_A7_TLBDATA2_OS		__BITS(75-64,74-64)
+#define ARM_A7_TLBDATA2_OS_NC		0
+#define ARM_A7_TLBDATA2_OS_WB_WA	1
+#define ARM_A7_TLBDATA2_OS_WT		2
+#define ARM_A7_TLBDATA2_OS_WB		3
+#define ARM_A7_TLBDATA2_SH		__BITS(73-64,72-64)
+#define ARM_A7_TLBDATA2_SH_NONE		0
+#define ARM_A7_TLBDATA2_SH_UNUSED	1
+#define ARM_A7_TLBDATA2_SH_OS		2
+#define ARM_A7_TLBDATA2_SH_IS		3
+#define ARM_A7_TLBDATA2_XN2		__BIT(71-64)
+#define ARM_A7_TLBDATA2_XN1		__BIT(70-64)
+#define ARM_A7_TLBDATA2_PXN		__BIT(69-64)
+
+#define ARM_A7_TLBDATA12_PA		__BITS(68-32,41-32)
+
+#define ARM_A7_TLBDATA1_NS		__BIT(40-32)
+#define ARM_A7_TLBDATA1_HAP		__BITS(39-32,38-32)
+#define ARM_A7_TLBDATA1_AP		__BITS(37-32,35-32)
+#define ARM_A7_TLBDATA1_nG		__BIT(34-32)
+
+#define ARM_A7_TLBDATA01_ASID		__BITS(33,26)
+
+#define ARM_A7_TLBDATA0_VMID		__BITS(25,18)
+#define ARM_A7_TLBDATA0_VA		__BITS(17,5)
+#define ARM_A7_TLBDATA0_NS_WALK		__BIT(4)
+#define ARM_A7_TLBDATA0_SIZE		__BITS(3,1)
+#define ARM_A7_TLBDATA0_SIZE_V7_4KB	0
+#define ARM_A7_TLBDATA0_SIZE_LPAE_4KB	1
+#define ARM_A7_TLBDATA0_SIZE_V7_64KB	2
+#define ARM_A7_TLBDATA0_SIZE_LPAE_64KB	3
+#define ARM_A7_TLBDATA0_SIZE_V7_1MB	4
+#define ARM_A7_TLBDATA0_SIZE_LPAE_2MB	5
+#define ARM_A7_TLBDATA0_SIZE_V7_16MB	6
+#define ARM_A7_TLBDATA0_SIZE_LPAE_1GB	7
+
+#define ARM_TLBDATA_VALID		__BIT(0)
+
+#define ARM_TLBDATAOP_WAY		__BIT(31)
+#define ARM_A5_TLBDATAOP_INDEX		__BITS(5,0)
+#define ARM_A7_TLBDATAOP_INDEX		__BITS(6,0)
+
+#if !defined(__ASSEMBLER__) && defined(_KERNEL)
+static inline bool
+arm_cond_ok_p(uint32_t insn, uint32_t psr)
+{
+	const uint32_t __cond = __SHIFTOUT(insn, INSN_COND_MASK);
+
+	bool __ok;
+	const bool __z = (psr & PSR_Z_bit);
+	const bool __n = (psr & PSR_N_bit);
+	const bool __c = (psr & PSR_C_bit);
+	const bool __v = (psr & PSR_V_bit);
+	switch (__cond & ~1) {
+	case INSN_COND_EQ:	// Z == 1
+		__ok = __z;
+		break;
+	case INSN_COND_CS:	// C == 1
+		__ok = __c;
+		break;
+	case INSN_COND_MI:	// N == 1
+		__ok = __n;
+		break;
+	case INSN_COND_VS:	// V == 1
+		__ok = __v;
+		break;
+	case INSN_COND_HI:	// C == 1 && Z == 0
+		__ok = __c && !__z;
+		break;
+	case INSN_COND_GE:	// N == V
+		__ok = __n == __v;
+		break;
+	case INSN_COND_GT:	// N == V && Z == 0
+		__ok = __n == __v && !__z;
+		break;
+	default: /* INSN_COND_AL or unconditional */
+		return true;
+	}
+
+	return (__cond & 1) ? !__ok : __ok;
+}
+#endif /* !__ASSEMBLER && _KERNEL */
+
 #if !defined(__ASSEMBLER__) && !defined(_RUMPKERNEL)
 #define	ARMREG_READ_INLINE(name, __insnstring)			\
 static inline uint32_t armreg_##name##_read(void)		\
@@ -656,6 +876,20 @@ static inline void armreg_##name##_write(uint32_t __val)	\
 	__asm __volatile("mcr " __insnstring :: "r"(__val));	\
 }
 
+#define	ARMREG_READ_INLINE2(name, __insnstring)			\
+static inline uint32_t armreg_##name##_read(void)		\
+{								\
+	uint32_t __rv;						\
+	__asm __volatile(__insnstring : "=r"(__rv));	\
+	return __rv;						\
+}
+
+#define	ARMREG_WRITE_INLINE2(name, __insnstring)		\
+static inline void armreg_##name##_write(uint32_t __val)	\
+{								\
+	__asm __volatile(__insnstring :: "r"(__val));		\
+}
+
 #define	ARMREG_READ64_INLINE(name, __insnstring)		\
 static inline uint64_t armreg_##name##_read(void)		\
 {								\
@@ -671,22 +905,24 @@ static inline void armreg_##name##_write(uint64_t __val)	\
 }
 
 /* cp10 registers */
-ARMREG_READ_INLINE(fpsid, "p10,7,%0,c0,c0,0") /* VFP System ID */
-ARMREG_READ_INLINE(fpscr, "p10,7,%0,c1,c0,0") /* VFP Status/Control Register */
-ARMREG_WRITE_INLINE(fpscr, "p10,7,%0,c1,c0,0") /* VFP Status/Control Register */
-ARMREG_READ_INLINE(mvfr1, "p10,7,%0,c6,c0,0") /* Media and VFP Feature Register 1 */
-ARMREG_READ_INLINE(mvfr0, "p10,7,%0,c7,c0,0") /* Media and VFP Feature Register 0 */
-ARMREG_READ_INLINE(fpexc, "p10,7,%0,c8,c0,0") /* VFP Exception Register */
-ARMREG_WRITE_INLINE(fpexc, "p10,7,%0,c8,c0,0") /* VFP Exception Register */
-ARMREG_READ_INLINE(fpinst, "p10,7,%0,c9,c0,0") /* VFP Exception Instruction */
-ARMREG_WRITE_INLINE(fpinst, "p10,7,%0,c9,c0,0") /* VFP Exception Instruction */
-ARMREG_READ_INLINE(fpinst2, "p10,7,%0,c10,c0,0") /* VFP Exception Instruction 2 */
-ARMREG_WRITE_INLINE(fpinst2, "p10,7,%0,c10,c0,0") /* VFP Exception Instruction 2 */
+ARMREG_READ_INLINE2(fpsid, "vmrs\t%0, fpsid") /* VFP System ID */
+ARMREG_READ_INLINE2(fpscr, "vmrs\t%0, fpscr") /* VFP Status/Control Register */
+ARMREG_WRITE_INLINE2(fpscr, "vmsr\tfpscr, %0") /* VFP Status/Control Register */
+ARMREG_READ_INLINE2(mvfr1, "vmrs\t%0, mvfr1") /* Media and VFP Feature Register 1 */
+ARMREG_READ_INLINE2(mvfr0, "vmrs\t%0, mvfr0") /* Media and VFP Feature Register 0 */
+ARMREG_READ_INLINE2(fpexc, "vmrs\t%0, fpexc") /* VFP Exception Register */
+ARMREG_WRITE_INLINE2(fpexc, "vmsr\tfpexc, %0") /* VFP Exception Register */
+ARMREG_READ_INLINE2(fpinst, "fmrx\t%0, fpinst") /* VFP Exception Instruction */
+ARMREG_WRITE_INLINE2(fpinst, "fmxr\tfpinst, %0") /* VFP Exception Instruction */
+ARMREG_READ_INLINE2(fpinst2, "fmrx\t%0, fpinst2") /* VFP Exception Instruction 2 */
+ARMREG_WRITE_INLINE2(fpinst2, "fmxr\tfpinst2, %0") /* VFP Exception Instruction 2 */
 
 /* cp15 c0 registers */
 ARMREG_READ_INLINE(midr, "p15,0,%0,c0,c0,0") /* Main ID Register */
 ARMREG_READ_INLINE(ctr, "p15,0,%0,c0,c0,1") /* Cache Type Register */
+ARMREG_READ_INLINE(tlbtr, "p15,0,%0,c0,c0,3") /* TLB Type Register */
 ARMREG_READ_INLINE(mpidr, "p15,0,%0,c0,c0,5") /* Multiprocess Affinity Register */
+ARMREG_READ_INLINE(revidr, "p15,0,%0,c0,c0,6") /* Revision ID Register */
 ARMREG_READ_INLINE(pfr0, "p15,0,%0,c0,c1,0") /* Processor Feature Register 0 */
 ARMREG_READ_INLINE(pfr1, "p15,0,%0,c0,c1,1") /* Processor Feature Register 1 */
 ARMREG_READ_INLINE(mmfr0, "p15,0,%0,c0,c1,4") /* Memory Model Feature Register 0 */
@@ -704,12 +940,14 @@ ARMREG_READ_INLINE(clidr, "p15,1,%0,c0,c0,1") /* Cache Level ID Register */
 ARMREG_READ_INLINE(csselr, "p15,2,%0,c0,c0,0") /* Cache Size Selection Register */
 ARMREG_WRITE_INLINE(csselr, "p15,2,%0,c0,c0,0") /* Cache Size Selection Register */
 /* cp15 c1 registers */
-ARMREG_READ_INLINE(sctrl, "p15,0,%0,c1,c0,0") /* System Control Register */
-ARMREG_WRITE_INLINE(sctrl, "p15,0,%0,c1,c0,0") /* System Control Register */
+ARMREG_READ_INLINE(sctlr, "p15,0,%0,c1,c0,0") /* System Control Register */
+ARMREG_WRITE_INLINE(sctlr, "p15,0,%0,c1,c0,0") /* System Control Register */
 ARMREG_READ_INLINE(auxctl, "p15,0,%0,c1,c0,1") /* Auxiliary Control Register */
 ARMREG_WRITE_INLINE(auxctl, "p15,0,%0,c1,c0,1") /* Auxiliary Control Register */
 ARMREG_READ_INLINE(cpacr, "p15,0,%0,c1,c0,2") /* Co-Processor Access Control Register */
 ARMREG_WRITE_INLINE(cpacr, "p15,0,%0,c1,c0,2") /* Co-Processor Access Control Register */
+ARMREG_READ_INLINE(scr, "p15,0,%0,c1,c1,0") /* Secure Configuration Register */
+ARMREG_READ_INLINE(nsacr, "p15,0,%0,c1,c1,2") /* Non-Secure Access Control Register */
 /* cp15 c2 registers */
 ARMREG_READ_INLINE(ttbr, "p15,0,%0,c2,c0,0") /* Translation Table Base Register 0 */
 ARMREG_WRITE_INLINE(ttbr, "p15,0,%0,c2,c0,0") /* Translation Table Base Register 0 */
@@ -717,6 +955,9 @@ ARMREG_READ_INLINE(ttbr1, "p15,0,%0,c2,c0,1") /* Translation Table Base Register
 ARMREG_WRITE_INLINE(ttbr1, "p15,0,%0,c2,c0,1") /* Translation Table Base Register 1 */
 ARMREG_READ_INLINE(ttbcr, "p15,0,%0,c2,c0,2") /* Translation Table Base Register */
 ARMREG_WRITE_INLINE(ttbcr, "p15,0,%0,c2,c0,2") /* Translation Table Base Register */
+/* cp15 c3 registers */
+ARMREG_READ_INLINE(dacr, "p15,0,%0,c3,c0,0") /* Domain Access Control Register */
+ARMREG_WRITE_INLINE(dacr, "p15,0,%0,c3,c0,0") /* Domain Access Control Register */
 /* cp15 c5 registers */
 ARMREG_READ_INLINE(dfsr, "p15,0,%0,c5,c0,0") /* Data Fault Status Register */
 ARMREG_READ_INLINE(ifsr, "p15,0,%0,c5,c0,1") /* Instruction Fault Status Register */
@@ -725,20 +966,24 @@ ARMREG_READ_INLINE(dfar, "p15,0,%0,c6,c0,0") /* Data Fault Address Register */
 ARMREG_READ_INLINE(ifar, "p15,0,%0,c6,c0,2") /* Instruction Fault Address Register */
 /* cp15 c7 registers */
 ARMREG_WRITE_INLINE(icialluis, "p15,0,%0,c7,c1,0") /* Instruction Inv All (IS) */
-ARMREG_WRITE_INLINE(bpiallis, "p15,0,%0,c7,c1,6") /* Branch Invalidate All (IS) */
+ARMREG_WRITE_INLINE(bpiallis, "p15,0,%0,c7,c1,6") /* Branch Predictor Invalidate All (IS) */
 ARMREG_READ_INLINE(par, "p15,0,%0,c7,c4,0") /* Physical Address Register */
 ARMREG_WRITE_INLINE(iciallu, "p15,0,%0,c7,c5,0") /* Instruction Invalidate All */
 ARMREG_WRITE_INLINE(icimvau, "p15,0,%0,c7,c5,1") /* Instruction Invalidate MVA */
 ARMREG_WRITE_INLINE(isb, "p15,0,%0,c7,c5,4") /* Instruction Synchronization Barrier */
-ARMREG_WRITE_INLINE(bpiall, "p15,0,%0,c5,c1,6") /* Breakpoint Invalidate All */
+ARMREG_WRITE_INLINE(bpiall, "p15,0,%0,c7,c5,6") /* Branch Predictor Invalidate All */
+ARMREG_WRITE_INLINE(bpimva, "p15,0,%0,c7,c5,7") /* Branch Predictor invalidate by MVA */
 ARMREG_WRITE_INLINE(dcimvac, "p15,0,%0,c7,c6,1") /* Data Invalidate MVA to PoC */
 ARMREG_WRITE_INLINE(dcisw, "p15,0,%0,c7,c6,2") /* Data Invalidate Set/Way */
 ARMREG_WRITE_INLINE(ats1cpr, "p15,0,%0,c7,c8,0") /* AddrTrans CurState PL1 Read */
+ARMREG_WRITE_INLINE(ats1cpw, "p15,0,%0,c7,c8,1") /* AddrTrans CurState PL1 Write */
+ARMREG_WRITE_INLINE(ats1cur, "p15,0,%0,c7,c8,2") /* AddrTrans CurState PL0 Read */
+ARMREG_WRITE_INLINE(ats1cuw, "p15,0,%0,c7,c8,3") /* AddrTrans CurState PL0 Write */
 ARMREG_WRITE_INLINE(dccmvac, "p15,0,%0,c7,c10,1") /* Data Clean MVA to PoC */
 ARMREG_WRITE_INLINE(dccsw, "p15,0,%0,c7,c10,2") /* Data Clean Set/Way */
 ARMREG_WRITE_INLINE(dsb, "p15,0,%0,c7,c10,4") /* Data Synchronization Barrier */
 ARMREG_WRITE_INLINE(dmb, "p15,0,%0,c7,c10,5") /* Data Memory Barrier */
-ARMREG_WRITE_INLINE(dccmvau, "p15,0,%0,c7,c14,1") /* Data Clean MVA to PoU */
+ARMREG_WRITE_INLINE(dccmvau, "p15,0,%0,c7,c11,1") /* Data Clean MVA to PoU */
 ARMREG_WRITE_INLINE(dccimvac, "p15,0,%0,c7,c14,1") /* Data Clean&Inv MVA to PoC */
 ARMREG_WRITE_INLINE(dccisw, "p15,0,%0,c7,c14,2") /* Data Clean&Inv Set/Way */
 /* cp15 c8 registers */
@@ -769,9 +1014,19 @@ ARMREG_READ_INLINE(pmccntr, "p15,0,%0,c9,c13,0") /* PMC Cycle Counter */
 ARMREG_WRITE_INLINE(pmccntr, "p15,0,%0,c9,c13,0") /* PMC Cycle Counter */
 ARMREG_READ_INLINE(pmuserenr, "p15,0,%0,c9,c14,0") /* PMC User Enable */
 ARMREG_WRITE_INLINE(pmuserenr, "p15,0,%0,c9,c14,0") /* PMC User Enable */
+ARMREG_READ_INLINE(l2ctrl, "p15,1,%0,c9,c0,2") /* A7/A15 L2 Control Register */
+/* cp10 c10 registers */
+ARMREG_READ_INLINE(prrr, "p15,0,%0,c10,c2,0") /* Primary Region Remap Register */
+ARMREG_WRITE_INLINE(prrr, "p15,0,%0,c10,c2,0") /* Primary Region Remap Register */
+ARMREG_READ_INLINE(nrrr, "p15,0,%0,c10,c2,1") /* Normal Region Remap Register */
+ARMREG_WRITE_INLINE(nrrr, "p15,0,%0,c10,c2,1") /* Normal Region Remap Register */
 /* cp15 c13 registers */
 ARMREG_READ_INLINE(contextidr, "p15,0,%0,c13,c0,1") /* Context ID Register */
 ARMREG_WRITE_INLINE(contextidr, "p15,0,%0,c13,c0,1") /* Context ID Register */
+ARMREG_READ_INLINE(tpidrurw, "p15,0,%0,c13,c0,2") /* User read-write Thread ID Register */
+ARMREG_WRITE_INLINE(tpidrurw, "p15,0,%0,c13,c0,2") /* User read-write Thread ID Register */
+ARMREG_READ_INLINE(tpidruro, "p15,0,%0,c13,c0,3") /* User read-only Thread ID Register */
+ARMREG_WRITE_INLINE(tpidruro, "p15,0,%0,c13,c0,3") /* User read-only Thread ID Register */
 ARMREG_READ_INLINE(tpidrprw, "p15,0,%0,c13,c0,4") /* PL1 only Thread ID Register */
 ARMREG_WRITE_INLINE(tpidrprw, "p15,0,%0,c13,c0,4") /* PL1 only Thread ID Register */
 /* cp14 c12 registers */
@@ -806,14 +1061,14 @@ ARMREG_WRITE_INLINE(pmcrv6, "p15,0,%0,c15,c12,0") /* PMC Control Register (armv6
 ARMREG_READ_INLINE(pmccntrv6, "p15,0,%0,c15,c12,1") /* PMC Cycle Counter (armv6) */
 ARMREG_WRITE_INLINE(pmccntrv6, "p15,0,%0,c15,c12,1") /* PMC Cycle Counter (armv6) */
 
+ARMREG_READ_INLINE(tlbdata0, "p15,3,%0,c15,c0,0") /* TLB Data Register 0 (cortex) */
+ARMREG_READ_INLINE(tlbdata1, "p15,3,%0,c15,c0,1") /* TLB Data Register 1 (cortex) */
+ARMREG_READ_INLINE(tlbdata2, "p15,3,%0,c15,c0,2") /* TLB Data Register 2 (cortex) */
+ARMREG_WRITE_INLINE(tlbdataop, "p15,3,%0,c15,c4,2") /* TLB Data Read Operation (cortex) */
+
+ARMREG_READ_INLINE(sheeva_xctrl, "p15,1,%0,c15,c1,0") /* Sheeva eXtra Control register */
+ARMREG_WRITE_INLINE(sheeva_xctrl, "p15,1,%0,c15,c1,0") /* Sheeva eXtra Control register */
+
 #endif /* !__ASSEMBLER__ */
 
-
-#define	MPIDR_31		0x80000000
-#define	MPIDR_U			0x40000000	// 1 = Uniprocessor
-#define	MPIDR_MT		0x01000000	// AFF0 for SMT
-#define	MPIDR_AFF2		0x00ff0000
-#define	MPIDR_AFF1		0x0000ff00
-#define	MPIDR_AFF0		0x000000ff
-
 #endif	/* _ARM_ARMREG_H */

sys/arch/arm/include/asm.h

@@ -1,4 +1,4 @@
-/*	$NetBSD: asm.h,v 1.25 2013/11/30 20:11:11 matt Exp $	*/
+/*	$NetBSD: asm.h,v 1.27 2014/03/04 15:27:58 matt Exp $	*/
 
 /*
  * Copyright (c) 1990 The Regents of the University of California.
@@ -34,8 +34,8 @@
  *	from: @(#)asm.h	5.5 (Berkeley) 5/7/91
  */
 
-#ifndef _ARM32_ASM_H_
-#define _ARM32_ASM_H_
+#ifndef _ARM_ASM_H_
+#define _ARM_ASM_H_
 
 #include <arm/cdefs.h>
 
@@ -103,7 +103,6 @@
 #define	ARM_ENTRY_NP(y)		_ARM_ENTRY(_C_LABEL(y))
 #define	THUMB_ENTRY(y)		_THUMB_ENTRY(_C_LABEL(y)); _PROF_PROLOGUE
 #define	THUMB_ENTRY_NP(y)	_THUMB_ENTRY(_C_LABEL(y))
-#define	END(y)			_END(_C_LABEL(y))
 #define	ASENTRY(y)		_ENTRY(_ASM_LABEL(y)); _PROF_PROLOGUE
 #define	ASENTRY_NP(y)		_ENTRY(_ASM_LABEL(y))
 #define	ASEND(y)		_END(_ASM_LABEL(y))

sys/arch/arm/include/bootconfig.h

@@ -1,4 +1,4 @@
-/*	$NetBSD: bootconfig.h,v 1.6 2012/08/31 23:59:52 matt Exp $	*/
+/*	$NetBSD: bootconfig.h,v 1.7 2015/01/06 00:43:21 jmcneill Exp $	*/
 
 /*
  * Copyright (c) 1994 Mark Brinicombe.
@@ -42,6 +42,7 @@
 #define BOOTOPT_TYPE_INT		2
 #define BOOTOPT_TYPE_BININT		3
 #define BOOTOPT_TYPE_HEXINT		4
+#define BOOTOPT_TYPE_MACADDR		5
 #define BOOTOPT_TYPE_MASK		7
 
 struct boot_physmem {

sys/arch/arm/include/bswap.h

@@ -1,11 +1,15 @@
-/*      $NetBSD: bswap.h,v 1.4 2006/01/31 07:49:18 dsl Exp $      */
+/*      $NetBSD: bswap.h,v 1.6 2014/01/29 01:36:43 matt Exp $      */
 
-#ifndef _MACHINE_BSWAP_H_
-#define	_MACHINE_BSWAP_H_
+#ifndef _ARM_BSWAP_H_
+#define	_ARM_BSWAP_H_
 
+#ifdef __aarch64__
+#include <aarch64/byte_swap.h>
+#else
 #include <arm/byte_swap.h>
+#endif
 
 #define __BSWAP_RENAME
 #include <sys/bswap.h>
 
-#endif /* !_MACHINE_BSWAP_H_ */
+#endif /* !_ARM_BSWAP_H_ */

sys/arch/arm/include/bus_defs.h

@@ -1,4 +1,4 @@
-/*	$NetBSD: bus_defs.h,v 1.9 2013/02/16 06:49:59 matt Exp $	*/
+/*	$NetBSD: bus_defs.h,v 1.10 2014/01/29 00:42:15 matt Exp $	*/
 
 /*-
  * Copyright (c) 1996, 1997, 1998, 2001 The NetBSD Foundation, Inc.
@@ -61,8 +61,8 @@
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#ifndef _ARM32_BUS_DEFS_H_
-#define _ARM32_BUS_DEFS_H_
+#ifndef _ARM_BUS_DEFS_H_
+#define _ARM_BUS_DEFS_H_
 
 #if defined(_KERNEL_OPT)
 #include "opt_arm_bus_space.h"
@@ -500,4 +500,4 @@ struct arm32_bus_dma_cookie {
 #endif /* _ARM32_BUS_DMA_PRIVATE */
 #define	_BUS_DMA_MIGHT_NEED_BOUNCE	0x01	/* may need bounce buffers */
 
-#endif /* _ARM32_BUS_DEFS_H_ */
+#endif /* _ARM_BUS_DEFS_H_ */

sys/arch/arm/include/bus_funcs.h

@@ -1,4 +1,4 @@
-/*	$NetBSD: bus_funcs.h,v 1.5 2013/01/17 01:32:02 matt Exp $	*/
+/*	$NetBSD: bus_funcs.h,v 1.6 2014/01/29 00:42:15 matt Exp $	*/
 
 /*-
  * Copyright (c) 1996, 1997, 1998, 2001 The NetBSD Foundation, Inc.
@@ -61,8 +61,8 @@
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#ifndef _ARM32_BUS_FUNCS_H_
-#define _ARM32_BUS_FUNCS_H_
+#ifndef _ARM_BUS_FUNCS_H_
+#define _ARM_BUS_FUNCS_H_
 
 #ifdef _KERNEL_OPT
 #include "opt_cputypes.h"
@@ -692,4 +692,4 @@ void 	_bus_dmatag_destroy(bus_dma_tag_t);
 
 #endif /* _ARM32_BUS_DMA_PRIVATE */
 
-#endif /* _ARM32_BUS_FUNCS_H_ */
+#endif /* _ARM_BUS_FUNCS_H_ */

sys/arch/arm/include/cdefs.h

@@ -1,11 +1,22 @@
-/*	$NetBSD: cdefs.h,v 1.9 2013/08/17 00:21:47 matt Exp $	*/
+/*	$NetBSD: cdefs.h,v 1.15 2014/06/23 03:40:57 christos Exp $	*/
 
 #ifndef	_ARM_CDEFS_H_
 #define	_ARM_CDEFS_H_
 
-#if defined (__ARM_ARCH_7__) || defined (__ARM_ARCH_7A__) || \
-    defined (__ARM_ARCH_7R__) || defined (__ARM_ARCH_7M__) || \
-    defined (__ARM_ARCH_7EM__) /* 7R, 7M, 7EM are for non MMU arms */
+#ifndef __lint__
+#if (__GNUC__ == 4 && __GNUC_MINOR__ < 1) || __GNUC__ < 4
+#error GCC 4.1 or compatible required.
+#endif
+#endif
+
+#if defined (__ARM_ARCH_8A__)
+#define _ARM_ARCH_8		/* ARMv8 64-bit in AARCH32 */
+#endif
+
+#if defined (_ARM_ARCH_8) || defined (__ARM_ARCH_7__) || \
+    defined (__ARM_ARCH_7A__) || defined (__ARM_ARCH_7R__) || \
+    defined (__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__)
+	/* 7R, 7M, 7EM are for non MMU arms */
 #define _ARM_ARCH_7
 #endif
 
@@ -40,8 +51,10 @@
 #define	_ARM_ARCH_DWORD_OK
 #endif
 
-#ifdef __ARM_EABI__
-#define __ALIGNBYTES		(8 - 1)
+#if defined(__ARM_PCS_AAPCS64)
+#define __ALIGNBYTES		(sizeof(__int128_t) - 1)
+#elif defined(__ARM_EABI__)
+#define __ALIGNBYTES		(sizeof(long long) - 1)
 #else
 #define __ALIGNBYTES		(sizeof(int) - 1)
 #endif

sys/arch/arm/include/cpu.h

@@ -128,13 +128,16 @@ extern int cpu_fpu_present;
 /*
  * Per-CPU information.  For now we assume one CPU.
  */
+#ifdef _KERNEL
 static inline int curcpl(void);
 static inline void set_curcpl(int);
 static inline void cpu_dosoftints(void);
+#endif
 
 #ifdef _KMEMUSER
 #include <sys/intr.h>
 #endif
+#include <sys/atomic.h>
 #include <sys/cpu_data.h>
 #include <sys/device_if.h>
 #include <sys/evcnt.h>
@@ -148,20 +151,29 @@ struct cpu_info {
 	uint32_t ci_arm_cpurev;		/* CPU revision */
 	uint32_t ci_ctrl;		/* The CPU control register */
 	int ci_cpl;			/* current processor level (spl) */
-	int ci_astpending;		/* */
+	volatile int ci_astpending;	/* */
 	int ci_want_resched;		/* resched() was called */
 	int ci_intr_depth;		/* */
 	struct cpu_softc *ci_softc;	/* platform softc */
 	lwp_t *ci_softlwps[SOFTINT_COUNT];
 	volatile uint32_t ci_softints;
 	lwp_t *ci_curlwp;		/* current lwp */
+	lwp_t *ci_lastlwp;		/* last lwp */
 	struct evcnt ci_arm700bugcount;
 	int32_t ci_mtx_count;
 	int ci_mtx_oldspl;
 	register_t ci_undefsave[3];
 	uint32_t ci_vfp_id;
 	uint64_t ci_lastintr;
+	struct pmap_tlb_info *ci_tlb_info;
+	struct pmap *ci_pmap_lastuser;
+	struct pmap *ci_pmap_cur;
+	tlb_asid_t ci_pmap_asid_cur;
+	struct trapframe *ci_ddb_regs;
 	struct evcnt ci_abt_evs[16];
+	struct evcnt ci_und_ev;
+	struct evcnt ci_und_cp15_ev;
+	struct evcnt ci_vfp_evs[3];
 #if defined(MP_CPU_INFO_MEMBERS)
 	MP_CPU_INFO_MEMBERS
 #endif
@@ -169,7 +181,15 @@ struct cpu_info {
 
 extern struct cpu_info cpu_info_store;
 
-#if defined(TPIDRPRW_IS_CURLWP)
+struct lwp *arm_curlwp(void);
+struct cpu_info *arm_curcpu(void);
+
+#if defined(_MODULE)
+
+#define	curlwp		arm_curlwp()
+#define curcpu()	arm_curcpu()
+
+#elif defined(TPIDRPRW_IS_CURLWP)
 static inline struct lwp *
 _curlwp(void)
 {
@@ -182,13 +202,16 @@ _curlwp_set(struct lwp *l)
 	armreg_tpidrprw_write((uintptr_t)l);
 }
 
-#define	curlwp		(_curlwp())
-static inline struct cpu_info *
-curcpu(void)
-{
-	return curlwp->l_cpu;
-}
+// Also in <sys/lwp.h> but also here if this was included before <sys/lwp.h> 
+static inline struct cpu_info *lwp_getcpu(struct lwp *);
+
+#define	curlwp		_curlwp()
+// curcpu() expands into two instructions: a mrc and a ldr
+#define	curcpu()	lwp_getcpu(_curlwp())
 #elif defined(TPIDRPRW_IS_CURCPU)
+#ifdef __HAVE_PREEMPTION
+#error __HAVE_PREEMPTION requires TPIDRPRW_IS_CURLWP
+#endif
 static inline struct cpu_info *
 curcpu(void)
 {
@@ -196,8 +219,10 @@ curcpu(void)
 }
 #elif !defined(MULTIPROCESSOR)
 #define	curcpu()	(&cpu_info_store)
+#elif !defined(__HAVE_PREEMPTION)
+#error MULTIPROCESSOR && !__HAVE_PREEMPTION requires TPIDRPRW_IS_CURCPU or TPIDRPRW_IS_CURLWP
 #else
-#error MULTIPROCESSOR requires TPIDRPRW_IS_CURLWP or TPIDRPRW_IS_CURCPU
+#error MULTIPROCESSOR && __HAVE_PREEMPTION requires TPIDRPRW_IS_CURLWP
 #endif /* !TPIDRPRW_IS_CURCPU && !TPIDRPRW_IS_CURLWP */
 
 #ifndef curlwp
@@ -207,9 +232,9 @@ curcpu(void)
 #define CPU_INFO_ITERATOR	int
 #if defined(MULTIPROCESSOR)
 extern struct cpu_info *cpu_info[];
-#define cpu_number()	(curcpu()->ci_cpuid)
+#define cpu_number()		(curcpu()->ci_index)
 void cpu_boot_secondary_processors(void);
-#define CPU_IS_PRIMARY(ci)	((ci)->ci_cpuid == 0)
+#define CPU_IS_PRIMARY(ci)	((ci)->ci_index == 0)
 #define CPU_INFO_FOREACH(cii, ci)			\
 	cii = 0, ci = cpu_info[0]; cii < ncpu && (ci = cpu_info[cii]) != NULL; cii++
 #else 
@@ -257,21 +282,29 @@ void	cpu_proc_fork(struct proc *, struct proc *);
  * Scheduling glue
  */
 
-#define setsoftast()			(curcpu()->ci_astpending = 1)
+#ifdef __HAVE_PREEMPTION
+#define setsoftast(ci)		atomic_or_uint(&(ci)->ci_astpending, __BIT(0))
+#else
+#define setsoftast(ci)		((ci)->ci_astpending = __BIT(0))
+#endif
 
 /*
  * Notify the current process (p) that it has a signal pending,
  * process as soon as possible.
  */
 
-#define cpu_signotify(l)		setsoftast()
+#define cpu_signotify(l)		setsoftast((l)->l_cpu)
 
 /*
  * Give a profiling tick to the current process when the user profiling
  * buffer pages are invalid.  On the i386, request an ast to send us
  * through trap(), marking the proc as needing a profiling tick.
  */
-#define	cpu_need_proftick(l)	((l)->l_pflag |= LP_OWEUPC, setsoftast())
+#define	cpu_need_proftick(l)	((l)->l_pflag |= LP_OWEUPC, \
+				 setsoftast((l)->l_cpu))
+
+/* for preeemption. */
+void	cpu_set_curpri(int);
 
 /*
  * We've already preallocated the stack for the idlelwps for additional CPUs.  

sys/arch/arm/include/cpu_counter.h

@@ -1,4 +1,4 @@
-/*	$NetBSD: cpu_counter.h,v 1.2 2012/08/29 18:45:40 matt Exp $	*/
+/*	$NetBSD: cpu_counter.h,v 1.3 2014/02/26 01:54:10 matt Exp $	*/
 
 /*-
  * Copyright (c) 2012 The NetBSD Foundation, Inc.
@@ -54,7 +54,7 @@ static __inline uint32_t
 cpu_counter32(void)
 {
 #if defined(CPU_CORTEX) && defined(CPU_ARM11)
-	const bool cortex_p = CPU_ID_CORTEX_P(curcpu()->ci_cpu_id);
+	const bool cortex_p = CPU_ID_CORTEX_P(curcpu()->ci_arm_cpuid);
 #elif defined(CPU_CORTEX)
 	const bool cortex_p = true;
 #elif defined(CPU_ARM11)

sys/arch/arm/include/cpuconf.h

@@ -1,4 +1,4 @@
-/*	$NetBSD: cpuconf.h,v 1.21 2013/05/19 15:51:10 rkujawa Exp $	*/
+/*	$NetBSD: cpuconf.h,v 1.25 2015/07/08 15:18:04 skrll Exp $	*/
 
 /*
  * Copyright (c) 2002 Wasabi Systems, Inc.
@@ -80,10 +80,7 @@
 			 defined(CPU_SA1110) +				\
 			 defined(CPU_FA526) +				\
 			 defined(CPU_IXP12X0) +				\
-			 defined(CPU_XSCALE_80200) +			\
-			 defined(CPU_XSCALE_80321) +			\
-			 defined(__CPU_XSCALE_PXA2XX) +			\
-			 defined(CPU_XSCALE_IXP425)) +			\
+			 defined(CPU_XSCALE) +				\
 			 defined(CPU_SHEEVA))
 #else
 #define	CPU_NTYPES	2
@@ -118,15 +115,13 @@
 
 #if !defined(_KERNEL_OPT) ||						\
     (defined(CPU_ARM9E) || defined(CPU_ARM10) ||			\
-     defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) ||		\
-     defined(__CPU_XSCALE_PXA2XX) || defined(CPU_XSCALE_IXP425)) ||	\
-     defined(CPU_SHEEVA)
+     defined(CPU_XSCALE) || defined(CPU_SHEEVA))
 #define	ARM_ARCH_5	1
 #else
 #define	ARM_ARCH_5	0
 #endif
 
-#if defined(CPU_ARM11) || defined(CPU_CORTEXA8) || defined(CPU_ARM11MPCORE)
+#if defined(CPU_ARM11) || defined(CPU_ARM11MPCORE)
 #define ARM_ARCH_6	1
 #else
 #define ARM_ARCH_6	0
@@ -205,27 +200,21 @@
 #endif
 
 #if !defined(_KERNEL_OPT) ||						\
-    (defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) ||		\
-     defined(__CPU_XSCALE_PXA2XX) || defined(CPU_XSCALE_IXP425))
+    defined(CPU_XSCALE)
 #define	ARM_MMU_XSCALE		1
 #else
 #define	ARM_MMU_XSCALE		0
 #endif
 
 #if !defined(_KERNEL_OPT) ||						\
-	defined(CPU_ARM11MPCORE) && defined(ARM11MPCORE_COMPAT_MMU) ||	\
-	defined(CPU_ARM1136) || \
-	defined(CPU_ARM1176) || \
-	defined(CPU_ARM11) && \
-	!defined(CPU_CORTEX) && \
-	!defined(CPU_ARM11MPCORE) && !defined(CPU_PJ4B)
+	(defined(CPU_ARM11) && defined(ARM11_COMPAT_MMU))
 #define	ARM_MMU_V6C		1
 #else
 #define	ARM_MMU_V6C		0
 #endif
 
 #if !defined(_KERNEL_OPT) ||						\
-	defined(CPU_ARM11MPCORE) && !defined(ARM11MPCORE_COMPAT_MMU)
+	(defined(CPU_ARM11) && !defined(ARM11_COMPAT_MMU))
 #define	ARM_MMU_V6N		1
 #else
 #define	ARM_MMU_V6N		0
@@ -233,14 +222,26 @@
 
 #define	ARM_MMU_V6	(ARM_MMU_V6C + ARM_MMU_V6N)
 
-
 #if !defined(_KERNEL_OPT) ||						\
-	 defined(CPU_CORTEX) || defined(CPU_PJ4B)
+	 defined(CPU_ARMV7)
 #define	ARM_MMU_V7		1
 #else
 #define	ARM_MMU_V7		0
 #endif
 
+/*
+ * Can we use the ASID support in armv6+ MMUs?
+ */
+#if !defined(_LOCORE)
+#define	ARM_MMU_EXTENDED	((ARM_MMU_MEMC + ARM_MMU_GENERIC	\
+				  + ARM_MMU_SA1 + ARM_MMU_XSCALE	\
+				  + ARM_MMU_V6C) == 0			\
+				 && (ARM_MMU_V6N + ARM_MMU_V7) > 0)
+#if ARM_MMU_EXTENDED == 0
+#undef ARM_MMU_EXTENDED
+#endif
+#endif
+
 #define	ARM_NMMUS		(ARM_MMU_MEMC + ARM_MMU_GENERIC +	\
 				 ARM_MMU_SA1 + ARM_MMU_XSCALE +		\
 				 ARM_MMU_V6N + ARM_MMU_V6C + ARM_MMU_V7)

sys/arch/arm/include/cpufunc.h

@@ -39,8 +39,8 @@
  * Prototypes for cpu, mmu and tlb related functions.
  */
 
-#ifndef _ARM32_CPUFUNC_H_
-#define _ARM32_CPUFUNC_H_
+#ifndef _ARM_CPUFUNC_H_
+#define _ARM_CPUFUNC_H_
 
 #ifdef _KERNEL
 
@@ -48,6 +48,7 @@
 #include <arm/armreg.h>
 #include <arm/cpuconf.h>
 #include <arm/armreg.h>
+#include <arm/cpufunc_proto.h>
 
 struct cpu_functions {
 
@@ -60,18 +61,22 @@ struct cpu_functions {
 
 	u_int	(*cf_control)		(u_int, u_int);
 	void	(*cf_domains)		(u_int);
+#if defined(ARM_MMU_EXTENDED)
+	void	(*cf_setttb)		(u_int, tlb_asid_t);
+#else
 	void	(*cf_setttb)		(u_int, bool);
+#endif
 	u_int	(*cf_faultstatus)	(void);
 	u_int	(*cf_faultaddress)	(void);
 
 	/* TLB functions */
 
 	void	(*cf_tlb_flushID)	(void);
-	void	(*cf_tlb_flushID_SE)	(u_int);
+	void	(*cf_tlb_flushID_SE)	(vaddr_t);
 	void	(*cf_tlb_flushI)	(void);
-	void	(*cf_tlb_flushI_SE)	(u_int);
+	void	(*cf_tlb_flushI_SE)	(vaddr_t);
 	void	(*cf_tlb_flushD)	(void);
-	void	(*cf_tlb_flushD_SE)	(u_int);
+	void	(*cf_tlb_flushD_SE)	(vaddr_t);
 
 	/*
 	 * Cache operations:
@@ -152,7 +157,11 @@ struct cpu_functions {
 	int	(*cf_dataabt_fixup)	(void *);
 	int	(*cf_prefetchabt_fixup)	(void *);
 
+#if defined(ARM_MMU_EXTENDED)
+	void	(*cf_context_switch)	(u_int, tlb_asid_t);
+#else
 	void	(*cf_context_switch)	(u_int);
+#endif
 
 	void	(*cf_setup)		(char *);
 };
@@ -221,383 +230,15 @@ void	cpufunc_domains		(u_int);
 u_int	cpufunc_faultstatus	(void);
 u_int	cpufunc_faultaddress	(void);
 
-#if defined(CPU_ARM2) || defined(CPU_ARM250) || defined(CPU_ARM3)
-void	arm3_cache_flush	(void);
-#endif	/* CPU_ARM2 || CPU_ARM250 || CPU_ARM3 */
-
-#ifdef CPU_ARM2
-u_int	arm2_id			(void);
-#endif /* CPU_ARM2 */
-
-#ifdef CPU_ARM250
-u_int	arm250_id		(void);
-#endif
-
-#ifdef CPU_ARM3
-u_int	arm3_control		(u_int, u_int);
-#endif	/* CPU_ARM3 */
-
-#if defined(CPU_ARM6) || defined(CPU_ARM7)
-void	arm67_setttb		(u_int, bool);
-void	arm67_tlb_flush		(void);
-void	arm67_tlb_purge		(u_int);
-void	arm67_cache_flush	(void);
-void	arm67_context_switch	(u_int);
-#endif	/* CPU_ARM6 || CPU_ARM7 */
-
-#ifdef CPU_ARM6
-void	arm6_setup		(char *);
-#endif	/* CPU_ARM6 */
-
-#ifdef CPU_ARM7
-void	arm7_setup		(char *);
-#endif	/* CPU_ARM7 */
-
-#ifdef CPU_ARM7TDMI
-int	arm7_dataabt_fixup	(void *);
-void	arm7tdmi_setup		(char *);
-void	arm7tdmi_setttb		(u_int, bool);
-void	arm7tdmi_tlb_flushID	(void);
-void	arm7tdmi_tlb_flushID_SE	(u_int);
-void	arm7tdmi_cache_flushID	(void);
-void	arm7tdmi_context_switch	(u_int);
-#endif /* CPU_ARM7TDMI */
-
-#ifdef CPU_ARM8
-void	arm8_setttb		(u_int, bool);
-void	arm8_tlb_flushID	(void);
-void	arm8_tlb_flushID_SE	(u_int);
-void	arm8_cache_flushID	(void);
-void	arm8_cache_flushID_E	(u_int);
-void	arm8_cache_cleanID	(void);
-void	arm8_cache_cleanID_E	(u_int);
-void	arm8_cache_purgeID	(void);
-void	arm8_cache_purgeID_E	(u_int entry);
-
-void	arm8_cache_syncI	(void);
-void	arm8_cache_cleanID_rng	(vaddr_t, vsize_t);
-void	arm8_cache_cleanD_rng	(vaddr_t, vsize_t);
-void	arm8_cache_purgeID_rng	(vaddr_t, vsize_t);
-void	arm8_cache_purgeD_rng	(vaddr_t, vsize_t);
-void	arm8_cache_syncI_rng	(vaddr_t, vsize_t);
-
-void	arm8_context_switch	(u_int);
-
-void	arm8_setup		(char *);
-
-u_int	arm8_clock_config	(u_int, u_int);
-#endif
-
-#ifdef CPU_FA526
-void	fa526_setup		(char *);
-void	fa526_setttb		(u_int, bool);
-void	fa526_context_switch	(u_int);
-void	fa526_cpu_sleep		(int);
-void	fa526_tlb_flushI_SE	(u_int);
-void	fa526_tlb_flushID_SE	(u_int);
-void	fa526_flush_prefetchbuf	(void);
-void	fa526_flush_brnchtgt_E	(u_int);
-
-void	fa526_icache_sync_all	(void);
-void	fa526_icache_sync_range(vaddr_t, vsize_t);
-void	fa526_dcache_wbinv_all	(void);
-void	fa526_dcache_wbinv_range(vaddr_t, vsize_t);
-void	fa526_dcache_inv_range	(vaddr_t, vsize_t);
-void	fa526_dcache_wb_range	(vaddr_t, vsize_t);
-void	fa526_idcache_wbinv_all(void);
-void	fa526_idcache_wbinv_range(vaddr_t, vsize_t);
-#endif
-
-#ifdef CPU_SA110
-void	sa110_setup		(char *);
-void	sa110_context_switch	(u_int);
-#endif	/* CPU_SA110 */
-
-#if defined(CPU_SA1100) || defined(CPU_SA1110)
-void	sa11x0_drain_readbuf	(void);
-
-void	sa11x0_context_switch	(u_int);
-void	sa11x0_cpu_sleep	(int);
-
-void	sa11x0_setup		(char *);
-#endif
-
-#if defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110)
-void	sa1_setttb		(u_int, bool);
-
-void	sa1_tlb_flushID_SE	(u_int);
-
-void	sa1_cache_flushID	(void);
-void	sa1_cache_flushI	(void);
-void	sa1_cache_flushD	(void);
-void	sa1_cache_flushD_SE	(u_int);
-
-void	sa1_cache_cleanID	(void);
-void	sa1_cache_cleanD	(void);
-void	sa1_cache_cleanD_E	(u_int);
-
-void	sa1_cache_purgeID	(void);
-void	sa1_cache_purgeID_E	(u_int);
-void	sa1_cache_purgeD	(void);
-void	sa1_cache_purgeD_E	(u_int);
-
-void	sa1_cache_syncI		(void);
-void	sa1_cache_cleanID_rng	(vaddr_t, vsize_t);
-void	sa1_cache_cleanD_rng	(vaddr_t, vsize_t);
-void	sa1_cache_purgeID_rng	(vaddr_t, vsize_t);
-void	sa1_cache_purgeD_rng	(vaddr_t, vsize_t);
-void	sa1_cache_syncI_rng	(vaddr_t, vsize_t);
-
-#endif
-
-#ifdef CPU_ARM9
-void	arm9_setttb		(u_int, bool);
-
-void	arm9_tlb_flushID_SE	(u_int);
-
-void	arm9_icache_sync_all	(void);
-void	arm9_icache_sync_range	(vaddr_t, vsize_t);
-
-void	arm9_dcache_wbinv_all	(void);
-void	arm9_dcache_wbinv_range (vaddr_t, vsize_t);
-void	arm9_dcache_inv_range	(vaddr_t, vsize_t);
-void	arm9_dcache_wb_range	(vaddr_t, vsize_t);
-
-void	arm9_idcache_wbinv_all	(void);
-void	arm9_idcache_wbinv_range (vaddr_t, vsize_t);
-
-void	arm9_context_switch	(u_int);
-
-void	arm9_setup		(char *);
-
-extern unsigned arm9_dcache_sets_max;
-extern unsigned arm9_dcache_sets_inc;
-extern unsigned arm9_dcache_index_max;
-extern unsigned arm9_dcache_index_inc;
-#endif
-
-#if defined(CPU_ARM9E) || defined(CPU_ARM10) || defined(CPU_SHEEVA)
-void	arm10_tlb_flushID_SE	(u_int);
-void	arm10_tlb_flushI_SE	(u_int);
-
-void	arm10_context_switch	(u_int);
-
-void	arm10_setup		(char *);
-#endif
-
-#if defined(CPU_ARM9E) || defined (CPU_ARM10) || defined(CPU_SHEEVA)
-void	armv5_ec_setttb			(u_int, bool);
-
-void	armv5_ec_icache_sync_all	(void);
-void	armv5_ec_icache_sync_range	(vaddr_t, vsize_t);
-
-void	armv5_ec_dcache_wbinv_all	(void);
-void	armv5_ec_dcache_wbinv_range	(vaddr_t, vsize_t);
-void	armv5_ec_dcache_inv_range	(vaddr_t, vsize_t);
-void	armv5_ec_dcache_wb_range	(vaddr_t, vsize_t);
-
-void	armv5_ec_idcache_wbinv_all	(void);
-void	armv5_ec_idcache_wbinv_range	(vaddr_t, vsize_t);
-#endif
-
-#if defined (CPU_ARM10) || defined (CPU_ARM11MPCORE)
-void	armv5_setttb		(u_int, bool);
-
-void	armv5_icache_sync_all	(void);
-void	armv5_icache_sync_range	(vaddr_t, vsize_t);
-
-void	armv5_dcache_wbinv_all	(void);
-void	armv5_dcache_wbinv_range (vaddr_t, vsize_t);
-void	armv5_dcache_inv_range	(vaddr_t, vsize_t);
-void	armv5_dcache_wb_range	(vaddr_t, vsize_t);
-
-void	armv5_idcache_wbinv_all	(void);
-void	armv5_idcache_wbinv_range (vaddr_t, vsize_t);
-
-extern unsigned armv5_dcache_sets_max;
-extern unsigned armv5_dcache_sets_inc;
-extern unsigned armv5_dcache_index_max;
-extern unsigned armv5_dcache_index_inc;
-#endif
-
-#if defined(CPU_ARM11MPCORE)
-void	arm11mpcore_setup		(char *);
-#endif
-
-#if defined(CPU_ARM11) || defined(CPU_CORTEX)
-void	arm11_setttb		(u_int, bool);
-
-void	arm11_tlb_flushID_SE	(u_int);
-void	arm11_tlb_flushI_SE	(u_int);
-
-void	arm11_context_switch	(u_int);
-
-void	arm11_cpu_sleep		(int);
-void	arm11_setup		(char *string);
-void	arm11_tlb_flushID	(void);
-void	arm11_tlb_flushI	(void);
-void	arm11_tlb_flushD	(void);
-void	arm11_tlb_flushD_SE	(u_int va);
-
-void	armv11_dcache_wbinv_all (void);
-void	armv11_idcache_wbinv_all(void);
-
-void	arm11_drain_writebuf	(void);
-void	arm11_sleep		(int);
-
-void	armv6_setttb		(u_int, bool);
-
-void	armv6_icache_sync_all	(void);
-void	armv6_icache_sync_range	(vaddr_t, vsize_t);
-
-void	armv6_dcache_wbinv_all	(void);
-void	armv6_dcache_wbinv_range (vaddr_t, vsize_t);
-void	armv6_dcache_inv_range	(vaddr_t, vsize_t);
-void	armv6_dcache_wb_range	(vaddr_t, vsize_t);
-
-void	armv6_idcache_wbinv_all	(void);
-void	armv6_idcache_wbinv_range (vaddr_t, vsize_t);
-#endif
-
-#if defined(CPU_CORTEX)
-void	armv7_setttb(u_int, bool);
-
-void	armv7_icache_sync_range(vaddr_t, vsize_t);
-void	armv7_dcache_wb_range(vaddr_t, vsize_t);
-void	armv7_dcache_wbinv_range(vaddr_t, vsize_t);
-void	armv7_dcache_inv_range(vaddr_t, vsize_t);
-void	armv7_idcache_wbinv_range(vaddr_t, vsize_t);
-
-void	armv7_icache_sync_all(void);
-void	armv7_cpu_sleep(int);
-void	armv7_context_switch(u_int);
-void	armv7_tlb_flushID_SE(u_int);
-void	armv7_drain_writebuf(void);
-void	armv7_setup(char *string);
-#endif
-
-#if defined(CPU_CORTEX) || defined(CPU_PJ4B)
-void 	armv7_dcache_wbinv_all (void);
-void	armv7_idcache_wbinv_all(void);
-#endif
-
-#if defined(CPU_PJ4B)
-void	pj4b_setttb(u_int, bool);
-void	pj4b_tlb_flushID(void);
-void	pj4b_tlb_flushID_SE(u_int);
-
-void	pj4b_icache_sync_range(vm_offset_t, vm_size_t);
-void	pj4b_idcache_wbinv_range(vm_offset_t, vm_size_t);
-void	pj4b_dcache_wbinv_range(vm_offset_t, vm_size_t);
-void	pj4b_dcache_inv_range(vm_offset_t, vm_size_t);
-void	pj4b_dcache_wb_range(vm_offset_t, vm_size_t);
-
-void	pj4b_drain_writebuf(void);
-void	pj4b_drain_readbuf(void);
-void	pj4b_flush_brnchtgt_all(void);
-void	pj4b_flush_brnchtgt_va(u_int);
-void	pj4b_context_switch(u_int);
-void	pj4b_sleep(int);
-
-void	pj4bv7_setup(char *string);
-void	pj4b_config(void);
-
-#endif /* CPU_PJ4B */
-
-#if defined(CPU_ARM1136) || defined(CPU_ARM1176)
-void	arm11x6_setttb			(u_int, bool);
-void	arm11x6_idcache_wbinv_all	(void);
-void	arm11x6_dcache_wbinv_all	(void);
-void	arm11x6_icache_sync_all		(void);
-void	arm11x6_flush_prefetchbuf	(void);
-void	arm11x6_icache_sync_range	(vaddr_t, vsize_t);
-void	arm11x6_idcache_wbinv_range	(vaddr_t, vsize_t);
-void	arm11x6_setup			(char *string);
-void	arm11x6_sleep			(int);	/* no ref. for errata */
-#endif
-#if defined(CPU_ARM1136)
-void	arm1136_sleep_rev0		(int);	/* for errata 336501 */
-#endif
-
-
-#if defined(CPU_ARM9) || defined(CPU_ARM9E) || defined(CPU_ARM10) || \
-    defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) || \
-    defined(CPU_FA526) || \
-    defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
-    defined(__CPU_XSCALE_PXA2XX) || defined(CPU_XSCALE_IXP425) || \
-    defined(CPU_CORTEX) || defined(CPU_SHEEVA)
-
-void	armv4_tlb_flushID	(void);
-void	armv4_tlb_flushI	(void);
-void	armv4_tlb_flushD	(void);
-void	armv4_tlb_flushD_SE	(u_int);
-
-void	armv4_drain_writebuf	(void);
-#endif
-
-#if defined(CPU_IXP12X0)
-void	ixp12x0_drain_readbuf	(void);
-void	ixp12x0_context_switch	(u_int);
-void	ixp12x0_setup		(char *);
-#endif
-
-#if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
-    defined(__CPU_XSCALE_PXA2XX) || defined(CPU_XSCALE_IXP425) || \
-    defined(CPU_CORTEX)
-
-void	xscale_cpwait		(void);
-#define	cpu_cpwait()		cpufuncs.cf_cpwait()
-
-void	xscale_cpu_sleep	(int);
-
-u_int	xscale_control		(u_int, u_int);
-
-void	xscale_setttb		(u_int, bool);
-
-void	xscale_tlb_flushID_SE	(u_int);
-
-void	xscale_cache_flushID	(void);
-void	xscale_cache_flushI	(void);
-void	xscale_cache_flushD	(void);
-void	xscale_cache_flushD_SE	(u_int);
-
-void	xscale_cache_cleanID	(void);
-void	xscale_cache_cleanD	(void);
-void	xscale_cache_cleanD_E	(u_int);
-
-void	xscale_cache_clean_minidata (void);
-
-void	xscale_cache_purgeID	(void);
-void	xscale_cache_purgeID_E	(u_int);
-void	xscale_cache_purgeD	(void);
-void	xscale_cache_purgeD_E	(u_int);
-
-void	xscale_cache_syncI	(void);
-void	xscale_cache_cleanID_rng (vaddr_t, vsize_t);
-void	xscale_cache_cleanD_rng	(vaddr_t, vsize_t);
-void	xscale_cache_purgeID_rng (vaddr_t, vsize_t);
-void	xscale_cache_purgeD_rng	(vaddr_t, vsize_t);
-void	xscale_cache_syncI_rng	(vaddr_t, vsize_t);
-void	xscale_cache_flushD_rng	(vaddr_t, vsize_t);
-
-void	xscale_context_switch	(u_int);
-
-void	xscale_setup		(char *);
-#endif	/* CPU_XSCALE_80200 || CPU_XSCALE_80321 || __CPU_XSCALE_PXA2XX || CPU_XSCALE_IXP425 || CPU_CORTEX */
-
-#if defined(CPU_SHEEVA)
-void	sheeva_dcache_wbinv_range (vaddr_t, vsize_t);
-void	sheeva_dcache_inv_range	(vaddr_t, vsize_t);
-void	sheeva_dcache_wb_range	(vaddr_t, vsize_t);
-void	sheeva_idcache_wbinv_range (vaddr_t, vsize_t);
-void	sheeva_setup(char *);
-void	sheeva_cpu_sleep(int);
-#endif
-
 #define tlb_flush	cpu_tlb_flushID
 #define setttb		cpu_setttb
 #define drain_writebuf	cpu_drain_writebuf
 
+
+#if defined(CPU_XSCALE)
+#define	cpu_cpwait()		cpufuncs.cf_cpwait()
+#endif
+
 #ifndef cpu_cpwait
 #define	cpu_cpwait()
 #endif
@@ -646,16 +287,32 @@ disable_interrupts(uint32_t mask)
 static __inline uint32_t
 enable_interrupts(uint32_t mask)
 {
-	uint32_t	ret, tmp;
+	uint32_t	ret;
 	mask &= (I32_bit | F32_bit);
 
-	__asm volatile(
-		"mrs     %0, cpsr\n"	/* Get the CPSR */
-		"bic	 %1, %0, %2\n"	/* Clear bits */
-		"msr     cpsr_c, %1\n"	/* Set the control field of CPSR */
-	: "=&r" (ret), "=&r" (tmp)
-	: "r" (mask)
-	: "memory");
+	/* Get the CPSR */
+	__asm __volatile("mrs\t%0, cpsr\n" : "=r"(ret));
+#ifdef _ARM_ARCH_6
+	if (__builtin_constant_p(mask)) {
+		switch (mask) {
+		case I32_bit | F32_bit:
+			__asm __volatile("cpsie\tif");
+			break;
+		case I32_bit:
+			__asm __volatile("cpsie\ti");
+			break;
+		case F32_bit:
+			__asm __volatile("cpsie\tf");
+			break;
+		default:
+			break;
+		}
+		return ret;
+	}
+#endif /* _ARM_ARCH_6 */
+
+	/* Set the control field of CPSR */
+	__asm volatile("msr\tcpsr_c, %0" :: "r"(ret & ~mask));
 
 	return ret;
 }
@@ -737,21 +394,30 @@ void cpu_reset		(void) __dead;
 /*
  * Cache info variables.
  */
+#define	CACHE_TYPE_VIVT		0
+#define	CACHE_TYPE_xxPT		1
+#define	CACHE_TYPE_VIPT		1
+#define	CACHE_TYPE_PIxx		2
+#define	CACHE_TYPE_PIPT		3
 
 /* PRIMARY CACHE VARIABLES */
 struct arm_cache_info {
 	u_int icache_size;
 	u_int icache_line_size;
 	u_int icache_ways;
+	u_int icache_way_size;
 	u_int icache_sets;
 
 	u_int dcache_size;
 	u_int dcache_line_size;
 	u_int dcache_ways;
+	u_int dcache_way_size;
 	u_int dcache_sets;
 
-	u_int cache_type;
+	uint8_t cache_type;
 	bool cache_unified;
+	uint8_t icache_type;
+	uint8_t dcache_type;
 };
 
 extern u_int arm_cache_prefer_mask;
@@ -779,6 +445,6 @@ u_int get_stackptr	(u_int);
 
 #endif /* _KERNEL || _KMEMUSER */
 
-#endif	/* _ARM32_CPUFUNC_H_ */
+#endif	/* _ARM_CPUFUNC_H_ */
 
 /* End of cpufunc.h */

sys/arch/arm/include/cpufunc_proto.h

@@ -0,0 +1,424 @@
+/*	cpufunc.h,v 1.40.22.4 2007/11/08 10:59:33 matt Exp	*/
+
+/*
+ * Copyright (c) 1997 Mark Brinicombe.
+ * Copyright (c) 1997 Causality Limited
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by Causality Limited.
+ * 4. The name of Causality Limited may not be used to endorse or promote
+ *    products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * RiscBSD kernel project
+ *
+ * cpufunc.h
+ *
+ * Prototypes for cpu, mmu and tlb related functions.
+ */
+
+#ifndef _ARM_CPUFUNC_PROTO_H_
+#define _ARM_CPUFUNC_PROTO_H_
+
+#ifdef _KERNEL
+
+#include <sys/types.h>
+#include <arm/armreg.h>
+#include <arm/cpuconf.h>
+
+#if defined(CPU_ARM2) || defined(CPU_ARM250) || defined(CPU_ARM3)
+void	arm3_cache_flush	(void);
+#endif	/* CPU_ARM2 || CPU_ARM250 || CPU_ARM3 */
+
+#ifdef CPU_ARM2
+u_int	arm2_id			(void);
+#endif /* CPU_ARM2 */
+
+#ifdef CPU_ARM250
+u_int	arm250_id		(void);
+#endif
+
+#ifdef CPU_ARM3
+u_int	arm3_control		(u_int, u_int);
+#endif	/* CPU_ARM3 */
+
+#if defined(CPU_ARM6) || defined(CPU_ARM7)
+void	arm67_setttb		(u_int, bool);
+void	arm67_tlb_flush		(void);
+void	arm67_tlb_purge		(vaddr_t);
+void	arm67_cache_flush	(void);
+void	arm67_context_switch	(u_int);
+#endif	/* CPU_ARM6 || CPU_ARM7 */
+
+#ifdef CPU_ARM6
+void	arm6_setup		(char *);
+#endif	/* CPU_ARM6 */
+
+#ifdef CPU_ARM7
+void	arm7_setup		(char *);
+#endif	/* CPU_ARM7 */
+
+#ifdef CPU_ARM7TDMI
+int	arm7_dataabt_fixup	(void *);
+void	arm7tdmi_setup		(char *);
+void	arm7tdmi_setttb		(u_int, bool);
+void	arm7tdmi_tlb_flushID	(void);
+void	arm7tdmi_tlb_flushID_SE	(vaddr_t);
+void	arm7tdmi_cache_flushID	(void);
+void	arm7tdmi_context_switch	(u_int);
+#endif /* CPU_ARM7TDMI */
+
+#ifdef CPU_ARM8
+void	arm8_setttb		(u_int, bool);
+void	arm8_tlb_flushID	(void);
+void	arm8_tlb_flushID_SE	(vaddr_t);
+void	arm8_cache_flushID	(void);
+void	arm8_cache_flushID_E	(u_int);
+void	arm8_cache_cleanID	(void);
+void	arm8_cache_cleanID_E	(u_int);
+void	arm8_cache_purgeID	(void);
+void	arm8_cache_purgeID_E	(u_int entry);
+
+void	arm8_cache_syncI	(void);
+void	arm8_cache_cleanID_rng	(vaddr_t, vsize_t);
+void	arm8_cache_cleanD_rng	(vaddr_t, vsize_t);
+void	arm8_cache_purgeID_rng	(vaddr_t, vsize_t);
+void	arm8_cache_purgeD_rng	(vaddr_t, vsize_t);
+void	arm8_cache_syncI_rng	(vaddr_t, vsize_t);
+
+void	arm8_context_switch	(u_int);
+
+void	arm8_setup		(char *);
+
+u_int	arm8_clock_config	(u_int, u_int);
+#endif
+
+#ifdef CPU_FA526
+void	fa526_setup		(char *);
+void	fa526_setttb		(u_int, bool);
+void	fa526_context_switch	(u_int);
+void	fa526_cpu_sleep		(int);
+void	fa526_tlb_flushI_SE	(vaddr_t);
+void	fa526_tlb_flushID_SE	(vaddr_t);
+void	fa526_flush_prefetchbuf	(void);
+void	fa526_flush_brnchtgt_E	(u_int);
+
+void	fa526_icache_sync_all	(void);
+void	fa526_icache_sync_range(vaddr_t, vsize_t);
+void	fa526_dcache_wbinv_all	(void);
+void	fa526_dcache_wbinv_range(vaddr_t, vsize_t);
+void	fa526_dcache_inv_range	(vaddr_t, vsize_t);
+void	fa526_dcache_wb_range	(vaddr_t, vsize_t);
+void	fa526_idcache_wbinv_all(void);
+void	fa526_idcache_wbinv_range(vaddr_t, vsize_t);
+#endif
+
+#ifdef CPU_SA110
+void	sa110_setup		(char *);
+void	sa110_context_switch	(u_int);
+#endif	/* CPU_SA110 */
+
+#if defined(CPU_SA1100) || defined(CPU_SA1110)
+void	sa11x0_drain_readbuf	(void);
+
+void	sa11x0_context_switch	(u_int);
+void	sa11x0_cpu_sleep	(int);
+
+void	sa11x0_setup		(char *);
+#endif
+
+#if defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110)
+void	sa1_setttb		(u_int, bool);
+
+void	sa1_tlb_flushID_SE	(vaddr_t);
+
+void	sa1_cache_flushID	(void);
+void	sa1_cache_flushI	(void);
+void	sa1_cache_flushD	(void);
+void	sa1_cache_flushD_SE	(vaddr_t);
+
+void	sa1_cache_cleanID	(void);
+void	sa1_cache_cleanD	(void);
+void	sa1_cache_cleanD_E	(u_int);
+
+void	sa1_cache_purgeID	(void);
+void	sa1_cache_purgeID_E	(u_int);
+void	sa1_cache_purgeD	(void);
+void	sa1_cache_purgeD_E	(u_int);
+
+void	sa1_cache_syncI		(void);
+void	sa1_cache_cleanID_rng	(vaddr_t, vsize_t);
+void	sa1_cache_cleanD_rng	(vaddr_t, vsize_t);
+void	sa1_cache_purgeID_rng	(vaddr_t, vsize_t);
+void	sa1_cache_purgeD_rng	(vaddr_t, vsize_t);
+void	sa1_cache_syncI_rng	(vaddr_t, vsize_t);
+
+#endif
+
+#ifdef CPU_ARM9
+void	arm9_setttb		(u_int, bool);
+
+void	arm9_tlb_flushID_SE	(vaddr_t);
+
+void	arm9_icache_sync_all	(void);
+void	arm9_icache_sync_range	(vaddr_t, vsize_t);
+
+void	arm9_dcache_wbinv_all	(void);
+void	arm9_dcache_wbinv_range (vaddr_t, vsize_t);
+void	arm9_dcache_inv_range	(vaddr_t, vsize_t);
+void	arm9_dcache_wb_range	(vaddr_t, vsize_t);
+
+void	arm9_idcache_wbinv_all	(void);
+void	arm9_idcache_wbinv_range (vaddr_t, vsize_t);
+
+void	arm9_context_switch	(u_int);
+
+void	arm9_setup		(char *);
+
+extern unsigned arm9_dcache_sets_max;
+extern unsigned arm9_dcache_sets_inc;
+extern unsigned arm9_dcache_index_max;
+extern unsigned arm9_dcache_index_inc;
+#endif
+
+#if defined(CPU_ARM9E) || defined(CPU_ARM10) || defined(CPU_SHEEVA)
+void	arm10_tlb_flushID_SE	(vaddr_t);
+void	arm10_tlb_flushI_SE	(vaddr_t);
+
+void	arm10_context_switch	(u_int);
+
+void	arm10_setup		(char *);
+#endif
+
+#if defined(CPU_ARM9E) || defined (CPU_ARM10) || defined(CPU_SHEEVA)
+void	armv5_ec_setttb			(u_int, bool);
+
+void	armv5_ec_icache_sync_all	(void);
+void	armv5_ec_icache_sync_range	(vaddr_t, vsize_t);
+
+void	armv5_ec_dcache_wbinv_all	(void);
+void	armv5_ec_dcache_wbinv_range	(vaddr_t, vsize_t);
+void	armv5_ec_dcache_inv_range	(vaddr_t, vsize_t);
+void	armv5_ec_dcache_wb_range	(vaddr_t, vsize_t);
+
+void	armv5_ec_idcache_wbinv_all	(void);
+void	armv5_ec_idcache_wbinv_range	(vaddr_t, vsize_t);
+#endif
+
+#if defined (CPU_ARM10) || defined (CPU_ARM11MPCORE)
+void	armv5_setttb		(u_int, bool);
+
+void	armv5_icache_sync_all	(void);
+void	armv5_icache_sync_range	(vaddr_t, vsize_t);
+
+void	armv5_dcache_wbinv_all	(void);
+void	armv5_dcache_wbinv_range (vaddr_t, vsize_t);
+void	armv5_dcache_inv_range	(vaddr_t, vsize_t);
+void	armv5_dcache_wb_range	(vaddr_t, vsize_t);
+
+void	armv5_idcache_wbinv_all	(void);
+void	armv5_idcache_wbinv_range (vaddr_t, vsize_t);
+
+extern unsigned armv5_dcache_sets_max;
+extern unsigned armv5_dcache_sets_inc;
+extern unsigned armv5_dcache_index_max;
+extern unsigned armv5_dcache_index_inc;
+#endif
+
+#if defined(CPU_ARM11MPCORE)
+void	arm11mpcore_setup		(char *);
+#endif
+
+#if defined(CPU_ARM11)
+#if defined(ARM_MMU_EXTENDED)
+void	arm11_setttb		(u_int, tlb_asid_t);
+void	arm11_context_switch	(u_int, tlb_asid_t);
+#else
+void	arm11_setttb		(u_int, bool);
+void	arm11_context_switch	(u_int);
+#endif
+
+void	arm11_cpu_sleep		(int);
+void	arm11_setup		(char *string);
+void	arm11_tlb_flushID	(void);
+void	arm11_tlb_flushI	(void);
+void	arm11_tlb_flushD	(void);
+void	arm11_tlb_flushID_SE	(vaddr_t);
+void	arm11_tlb_flushI_SE	(vaddr_t);
+void	arm11_tlb_flushD_SE	(vaddr_t);
+
+void	armv11_dcache_wbinv_all (void);
+void	armv11_idcache_wbinv_all(void);
+
+void	arm11_drain_writebuf	(void);
+void	arm11_sleep		(int);
+
+void	armv6_setttb		(u_int, bool);
+
+void	armv6_icache_sync_all	(void);
+void	armv6_icache_sync_range	(vaddr_t, vsize_t);
+
+void	armv6_dcache_wbinv_all	(void);
+void	armv6_dcache_wbinv_range (vaddr_t, vsize_t);
+void	armv6_dcache_inv_range	(vaddr_t, vsize_t);
+void	armv6_dcache_wb_range	(vaddr_t, vsize_t);
+
+void	armv6_idcache_wbinv_all	(void);
+void	armv6_idcache_wbinv_range (vaddr_t, vsize_t);
+#endif
+
+#if defined(CPU_ARMV7)
+#if defined(ARM_MMU_EXTENDED)
+void	armv7_setttb(u_int, tlb_asid_t);
+void	armv7_context_switch(u_int, tlb_asid_t);
+#else
+void	armv7_setttb(u_int, bool);
+void	armv7_context_switch(u_int);
+#endif
+
+void	armv7_icache_sync_range(vaddr_t, vsize_t);
+void	armv7_icache_sync_all(void);
+
+void	armv7_dcache_inv_range(vaddr_t, vsize_t);
+void	armv7_dcache_wb_range(vaddr_t, vsize_t);
+void	armv7_dcache_wbinv_range(vaddr_t, vsize_t);
+void 	armv7_dcache_wbinv_all(void);
+
+void	armv7_idcache_wbinv_range(vaddr_t, vsize_t);
+void	armv7_idcache_wbinv_all(void);
+
+void	armv7_tlb_flushID(void);
+void	armv7_tlb_flushI(void);
+void	armv7_tlb_flushD(void);
+
+void	armv7_tlb_flushID_SE(vaddr_t);
+void	armv7_tlb_flushI_SE(vaddr_t);
+void	armv7_tlb_flushD_SE(vaddr_t);
+
+void	armv7_cpu_sleep(int);
+void	armv7_drain_writebuf(void);
+void	armv7_setup(char *string);
+#endif /* CPU_ARMV7 */
+
+#if defined(CPU_PJ4B)
+void	pj4b_cpu_sleep(int);
+void	pj4bv7_setup(char *string);
+void	pj4b_config(void);
+void	pj4b_io_coherency_barrier(vaddr_t, paddr_t, vsize_t);
+void	pj4b_dcache_cfu_inv_range(vaddr_t, vsize_t);
+void	pj4b_dcache_cfu_wb_range(vaddr_t, vsize_t);
+void	pj4b_dcache_cfu_wbinv_range(vaddr_t, vsize_t);
+#endif /* CPU_PJ4B */
+
+#if defined(CPU_ARM1136) || defined(CPU_ARM1176)
+void	arm11x6_idcache_wbinv_all	(void);
+void	arm11x6_dcache_wbinv_all	(void);
+void	arm11x6_icache_sync_all		(void);
+void	arm11x6_flush_prefetchbuf	(void);
+void	arm11x6_icache_sync_range	(vaddr_t, vsize_t);
+void	arm11x6_idcache_wbinv_range	(vaddr_t, vsize_t);
+void	arm11x6_setup			(char *string);
+void	arm11x6_sleep			(int);	/* no ref. for errata */
+#endif
+#if defined(CPU_ARM1136)
+void	arm1136_sleep_rev0		(int);	/* for errata 336501 */
+#endif
+
+
+#if defined(CPU_ARM9) || defined(CPU_ARM9E) || defined(CPU_ARM10) || \
+    defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) || \
+    defined(CPU_FA526) || defined(CPU_XSCALE) || defined(CPU_SHEEVA)
+
+void	armv4_tlb_flushID	(void);
+void	armv4_tlb_flushI	(void);
+void	armv4_tlb_flushD	(void);
+void	armv4_tlb_flushD_SE	(vaddr_t);
+
+void	armv4_drain_writebuf	(void);
+#endif
+
+#if defined(CPU_IXP12X0)
+void	ixp12x0_drain_readbuf	(void);
+void	ixp12x0_context_switch	(u_int);
+void	ixp12x0_setup		(char *);
+#endif
+
+#if defined(CPU_XSCALE)
+void	xscale_cpwait		(void);
+
+void	xscale_cpu_sleep	(int);
+
+u_int	xscale_control		(u_int, u_int);
+
+void	xscale_setttb		(u_int, bool);
+
+void	xscale_tlb_flushID_SE	(vaddr_t);
+
+void	xscale_cache_flushID	(void);
+void	xscale_cache_flushI	(void);
+void	xscale_cache_flushD	(void);
+void	xscale_cache_flushD_SE	(vaddr_t);
+
+void	xscale_cache_cleanID	(void);
+void	xscale_cache_cleanD	(void);
+void	xscale_cache_cleanD_E	(u_int);
+
+void	xscale_cache_clean_minidata (void);
+
+void	xscale_cache_purgeID	(void);
+void	xscale_cache_purgeID_E	(u_int);
+void	xscale_cache_purgeD	(void);
+void	xscale_cache_purgeD_E	(u_int);
+
+void	xscale_cache_syncI	(void);
+void	xscale_cache_cleanID_rng (vaddr_t, vsize_t);
+void	xscale_cache_cleanD_rng	(vaddr_t, vsize_t);
+void	xscale_cache_purgeID_rng (vaddr_t, vsize_t);
+void	xscale_cache_purgeD_rng	(vaddr_t, vsize_t);
+void	xscale_cache_syncI_rng	(vaddr_t, vsize_t);
+void	xscale_cache_flushD_rng	(vaddr_t, vsize_t);
+
+void	xscale_context_switch	(u_int);
+
+void	xscale_setup		(char *);
+#endif	/* CPU_XSCALE */
+
+#if defined(CPU_SHEEVA)
+void	sheeva_dcache_wbinv_range (vaddr_t, vsize_t);
+void	sheeva_dcache_inv_range	(vaddr_t, vsize_t);
+void	sheeva_dcache_wb_range	(vaddr_t, vsize_t);
+void	sheeva_idcache_wbinv_range (vaddr_t, vsize_t);
+void	sheeva_setup(char *);
+void	sheeva_cpu_sleep(int);
+
+void	sheeva_sdcache_inv_range(vaddr_t, paddr_t, vsize_t);
+void	sheeva_sdcache_wb_range(vaddr_t, paddr_t, vsize_t);
+void	sheeva_sdcache_wbinv_range(vaddr_t, paddr_t, vsize_t);
+void	sheeva_sdcache_wbinv_all(void);
+#endif
+
+#endif /* _KERNEL */
+
+#endif	/* _ARM_CPUFUNC_PROTO_H_ */

sys/arch/arm/include/db_machdep.h

@@ -1,4 +1,4 @@
-/*	$NetBSD: db_machdep.h,v 1.18 2012/02/16 02:26:35 christos Exp $	*/
+/*	$NetBSD: db_machdep.h,v 1.22 2014/09/13 18:08:38 matt Exp $	*/
 
 /*
  * Copyright (c) 1996 Scott K Stevens
@@ -48,8 +48,14 @@ typedef	long		db_expr_t;	/* expression - signed */
 
 typedef trapframe_t db_regs_t;
 
-extern db_regs_t	ddb_regs;	/* register state */
+#ifndef MULTIPROCESSOR
+extern db_regs_t ddb_regs;	/* register state */
 #define	DDB_REGS	(&ddb_regs)
+#else
+extern db_regs_t *ddb_regp;
+#define DDB_REGS	(ddb_regp)
+#define ddb_regs	(*ddb_regp)
+#endif
 
 #ifdef __PROG26
 #define	PC_REGS(regs)	((regs)->tf_r15 & R15_PC)
@@ -99,8 +105,8 @@ extern db_regs_t	ddb_regs;	/* register state */
 #define inst_load(ins)		(0)
 #define inst_store(ins)		(0)
 #define inst_unconditional_flow_transfer(ins)	\
-	((((ins) & INSN_COND_MASK) == INSN_COND_AL) && \
-	 (inst_branch(ins) || inst_call(ins) || inst_return(ins)))
+	(__SHIFTOUT((ins), INSN_COND_MASK) == INSN_COND_AL \
+	 && (inst_branch(ins) || inst_call(ins) || inst_return(ins)))
 
 #define getreg_val			(0)
 #define next_instr_address(pc, bd)	((bd) ? (pc) : ((pc) + INSN_SIZE))
@@ -112,7 +118,7 @@ extern db_regs_t	ddb_regs;	/* register state */
 u_int branch_taken(u_int insn, u_int pc, db_regs_t *db_regs);
 int kdb_trap(int, db_regs_t *);
 void db_machine_init(void);
-int db_validate_address(vm_offset_t addr);
+int db_validate_address(vaddr_t addr);
 
 #define DB_ELF_SYMBOLS
 #define DB_ELFSIZE 32
@@ -127,4 +133,9 @@ typedef register_t	kgdb_reg_t;
 #define KGDB_REGNUM_SPSR	16 + 8*3 + 1
 #define KGDB_BUFLEN		1024
 
+/*
+ * MP stuff
+ */
+extern volatile struct cpu_info *db_onproc;
+extern volatile struct cpu_info *db_newcpu;
 #endif	/* _ARM_DB_MACHDEP_H_ */

sys/arch/arm/include/elf_machdep.h

@@ -1,4 +1,4 @@
-/*	$NetBSD: elf_machdep.h,v 1.14 2013/10/29 00:45:00 matt Exp $	*/
+/*	$NetBSD: elf_machdep.h,v 1.17 2014/02/25 19:20:09 matt Exp $	*/
 
 #ifndef _ARM_ELF_MACHDEP_H_
 #define _ARM_ELF_MACHDEP_H_
@@ -127,133 +127,6 @@
 #define R_ARM_RPC24		254
 #define R_ARM_RBASE		255
 
-#define	R_AARCH64_ABS64			257	/* S + A */
-#define	R_AARCH64_ABS32			258	/* S + A */
-#define	R_AARCH64_ABS16			259	/* S + A */
-#define	R_AARCH64_PREL64		260	/* S + A - P */
-#define	R_AARCH64_PREL32		261	/* S + A - P */
-#define	R_AARCH64_PREL16		262	/* S + A - P */
-#define R_AARCH64_MOVW_UABS_G0		263	/* S + A [bits 0..15] */
-#define R_AARCH64_MOVW_UABS_G0_NC	264	/* S + A [bits 0..15] */
-#define R_AARCH64_MOVW_UABS_G1		265	/* S + A [bits 16..31] */
-#define R_AARCH64_MOVW_UABS_G1_NC	266	/* S + A [bits 16..31] */
-#define R_AARCH64_MOVW_UABS_G2		267	/* S + A [bits 32..47] */
-#define R_AARCH64_MOVW_UABS_G2_NC	268	/* S + A [bits 32..47] */
-#define R_AARCH64_MOVW_UABS_G3		269	/* S + A [bits 48..63] */
-#define R_AARCH64_MOVW_SABS_G0		270	/* S + A [bits 0..15] */
-#define R_AARCH64_MOVW_SABS_G1		271	/* S + A [bits 16..31] */
-#define R_AARCH64_MOVW_SABS_G2		272	/* S + A [bits 32..47] */
-#define	R_AARCH64_LD_PREL_LO19		273	/* S + A - P */
-#define	R_AARCH64_ADR_PREL_LO21		274	/* S + A - P */
-#define	R_AARCH64_ADR_PREL_PG_HI21	275	/* Page(S + A) - Page(P) */
-#define	R_AARCH64_ADR_PREL_PG_HI21_NC	276	/* Page(S + A) - Page(P) */
-#define	R_AARCH64_ADR_ABS_LO21_NC	277	/* S + A */
-#define	R_AARCH64_LDST8_ABS_LO12_NC	278	/* S + A */
-#define R_AARCH_TSTBR14			279	/* S + A - P */
-#define R_AARCH_CONDBR19		281	/* S + A - P */
-#define R_AARCH_JUMP26			282	/* S + A - P */
-#define R_AARCH_CALL26			283	/* S + A - P */
-#define R_AARCH_LDST16_ABS_LO12_NC	284	/* S + A */
-#define R_AARCH_LDST32_ABS_LO12_NC	285	/* S + A */
-#define R_AARCH_LDST64_ABS_LO12_NC	286	/* S + A */
-#define R_AARCH64_MOVW_PREL_G0		287	/* S + A - P */
-#define R_AARCH64_MOVW_PREL_G0_NC	288	/* S + A - P */
-#define R_AARCH64_MOVW_PREL_G1		289	/* S + A - P */
-#define R_AARCH64_MOVW_PREL_G1_NC	290	/* S + A - P */
-#define R_AARCH64_MOVW_PREL_G2		291	/* S + A - P */
-#define R_AARCH64_MOVW_PREL_G2_NC	292	/* S + A - P */
-#define R_AARCH64_MOVW_PREL_G3		293	/* S + A - P */
-
-#define R_AARCH64_LDST128_ABS_LO12_NC	299	/* S + A */
-#define R_AARCH64_MOVW_GOTOFF_G0	300	/* G(GDAT(S + A)) - GOT */
-#define R_AARCH64_MOVW_GOTOFF_G0_NC	301	/* G(GDAT(S + A)) - GOT */
-#define R_AARCH64_MOVW_GOTOFF_G1	302	/* G(GDAT(S + A)) - GOT */
-#define R_AARCH64_MOVW_GOTOFF_G1_NC	303	/* G(GDAT(S + A)) - GOT */
-#define R_AARCH64_MOVW_GOTOFF_G2	304	/* G(GDAT(S + A)) - GOT */
-#define R_AARCH64_MOVW_GOTOFF_G2_NC	305	/* G(GDAT(S + A)) - GOT */
-#define R_AARCH64_MOVW_GOTOFF_G3	306	/* G(GDAT(S + A)) - GOT */
-#define R_AARCH64_GOTREL64		307	/* S + A - GOT */
-#define R_AARCH64_GOTREL32		308	/* S + A - GOT */
-#define R_AARCH64_GOT_LD_PREL19		309	/* G(GDAT(S + A)) - P */
-#define R_AARCH64_LD64_GOTOFF_LO15	310	/* G(GDAT(S + A)) - GOT */
-#define R_AARCH64_ADR_GOT_PAGE		311	/* Page(G(GDAT(S + A))) - Page(GOT) */
-#define R_AARCH64_LD64_GOT_LO12_NC	312	/* G(GDAT(S + A)) */
-#define R_AARCH64_LD64_GOTPAGE_LO15	313	/* G(GDAT(S + A)) - Page(GOT) */
-
-#define R_AARCH64_TLSGD_ADR_PREL21		512	/* G(GTLSIDX(S,A)) - P */
-#define R_AARCH64_TLSGD_ADR_PAGE21		513	/* Page(G(GTLSIDX(S,A))) - Page(P) */
-#define R_AARCH64_TLSGD_ADD_LO12_NC		514	/* G(GTLSIDX(S,A)) */
-#define R_AARCH64_TLSGD_MOVW_G1			515	/* G(GTLSIDX(S,A)) - GOT */
-#define R_AARCH64_TLSGD_MOVW_G0_NV		516	/* G(GTLSIDX(S,A)) - GOT */
-#define R_AARCH64_TLSLD_ADR_PREL21		517	/* G(GLDM(S,A)) - P */
-#define R_AARCH64_TLSLD_ADR_PAGE21		518	/* Page(G(GLDM(S))) - Page(P) */
-#define R_AARCH64_TLSLD_ADD_LO12_NC		519	/* G(GLDM(S)) */
-#define R_AARCH64_TLSLD_MOVW_G1			520	/* G(GLDM(S)) - GOT */
-#define R_AARCH64_TLSLD_MOVW_G0_NC		521	/* G(GLDM(S)) - GOT */
-#define R_AARCH64_TLSLD_LD_PREL21		522	/* G(GLDM(S)) - P */
-#define R_AARCH64_TLSLD_MOVW_DTPREL_G2		523	/* DTPREL(S+A) */
-#define R_AARCH64_TLSLD_MOVW_DTPREL_G1		524	/* DTPREL(S+A) */
-#define R_AARCH64_TLSLD_MOVW_DTPREL_G1_NC	525	/* DTPREL(S+A) */
-#define R_AARCH64_TLSLD_MOVW_DTPREL_G0		526	/* DTPREL(S+A) */
-#define R_AARCH64_TLSLD_MOVW_DTPREL_G0_NC	528	/* DTPREL(S+A) */
-#define R_AARCH64_TLSLD_ADD_DTPREL_HI12		528	/* DTPREL(S+A) */
-#define R_AARCH64_TLSLD_ADD_DTPREL_HI12		528	/* DTPREL(S+A) */
-#define R_AARCH64_TLSLD_ADD_DTPREL_LO12		529	/* DTPREL(S+A) */
-#define R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC	530	/* DTPREL(S+A) */
-#define R_AARCH64_TLSLD_LDST8_DTPREL_LO12	531	/* DTPREL(S+A) */
-#define R_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC	532	/* DTPREL(S+A) */
-#define R_AARCH64_TLSLD_LDST16_DTPREL_LO12	533	/* DTPREL(S+A) */
-#define R_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC	534	/* DTPREL(S+A) */
-#define R_AARCH64_TLSLD_LDST32_DTPREL_LO12	535	/* DTPREL(S+A) */
-#define R_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC	536	/* DTPREL(S+A) */
-#define R_AARCH64_TLSLD_LDST64_DTPREL_LO12	537	/* DTPREL(S+A) */
-#define R_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC	538	/* DTPREL(S+A) */
-#define R_AARCH64_TLSIE_MOVW_GOTTPREL_G1	539	/* G(GTPREL(S+A)) - GOT */
-#define R_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC	540	/* G(GTPREL(S+A)) - GOT */
-#define R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21	541	/* Page(G(GTPREL(S+A))) - Page(P) */
-#define R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC	542	/* G(GTPREL(S+A)) */
-#define R_AARCH64_TLSIE_LD_GOTTPREL_PREL19	543	/* G(GTPREL(S+A)) - P */
-#define R_AARCH64_TLSLE_MOVW_TPREL_G2	544	/* TPREL(S+A) */
-#define R_AARCH64_MOVW_TPREL_G1		545	/* TPREL(S+A) */
-#define R_AARCH64_MOVW_TPREL_G1_NC	546	/* TPREL(S+A) */
-#define R_AARCH64_MOVW_TPREL_G0		547	/* TPREL(S+A) */
-#define R_AARCH64_MOVW_TPREL_G0_NC	548	/* TPREL(S+A) */
-#define R_AARCH64_ADD_TPREL_HI12	549	/* TPREL(S+A) */
-#define R_AARCH64_ADD_TPREL_LO12	550	/* TPREL(S+A) */
-#define R_AARCH64_ADD_TPREL_LO12_NC	551	/* TPREL(S+A) */
-#define R_AARCH64_LDST8_TPREL_LO12	552	/* TPREL(S+A) */
-#define R_AARCH64_LDST8_TPREL_LO12_NC	553	/* TPREL(S+A) */
-#define R_AARCH64_LDST16_TPREL_LO12	554	/* TPREL(S+A) */
-#define R_AARCH64_LDST16_TPREL_LO12_NC	555	/* TPREL(S+A) */
-#define R_AARCH64_LDST32_TPREL_LO12	556	/* TPREL(S+A) */
-#define R_AARCH64_LDST32_TPREL_LO12_NC	557	/* TPREL(S+A) */
-#define R_AARCH64_LDST64_TPREL_LO12	558	/* TPREL(S+A) */
-#define R_AARCH64_LDST64_TPREL_LO12_NC	559	/* TPREL(S+A) */
-#define R_AARCH64_TLSDESC_LD_PREL19	560	/* G(GTLSDESC(S+A)) - P */
-#define R_AARCH64_TLSDESC_LD_PREL21	561	/* G(GTLSDESC(S+A)) - P */
-#define R_AARCH64_TLSDESC_LD_PAGE21	562	/* Page(G(GTLSDESC(S+A))) - Page(P) */
-#define R_AARCH64_TLSDESC_LD64_LO12	563	/* G(GTLSDESC(S+A)) */
-#define R_AARCH64_TLSDESC_ADD_LO12	564	/* G(GTLSDESC(S+A)) */
-#define R_AARCH64_TLSDESC_OFF_G1	565	/* G(GTLSDESC(S+A)) - GOT */
-#define R_AARCH64_TLSDESC_OFF_G0_NC	566	/* G(GTLSDESC(S+A)) - GOT */
-#define R_AARCH64_TLSDESC_LDR		567	/* */
-#define R_AARCH64_TLSDESC_ADD		568	/* */
-#define R_AARCH64_TLSDESC_CALL		569	/* */
-#define R_AARCH64_TLSLE_LDST128_TPREL_LO12	570	/* TPREL(S+A) */
-#define R_AARCH64_TLSLE_LDST128_TPREL_LO12_NC	571	/* TPREL(S+A) */
-#define R_AARCH64_TLSLD_LDST128_DTPREL_LO12	572	/* DTPREL(S+A) */
-#define R_AARCH64_TLSLD_LDST128_DTPREL_LO12_NC	572	/* DTPREL(S+A) */
-
-#define R_AARCH64_COPY		1024
-#define R_AARCH64_GLOB_DAT	1025	/* S + A */
-#define R_AARCH64_JUMP_SLOT	1026	/* S + A */
-#define R_AARCH64_RELATIVE	1027	/* Delta(S) + A */
-#define R_AARCH64_TLS_DTPREL64	1028	/* DTPREL(S+A) */
-#define R_AARCH64_TLS_DTPMOD64	1029	/* LBM(S) */
-#define R_AARCH64_TLS_TPREL64	1030	/* TPREL(S+A) */
-#define R_AARCH64_TLSDESC	1031	/* TLSDESC(S+A) */
-#define R_AARCH64_IRELATIVE	1032	/* Indirect(Delta(S) + A) */
-
 #define R_TYPE(name)		__CONCAT(R_ARM_,name)
 
 /* Processor specific program header flags */
@@ -263,27 +136,25 @@
 
 /* Processor specific program header types */
 #define PT_ARM_EXIDX		(PT_LOPROC + 1)
-#define PT_AARCH64_ARCHEXT	(PT_LOPROC + 0)
-#define PT_AARCH64_UNWIND	(PT_LOPROC + 1)
 
 /* Processor specific section header flags */
 #define SHF_ENTRYSECT		0x10000000
 #define SHF_COMDEF		0x80000000
 
-#define SHT_AARCH64_ATTRIBUTES	(SHT_LOPROC + 3)
-
 /* Processor specific symbol types */
 #define STT_ARM_TFUNC		STT_LOPROC
 
 #ifdef _KERNEL
 #ifdef ELFSIZE
 #define	ELF_MD_PROBE_FUNC	ELFNAME2(arm_netbsd,probe)
+#define	ELF_MD_COREDUMP_SETUP	ELFNAME2(arm_netbsd,coredump_setup)
 #endif
 
 struct exec_package;
 
 int arm_netbsd_elf32_probe(struct lwp *, struct exec_package *, void *, char *,
 	vaddr_t *);
+void arm_netbsd_elf32_coredump_setup(struct lwp *, void *);
 #endif
 
 #endif /* _ARM_ELF_MACHDEP_H_ */

sys/arch/arm/include/endian_machdep.h

@@ -1,7 +1,7 @@
-/* $NetBSD: endian_machdep.h,v 1.8 2006/01/30 21:52:38 dsl Exp $ */
+/* $NetBSD: endian_machdep.h,v 1.9 2014/01/29 01:03:13 matt Exp $ */
 
-/* GCC predefines __ARMEB__ when building for big-endian ARM. */
-#ifdef __ARMEB__
+/* __ARMEB__ or __AARCH64EB__ is predefined when building big-endian ARM. */
+#if defined(__ARMEB__) || defined(__AARCH64EB__)
 #define _BYTE_ORDER _BIG_ENDIAN
 #else
 #define _BYTE_ORDER _LITTLE_ENDIAN

sys/arch/arm/include/fenv.h

@@ -1,4 +1,4 @@
-/*	$NetBSD: fenv.h,v 1.1 2013/04/23 05:41:12 matt Exp $	*/
+/*	$NetBSD: fenv.h,v 1.3 2015/03/17 12:20:02 joerg Exp $	*/
 
 /* 
  * Based on ieeefp.h written by J.T. Conklin, Apr 28, 1995
@@ -8,7 +8,17 @@
 #ifndef _ARM_FENV_H_
 #define _ARM_FENV_H_
 
-typedef int fenv_t;
+#include <sys/cdefs.h>
+
+#ifdef __ARM_PCS_AAPCS64
+/* AArch64 split FPSCR into two registers FPCR and FPSR */
+typedef struct {
+	unsigned int __fpcr;
+	unsigned int __fpsr;
+} fenv_t;
+#else
+typedef int fenv_t;		/* FPSCR */
+#endif
 typedef int fexcept_t;
 
 #define	FE_INVALID	0x01	/* invalid operation exception */

sys/arch/arm/include/float.h

@@ -1,8 +1,63 @@
-/*	$NetBSD: float.h,v 1.7 2013/01/24 10:13:35 matt Exp $	*/
+/* $NetBSD: float.h,v 1.8 2014/01/29 01:10:36 matt Exp $ */
+
+/*-
+ * Copyright (c) 2014 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Matt Thomas of 3am Software Foundry.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #ifndef _ARM_FLOAT_H_
 #define _ARM_FLOAT_H_
 
+#include <sys/cdefs.h>
+
+#ifdef __ARM_PCS_AAPCS64
+
+#define LDBL_MANT_DIG	__LDBL_MANT_DIG__
+#define LDBL_DIG	__LDBL_DIG__
+#define LDBL_MIN_EXP	__LDBL_MIN_EXP__
+#define LDBL_MIN_10_EXP	__LDBL_MIN_10_EXP__
+#define LDBL_MAX_EXP	__LDBL_MAX_EXP__
+#define LDBL_MAX_10_EXP	__LDBL_MAX_10_EXP__
+#define LDBL_EPSILON	__LDBL_EPSILON__
+#define LDBL_MIN	__LDBL_MIN__
+#define LDBL_MAX	__LDBL_MAX__
+
+#endif /* __ARM_PCS_AAPCS64 */
+
 #include <sys/float_ieee754.h>
 
+#if defined(__ARM_PCS_AAPCS64) \
+    && ((!defined(_ANSI_SOURCE) && !defined(_POSIX_C_SOURCE) \
+	 && !defined(_XOPEN_SOURCE)) \
+	|| (__STDC_VERSION__ - 0) >= 199901L \
+	|| (_POSIX_C_SOURCE - 0) >= 200112L \
+	|| ((_XOPEN_SOURCE  - 0) >= 600) \
+	|| defined(_ISOC99_SOURCE) || defined(_NETBSD_SOURCE))
+#define DECIMAL_DIG	__DECIMAL_DIG__
+#endif /* __ARM_PCS_AAPCS64 && ... */
+
 #endif /* !_ARM_FLOAT_H_ */

sys/arch/arm/include/ieee.h

@@ -1,13 +1,4 @@
-/*	$NetBSD: ieee.h,v 1.9 2005/12/11 12:16:47 christos Exp $	*/
+/* $NetBSD: ieee.h,v 1.11 2014/01/31 19:38:06 matt Exp $ */
 
+#include <arm/math.h>		/* for #define __HAVE_LONG_DOUBLE 128 */
 #include <sys/ieee754.h>
-
-/*
- * A NaN is a `signalling NaN' if its QUIETNAN bit is clear in its
- * high fraction; if the bit is set, it is a `quiet NaN'.
- */
-
-#if 0
-#define	SNG_QUIETNAN	(1 << 22)
-#define	DBL_QUIETNAN	(1 << 19)
-#endif

sys/arch/arm/include/int_const.h

@@ -1,4 +1,4 @@
-/*	$NetBSD: int_const.h,v 1.3 2010/05/29 17:33:57 tnozaki Exp $	*/
+/*	$NetBSD: int_const.h,v 1.4 2014/07/25 21:43:13 joerg Exp $	*/
 
 /*-
  * Copyright (c) 2001 The NetBSD Foundation, Inc.
@@ -32,6 +32,9 @@
 #ifndef _ARM_INT_CONST_H_
 #define _ARM_INT_CONST_H_
 
+#ifdef __INTMAX_C_SUFFIX__
+#include <sys/common_int_const.h>
+#else
 /*
  * 7.18.4 Macros for integer constants
  */
@@ -52,5 +55,6 @@
 
 #define	INTMAX_C(c)	c ## LL
 #define	UINTMAX_C(c)	c ## ULL
+#endif
 
 #endif /* !_ARM_INT_CONST_H_ */

sys/arch/arm/include/int_fmtio.h

@@ -1,4 +1,4 @@
-/*	$NetBSD: int_fmtio.h,v 1.5 2008/08/29 19:08:29 matt Exp $	*/
+/*	$NetBSD: int_fmtio.h,v 1.9 2014/08/13 19:48:17 matt Exp $	*/
 
 /*-
  * Copyright (c) 2001 The NetBSD Foundation, Inc.
@@ -32,12 +32,14 @@
 #ifndef _ARM_INT_FMTIO_H_
 #define _ARM_INT_FMTIO_H_
 
+#ifdef __INTPTR_FMTd__
+#include <sys/common_int_fmtio.h>
+#else
 /*
  * 7.8.1 Macros for format specifiers
  */
 
 /* fprintf macros for signed integers */
-
 #define	PRId8		"d"	/* int8_t		*/
 #define	PRId16		"d"	/* int16_t		*/
 #define	PRId32		"d"	/* int32_t		*/
@@ -51,7 +53,7 @@
 #define	PRIdFAST32	"d"	/* int_fast32_t		*/
 #define	PRIdFAST64	"lld"	/* int_fast64_t		*/
 #define	PRIdMAX		"lld"	/* intmax_t		*/
-#define	PRIdPTR		"d"	/* intptr_t		*/
+#define	PRIdPTR		"ld"	/* intptr_t		*/
 
 #define	PRIi8		"i"	/* int8_t		*/
 #define	PRIi16		"i"	/* int16_t		*/
@@ -66,7 +68,7 @@
 #define	PRIiFAST32	"i"	/* int_fast32_t		*/
 #define	PRIiFAST64	"lli"	/* int_fast64_t		*/
 #define	PRIiMAX		"lli"	/* intmax_t		*/
-#define	PRIiPTR		"i"	/* intptr_t		*/
+#define	PRIiPTR		"li"	/* intptr_t		*/
 
 /* fprintf macros for unsigned integers */
 
@@ -83,7 +85,7 @@
 #define	PRIoFAST32	"o"	/* uint_fast32_t	*/
 #define	PRIoFAST64	"llo"	/* uint_fast64_t	*/
 #define	PRIoMAX		"llo"	/* uintmax_t		*/
-#define	PRIoPTR		"o"	/* uintptr_t		*/
+#define	PRIoPTR		"lo"	/* uintptr_t		*/
 
 #define	PRIu8		"u"	/* uint8_t		*/
 #define	PRIu16		"u"	/* uint16_t		*/
@@ -98,7 +100,7 @@
 #define	PRIuFAST32	"u"	/* uint_fast32_t	*/
 #define	PRIuFAST64	"llu"	/* uint_fast64_t	*/
 #define	PRIuMAX		"llu"	/* uintmax_t		*/
-#define	PRIuPTR		"u"	/* uintptr_t		*/
+#define	PRIuPTR		"lu"	/* uintptr_t		*/
 
 #define	PRIx8		"x"	/* uint8_t		*/
 #define	PRIx16		"x"	/* uint16_t		*/
@@ -113,7 +115,7 @@
 #define	PRIxFAST32	"x"	/* uint_fast32_t	*/
 #define	PRIxFAST64	"llx"	/* uint_fast64_t	*/
 #define	PRIxMAX		"llx"	/* uintmax_t		*/
-#define	PRIxPTR		"x"	/* uintptr_t		*/
+#define	PRIxPTR		"lx"	/* uintptr_t		*/
 
 #define	PRIX8		"X"	/* uint8_t		*/
 #define	PRIX16		"X"	/* uint16_t		*/
@@ -128,7 +130,7 @@
 #define	PRIXFAST32	"X"	/* uint_fast32_t	*/
 #define	PRIXFAST64	"llX"	/* uint_fast64_t	*/
 #define	PRIXMAX		"llX"	/* uintmax_t		*/
-#define	PRIXPTR		"X"	/* uintptr_t		*/
+#define	PRIXPTR		"lX"	/* uintptr_t		*/
 
 /* fscanf macros for signed integers */
 
@@ -160,7 +162,7 @@
 #define	SCNiFAST32	"i"	/* int_fast32_t		*/
 #define	SCNiFAST64	"lli"	/* int_fast64_t		*/
 #define	SCNiMAX		"lli"	/* intmax_t		*/
-#define	SCNiPTR		"i"	/* intptr_t		*/
+#define	SCNiPTR		"li"	/* intptr_t		*/
 
 /* fscanf macros for unsigned integers */
 
@@ -177,7 +179,7 @@
 #define	SCNoFAST32	"o"	/* uint_fast32_t	*/
 #define	SCNoFAST64	"llo"	/* uint_fast64_t	*/
 #define	SCNoMAX		"llo"	/* uintmax_t		*/
-#define	SCNoPTR		"o"	/* uintptr_t		*/
+#define	SCNoPTR		"lo"	/* uintptr_t		*/
 
 #define	SCNu8		"hhu"	/* uint8_t		*/
 #define	SCNu16		"hu"	/* uint16_t		*/
@@ -192,7 +194,7 @@
 #define	SCNuFAST32	"u"	/* uint_fast32_t	*/
 #define	SCNuFAST64	"llu"	/* uint_fast64_t	*/
 #define	SCNuMAX		"llu"	/* uintmax_t		*/
-#define	SCNuPTR		"u"	/* uintptr_t		*/
+#define	SCNuPTR		"lu"	/* uintptr_t		*/
 
 #define	SCNx8		"hhx"	/* uint8_t		*/
 #define	SCNx16		"hx"	/* uint16_t		*/
@@ -207,6 +209,8 @@
 #define	SCNxFAST32	"x"	/* uint_fast32_t	*/
 #define	SCNxFAST64	"llx"	/* uint_fast64_t	*/
 #define	SCNxMAX		"llx"	/* uintmax_t		*/
-#define	SCNxPTR		"x"	/* uintptr_t		*/
+#define	SCNxPTR		"lx"	/* uintptr_t		*/
+
+#endif /* !__INTPTR_FMTd__ */
 
 #endif /* !_ARM_INT_FMTIO_H_ */

sys/arch/arm/include/int_limits.h

@@ -1,4 +1,4 @@
-/*	$NetBSD: int_limits.h,v 1.9 2008/08/29 19:08:29 matt Exp $	*/
+/*	$NetBSD: int_limits.h,v 1.11 2014/07/25 21:43:13 joerg Exp $	*/
 
 /*-
  * Copyright (c) 2001 The NetBSD Foundation, Inc.
@@ -32,6 +32,9 @@
 #ifndef _ARM_INT_LIMITS_H_
 #define _ARM_INT_LIMITS_H_
 
+#ifdef __SIG_ATOMIC_MAX__
+#include <sys/common_int_limits.h>
+#else
 /*
  * 7.18.2 Limits of specified-width integer types
  */
@@ -98,9 +101,15 @@
 
 /* 7.18.2.4 Limits of integer types capable of holding object pointers */
 
+#ifdef _LP64
+#define	INTPTR_MIN	(-0x7fffffffffffffffL-1)	/* intptr_t	  */
+#define	INTPTR_MAX	0x7fffffffffffffffL		/* intptr_t	  */
+#define	UINTPTR_MAX	0xffffffffffffffffUL		/* uintptr_t	  */
+#else
 #define	INTPTR_MIN	(-0x7fffffffL-1)		/* intptr_t	  */
 #define	INTPTR_MAX	0x7fffffffL			/* intptr_t	  */
 #define	UINTPTR_MAX	0xffffffffUL			/* uintptr_t	  */
+#endif
 
 /* 7.18.2.5 Limits of greatest-width integer types */
 
@@ -114,14 +123,24 @@
  */
 
 /* limits of ptrdiff_t */
+#ifdef _LP64
+#define	PTRDIFF_MIN	(-0x7fffffffffffffffL-1)	/* ptrdiff_t	  */
+#define	PTRDIFF_MAX	0x7fffffffffffffffL		/* ptrdiff_t	  */
+#else
 #define	PTRDIFF_MIN	(-0x7fffffffL-1)		/* ptrdiff_t	  */
 #define	PTRDIFF_MAX	0x7fffffffL			/* ptrdiff_t	  */
+#endif
 
 /* limits of sig_atomic_t */
 #define	SIG_ATOMIC_MIN	(-0x7fffffff-1)			/* sig_atomic_t	  */
 #define	SIG_ATOMIC_MAX	0x7fffffff			/* sig_atomic_t	  */
 
 /* limit of size_t */
+#ifdef _LP64
+#define	SIZE_MAX	0xffffffffffffffffUL		/* size_t	  */
+#else
 #define	SIZE_MAX	0xffffffffUL			/* size_t	  */
+#endif
+#endif
 
 #endif /* !_ARM_INT_LIMITS_H_ */

sys/arch/arm/include/int_mwgwtypes.h

@@ -1,11 +1,11 @@
-/*	$NetBSD: int_mwgwtypes.h,v 1.4 2008/04/28 20:23:14 martin Exp $	*/
+/* $NetBSD: int_mwgwtypes.h,v 1.7 2014/07/25 21:43:13 joerg Exp $ */
 
 /*-
- * Copyright (c) 2001 The NetBSD Foundation, Inc.
+ * Copyright (c) 2014 The NetBSD Foundation, Inc.
  * All rights reserved.
  *
  * This code is derived from software contributed to The NetBSD Foundation
- * by Klaus Klein.
+ * by Matt Thomas of 3am Software Foundry.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -32,55 +32,96 @@
 #ifndef _ARM_INT_MWGWTYPES_H_
 #define _ARM_INT_MWGWTYPES_H_
 
+#ifdef __UINT_FAST64_TYPE__
+#include <sys/common_int_mwgwtypes.h>
+#else
 /*
  * 7.18.1 Integer types
  */
 
 /* 7.18.1.2 Minimum-width integer types */
 
-typedef	signed char		  int_least8_t;
-typedef	unsigned char		 uint_least8_t;
-typedef	short int		 int_least16_t;
-typedef	unsigned short int	uint_least16_t;
-typedef	int			 int_least32_t;
-typedef	unsigned int		uint_least32_t;
-#ifdef __COMPILER_INT64__
-typedef	__COMPILER_INT64__	 int_least64_t;
-typedef	__COMPILER_UINT64__	uint_least64_t;
-#else
-/* LONGLONG */
-typedef	long long int		 int_least64_t;
-/* LONGLONG */
-typedef	unsigned long long int	uint_least64_t;
+#ifndef __INT_LEAST8_TYPE__
+# define __INT_LEAST8_TYPE__	signed char
+#endif
+#ifndef __UINT_LEAST8_TYPE__
+# define __UINT_LEAST8_TYPE__	unsigned char
+#endif
+#ifndef __INT_LEAST16_TYPE__
+# define __INT_LEAST16_TYPE__	short int
+#endif
+#ifndef __UINT_LEAST16_TYPE__
+# define __UINT_LEAST16_TYPE__	short unsigned int
+#endif
+#ifndef __INT_LEAST32_TYPE__
+# define __INT_LEAST32_TYPE__	int
+#endif
+#ifndef __UINT_LEAST32_TYPE__
+# define __UINT_LEAST32_TYPE__	unsigned int
+#endif
+#ifndef __INT_LEAST64_TYPE__
+# define __INT_LEAST64_TYPE__	long long int
+#endif
+#ifndef __UINT_LEAST64_TYPE__
+# define __UINT_LEAST64_TYPE__	long long unsigned int
 #endif
 
+typedef	__INT_LEAST8_TYPE__	  int_least8_t;
+typedef	__UINT_LEAST8_TYPE__	 uint_least8_t;
+typedef	__INT_LEAST16_TYPE__	 int_least16_t;
+typedef	__UINT_LEAST16_TYPE__	uint_least16_t;
+typedef	__INT_LEAST32_TYPE__	 int_least32_t;
+typedef	__UINT_LEAST32_TYPE__	uint_least32_t;
+typedef	__INT_LEAST64_TYPE__	 int_least64_t;
+typedef	__UINT_LEAST64_TYPE__	uint_least64_t;
+
 /* 7.18.1.3 Fastest minimum-width integer types */
-typedef	int			   int_fast8_t;
-typedef	unsigned int		  uint_fast8_t;
-typedef	int			  int_fast16_t;
-typedef	unsigned int		 uint_fast16_t;
-typedef	int			  int_fast32_t;
-typedef	unsigned int		 uint_fast32_t;
-#ifdef __COMPILER_INT64__
-typedef	__COMPILER_INT64__	  int_fast64_t;
-typedef	__COMPILER_UINT64__	 uint_fast64_t;
-#else
-/* LONGLONG */
-typedef	long long int		  int_fast64_t;
-/* LONGLONG */
-typedef	unsigned long long int	 uint_fast64_t;
+
+#ifndef __INT_FAST8_TYPE__
+# define __INT_FAST8_TYPE__	int
 #endif
+#ifndef __UINT_FAST8_TYPE__
+# define __UINT_FAST8_TYPE__	unsigned int
+#endif
+#ifndef __INT_FAST16_TYPE__
+# define __INT_FAST16_TYPE__	int
+#endif
+#ifndef __UINT_FAST16_TYPE__
+# define __UINT_FAST16_TYPE__	unsigned int
+#endif
+#ifndef __INT_FAST32_TYPE__
+# define __INT_FAST32_TYPE__	int
+#endif
+#ifndef __UINT_FAST32_TYPE__
+# define __UINT_FAST32_TYPE__	unsigned int
+#endif
+#ifndef __INT_FAST64_TYPE__
+# define __INT_FAST64_TYPE__	long long int
+#endif
+#ifndef __UINT_FAST64_TYPE__
+# define __UINT_FAST64_TYPE__	long long unsigned int
+#endif
+
+typedef	__INT_FAST8_TYPE__	   int_fast8_t;
+typedef	__UINT_FAST8_TYPE__	  uint_fast8_t;
+typedef	__INT_FAST16_TYPE__	  int_fast16_t;
+typedef	__UINT_FAST16_TYPE__	 uint_fast16_t;
+typedef	__INT_FAST32_TYPE__	  int_fast32_t;
+typedef	__UINT_FAST32_TYPE__	 uint_fast32_t;
+typedef	__INT_FAST64_TYPE__	  int_fast64_t;
+typedef	__UINT_FAST64_TYPE__	 uint_fast64_t;
 
 /* 7.18.1.5 Greatest-width integer types */
 
-#ifdef __COMPILER_INT64__
-typedef	__COMPILER_INT64__	      intmax_t;
-typedef	__COMPILER_UINT64__	     uintmax_t;
-#else
-/* LONGLONG */
-typedef	long long int		      intmax_t;
-/* LONGLONG */
-typedef	unsigned long long int	     uintmax_t;
+#ifndef __INTMAX_TYPE__
+# define __INTMAX_TYPE__	long long int
+#endif
+#ifndef __UINTMAX_TYPE__
+# define __UINTMAX_TYPE__	unsigned __INTMAX_TYPE__
+#endif
+
+typedef	__INTMAX_TYPE__	     	      intmax_t;
+typedef	__UINTMAX_TYPE__	     uintmax_t;
 #endif
 
 #endif /* !_ARM_INT_MWGWTYPES_H_ */

sys/arch/arm/include/int_types.h

@@ -1,9 +1,12 @@
-/*	$NetBSD: int_types.h,v 1.9 2008/08/29 19:08:29 matt Exp $	*/
+/*	$NetBSD: int_types.h,v 1.17 2014/07/25 21:43:13 joerg Exp $	*/
 
-/*
- * Copyright (c) 1990 The Regents of the University of California.
+/*-
+ * Copyright (c) 2014 The NetBSD Foundation, Inc.
  * All rights reserved.
  *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Matt Thomas of 3am Software Foundry.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
@@ -12,28 +15,26 @@
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the University nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
  *
- * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- *	from: @(#)types.h	7.5 (Berkeley) 3/9/91
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
  */
 
-#ifndef	_ARM32_INT_TYPES_H_
-#define	_ARM32_INT_TYPES_H_
+#ifndef _ARM_INT_TYPES_H_
+#define _ARM_INT_TYPES_H_
 
+#ifdef __UINTPTR_TYPE__
+#include <sys/common_int_types.h>
+#else
 #include <sys/cdefs.h>
 
 /*
@@ -42,21 +43,43 @@
 
 /* 7.18.1.1 Exact-width integer types */
 
-typedef	signed char		 __int8_t;
-typedef	unsigned char		__uint8_t;
-typedef	short int		__int16_t;
-typedef	unsigned short int     __uint16_t;
-typedef	int			__int32_t;
-typedef	unsigned int	       __uint32_t;
-#ifdef __COMPILER_INT64__
-typedef	__COMPILER_INT64__	__int64_t;
-typedef	__COMPILER_UINT64__    __uint64_t;
-#else
-/* LONGLONG */
-typedef	long long int		__int64_t;
-/* LONGLONG */
-typedef	unsigned long long int __uint64_t;
+#ifndef __UINT8_TYPE__
+# define __UINT8_TYPE__		unsigned char
 #endif
+#ifndef __INT8_TYPE__
+# define __INT8_TYPE__		signed char
+#endif
+#ifndef __UINT16_TYPE__
+# ifndef __INT16_TYPE__
+#  define __INT16_TYPE__	short int
+# endif
+# define __UINT16_TYPE__	unsigned __INT16_TYPE__
+#endif
+#ifndef __UINT32_TYPE__
+# ifndef __INT32_TYPE__
+#  define __INT32_TYPE__	int
+# endif
+# define __UINT32_TYPE__	unsigned __INT32_TYPE__
+#endif
+#ifndef __UINT64_TYPE__
+# ifndef __INT64_TYPE__
+#  define __INT64_TYPE__	long long int
+# endif
+# define __UINT64_TYPE__	unsigned __INT64_TYPE__
+#endif
+
+#ifdef __clang__
+typedef	signed __INT8_TYPE__	   __int8_t;
+#else
+typedef	__INT8_TYPE__		   __int8_t;
+#endif
+typedef	__UINT8_TYPE__		  __uint8_t;
+typedef	__INT16_TYPE__		  __int16_t;
+typedef	__UINT16_TYPE__		 __uint16_t;
+typedef	__INT32_TYPE__		  __int32_t;
+typedef	__UINT32_TYPE__		 __uint32_t;
+typedef	__INT64_TYPE__		  __int64_t;
+typedef	__UINT64_TYPE__		 __uint64_t;
 
 #if !defined(__minix)
 #define	__BIT_TYPES_DEFINED__
@@ -64,7 +87,15 @@ typedef	unsigned long long int __uint64_t;
 
 /* 7.18.1.4 Integer types capable of holding object pointers */
 
-typedef	int		       __intptr_t;
-typedef	unsigned int	      __uintptr_t;
+#ifndef __UINTPTR_TYPE__
+# ifndef __INTPTR_TYPE__
+#  define __INTPTR_TYPE__	long int
+# endif
+# define __UINTPTR_TYPE__	unsigned __INTPTR_TYPE__
+#endif
 
-#endif	/* !_ARM32_INT_TYPES_H_ */
+typedef	__INTPTR_TYPE__		 __intptr_t;
+typedef	__UINTPTR_TYPE__	__uintptr_t;
+#endif
+
+#endif	/* !_ARM_INT_TYPES_H_ */

sys/arch/arm/include/isa_machdep.h

@@ -1,4 +1,4 @@
-/*	$NetBSD: isa_machdep.h,v 1.10 2012/10/27 17:17:39 chs Exp $	*/
+/*	$NetBSD: isa_machdep.h,v 1.11 2014/01/29 00:42:15 matt Exp $	*/
 
 /*-
  * Copyright (c) 1996, 1997, 1998 The NetBSD Foundation, Inc.
@@ -30,8 +30,8 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 
-#ifndef _ARM32_ISA_MACHDEP_H_
-#define _ARM32_ISA_MACHDEP_H_
+#ifndef _ARM_ISA_MACHDEP_H_
+#define _ARM_ISA_MACHDEP_H_
 
 #include <sys/bus.h>
 #include <dev/isa/isadmavar.h>
@@ -143,4 +143,4 @@ void	isa_intr_init(void);
 void sysbeep(int, int);		/* beep with the system speaker */
 void isa_fillw(u_int val, void *addr, size_t len);
 
-#endif	/* _ARM32_ISA_MACHDEP_H_ XXX */
+#endif	/* _ARM_ISA_MACHDEP_H_ */

sys/arch/arm/include/limits.h

@@ -1,4 +1,4 @@
-/*	$NetBSD: limits.h,v 1.13 2013/04/11 00:57:34 christos Exp $	*/
+/*	$NetBSD: limits.h,v 1.18 2014/02/24 16:57:57 christos Exp $	*/
 
 /*
  * Copyright (c) 1988 The Regents of the University of California.
@@ -31,8 +31,8 @@
  *	from: @(#)limits.h	7.2 (Berkeley) 6/28/90
  */
 
-#ifndef	_ARM32_LIMITS_H_
-#define	_ARM32_LIMITS_H_
+#ifndef _ARM_LIMITS_H_
+#define _ARM_LIMITS_H_
 
 #include <sys/featuretest.h>
 
@@ -44,15 +44,21 @@
 
 #define	USHRT_MAX	0xffff		/* max value for an unsigned short */
 #define	SHRT_MAX	0x7fff		/* max value for a short */
-#define SHRT_MIN        (-0x7fff-1)     /* min value for a short */
+#define	SHRT_MIN	(-0x7fff-1)	/* min value for a short */
 
 #define	UINT_MAX	0xffffffffU	/* max value for an unsigned int */
 #define	INT_MAX		0x7fffffff	/* max value for an int */
 #define	INT_MIN		(-0x7fffffff-1)	/* min value for an int */
 
+#ifdef _LP64
+#define	ULONG_MAX	0xffffffffffffffffUL	/* max unsigned long */
+#define	LONG_MAX	0x7fffffffffffffffL	/* max signed long */
+#define	LONG_MIN	(-0x7fffffffffffffffL-1) /* min signed long */
+#else
 #define	ULONG_MAX	0xffffffffUL	/* max value for an unsigned long */
 #define	LONG_MAX	0x7fffffffL	/* max value for a long */
 #define	LONG_MIN	(-0x7fffffffL-1)	/* min value for a long */
+#endif
 
 #if defined(_POSIX_C_SOURCE) || defined(_XOPEN_SOURCE) || \
     defined(_NETBSD_SOURCE)
@@ -67,7 +73,7 @@
 
 #if defined(_NETBSD_SOURCE)
 #define	SSIZE_MIN	LONG_MIN	/* min value for a ssize_t */
-#define	SIZE_T_MAX	LONG_MAX	/* max value for a size_t */
+#define	SIZE_T_MAX	ULONG_MAX	/* max value for a size_t */
 
 #define	UQUAD_MAX	0xffffffffffffffffULL		/* max unsigned quad */
 #define	QUAD_MAX	0x7fffffffffffffffLL		/* max signed quad */
@@ -77,16 +83,27 @@
 #endif /* _POSIX_C_SOURCE || _XOPEN_SOURCE || _NETBSD_SOURCE */
 
 #if defined(_XOPEN_SOURCE) || defined(_NETBSD_SOURCE)
+#ifdef _LP64
+#define LONG_BIT	64
+#else
 #define LONG_BIT	32
+#endif
 #define WORD_BIT	32
 
-#define DBL_DIG		15
-#define DBL_MAX		1.7976931348623157E+308
-#define DBL_MIN		2.2250738585072014E-308
+#define DBL_DIG		__DBL_DIG__
+#define DBL_MAX		__DBL_MAX__
+#define DBL_MIN		__DBL_MIN__
 
-#define FLT_DIG		6
-#define FLT_MAX		3.40282347E+38F
-#define FLT_MIN		1.17549435E-38F
+#define FLT_DIG		__FLT_DIG__
+#define FLT_MAX		__FLT_MAX__
+#define FLT_MIN		__FLT_MIN__
+
+#ifdef __ARM_PCS_AAPCS64
+#define LDBL_DIG	__LDBL_DIG__
+#define LDBL_MAX	__LDBL_MAX__
+#define LDBL_MIN	__LDBL_MIN__
 #endif
 
-#endif	/* _ARM32_LIMITS_H_ */
+#endif /* _XOPEN_SOURCE || _NETBSD_SOURCE */
+
+#endif	/* _ARM_LIMITS_H_ */

sys/arch/arm/include/lock.h

@@ -1,4 +1,4 @@
-/*	$NetBSD: lock.h,v 1.25 2013/08/18 04:31:08 matt Exp $	*/
+/*	$NetBSD: lock.h,v 1.32 2015/02/25 13:52:42 joerg Exp $	*/
 
 /*-
  * Copyright (c) 2000, 2001 The NetBSD Foundation, Inc.
@@ -73,116 +73,115 @@ __cpu_simple_lock_set(__cpu_simple_lock_t *__ptr)
 #define	mb_memory	drain_writebuf		/* in cpufunc.h */
 #endif
 
-#if defined(_KERNEL)
-static __inline unsigned char
-__swp(__cpu_simple_lock_t __val, volatile __cpu_simple_lock_t *__ptr)
-{
 #ifdef _ARM_ARCH_6
-	uint32_t __rv, __tmp;
-	if (sizeof(*__ptr) == 1) {
-		__asm volatile(
-			"1:\t"
-			"ldrexb\t%[__rv], [%[__ptr]]"			"\n\t"
-			"cmp\t%[__rv],%[__val]"				"\n\t"
-#ifdef __thumb__
-			"itt\tne"					"\n\t"
-#endif
-			"strexbne\t%[__tmp], %[__val], [%[__ptr]]"	"\n\t"
-			"cmpne\t%[__tmp], #0"				"\n\t"
-			"bne\t1b"					"\n\t"
-#ifdef _ARM_ARCH_7
-			"dmb"
-#else
-			"mcr\tp15, 0, %[__tmp], c7, c10, 5"
-#endif
-		    : [__rv] "=&r" (__rv), [__tmp] "=&r"(__tmp)
-		    : [__val] "r" (__val), [__ptr] "r" (__ptr) : "cc", "memory");
+static __inline unsigned int
+__arm_load_exclusive(__cpu_simple_lock_t *__alp)
+{
+	unsigned int __rv;
+	if (/*CONSTCOND*/sizeof(*__alp) == 1) {
+		__asm __volatile("ldrexb\t%0,[%1]" : "=r"(__rv) : "r"(__alp));
 	} else {
-		__asm volatile(
-			"1:\t"
-			"ldrex\t%[__rv], [%[__ptr]]"			"\n\t"
-			"cmp\t%[__rv],%[__val]"				"\n\t"
-#ifdef __thumb__
-			"itt\tne"					"\n\t"
-#endif
-			"strexne\t%[__tmp], %[__val], [%[__ptr]]"	"\n\t"
-			"cmpne\t%[__tmp], #0"				"\n\t"
-			"bne\t1b"					"\n\t"
-#ifdef _ARM_ARCH_7
-			"nop"
-#else
-			"mcr\tp15, 0, %[__tmp], c7, c10, 5"
-#endif
-		    : [__rv] "=&r" (__rv), [__tmp] "=&r"(__tmp)
-		    : [__val] "r" (__val), [__ptr] "r" (__ptr) : "cc", "memory");
+		__asm __volatile("ldrex\t%0,[%1]" : "=r"(__rv) : "r"(__alp));
 	}
 	return __rv;
-#else
+}
+
+/* returns 0 on success and 1 on failure */
+static __inline unsigned int
+__arm_store_exclusive(__cpu_simple_lock_t *__alp, unsigned int __val)
+{
+	unsigned int __rv;
+	if (/*CONSTCOND*/sizeof(*__alp) == 1) {
+		__asm __volatile("strexb\t%0,%1,[%2]"
+		    : "=&r"(__rv) : "r"(__val), "r"(__alp) : "cc", "memory");
+	} else {
+		__asm __volatile("strex\t%0,%1,[%2]"
+		    : "=&r"(__rv) : "r"(__val), "r"(__alp) : "cc", "memory");
+	}
+	return __rv;
+}
+#elif defined(_KERNEL)
+static __inline unsigned char
+__swp(unsigned char __val, __cpu_simple_lock_t *__ptr)
+{
 	uint32_t __val32;
-	__asm volatile("swpb %0, %1, [%2]"
+	__asm volatile("swpb	%0, %1, [%2]"
 	    : "=&r" (__val32) : "r" (__val), "r" (__ptr) : "memory");
 	return __val32;
-#endif
 }
 #else
 /*
- * On Cortex-A9 (SMP), SWP no longer guarantees atomic results.  Thus we pad
- * out SWP so that when the A9 generates an undefined exception we can replace
+ * On MP Cortex, SWP no longer guarantees atomic results.  Thus we pad
+ * out SWP so that when the cpu generates an undefined exception we can replace
  * the SWP/MOV instructions with the right LDREX/STREX instructions.
  *
  * This is why we force the SWP into the template needed for LDREX/STREX
  * including the extra instructions and extra register for testing the result.
  */
 static __inline int
-__swp(int __val, volatile int *__ptr)
+__swp(int __val, __cpu_simple_lock_t *__ptr)
 {
-	int __rv, __tmp;
+	int __tmp, __rv;
 	__asm volatile(
-		"1:\t"
-#ifdef _ARM_ARCH_6
-		"ldrex\t%[__rv], [%[__ptr]]"			"\n\t"
-		"cmp\t%[__rv],%[__val]"				"\n\t"
-#ifdef __thumb__
-		"it\tne"					"\n\t"
-#endif
-		"strexne\t%[__tmp], %[__val], [%[__ptr]]"	"\n\t"
+#if 1
+	"1:\t"	"swp	%[__rv], %[__val], [%[__ptr]]"
+	"\n\t"	"b	2f"
 #else
-		"swp\t%[__rv], %[__val], [%[__ptr]]"		"\n\t"
-		"mov\t%[__tmp], #0"				"\n\t"
-		"cmp\t%[__rv],%[__val]"				"\n\t"
+	"1:\t"	"ldrex	%[__rv],[%[__ptr]]"
+	"\n\t"	"strex	%[__tmp],%[__val],[%[__ptr]]"
 #endif
-		"cmpne\t%[__tmp], #0"				"\n\t"
-		"bne\t1b"					"\n\t"
-#ifdef _ARM_ARCH_7
-		"dmb"
-#elif defined(_ARM_ARCH_6)
-		"mcr\tp15, 0, %[__tmp], c7, c10, 5"
-#else
-		"nop"
-#endif
-	    : [__rv] "=&r" (__rv), [__tmp] "=&r"(__tmp)
+	"\n\t"	"cmp	%[__tmp],#0"
+	"\n\t"	"bne	1b"
+	"\n"	"2:"
+	    : [__rv] "=&r" (__rv), [__tmp] "=&r" (__tmp)
 	    : [__val] "r" (__val), [__ptr] "r" (__ptr) : "cc", "memory");
 	return __rv;
 }
-#endif /* _KERNEL */
+#endif /* !_ARM_ARCH_6 */
+
+static __inline void
+__arm_membar_producer(void)
+{
+#ifdef _ARM_ARCH_7
+	__asm __volatile("dsb" ::: "memory");
+#elif defined(_ARM_ARCH_6)
+	__asm __volatile("mcr\tp15,0,%0,c7,c10,4" :: "r"(0) : "memory");
+#endif
+}
+
+static __inline void
+__arm_membar_consumer(void)
+{
+#ifdef _ARM_ARCH_7
+	__asm __volatile("dmb" ::: "memory");
+#elif defined(_ARM_ARCH_6)
+	__asm __volatile("mcr\tp15,0,%0,c7,c10,5" :: "r"(0) : "memory");
+#endif
+}
 
 static __inline void __unused
-__cpu_simple_lock_init(__cpu_simple_lock_t *alp)
+__cpu_simple_lock_init(__cpu_simple_lock_t *__alp)
 {
 
-	*alp = __SIMPLELOCK_UNLOCKED;
-#ifdef _ARM_ARCH_7
-	__asm __volatile("dsb");
-#endif
+	*__alp = __SIMPLELOCK_UNLOCKED;
+	__arm_membar_producer();
 }
 
 #if !defined(__thumb__) || defined(_ARM_ARCH_T2)
 static __inline void __unused
-__cpu_simple_lock(__cpu_simple_lock_t *alp)
+__cpu_simple_lock(__cpu_simple_lock_t *__alp)
 {
-
-	while (__swp(__SIMPLELOCK_LOCKED, alp) != __SIMPLELOCK_UNLOCKED)
+#ifdef _ARM_ARCH_6
+	__arm_membar_consumer();
+	do {
+		/* spin */
+	} while (__arm_load_exclusive(__alp) != __SIMPLELOCK_UNLOCKED
+		 || __arm_store_exclusive(__alp, __SIMPLELOCK_LOCKED));
+	__arm_membar_producer();
+#else
+	while (__swp(__SIMPLELOCK_LOCKED, __alp) != __SIMPLELOCK_UNLOCKED)
 		continue;
+#endif
 }
 #else
 void __cpu_simple_lock(__cpu_simple_lock_t *);
@@ -190,25 +189,41 @@ void __cpu_simple_lock(__cpu_simple_lock_t *);
 
 #if !defined(__thumb__) || defined(_ARM_ARCH_T2)
 static __inline int __unused
-__cpu_simple_lock_try(__cpu_simple_lock_t *alp)
+__cpu_simple_lock_try(__cpu_simple_lock_t *__alp)
 {
-
-	return (__swp(__SIMPLELOCK_LOCKED, alp) == __SIMPLELOCK_UNLOCKED);
+#ifdef _ARM_ARCH_6
+	__arm_membar_consumer();
+	do {
+		if (__arm_load_exclusive(__alp) != __SIMPLELOCK_UNLOCKED) {
+			return 0;
+		}
+	} while (__arm_store_exclusive(__alp, __SIMPLELOCK_LOCKED));
+	__arm_membar_producer();
+	return 1;
+#else
+	return (__swp(__SIMPLELOCK_LOCKED, __alp) == __SIMPLELOCK_UNLOCKED);
+#endif
 }
 #else
 int __cpu_simple_lock_try(__cpu_simple_lock_t *);
 #endif
 
 static __inline void __unused
-__cpu_simple_unlock(__cpu_simple_lock_t *alp)
+__cpu_simple_unlock(__cpu_simple_lock_t *__alp)
 {
 
-#ifdef _ARM_ARCH_7
-	__asm __volatile("dmb");
-#endif
-	*alp = __SIMPLELOCK_UNLOCKED;
-#ifdef _ARM_ARCH_7
-	__asm __volatile("dsb");
+#ifdef _ARM_ARCH_8
+	if (sizeof(*__alp) == 1) {
+		__asm __volatile("stlb\t%0, [%1]"
+		    :: "r"(__SIMPLELOCK_UNLOCKED), "r"(__alp) : "memory");
+	} else {
+		__asm __volatile("stl\t%0, [%1]"
+		    :: "r"(__SIMPLELOCK_UNLOCKED), "r"(__alp) : "memory");
+	}
+#else
+	__arm_membar_consumer();
+	*__alp = __SIMPLELOCK_UNLOCKED;
+	__arm_membar_producer();
 #endif
 }
 

sys/arch/arm/include/locore.h

@@ -1,4 +1,4 @@
-/*	cpu.h,v 1.45.4.7 2008/01/28 18:20:39 matt Exp	*/
+/*	$NetBSD: locore.h,v 1.26 2015/06/09 08:13:17 skrll Exp $	*/
 
 /*
  * Copyright (c) 1994-1996 Mark Brinicombe.
@@ -51,8 +51,11 @@
 #ifdef _KERNEL_OPT
 #include "opt_cpuoptions.h"
 #include "opt_cputypes.h"
+#include "opt_arm_debug.h"
 #endif
 
+#include <sys/pcu.h>
+
 #include <arm/cpuconf.h>
 #include <arm/armreg.h>
 
@@ -76,7 +79,7 @@
 	mrs	r0, cpsr ; \
 	bic	r0, r0, #(I32_bit) ; \
 	msr	cpsr_c, r0 ; \
-	ldmfd	sp!, {r0}		
+	ldmfd	sp!, {r0}
 #else
 /* Not yet used in 26-bit code */
 #endif
@@ -86,7 +89,13 @@
 #define GET_CURLWP(rX)		GET_CURCPU(rX); ldr rX, [rX, #CI_CURLWP]
 #elif defined (TPIDRPRW_IS_CURLWP)
 #define GET_CURLWP(rX)		mrc	p15, 0, rX, c13, c0, 4
+#if defined (MULTIPROCESSOR)
 #define GET_CURCPU(rX)		GET_CURLWP(rX); ldr rX, [rX, #L_CPU]
+#elif defined(_ARM_ARCH_7)
+#define GET_CURCPU(rX)		movw rX, #:lower16:cpu_info_store; movt rX, #:upper16:cpu_info_store
+#else
+#define GET_CURCPU(rX)		ldr rX, =_C_LABEL(cpu_info_store)
+#endif
 #elif !defined(MULTIPROCESSOR)
 #define GET_CURCPU(rX)		ldr rX, =_C_LABEL(cpu_info_store)
 #define GET_CURLWP(rX)		GET_CURCPU(rX); ldr rX, [rX, #CI_CURLWP]
@@ -111,16 +120,24 @@
  */
 
 #ifdef __PROG32
+#ifdef __NO_FIQ
 #define VALID_R15_PSR(r15,psr)						\
-	(((psr) & PSR_MODE) == PSR_USR32_MODE &&			\
-		((psr) & (I32_bit | F32_bit)) == 0)
+	(((psr) & PSR_MODE) == PSR_USR32_MODE && ((psr) & I32_bit) == 0)
+#else
+#define VALID_R15_PSR(r15,psr)						\
+	(((psr) & PSR_MODE) == PSR_USR32_MODE && ((psr) & IF32_bits) == 0)
+#endif
 #else
 #define VALID_R15_PSR(r15,psr)						\
 	(((r15) & R15_MODE) == R15_MODE_USR &&				\
 		((r15) & (R15_IRQ_DISABLE | R15_FIQ_DISABLE)) == 0)
 #endif
 
-
+/*
+ * Translation Table Base Register Share/Cache settings
+ */
+#define	TTBR_UPATTR	(TTBR_S | TTBR_RGN_WBNWA | TTBR_C)
+#define	TTBR_MPATTR	(TTBR_S | TTBR_RGN_WBNWA /* | TTBR_NOS */ | TTBR_IRGN_WBNWA)
 
 /* The address of the vector page. */
 extern vaddr_t vector_page;
@@ -149,8 +166,25 @@ void	cpu_attach(device_t, cpuid_t);
 
 /* 1 == use cpu_sleep(), 0 == don't */
 extern int cpu_do_powersave;
+extern int cpu_printfataltraps;
 extern int cpu_fpu_present;
 extern int cpu_hwdiv_present;
+extern int cpu_neon_present;
+extern int cpu_simd_present;
+extern int cpu_simdex_present;
+extern int cpu_umull_present;
+extern int cpu_synchprim_present;
+
+extern int cpu_instruction_set_attributes[6];
+extern int cpu_memory_model_features[4];
+extern int cpu_processor_features[2];
+extern int cpu_media_and_vfp_features[2];
+
+extern bool arm_has_tlbiasid_p;
+#ifdef MULTIPROCESSOR
+extern u_int arm_cpu_max;
+extern volatile u_int arm_cpu_hatched;
+#endif
 
 #if !defined(CPU_ARMV7)
 #define	CPU_IS_ARMV7_P()		false
@@ -160,6 +194,91 @@ extern bool cpu_armv7_p;
 #else
 #define	CPU_IS_ARMV7_P()		true
 #endif
+#if !defined(CPU_ARMV6)
+#define	CPU_IS_ARMV6_P()		false
+#elif defined(CPU_ARMV7) || defined(CPU_PRE_ARMV6)
+extern bool cpu_armv6_p;
+#define	CPU_IS_ARMV6_P()		(cpu_armv6_p)
+#else
+#define	CPU_IS_ARMV6_P()		true
+#endif
+
+/*
+ * Used by the fault code to read the current instruction.
+ */
+static inline uint32_t
+read_insn(vaddr_t va, bool user_p)
+{
+	uint32_t insn;
+	if (user_p) {
+		__asm __volatile("ldrt %0, [%1]" : "=&r"(insn) : "r"(va));
+	} else {
+		insn = *(const uint32_t *)va;
+	}
+#if defined(__ARMEB__) && defined(_ARM_ARCH_7)
+	insn = bswap32(insn);
+#endif
+	return insn;
+}
+
+/*
+ * Used by the fault code to read the current thumb instruction.
+ */
+static inline uint32_t
+read_thumb_insn(vaddr_t va, bool user_p)
+{
+	va &= ~1;
+	uint32_t insn;
+	if (user_p) {
+#if defined(__thumb__) && defined(_ARM_ARCH_T2)
+		__asm __volatile("ldrht %0, [%1, #0]" : "=&r"(insn) : "r"(va));
+#elif defined(_ARM_ARCH_7)
+		__asm __volatile("ldrht %0, [%1], #0" : "=&r"(insn) : "r"(va));
+#else
+		__asm __volatile("ldrt %0, [%1]" : "=&r"(insn) : "r"(va & ~3));
+#ifdef __ARMEB__
+		insn = (uint16_t) (insn >> (((va ^ 2) & 2) << 3));
+#else
+		insn = (uint16_t) (insn >> ((va & 2) << 3));
+#endif
+#endif
+	} else {
+		insn = *(const uint16_t *)va;
+	}
+#if defined(__ARMEB__) && defined(_ARM_ARCH_7)
+	insn = bswap16(insn);
+#endif
+	return insn;
+}
+
+#ifndef _RUMPKERNEL
+static inline void
+arm_dmb(void)
+{
+	if (CPU_IS_ARMV6_P())
+		armreg_dmb_write(0);
+	else if (CPU_IS_ARMV7_P())
+		__asm __volatile("dmb" ::: "memory");
+}
+
+static inline void
+arm_dsb(void)
+{
+	if (CPU_IS_ARMV6_P())
+		armreg_dsb_write(0);
+	else if (CPU_IS_ARMV7_P())
+		__asm __volatile("dsb" ::: "memory");
+}
+
+static inline void
+arm_isb(void)
+{
+	if (CPU_IS_ARMV6_P())
+		armreg_isb_write(0);
+	else if (CPU_IS_ARMV7_P())
+		__asm __volatile("isb" ::: "memory");
+}
+#endif
 
 /*
  * Random cruft
@@ -167,9 +286,8 @@ extern bool cpu_armv7_p;
 
 struct lwp;
 
-/* locore.S */
-void atomic_set_bit(u_int *, u_int);
-void atomic_clear_bit(u_int *, u_int);
+/* cpu.c */
+void	identify_arm_cpu(device_t, struct cpu_info *);
 
 /* cpuswitch.S */
 struct pcb;
@@ -191,7 +309,7 @@ void	swi_handler(trapframe_t *);
 void	ucas_ras_check(trapframe_t *);
 
 /* vfp_init.c */
-void	vfp_attach(void);
+void	vfp_attach(struct cpu_info *);
 void	vfp_discardcontext(bool);
 void	vfp_savecontext(void);
 void	vfp_kernel_acquire(void);

sys/arch/arm/include/math.h

@@ -1,3 +1,6 @@
-/*	$NetBSD: math.h,v 1.2 2002/02/19 13:08:14 simonb Exp $	*/
+/*	$NetBSD: math.h,v 1.4 2014/01/31 19:38:06 matt Exp $	*/
 
 #define	__HAVE_NANF
+#ifdef __ARM_PCS_AAPCS64
+#define __HAVE_LONG_DOUBLE	128
+#endif

sys/arch/arm/include/mcontext.h

@@ -1,4 +1,4 @@
-/*	$NetBSD: mcontext.h,v 1.16 2013/08/15 22:34:59 matt Exp $	*/
+/*	$NetBSD: mcontext.h,v 1.18 2015/03/24 08:38:29 matt Exp $	*/
 
 /*-
  * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc.
@@ -94,10 +94,12 @@ typedef struct {
 		__fpregset_t __fpregs;
 		__vfpregset_t __vfpregs;
 	} __fpu;
-	__greg_t	_mc_tlsbase;
 #if defined(__minix)
 	int mc_flags;
 	int mc_magic;
+#else
+	__greg_t	_mc_tlsbase;
+	__greg_t	_mc_user_tpid;
 #endif /* defined(__minix) */
 } mcontext_t, mcontext32_t;
 
@@ -110,7 +112,7 @@ typedef struct {
 
 #define	_UC_TLSBASE	0x00080000
 
-#define _UC_MACHINE_PAD	2		/* Padding appended to ucontext_t */
+#define _UC_MACHINE_PAD	1		/* Padding appended to ucontext_t */
 
 #define _UC_MACHINE_SP(uc)	((uc)->uc_mcontext.__gregs[_REG_SP])
 #define _UC_MACHINE_PC(uc)	((uc)->uc_mcontext.__gregs[_REG_PC])
@@ -150,6 +152,7 @@ typedef struct {
 #define	__UCONTEXT_SIZE	256
 #endif
 
+__BEGIN_DECLS
 static __inline void *
 __lwp_getprivate_fast(void)
 {
@@ -182,5 +185,6 @@ int setmcontext(const mcontext_t *mcp);
 int getmcontext(mcontext_t *mcp);
 #define MCF_MAGIC 0xc0ffee
 #endif /* defined(__minix) */
+__END_DECLS
 
 #endif	/* !_ARM_MCONTEXT_H_ */

sys/arch/arm/include/mutex.h

@@ -1,4 +1,4 @@
-/*	$NetBSD: mutex.h,v 1.13 2012/09/25 05:24:00 matt Exp $	*/
+/*	$NetBSD: mutex.h,v 1.20 2015/02/25 13:52:42 joerg Exp $	*/
 
 /*-
  * Copyright (c) 2002, 2007 The NetBSD Foundation, Inc.
@@ -35,15 +35,15 @@
 /*
  * The ARM mutex implementation is troublesome, because pre-v6 ARM lacks a
  * compare-and-swap operation.  However, there aren't any MP pre-v6 ARM
- * systems to speak of.  We are mostly concerned with atomicity with respect
- * to interrupts.
+ * systems to speak of.
  *
- * ARMv6, however, does have ldrex/strex, and can thus implement an MP-safe
- * compare-and-swap.
+ * ARMv6 and later, however, does have ldrex/strex, and can thus implement an
+ * MP-safe compare-and-swap.
  *
- * So, what we have done is impement simple mutexes using a compare-and-swap.
+ * So, what we have done is implement simple mutexes using a compare-and-swap.
  * We support pre-ARMv6 by implementing CAS as a restartable atomic sequence
- * that is checked by the IRQ vector.  MP-safe ARMv6 support will be added later.
+ * that is checked by the IRQ vector.
+ * 
  */
 
 #ifndef __MUTEX_PRIVATE
@@ -62,7 +62,7 @@ struct kmutex {
 		/* Spin mutex */
 		struct {
 			/*
-			 * Since the low bit of mtax_owner is used to flag this
+			 * Since the low bit of mtxa_owner is used to flag this
 			 * mutex as a spin mutex, we can't use the first byte
 			 * or the last byte to store the ipl or lock values.
 			 */
@@ -85,15 +85,28 @@ struct kmutex {
 #define	__HAVE_SIMPLE_MUTEXES		1
 
 /*
- * MUTEX_RECEIVE: no memory barrier required; we're synchronizing against
- * interrupts, not multiple processors.
+ * MUTEX_{GIVE,RECEIVE}: no memory barrier is required in the UP case;
+ * we're synchronizing against interrupts, not multiple processors.
  */
+#ifdef MULTIPROCESSOR
+#ifdef _ARM_ARCH_7
+#define	MUTEX_RECEIVE(mtx)		__asm __volatile("dmb" ::: "memory")
+#else
+#define	MUTEX_RECEIVE(mtx)		membar_consumer()
+#endif
+#else
 #define	MUTEX_RECEIVE(mtx)		/* nothing */
+#endif
 
-/*
- * MUTEX_GIVE: no memory barrier required; same reason.
- */
+#ifdef MULTIPROCESSOR
+#ifdef _ARM_ARCH_7
+#define	MUTEX_GIVE(mtx)			__asm __volatile("dsb" ::: "memory")
+#else
+#define	MUTEX_GIVE(mtx)			membar_producer()
+#endif
+#else
 #define	MUTEX_GIVE(mtx)			/* nothing */
+#endif
 
 #define	MUTEX_CAS(p, o, n)		\
     (atomic_cas_ulong((volatile unsigned long *)(p), (o), (n)) == (o))

sys/arch/arm/include/ofw.h

@@ -1,4 +1,4 @@
-/*	$NetBSD: ofw.h,v 1.3 2009/03/14 14:45:55 dsl Exp $	*/
+/*	$NetBSD: ofw.h,v 1.5 2014/09/13 17:41:03 matt Exp $	*/
 
 /*
  * Copyright 1997
@@ -33,8 +33,8 @@
  *    even if advised of the possibility of such damage.
  */
 
-#ifndef _MACHINE_OFW_H_
-#define _MACHINE_OFW_H_
+#ifndef _ARM_OFW_H_
+#define _ARM_OFW_H_
 
 
 /* Virtual address range reserved for OFW. */
@@ -52,13 +52,12 @@ void ofw_init(ofw_handle_t);
 void ofw_boot(int, char *);
 void ofw_getbootinfo(char **, char **);
 void ofw_configmem(void);
-void ofw_configisa(vm_offset_t *, vm_offset_t *);
-void ofw_configisadma(vm_offset_t *);
-int  ofw_isadmarangeintersect(vm_offset_t, vm_offset_t,
-				   vm_offset_t *, vm_offset_t *);
-vm_offset_t ofw_gettranslation(vm_offset_t);
-vm_offset_t ofw_map(vm_offset_t, vm_size_t, int);
-vm_offset_t ofw_getcleaninfo(void);
+void ofw_configisa(vaddr_t *, vaddr_t *);
+void ofw_configisadma(vaddr_t *);
+int  ofw_isadmarangeintersect(vaddr_t, vaddr_t, vaddr_t *, vaddr_t *);
+vaddr_t ofw_gettranslation(vaddr_t);
+vaddr_t ofw_map(vaddr_t, vsize_t, int);
+vaddr_t ofw_getcleaninfo(void);
 
 #ifdef	OFWGENCFG
 /* Implemented in <ofw/ofwgencfg_machdep.c> */
@@ -67,4 +66,4 @@ extern void cpu_reboot(int, char *);
 extern void ofrootfound(void);
 #endif
 
-#endif /* !_MACHINE_OFW_H_ */
+#endif /* !_ARM_OFW_H_ */

sys/arch/arm/include/pci_machdep.h

@@ -1,4 +1,4 @@
-/*	$NetBSD: pci_machdep.h,v 1.9 2012/09/06 02:02:03 matt Exp $	*/
+/*	$NetBSD: pci_machdep.h,v 1.10 2014/03/29 19:28:26 christos Exp $	*/
 
 /*
  * Modified for arm32 by Mark Brinicombe
@@ -67,7 +67,8 @@ struct arm32_pci_chipset {
 	void		*pc_intr_v;
 	int		(*pc_intr_map)(const struct pci_attach_args *,
 			    pci_intr_handle_t *);
-	const char	*(*pc_intr_string)(void *, pci_intr_handle_t);
+	const char	*(*pc_intr_string)(void *, pci_intr_handle_t,
+			    char *, size_t);
 	const struct evcnt *(*pc_intr_evcnt)(void *, pci_intr_handle_t);
 	void		*(*pc_intr_establish)(void *, pci_intr_handle_t,
 			    int, int (*)(void *), void *);
@@ -98,8 +99,8 @@ struct arm32_pci_chipset {
     (*(c)->pc_conf_write)((c)->pc_conf_v, (t), (r), (v))
 #define	pci_intr_map(pa, ihp)						\
     (*(pa)->pa_pc->pc_intr_map)((pa), (ihp))
-#define	pci_intr_string(c, ih)						\
-    (*(c)->pc_intr_string)((c)->pc_intr_v, (ih))
+#define	pci_intr_string(c, ih, buf, len)				\
+    (*(c)->pc_intr_string)((c)->pc_intr_v, (ih), (buf), (len))
 #define	pci_intr_evcnt(c, ih)						\
     (*(c)->pc_intr_evcnt)((c)->pc_intr_v, (ih))
 #define	pci_intr_establish(c, ih, l, h, a)				\

sys/arch/arm/include/pio.h

@@ -1,4 +1,4 @@
-/*	$NetBSD: pio.h,v 1.2 2011/07/01 21:20:33 dyoung Exp $	*/
+/*	$NetBSD: pio.h,v 1.3 2014/01/29 00:42:15 matt Exp $	*/
 
 /*
  * Copyright 1997
@@ -33,8 +33,8 @@
  *    even if advised of the possibility of such damage.
  */
 
-#ifndef _ARM32_PIO_H_
-#define _ARM32_PIO_H_
+#ifndef _ARM_PIO_H_
+#define _ARM_PIO_H_
 
 #include <sys/bus.h>
 
@@ -43,4 +43,4 @@ extern struct bus_space isa_io_bs_tag;
 #define	inb(port)	 bus_space_read_1( &isa_io_bs_tag, (bus_space_handle_t)isa_io_bs_tag.bs_cookie, (port))
 #define	outb(port, byte) bus_space_write_1(&isa_io_bs_tag, (bus_space_handle_t)isa_io_bs_tag.bs_cookie, (port), (byte))
 
-#endif /* _ARM32_PIO_H_ */
+#endif /* _ARM_PIO_H_ */

sys/arch/arm/include/proc.h

@@ -1,4 +1,4 @@
-/*	$NetBSD: proc.h,v 1.15 2013/09/11 04:24:48 matt Exp $	*/
+/*	$NetBSD: proc.h,v 1.17 2014/02/24 16:57:57 christos Exp $	*/
 
 /*
  * Copyright (c) 1994 Mark Brinicombe.
@@ -32,8 +32,8 @@
  * SUCH DAMAGE.
  */
 
-#ifndef	_ARM32_PROC_H_
-#define	_ARM32_PROC_H_
+#ifndef _ARM_PROC_H_
+#define _ARM_PROC_H_
 
 /*
  * Machine-dependent part of the proc structure for arm.
@@ -61,4 +61,4 @@ struct mdproc {
 
 #define	PROC0_MD_INITIALIZERS .p_md = { .md_march = MACHINE_ARCH },
 
-#endif /* _ARM32_PROC_H_ */
+#endif /* _ARM_PROC_H_ */

sys/arch/arm/include/profile.h

@@ -1,4 +1,4 @@
-/*	$NetBSD: profile.h,v 1.13 2013/11/30 21:07:59 joerg Exp $	*/
+/*	$NetBSD: profile.h,v 1.17 2015/01/11 20:52:57 joerg Exp $	*/
 
 /*
  * Copyright (c) 2001 Ben Harris
@@ -76,9 +76,10 @@
 	/*								\
 	 * Restore registers that were trashed during mcount		\
 	 */								\
-	__asm("pop	{r0-r3, pc}");					\
+	__asm("pop	{r0-r3, lr}");					\
+	__asm("pop	{pc}");						\
 	__asm(".size	" MCOUNT_ASM_NAME ", .-" MCOUNT_ASM_NAME);
-#else
+#elif defined(__ARM_DWARF_EH__)
 #define	MCOUNT								\
 	__asm(".text");							\
 	__asm(".align	0");						\
@@ -86,16 +87,14 @@
 	__asm(".type	" MCOUNT_ASM_NAME ",%function");		\
 	__asm(".global	" MCOUNT_ASM_NAME);				\
 	__asm(MCOUNT_ASM_NAME ":");					\
-	__asm(".fnstart");						\
 	__asm(".cfi_startproc");					\
 	/*								\
 	 * Preserve registers that are trashed during mcount		\
 	 */								\
-	__asm("push	{r0-r4, ip, lr}");				\
-	__asm(".save {r0-r4, lr}");					\
+	__asm("push	{r0-r3, ip, lr}");				\
 	__asm(".cfi_def_cfa_offset 24");				\
 	__asm(".cfi_offset 14, -4");					\
-	__asm(".cfi_offset 4, -8");					\
+	__asm(".cfi_offset 12, -8");					\
 	__asm(".cfi_offset 3, -12");					\
 	__asm(".cfi_offset 2, -16");					\
 	__asm(".cfi_offset 1, -20");					\
@@ -118,7 +117,52 @@
 	/*								\
 	 * Restore registers that were trashed during mcount		\
 	 */								\
-	__asm("pop	{r0-r4, lr, pc}");				\
+	__asm("pop	{r0-r3, lr}");					\
+	__asm("pop	{pc}");						\
+	__asm(".cfi_endproc");						\
+	__asm(".size	" MCOUNT_ASM_NAME ", .-" MCOUNT_ASM_NAME);
+#else
+#define	MCOUNT								\
+	__asm(".text");							\
+	__asm(".align	0");						\
+	__asm(".arm");							\
+	__asm(".type	" MCOUNT_ASM_NAME ",%function");		\
+	__asm(".global	" MCOUNT_ASM_NAME);				\
+	__asm(MCOUNT_ASM_NAME ":");					\
+	__asm(".fnstart");						\
+	__asm(".cfi_startproc");					\
+	/*								\
+	 * Preserve registers that are trashed during mcount		\
+	 */								\
+	__asm("push	{r0-r3, ip, lr}");				\
+	__asm(".save {r0-r3, lr}");					\
+	__asm(".cfi_def_cfa_offset 24");				\
+	__asm(".cfi_offset 14, -4");					\
+	__asm(".cfi_offset 12, -8");					\
+	__asm(".cfi_offset 3, -12");					\
+	__asm(".cfi_offset 2, -16");					\
+	__asm(".cfi_offset 1, -20");					\
+	__asm(".cfi_offset 0, -24");					\
+	/*								\
+	 * find the return address for mcount,				\
+	 * and the return address for mcount's caller.			\
+	 *								\
+	 * frompcindex = pc pushed by call into self.			\
+	 */								\
+	__asm("mov	r0, ip");					\
+	/*								\
+	 * selfpc = pc pushed by mcount call				\
+	 */								\
+	__asm("mov	r1, lr");					\
+	/*								\
+	 * Call the real mcount code					\
+	 */								\
+	__asm("bl	" ___STRING(_C_LABEL(_mcount)) PLTSYM);		\
+	/*								\
+	 * Restore registers that were trashed during mcount		\
+	 */								\
+	__asm("pop	{r0-r3, lr}");					\
+	__asm("pop	{pc}");						\
 	__asm(".cfi_endproc");						\
 	__asm(".fnend");						\
 	__asm(".size	" MCOUNT_ASM_NAME ", .-" MCOUNT_ASM_NAME);

sys/arch/arm/include/ptrace.h

@@ -1,4 +1,4 @@
-/*	$NetBSD: ptrace.h,v 1.6 2012/12/05 19:05:46 matt Exp $	*/
+/*	$NetBSD: ptrace.h,v 1.8 2015/09/25 16:05:17 christos Exp $	*/
 
 /*
  * Copyright (c) 1995 Frank Lancaster
@@ -51,3 +51,12 @@
 	"old PT_SETFPREGS", \
 	"PT_GETFPREGS", \
 	"PT_SETFPREGS",
+
+#include <machine/reg.h>
+#define PTRACE_REG_PC(r)	(r)->r_pc
+#define PTRACE_REG_SET_PC(r, v)	(r)->r_pc = (v)
+#define PTRACE_REG_SP(r)	(r)->r_sp
+#define PTRACE_REG_INTRV(r)	(r)->r[0]
+
+#define PTRACE_BREAKPOINT	((const uint8_t[]) { 0xe7, 0xff, 0xff, 0xff })
+#define PTRACE_BREAKPOINT_SIZE	4

sys/arch/arm/include/reg.h

@@ -1,4 +1,4 @@
-/*	$NetBSD: reg.h,v 1.5 2013/01/11 14:04:55 matt Exp $	*/
+/*	$NetBSD: reg.h,v 1.6 2014/01/29 00:42:15 matt Exp $	*/
 
 /*
  * Copyright (C) 1994, 1995 Frank Lancaster
@@ -33,8 +33,8 @@
  *	@(#)reg.h	5.5 (Berkeley) 1/18/91
  */
 
-#ifndef _ARM32_REG_H_
-#define _ARM32_REG_H_
+#ifndef _ARM_REG_H_
+#define _ARM_REG_H_
 
 struct reg {
 	unsigned int r[13];
@@ -57,4 +57,4 @@ struct fpreg {
 };
 
 
-#endif /* !_ARM32_REG_H_ */
+#endif /* !_ARM_REG_H_ */

sys/arch/arm/include/rwlock.h

@@ -1,4 +1,4 @@
-/*	$NetBSD: rwlock.h,v 1.5 2008/04/28 20:23:14 martin Exp $	*/
+/*	$NetBSD: rwlock.h,v 1.9 2015/02/25 13:52:42 joerg Exp $	*/
 
 /*-
  * Copyright (c) 2002, 2006 The NetBSD Foundation, Inc.
@@ -40,14 +40,21 @@ struct krwlock {
 
 #define	__HAVE_SIMPLE_RW_LOCKS		1
 
+#ifdef MULTIPROCESSOR
+#ifdef _ARM_ARCH_7
+#define	RW_RECEIVE(rw)			__asm __volatile("dmb" ::: "memory")
+#define	RW_GIVE(rw)			__asm __volatile("dsb" ::: "memory")
+#else
+#define	RW_RECEIVE(rw)			membar_consumer()
+#define	RW_GIVE(rw)			membar_producer()
+#endif
+#else
 #define	RW_RECEIVE(rw)			/* nothing */
 #define	RW_GIVE(rw)			/* nothing */
-
-unsigned long	_lock_cas(volatile unsigned long *,
-    unsigned long, unsigned long);
+#endif
 
 #define	RW_CAS(p, o, n)			\
-    (_lock_cas((volatile unsigned long *)(p), (o), (n)) == (o))
+    (atomic_cas_ulong((volatile unsigned long *)(p), (o), (n)) == (o))
 
 #endif	/* __RWLOCK_PRIVATE */
 

sys/arch/arm/include/signal.h

@@ -1,4 +1,4 @@
-/*	$NetBSD: signal.h,v 1.12 2011/06/30 20:09:20 wiz Exp $	*/
+/*	$NetBSD: signal.h,v 1.13 2014/01/29 00:42:15 matt Exp $	*/
 
 /*
  * Copyright (c) 1994-1996 Mark Brinicombe.
@@ -43,8 +43,8 @@
  * Created      : 30/09/94
  */
 
-#ifndef _ARM32_SIGNAL_H_
-#define _ARM32_SIGNAL_H_
+#ifndef _ARM_SIGNAL_H_
+#define _ARM_SIGNAL_H_
 
 #include <sys/featuretest.h>
 

sys/arch/arm/include/sljit_machdep.h

@@ -0,0 +1,59 @@
+/*	$NetBSD: sljit_machdep.h,v 1.1 2014/07/23 18:19:43 alnsn Exp $	*/
+
+/*-
+ * Copyright (c) 2014 Alexander Nasonov.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _ARM_SLJITARCH_H
+#define _ARM_SLJITARCH_H
+
+#include <sys/cdefs.h>
+
+#ifdef _KERNEL
+#include <machine/types.h>
+#include <arm/cpufunc.h>
+#else
+#include <stddef.h>
+#include <stdint.h>
+#include <arm/sysarch.h>
+#endif
+
+#if defined(_ARM_ARCH_T2)
+#define SLJIT_CONFIG_ARM_THUMB2 1
+#elif defined(_ARM_ARCH_7)
+#define SLJIT_CONFIG_ARM_V7 1
+#else
+#define SLJIT_CONFIG_ARM_V5 1
+#endif
+
+#ifdef _KERNEL
+#define SLJIT_CACHE_FLUSH(from, to) \
+	cpu_icache_sync_range((vaddr_t)(from), (vsize_t)((to) - (from)))
+#else
+#define SLJIT_CACHE_FLUSH(from, to) \
+	(void)arm_sync_icache((uintptr_t)(from), (size_t)((to) - (from)))
+#endif
+
+#endif

sys/arch/arm/include/sysarch.h

@@ -1,4 +1,4 @@
-/*	$NetBSD: sysarch.h,v 1.10 2013/02/01 15:23:11 matt Exp $	*/
+/*	$NetBSD: sysarch.h,v 1.12 2015/03/09 11:03:19 joerg Exp $	*/
 
 /*
  * Copyright (c) 1996-1997 Mark Brinicombe.
@@ -38,13 +38,19 @@
 #include <sys/cdefs.h>
 
 /*
- * Pickup definition of uintptr_t
+ * Pickup definition of size_t and uintptr_t
  */
+#include <machine/ansi.h>
 #include <sys/stdint.h>
 #ifndef _KERNEL
 #include <stdbool.h>
 #endif
 
+#ifdef	_BSD_SIZE_T_
+typedef	_BSD_SIZE_T_ size_t;
+#undef	_BSD_SIZE_T_
+#endif
+
 /*
  * Architecture specific syscalls (arm)
  */
@@ -70,7 +76,7 @@ struct arm_unaligned_faults_args {
 
 #ifndef _KERNEL
 __BEGIN_DECLS
-int	arm_sync_icache(u_int addr, int len);
+int	arm_sync_icache(uintptr_t, size_t);
 int	arm_drain_writebuf(void);
 int	sysarch(int, void *);
 __END_DECLS

sys/arch/arm/include/trap.h

@@ -1,4 +1,4 @@
-/*	$NetBSD: trap.h,v 1.8 2008/01/19 13:11:09 chris Exp $	*/
+/*	$NetBSD: trap.h,v 1.9 2014/03/15 05:54:20 ozaki-r Exp $	*/
 
 /*
  * Copyright (c) 1995 Mark Brinicombe.
@@ -62,6 +62,14 @@
 #define GDB_THUMB_BREAKPOINT	0xdefe		/* Thumb in GDB */
 #define KERNEL_BREAKPOINT	0xe7ffffff	/* Used by DDB */
 
+/*
+ * DTrace uses 0xe7fffef0 to 0xe7fffeff as breakpoints.
+ * The first byte is used to encode a cond value.
+ */
+#define DTRACE_BREAKPOINT	0xe7fffef0
+#define DTRACE_BREAKPOINT_MASK	0xfffffff0
+#define DTRACE_IS_BREAKPOINT(insn)	((insn & DTRACE_BREAKPOINT_MASK) == DTRACE_BREAKPOINT)
+
 #define KBPT_ASM		".word 0xe7ffdefe"
 
 #define USER_BREAKPOINT		GDB_BREAKPOINT

sys/arch/arm/include/types.h

@@ -1,4 +1,4 @@
-/*	$NetBSD: types.h,v 1.25 2013/07/02 05:57:00 matt Exp $	*/
+/*	$NetBSD: types.h,v 1.30 2015/08/27 12:30:50 pooka Exp $	*/
 
 /*
  * Copyright (c) 1990 The Regents of the University of California.
@@ -46,9 +46,6 @@ typedef struct label_t {	/* Used by setjmp & longjmp */
          
 /* NB: This should probably be if defined(_KERNEL) */
 #if defined(_NETBSD_SOURCE)
-typedef	unsigned long	vm_offset_t;	/* depreciated */
-typedef	unsigned long	vm_size_t;	/* depreciated */
-
 typedef unsigned long	paddr_t;
 typedef unsigned long	psize_t;
 typedef unsigned long	vaddr_t;
@@ -74,9 +71,9 @@ typedef unsigned short	tlb_asid_t;
  * to user-space, we don't want ABI breakage there.
  */
 #if defined(_KERNEL)
-typedef volatile unsigned char	__cpu_simple_lock_t;
+typedef unsigned char	__cpu_simple_lock_nv_t;
 #else
-typedef	volatile int		__cpu_simple_lock_t;
+typedef	int		__cpu_simple_lock_nv_t;
 #endif /* _KERNEL */
 
 #define	__SIMPLELOCK_LOCKED	1
@@ -92,6 +89,9 @@ typedef	volatile int		__cpu_simple_lock_t;
 #define	__HAVE_TLS_VARIANT_I
 #endif /* !defined(__minix) */
 #define	__HAVE_OLD_DISKLABEL
+#if defined(__ARM_EABI__) && defined(_ARM_ARCH_6)
+#define	__HAVE_ATOMIC64_OPS
+#endif
 
 #if defined(_KERNEL) || defined(_KMEMUSER)
 #define	PCU_FPU			0

sys/arch/arm/include/vfpreg.h

@@ -1,4 +1,4 @@
-/*      $NetBSD: vfpreg.h,v 1.10 2013/08/02 01:59:00 matt Exp $ */
+/*      $NetBSD: vfpreg.h,v 1.14 2015/02/09 07:55:52 slp Exp $ */
 
 /*
  * Copyright (c) 2008 ARM Ltd
@@ -29,10 +29,10 @@
  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#ifndef _VFPREG_H
-#define _VFPREG_H
+#ifndef _ARM_VFPREG_H_
+#define _ARM_VFPREG_H_
 
-/* FPSID regsiter */
+/* FPSID register */
 
 #define VFP_FPSID_IMP_MSK	0xff000000	/* Implementer */
 #define VFP_FPSID_IMP_ARM	0x41000000	/* Implementer: ARM */
@@ -64,6 +64,8 @@
 #define FPU_VFP_CORTEXA8	0x410330c0
 #define FPU_VFP_CORTEXA9	0x41033090
 #define FPU_VFP_CORTEXA15	0x410330f0
+#define FPU_VFP_CORTEXA15_QEMU	0x410430f0
+#define FPU_VFP_MV88SV58XX	0x56022090
 
 #define VFP_FPEXC_EX		0x80000000	/* EXception status bit */
 #define VFP_FPEXC_EN		0x40000000	/* VFP Enable bit */
@@ -78,7 +80,7 @@
 #define VFP_FPEXC_OFF		0x00000004	/* Potential overflow flag */
 #define VFP_FPEXC_DZF		0x00000002	/* Potential DivByZero flag */
 #define VFP_FPEXC_IOF		0x00000001	/* Potential inv. op. flag */
-#define VFP_FPEXE_FSUM		0x000000ff	/* all flag bits */
+#define VFP_FPEXC_FSUM		0x000000ff	/* all flag bits */
 
 #define VFP_FPSCR_N	0x80000000	/* set if compare <= result */
 #define VFP_FPSCR_Z	0x40000000	/* set if compare = result */
@@ -110,4 +112,4 @@
 #define VFP_FPSCR_DZC	0x00000002	/* DivByZero Cumulative Flag */
 #define VFP_FPSCR_IOC	0x00000001	/* Invalid Operation Cumulative Flag */
 
-#endif /* _VFPREG_H */
+#endif /* _ARM_VFPREG_H_ */

sys/arch/evbarm/Makefile

@@ -1,4 +1,4 @@
-#	$NetBSD: Makefile,v 1.9 2012/07/26 06:21:57 skrll Exp $
+#	$NetBSD: Makefile,v 1.10 2015/01/23 12:34:09 hkenken Exp $
 
 # Makefile for evbarm tags file and boot blocks
 
@@ -39,6 +39,7 @@ SEVBARM+=	${SYSDIR}/arch/evbarm/smdk2xx0/*.[ch]
 SEVBARM+=	${SYSDIR}/arch/evbarm/tisdp24xx/*.[ch]
 SEVBARM+=	${SYSDIR}/arch/evbarm/tsarm/*.[ch]
 SEVBARM+=	${SYSDIR}/arch/evbarm/viper/*.[ch]
+SEVBARM+=	${SYSDIR}/arch/evbarm/zynq/*.[ch]
 SEVBARM+=	${SYSDIR}/arch/arm/xscale/*.[ch]
 
 AEVBARM=	${SYSDIR}/arch/evbarm/adi_brh/*.S
@@ -66,6 +67,7 @@ AEVBARM+=	${SYSDIR}/arch/arm/xscale/*.S
 AEVBARM+=	${SYSDIR}/arch/evbarm/integrator/*.S
 AEVBARM+=	${SYSDIR}/arch/evbarm/iq80310/*.S
 AEVBARM+=	${SYSDIR}/arch/evbarm/iq80321/*.S
+AEVBARM+=	${SYSDIR}/arch/evbarm/zynq/*.S
 
 # Directories in which to place tags links
 DEVBARM=	include

sys/arch/evbarm/include/Makefile

@@ -1,7 +1,7 @@
-#	$NetBSD: Makefile,v 1.20 2013/05/02 03:56:40 matt Exp $
+#	$NetBSD: Makefile,v 1.22 2014/07/23 18:19:43 alnsn Exp $
 
 INCSDIR=	/usr/include/evbarm
 
-INCS=
+INCS=		sljit_machdep.h
 
 .include "../../arm/include/Makefile.common"

sys/arch/evbarm/include/autoconf.h

@@ -1,4 +1,4 @@
-/*	$NetBSD: autoconf.h,v 1.7 2012/10/27 17:17:48 chs Exp $	*/
+/*	$NetBSD: autoconf.h,v 1.8 2014/05/10 20:12:16 reinoud Exp $	*/
 
 /*-
  * Copyright (c) 2001 The NetBSD Foundation, Inc.
@@ -39,5 +39,6 @@ struct mainbus_attach_args {
 #endif
 
 extern void (*evbarm_device_register)(device_t, void *);
+extern void (*evbarm_device_register_post_config)(device_t, void *);
 
 #endif	/* _EVBARM_AUTOCONF_H_ */

sys/arch/evbarm/include/intr.h

@@ -1,4 +1,4 @@
-/*	$NetBSD: intr.h,v 1.24 2012/11/08 08:19:50 skrll Exp $	*/
+/*	$NetBSD: intr.h,v 1.26 2014/03/13 23:48:38 matt Exp $	*/
 
 /*
  * Copyright (c) 2001, 2003 Wasabi Systems, Inc.
@@ -65,6 +65,8 @@
 #define IST_EDGE_BOTH	6
 #define IST_SOFT	7
 
+#define IST_MPSAFE	0x100	/* interrupt is MPSAFE */
+
 #ifndef _LOCORE
 
 #include <sys/queue.h>
@@ -74,9 +76,6 @@
 int	_splraise(int);
 int	_spllower(int);
 void	splx(int);
-#ifdef __HAVE_FAST_SOFTINTS
-void	_setsoftintr(int);
-#endif
 
 #else	/* _LKM */
 

sys/arch/evbarm/include/loadfile_machdep.h

@@ -9,9 +9,14 @@
 #define READ(f, b, c)		read((f), (void*)LOADADDR(b), (c))
 #define BCOPY(s, d, c)		memcpy((void*)LOADADDR(d), (void*)(s), (c))
 #define BZERO(d, c)		memset((void*)LOADADDR(d), 0, (c))
-#define WARN(a)			(void)(printf a,			\
-				       printf((errno ? ": %s\n" : "\n"), \
-					      strerror(errno)))
+#define	WARN(a)			do { \
+					(void)printf a; \
+					if (errno) \
+						(void)printf(": %s\n", \
+						             strerror(errno)); \
+					else \
+						(void)printf("\n"); \
+				} while(/* CONSTCOND */0)
 #define PROGRESS(a)		(void)printf a
 #define ALLOC(a)		alloc(a)
 #define DEALLOC(a, b)		dealloc(a, b)

sys/arch/evbarm/include/sljit_machdep.h

@@ -0,0 +1,3 @@
+/*	$NetBSD: sljit_machdep.h,v 1.1 2014/07/23 18:19:43 alnsn Exp $	*/
+
+#include <arm/sljit_machdep.h>

sys/arch/evbarm/include/vmparam.h

@@ -1,4 +1,4 @@
-/*	$NetBSD: vmparam.h,v 1.28 2012/02/18 16:29:37 christos Exp $	*/
+/*	$NetBSD: vmparam.h,v 1.29 2015/02/23 20:34:38 joerg Exp $	*/
 
 /*
  * Copyright (c) 1988 The Regents of the University of California.
@@ -50,11 +50,6 @@
 #define	KERNEL_BASE		0x80000000
 #endif
 
-/*
- * Override the default pager_map size, there's not enough KVA.
- */
-#define PAGER_MAP_DEFAULT_SIZE		(4 * 1024 * 1024)
-
 /*
  * Size of User Raw I/O map
  */

sys/arch/i386/Makefile

@@ -1,4 +1,4 @@
-#	$NetBSD: Makefile,v 1.42 2011/09/02 22:12:48 dyoung Exp $
+#	$NetBSD: Makefile,v 1.43 2012/10/23 16:08:12 dyoung Exp $
 
 # Makefile for i386 tags file and boot blocks
 
@@ -35,10 +35,10 @@ DI386=	i386 eisa isa include pci
 
 tags:
 	-rm -f ${TI386}
-	-echo ${SI386} | xargs ctags -wadtf ${TI386}
+	-echo ${SI386} | xargs $(TOOL_CTAGS) -wadtf ${TI386}
 	-find -H ${SYSDIR}/external/bsd/acpica/dist/ -name '*.[ch]' | \
-	    sort -t / -u | xargs ctags -wadtf ${TI386}
-	-${FINDCOMM} | xargs ctags -wadtf ${TI386}
+	    sort -t / -u | xargs $(TOOL_CTAGS) -wadtf ${TI386}
+	-${FINDCOMM} | xargs $(TOOL_CTAGS) -wadtf ${TI386}
 	egrep "^ENTRY(.*)|^ALTENTRY(.*)" ${AI386} | \
 	    ${TOOL_SED} -e \
 	"s;\([^:]*\):\([^(]*\)(\([^, )]*\)\(.*\);\3	\1	/^\2(\3\4$$/;" \

sys/arch/i386/conf/stand.ldscript

@@ -1,4 +1,4 @@
-/*	$NetBSD: stand.ldscript,v 1.1 2013/11/01 00:19:04 christos Exp $	*/
+/*	$NetBSD: stand.ldscript,v 1.5 2015/08/22 23:49:54 uebayasi Exp $	*/
 
 OUTPUT_FORMAT("elf32-i386-minix", "elf32-i386-minix",
 	      "elf32-i386-minix")
@@ -6,59 +6,59 @@ OUTPUT_ARCH(i386)
 ENTRY(_start)
 SECTIONS
 {
-   /* Read-only sections, merged into text segment: */
-   .text :
-   AT (ADDR(.text) & 0x0fffffff)
-   {
-     *(.text)
-     *(.text.*)
-     *(.stub)
-   } =0
-   _etext = . ;
-   PROVIDE (etext = .) ;
+  /* Read-only sections, merged into text segment: */
+  .text :
+  {
+    *(.text)
+    *(.text.*)
+    *(.stub)
+  }
+  _etext = . ;
+  PROVIDE (etext = .) ;
 
-   .rodata :
-   AT (LOADADDR(.text) + (ADDR(.rodata) - ADDR(.text)))
-   {
-     *(.rodata)
-     *(.rodata.*)
-   }
+  .rodata :
+  {
+    *(.rodata)
+    *(.rodata.*)
+  }
 
-   __data_start = . ;
-   .data :
-   AT (LOADADDR(.text) + (ADDR(.data) - ADDR(.text)))
-   {
-     *(.data)
-   }
-   .data.cacheline_aligned :
-   AT (LOADADDR(.text) + (ADDR(.data.cacheline_aligned) - ADDR(.text)))
-   {
-     *(.data.cacheline_aligned)
-   }
-   .data.read_mostly :
-   AT (LOADADDR(.text) + (ADDR(.data.read_mostly) - ADDR(.text)))
-   {
-     *(.data.read_mostly)
-   }
-   _edata = . ;
-   PROVIDE (edata = .) ;
-   __bss_start = . ;
-   .bss :
-   AT (LOADADDR(.text) + (ADDR(.bss) - ADDR(.text)))
-   {
-     *(.bss)
-     *(.bss.*)
-     *(COMMON)
-     . = ALIGN(32 / 8);
-   }
-   . = ALIGN(32 / 8);
+  __data_start = . ;
+  .data :
+  {
+    *(.data)
+  }
+  .data.cacheline_aligned :
+  {
+    *(.data.cacheline_aligned)
+  }
+  .data.read_mostly :
+  {
+    *(.data.read_mostly)
+  }
+  _edata = . ;
+  PROVIDE (edata = .) ;
+  __bss_start = . ;
+  .bss :
+  {
+    *(.bss)
+    *(.bss.*)
+    *(COMMON)
+    . = ALIGN(32 / 8);
+  }
+  . = ALIGN(32 / 8);
   _end = . ;
   PROVIDE (end = .) ;
   /DISCARD/ : {
     *(.eh_frame_hdr)
     *(.eh_frame)
-    *(.rel.eh_frame)
-    *(.rela.eh_frame)
     *(.note.netbsd.ident)
   }
 }
+SECTIONS
+{
+  .text :
+  AT (ADDR(.text) & 0x0fffffff)
+  {
+    *(.text)
+  } =0
+}

sys/arch/i386/include/Makefile

@@ -1,29 +1,28 @@
-#	$NetBSD: Makefile,v 1.41 2012/11/05 00:57:42 alnsn Exp $
+#	$NetBSD: Makefile,v 1.43 2014/07/23 18:19:44 alnsn Exp $
 
 INCSDIR= /usr/include/i386
 
-INCS=	ansi.h asm.h \
-	bootinfo.h bswap.h byte_swap.h \
-	cdefs.h cpu.h \
+INCS=	ansi.h aout_machdep.h apmvar.h asm.h \
+	bioscall.h bootinfo.h bswap.h byte_swap.h \
+	cdefs.h cpu.h cputypes.h \
 	disklabel.h \
 	elf_machdep.h endian.h endian_machdep.h \
-	fenv.h float.h frame.h  \
-	\
-	ieee.h ieeefp.h \
+	fenv.h float.h frame.h freebsd_machdep.h \
+	gdt.h \
+	ibcs2_machdep.h ieee.h ieeefp.h \
 	int_const.h int_fmtio.h int_limits.h int_mwgwtypes.h int_types.h \
-	\
-	\
-	\
+	intr.h intrdefs.h \
+	joystick.h \
+	kcore.h \
 	limits.h lock.h \
-	math.h mcontext.h mutex.h multiboot.h \
-	npx.h \
-	param.h pcb.h pio.h proc.h profile.h \
-	ptrace.h \
-	rwlock.h \
-	segments.h setjmp.h signal.h \
-	sysarch.h \
+	math.h mcontext.h mutex.h mtrr.h multiboot.h \
+	param.h pcb.h pio.h pmap.h pmc.h proc.h profile.h psl.h \
+	pte.h ptrace.h \
+	reg.h rwlock.h \
+	segments.h setjmp.h signal.h sljit_machdep.h specialreg.h spkr.h \
+	svr4_machdep.h sysarch.h \
 	trap.h tss.h types.h \
-	vmparam.h \
+	vm86.h vmparam.h \
 	wchar_limits.h
 
 .include <bsd.kinc.mk>

sys/arch/i386/include/Makefile.inc

@@ -0,0 +1,11 @@
+# $NetBSD: Makefile.inc,v 1.3 2014/10/19 15:41:05 joerg Exp $
+
+CFLAGS+=	-msoft-float
+CFLAGS+=	-mno-mmx -mno-sse -mno-avx
+
+# this should really be !(RUMPKERNEL && PIC)
+.if !defined(RUMPKERNEL)
+CFLAGS+=	-fno-omit-frame-pointer
+.endif
+
+USE_SSP?=	yes

sys/arch/i386/include/acpi_machdep.h

@@ -0,0 +1,3 @@
+/*	$NetBSD: acpi_machdep.h,v 1.7 2003/05/11 18:18:08 fvdl Exp $	*/
+
+#include <x86/acpi_machdep.h>

sys/arch/i386/include/ansi.h

@@ -1,4 +1,4 @@
-/*	$NetBSD: ansi.h,v 1.25 2011/07/17 20:54:41 joerg Exp $	*/
+/*	$NetBSD: ansi.h,v 1.27 2015/06/17 14:32:31 martin Exp $	*/
 
 /*-
  * Copyright (c) 1990, 1993
@@ -47,7 +47,7 @@
  *	#undef	_BSD_SIZE_T_
  *	#endif
  */
-#define	_BSD_CLOCK_T_		unsigned long	/* clock() */
+#define	_BSD_CLOCK_T_		unsigned int	/* clock() */
 #define	_BSD_PTRDIFF_T_		int		/* ptr1 - ptr2 */
 #define	_BSD_SIZE_T_		unsigned int	/* sizeof() */
 #define	_BSD_SSIZE_T_		int		/* byte count or error */
@@ -56,7 +56,16 @@
 #define	_BSD_TIMER_T_		int		/* timer_t */
 #define	_BSD_SUSECONDS_T_	int		/* suseconds_t */
 #define	_BSD_USECONDS_T_	unsigned int	/* useconds_t */
+
+#if defined(__WCHAR_TYPE__)
+#define	_BSD_WCHAR_T_		__WCHAR_TYPE__	/* wchar_t */
+#else
 #define	_BSD_WCHAR_T_		int		/* wchar_t */
+#endif
+#if defined(__WINT_TYPE__)
+#define	_BSD_WINT_T_		__WINT_TYPE__	/* wint_t */
+#else
 #define	_BSD_WINT_T_		int		/* wint_t */
+#endif
 
 #endif	/* _I386_ANSI_H_ */

sys/arch/i386/include/aout_machdep.h

@@ -0,0 +1,3 @@
+/*	$NetBSD: aout_machdep.h,v 1.8 2003/02/26 21:28:59 fvdl Exp $	*/
+
+#include <x86/aout_machdep.h>

sys/arch/i386/include/apicvar.h

@@ -0,0 +1,3 @@
+/*	$NetBSD: apicvar.h,v 1.4 2003/02/26 21:28:59 fvdl Exp $	*/
+
+#include <x86/apicvar.h>

sys/arch/i386/include/apmvar.h

@@ -0,0 +1,39 @@
+/*	$NetBSD: apmvar.h,v 1.26 2012/10/01 17:30:39 dsl Exp $	*/
+/*-
+ * Copyright (c) 1995 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by John Kohl.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __I386_APM_H__
+#define __I386_APM_H__
+
+#include <dev/apm/apmbios.h>
+
+#ifndef _LOCORE
+#include <dev/apm/apmio.h>
+#endif /* _LCORE */
+
+#endif /* __i386_apm_h__ */

sys/arch/i386/include/autoconf.h

@@ -0,0 +1,3 @@
+/*	$NetBSD: autoconf.h,v 1.3 2011/10/18 23:25:20 dyoung Exp $	*/
+
+#include <x86/autoconf.h>

sys/arch/i386/include/bios32.h

@@ -0,0 +1,3 @@
+/*	$NetBSD: bios32.h,v 1.2 2003/02/26 21:28:59 fvdl Exp $	*/
+
+#include <x86/bios32.h>

sys/arch/i386/include/bioscall.h

@@ -0,0 +1,102 @@
+/*	$NetBSD: bioscall.h,v 1.11 2008/04/28 20:23:24 martin Exp $ */
+
+/*-
+ * Copyright (c) 1997, 2000 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by John Kohl and Jason R. Thorpe.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __I386_BIOSCALL_H__
+#define __I386_BIOSCALL_H__
+
+/*
+ * virtual & physical address of the trampoline
+ * that we use: page 1.
+ */
+#define BIOSTRAMP_BASE	PAGE_SIZE
+
+#ifndef _LOCORE
+#define	BIOSREG_LO	0
+#define	BIOSREG_HI	1
+
+typedef	union {
+	u_char biosreg_quarter[4];
+	u_short biosreg_half[2];
+	u_int biosreg_long;
+} bios_reg;
+
+struct bioscallregs {
+    bios_reg r_ax;
+    bios_reg r_bx;
+    bios_reg r_cx;
+    bios_reg r_dx;
+    bios_reg r_si;
+    bios_reg r_di;
+    bios_reg r_flags;
+    bios_reg r_es;
+};
+
+#define	AL	r_ax.biosreg_quarter[BIOSREG_LO]
+#define	AH	r_ax.biosreg_quarter[BIOSREG_HI]
+#define	AX	r_ax.biosreg_half[BIOSREG_LO]
+#define	AX_HI	r_ax.biosreg_half[BIOSREG_HI]
+#define	EAX	r_ax.biosreg_long
+
+#define	BL	r_bx.biosreg_quarter[BIOSREG_LO]
+#define	BH	r_bx.biosreg_quarter[BIOSREG_HI]
+#define	BX	r_bx.biosreg_half[BIOSREG_LO]
+#define	BX_HI	r_bx.biosreg_half[BIOSREG_HI]
+#define	EBX	r_bx.biosreg_long
+
+#define	CL	r_cx.biosreg_quarter[BIOSREG_LO]
+#define	CH	r_cx.biosreg_quarter[BIOSREG_HI]
+#define	CX	r_cx.biosreg_half[BIOSREG_LO]
+#define	CX_HI	r_cx.biosreg_half[BIOSREG_HI]
+#define	ECX	r_cx.biosreg_long
+
+#define	DL	r_dx.biosreg_quarter[BIOSREG_LO]
+#define	DH	r_dx.biosreg_quarter[BIOSREG_HI]
+#define	DX	r_dx.biosreg_half[BIOSREG_LO]
+#define	DX_HI	r_dx.biosreg_half[BIOSREG_HI]
+#define	EDX	r_dx.biosreg_long
+
+#define	SI	r_si.biosreg_half[BIOSREG_LO]
+#define	SI_HI	r_si.biosreg_half[BIOSREG_HI]
+#define	ESI	r_si.biosreg_long
+
+#define	DI	r_di.biosreg_half[BIOSREG_LO]
+#define	DI_HI	r_di.biosreg_half[BIOSREG_HI]
+#define	EDI	r_di.biosreg_long
+
+#define	FLAGS	 r_flags.biosreg_half[BIOSREG_LO]
+#define	FLAGS_HI r_flags.biosreg_half[BIOSREG_HI]
+#define	EFLAGS	 r_flags.biosreg_long
+
+#define ES	r_es.biosreg_half[BIOSREG_LO]
+
+void bioscall(int /* function*/ , struct bioscallregs * /* regs */);
+#endif
+#endif /* __I386_BIOSCALL_H__ */

sys/arch/i386/include/bus_defs.h

@@ -0,0 +1,3 @@
+/*	$NetBSD: bus_defs.h,v 1.1 2011/07/01 17:09:59 dyoung Exp $	*/
+
+#include <x86/bus_defs.h>

sys/arch/i386/include/bus_funcs.h

@@ -0,0 +1,3 @@
+/*	$NetBSD: bus_funcs.h,v 1.1 2011/07/01 17:09:59 dyoung Exp $	*/
+
+#include <x86/bus_funcs.h>

sys/arch/i386/include/bus_private.h

@@ -0,0 +1,3 @@
+/*	$NetBSD: bus_private.h,v 1.2 2005/12/11 12:17:43 christos Exp $	*/
+
+#include <x86/bus_private.h>

sys/arch/i386/include/clock.h

@@ -0,0 +1 @@
+/* $NetBSD: clock.h,v 1.2 2006/06/07 22:37:58 kardel Exp $ */

sys/arch/i386/include/coff_machdep.h

@@ -0,0 +1,38 @@
+/*	$NetBSD: coff_machdep.h,v 1.2 2008/04/28 20:23:24 martin Exp $	*/
+
+/*-
+ * Copyright (c) 1997 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Charles M. Hannum.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _I386_COFF_MACHDEP_H_
+#define _I386_COFF_MACHDEP_H_
+
+#define COFF_MAGIC_I386	0x14c
+#define	COFF_BADMAG(ex)	(ex->f_magic != COFF_MAGIC_I386)
+
+#endif /* !_I386_COFF_MACHDEP_H_ */

sys/arch/i386/include/cpu_counter.h

@@ -0,0 +1,29 @@
+/*	$NetBSD: cpu_counter.h,v 1.9 2008/05/10 14:53:54 ad Exp $	*/
+
+/*-
+ * Copyright (c) 2008 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <x86/cpu_counter.h>

sys/arch/i386/include/cpufunc.h

@@ -0,0 +1,3 @@
+/*	$NetBSD: cpufunc.h,v 1.40 2007/10/17 19:54:56 garbled Exp $	*/
+
+#include <x86/cpufunc.h>

sys/arch/i386/include/cputypes.h

@@ -0,0 +1,3 @@
+/*	$NetBSD: cputypes.h,v 1.15 2007/01/01 20:56:59 ad Exp $	*/
+
+#include <x86/cputypes.h>

sys/arch/i386/include/cpuvar.h

@@ -0,0 +1,3 @@
+/* 	$NetBSD: cpuvar.h,v 1.5 2003/03/01 18:30:03 fvdl Exp $ */
+
+#include <x86/cpuvar.h>

sys/arch/i386/include/db_machdep.h

@@ -0,0 +1,155 @@
+/*	$NetBSD: db_machdep.h,v 1.30 2011/05/26 15:34:13 joerg Exp $	*/
+
+/* 
+ * Mach Operating System
+ * Copyright (c) 1991,1990 Carnegie Mellon University
+ * All Rights Reserved.
+ * 
+ * Permission to use, copy, modify and distribute this software and its
+ * documentation is hereby granted, provided that both the copyright
+ * notice and this permission notice appear in all copies of the
+ * software, derivative works or modified versions, and any portions
+ * thereof, and that both notices appear in supporting documentation.
+ * 
+ * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
+ * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
+ * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
+ * 
+ * Carnegie Mellon requests users of this software to return to
+ * 
+ *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
+ *  School of Computer Science
+ *  Carnegie Mellon University
+ *  Pittsburgh PA 15213-3890
+ * 
+ * any improvements or extensions that they make and grant Carnegie Mellon
+ * the rights to redistribute these changes.
+ */
+
+#ifndef	_I386_DB_MACHDEP_H_
+#define	_I386_DB_MACHDEP_H_
+
+/*
+ * Machine-dependent defines for new kernel debugger.
+ */
+
+#if defined(_KERNEL_OPT)
+#include "opt_multiprocessor.h"
+#endif
+#include <sys/param.h>
+#include <uvm/uvm_extern.h>
+#include <machine/trap.h>
+
+typedef	vaddr_t		db_addr_t;	/* address - unsigned */
+#define	DDB_EXPR_FMT	"l"		/* expression is long */
+typedef	long		db_expr_t;	/* expression - signed */
+
+typedef struct trapframe db_regs_t;
+
+struct i386_frame {
+	struct i386_frame	*f_frame;
+	int			f_retaddr;
+	int			f_arg0;
+};
+
+#ifndef MULTIPROCESSOR
+extern db_regs_t ddb_regs;	/* register state */
+#define	DDB_REGS	(&ddb_regs)
+#else
+extern db_regs_t *ddb_regp;
+#define DDB_REGS	(ddb_regp)
+#define ddb_regs	(*ddb_regp)
+#endif
+
+#define	PC_REGS(regs)	((regs)->tf_eip)
+
+#define	BKPT_ADDR(addr)	(addr)		/* breakpoint address */
+#define	BKPT_INST	0xcc		/* breakpoint instruction */
+#define	BKPT_SIZE	(1)		/* size of breakpoint inst */
+#define	BKPT_SET(inst, addr)	(BKPT_INST)
+
+#define	FIXUP_PC_AFTER_BREAK(regs)	((regs)->tf_eip -= BKPT_SIZE)
+
+#define	db_clear_single_step(regs)	((regs)->tf_eflags &= ~PSL_T)
+#define	db_set_single_step(regs)	((regs)->tf_eflags |=  PSL_T)
+
+#define	IS_BREAKPOINT_TRAP(type, code)	((type) == T_BPTFLT)
+#define IS_WATCHPOINT_TRAP(type, code)	((type) == T_TRCTRAP && (code) & 15)
+
+#define	I_CALL		0xe8
+#define	I_CALLI		0xff
+#define	I_RET		0xc3
+#define	I_IRET		0xcf
+
+#define	inst_trap_return(ins)	(((ins)&0xff) == I_IRET)
+#define	inst_return(ins)	(((ins)&0xff) == I_RET)
+#define	inst_call(ins)		(((ins)&0xff) == I_CALL || \
+				 (((ins)&0xff) == I_CALLI && \
+				  ((ins)&0x3800) == 0x1000))
+#define inst_load(ins)		0
+#define inst_store(ins)		0
+
+/* access capability and access macros */
+
+#define DB_ACCESS_LEVEL		2	/* access any space */
+#define DB_CHECK_ACCESS(addr,size,task)				\
+	db_check_access(addr,size,task)
+#define DB_PHYS_EQ(task1,addr1,task2,addr2)			\
+	db_phys_eq(task1,addr1,task2,addr2)
+#define DB_VALID_KERN_ADDR(addr)				\
+	((addr) >= VM_MIN_KERNEL_ADDRESS && 			\
+	 (addr) < VM_MAX_KERNEL_ADDRESS)
+#define DB_VALID_ADDRESS(addr,user)				\
+	((!(user) && DB_VALID_KERN_ADDR(addr)) ||		\
+	 ((user) && (addr) < VM_MAX_ADDRESS))
+
+#if 0
+bool	 	db_check_access(vaddr_t, int, task_t);
+bool		db_phys_eq(task_t, vaddr_t, task_t, vaddr_t);
+#endif
+
+/* macros for printing OS server dependent task name */
+
+#define DB_TASK_NAME(task)	db_task_name(task)
+#define DB_TASK_NAME_TITLE	"COMMAND                "
+#define DB_TASK_NAME_LEN	23
+#define DB_NULL_TASK_NAME	"?                      "
+
+/*
+ * Constants for KGDB.
+ */
+typedef	long		kgdb_reg_t;
+#define	KGDB_NUMREGS	16
+#define	KGDB_BUFLEN	512
+
+#if 0
+void		db_task_name(/* task_t */);
+#endif
+
+/* macro for checking if a thread has used floating-point */
+
+#define db_thread_fp_used(thread)	((thread)->pcb->ims.ifps != 0)
+
+int kdb_trap(int, int, db_regs_t *);
+
+/*
+ * We define some of our own commands
+ */
+#ifdef _KERNEL
+#define DB_MACHINE_COMMANDS
+#endif
+
+/*
+ * We use Elf32 symbols in DDB.
+ */
+#define	DB_ELF_SYMBOLS
+#define	DB_ELFSIZE	32
+
+extern void db_machine_init(void);
+
+extern void cpu_debug_dump(void);
+
+/* i386/db_machdep.c */
+bool db_intrstack_p(const void *);
+
+#endif	/* _I386_DB_MACHDEP_H_ */

sys/arch/i386/include/eisa_machdep.h

@@ -0,0 +1,80 @@
+/*	$NetBSD: eisa_machdep.h,v 1.14 2015/04/27 08:30:11 knakahara Exp $	*/
+
+/*
+ * Copyright (c) 1996 Christopher G. Demetriou.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *      This product includes software developed by Christopher G. Demetriou
+ *	for the NetBSD Project.
+ * 4. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Machine-specific definitions for EISA autoconfiguration.
+ */
+
+/*
+ * i386-specific EISA definitions.
+ * NOT TO BE USED DIRECTLY BY MACHINE INDEPENDENT CODE.
+ */
+#define	EISA_ID			"EISA"
+#define	EISA_ID_LEN		(sizeof(EISA_ID) - 1)
+#define	EISA_ID_PADDR		0xfffd9
+
+extern struct x86_bus_dma_tag eisa_bus_dma_tag;
+
+/* EISA Edge/Level trigger control registers */
+#define ELCR0   0x4d0                   /* eisa irq 0-7 */
+#define ELCR1   0x4d1                   /* eisa irq 8-15 */
+
+#include <machine/intr.h> /* for intr_handle_t */
+/*
+ * Types provided to machine-independent EISA code.
+ */
+typedef void *eisa_chipset_tag_t;
+typedef intr_handle_t eisa_intr_handle_t;
+
+/*
+ * Functions provided to machine-independent EISA code.
+ */
+void		eisa_attach_hook(device_t, device_t,
+		    struct eisabus_attach_args *);
+int		eisa_maxslots(eisa_chipset_tag_t);
+int		eisa_intr_map(eisa_chipset_tag_t, u_int,
+		    eisa_intr_handle_t *);
+const char	*eisa_intr_string(eisa_chipset_tag_t, eisa_intr_handle_t,
+		    char *, size_t);
+const struct evcnt *eisa_intr_evcnt(eisa_chipset_tag_t, eisa_intr_handle_t);
+void		*eisa_intr_establish(eisa_chipset_tag_t,
+		    eisa_intr_handle_t, int, int, int (*)(void *), void *);
+void		eisa_intr_disestablish(eisa_chipset_tag_t, void *);
+
+int		eisa_conf_read_mem(eisa_chipset_tag_t, int, int, int,
+		    struct eisa_cfg_mem *);
+int		eisa_conf_read_irq(eisa_chipset_tag_t, int, int, int,
+		    struct eisa_cfg_irq *);
+int		eisa_conf_read_dma(eisa_chipset_tag_t, int, int, int,
+		    struct eisa_cfg_dma *);
+int		eisa_conf_read_io(eisa_chipset_tag_t, int, int, int,
+		    struct eisa_cfg_io *);

sys/arch/i386/include/fenv.h

@@ -1,4 +1,4 @@
-/*	$NetBSD: fenv.h,v 1.1 2010/07/31 21:47:54 joerg Exp $	*/
+/*	$NetBSD: fenv.h,v 1.2 2014/02/12 23:04:43 dsl Exp $	*/
 /*-
  * Copyright (c) 2004-2005 David Schultz <das (at) FreeBSD.ORG>
  * All rights reserved.
@@ -28,9 +28,21 @@
 #ifndef	_X86_FENV_H_
 #define	_X86_FENV_H_
 
+#ifndef _KERNEL
 #include <sys/stdint.h>
-#include <i386/npx.h>
+#endif
 
+/* Default x87 control word. */
+#define __INITIAL_NPXCW__       0x037f  
+/* Modern NetBSD uses the default control word.. */
+#define __NetBSD_NPXCW__        __INITIAL_NPXCW__
+/* NetBSD before 6.99.26 forced IEEE double precision. */
+#define __NetBSD_COMPAT_NPXCW__ 0x127f
+
+/* Default values for the mxcsr. All traps masked. */
+#define __INITIAL_MXCSR__       0x1f80
+
+#ifndef _KERNEL
 /*
  * Each symbol representing a floating point exception expands to an integer
  * constant expression with values, such that bitwise-inclusive ORs of _all
@@ -112,5 +124,6 @@ extern  fenv_t		__fe_dfl_env;
  * the user to affect the subsequent behavior of floating-point arithmetic.
  */
 typedef uint32_t fexcept_t;
+#endif
 
 #endif	/* ! _X86_FENV_H_ */

sys/arch/i386/include/frameasm.h

@@ -0,0 +1,156 @@
+/*	$NetBSD: frameasm.h,v 1.15 2011/07/26 12:57:35 yamt Exp $	*/
+
+#ifndef _I386_FRAMEASM_H_
+#define _I386_FRAMEASM_H_
+
+#ifdef _KERNEL_OPT
+#include "opt_multiprocessor.h"
+#include "opt_xen.h"
+#endif
+
+#if !defined(XEN)
+#define CLI(reg)        cli
+#define STI(reg)        sti
+#else
+/* XXX assym.h */
+#define TRAP_INSTR      int $0x82
+#define XEN_BLOCK_EVENTS(reg)   movb $1,EVTCHN_UPCALL_MASK(reg)
+#define XEN_UNBLOCK_EVENTS(reg) movb $0,EVTCHN_UPCALL_MASK(reg)
+#define XEN_TEST_PENDING(reg)   testb $0xFF,EVTCHN_UPCALL_PENDING(reg)
+
+#define CLI(reg)        movl    CPUVAR(VCPU),reg ;  \
+                        XEN_BLOCK_EVENTS(reg)
+#define STI(reg)        movl    CPUVAR(VCPU),reg ;  \
+			XEN_UNBLOCK_EVENTS(reg)
+#define STIC(reg)       movl    CPUVAR(VCPU),reg ;  \
+			XEN_UNBLOCK_EVENTS(reg)  ; \
+			testb $0xff,EVTCHN_UPCALL_PENDING(reg)
+#endif
+
+#ifndef TRAPLOG
+#define TLOG		/**/
+#else
+/*
+ * Fill in trap record
+ */
+#define TLOG						\
+9:							\
+	movl	%fs:CPU_TLOG_OFFSET, %eax;		\
+	movl	%fs:CPU_TLOG_BASE, %ebx;		\
+	addl	$SIZEOF_TREC,%eax;			\
+	andl	$SIZEOF_TLOG-1,%eax;			\
+	addl	%eax,%ebx;				\
+	movl	%eax,%fs:CPU_TLOG_OFFSET;		\
+	movl	%esp,TREC_SP(%ebx);			\
+	movl	$9b,TREC_HPC(%ebx);			\
+	movl	TF_EIP(%esp),%eax;			\
+	movl	%eax,TREC_IPC(%ebx);			\
+	rdtsc			;			\
+	movl	%eax,TREC_TSC(%ebx);			\
+	movl	$MSR_LASTBRANCHFROMIP,%ecx;		\
+	rdmsr			;			\
+	movl	%eax,TREC_LBF(%ebx);			\
+	incl	%ecx		;			\
+	rdmsr			;			\
+	movl	%eax,TREC_LBT(%ebx);			\
+	incl	%ecx		;			\
+	rdmsr			;			\
+	movl	%eax,TREC_IBF(%ebx);			\
+	incl	%ecx		;			\
+	rdmsr			;			\
+	movl	%eax,TREC_IBT(%ebx)
+#endif
+		
+/*
+ * These are used on interrupt or trap entry or exit.
+ */
+#define	INTRENTRY \
+	subl	$TF_PUSHSIZE,%esp	; \
+	movw	%gs,TF_GS(%esp)	; \
+	movw	%fs,TF_FS(%esp) ; \
+	movl	%eax,TF_EAX(%esp)	; \
+	movw	%es,TF_ES(%esp) ; \
+	movw	%ds,TF_DS(%esp) ; \
+	movl	$GSEL(GDATA_SEL, SEL_KPL),%eax	; \
+	movl	%edi,TF_EDI(%esp)	; \
+	movl	%esi,TF_ESI(%esp)	; \
+	movw	%ax,%ds	; \
+	movl	%ebp,TF_EBP(%esp)	; \
+	movw	%ax,%es	; \
+	movl	%ebx,TF_EBX(%esp)	; \
+	movw	%ax,%gs	; \
+	movl	%edx,TF_EDX(%esp)	; \
+	movl	$GSEL(GCPU_SEL, SEL_KPL),%eax	; \
+	movl	%ecx,TF_ECX(%esp)	; \
+	movl	%eax,%fs	; \
+	cld			; \
+	TLOG
+
+/*
+ * INTRFASTEXIT should be in sync with trap(), resume_iret and friends.
+ */
+#define	INTRFASTEXIT \
+	movw	TF_GS(%esp),%gs	; \
+	movw	TF_FS(%esp),%fs	; \
+	movw	TF_ES(%esp),%es	; \
+	movw	TF_DS(%esp),%ds	; \
+	movl	TF_EDI(%esp),%edi	; \
+	movl	TF_ESI(%esp),%esi	; \
+	movl	TF_EBP(%esp),%ebp	; \
+	movl	TF_EBX(%esp),%ebx	; \
+	movl	TF_EDX(%esp),%edx	; \
+	movl	TF_ECX(%esp),%ecx	; \
+	movl	TF_EAX(%esp),%eax	; \
+	addl	$(TF_PUSHSIZE+8),%esp	; \
+	iret
+
+#define	DO_DEFERRED_SWITCH \
+	cmpl	$0, CPUVAR(WANT_PMAPLOAD)		; \
+	jz	1f					; \
+	call	_C_LABEL(pmap_load)			; \
+	1:
+
+#define	DO_DEFERRED_SWITCH_RETRY \
+	1:						; \
+	cmpl	$0, CPUVAR(WANT_PMAPLOAD)		; \
+	jz	1f					; \
+	call	_C_LABEL(pmap_load)			; \
+	jmp	1b					; \
+	1:
+
+#define	CHECK_DEFERRED_SWITCH \
+	cmpl	$0, CPUVAR(WANT_PMAPLOAD)
+
+#define	CHECK_ASTPENDING(reg)	movl	CPUVAR(CURLWP),reg	; \
+				cmpl	$0, L_MD_ASTPENDING(reg)
+#define	CLEAR_ASTPENDING(reg)	movl	$0, L_MD_ASTPENDING(reg)
+
+/*
+ * IDEPTH_INCR:
+ * increase ci_idepth and switch to the interrupt stack if necessary.
+ * note that the initial value of ci_idepth is -1.
+ *
+ * => should be called with interrupt disabled.
+ * => save the old value of %esp in %eax.
+ */
+
+#define	IDEPTH_INCR \
+	incl	CPUVAR(IDEPTH); \
+	movl	%esp, %eax; \
+	jne	999f; \
+	movl	CPUVAR(INTRSTACK), %esp; \
+999:	pushl	%eax; /* eax == pointer to intrframe */ \
+
+/*
+ * IDEPTH_DECR:
+ * decrement ci_idepth and switch back to
+ * the original stack saved by IDEPTH_INCR.
+ *
+ * => should be called with interrupt disabled.
+ */
+
+#define	IDEPTH_DECR \
+	popl	%esp; \
+	decl	CPUVAR(IDEPTH)
+
+#endif /* _I386_FRAMEASM_H_ */

sys/arch/i386/include/freebsd_machdep.h

@@ -0,0 +1,118 @@
+/*	$NetBSD: freebsd_machdep.h,v 1.13 2014/02/12 23:24:09 dsl Exp $	*/
+
+/*
+ * Copyright (c) 1986, 1989, 1991, 1993
+ *	The Regents of the University of California.  All rights reserved.
+ *
+ * This code is derived from software contributed to Berkeley by
+ * William Jolitz.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ *	from: @(#)signal.h	8.1 (Berkeley) 6/11/93
+ *	from: Id: signal.h,v 1.4 1994/08/21 04:55:30 paul Exp 
+ *
+ *	from: @(#)frame.h	5.2 (Berkeley) 1/18/91
+ *	from: Id: frame.h,v 1.10 1995/03/16 18:11:42 bde Exp 
+ */
+#ifndef _FREEBSD_MACHDEP_H
+#define _FREEBSD_MACHDEP_H
+
+#include <compat/sys/sigtypes.h>
+
+/*
+ * signal support
+ */
+
+struct freebsd_osigcontext {
+	int	sc_onstack;	/* sigstack state to restore */
+	sigset13_t sc_mask;	/* signal mask to restore */
+	int	sc_esp;		/* machine state */
+	int	sc_ebp;
+	int	sc_isp;
+	int	sc_eip;
+	int	sc_eflags;
+	int	sc_es;
+	int	sc_ds;
+	int	sc_cs;
+	int	sc_ss;
+	int	sc_edi;
+	int	sc_esi;
+	int	sc_ebx;
+	int	sc_edx;
+	int	sc_ecx;
+	int	sc_eax;
+};
+
+/*
+ * The sequence of the fields/registers in struct sigcontext should match
+ * those in mcontext_t.
+ */
+struct freebsd_sigcontext {
+	sigset_t sc_mask;		/* signal mask to restore */
+	int	sc_onstack;		/* sigstack state to restore */
+	int	sc_gs;			/* machine state (struct trapframe): */
+	int	sc_fs;
+	int	sc_es;
+	int	sc_ds;
+	int	sc_edi;
+	int	sc_esi;
+	int	sc_ebp;
+	int	sc_isp;
+	int	sc_ebx;
+	int	sc_edx;
+	int	sc_ecx;
+	int	sc_eax;
+	int	sc_trapno;
+	int	sc_err;
+	int	sc_eip;
+	int	sc_cs;
+	int	sc_efl;
+	int	sc_esp;
+	int	sc_ss;
+	/*
+	 * XXX FPU state is 27 * 4 bytes h/w, 1 * 4 bytes s/w (probably not
+	 * needed here), or that + 16 * 4 bytes for emulators (probably all
+	 * needed here).  The "spare" bytes are mostly not spare.
+	 */
+	int	sc_fpregs[28];		/* machine state (FPU): */
+	int	sc_spare[17];
+};
+
+struct freebsd_sigframe {
+	int	sf_signum;
+	int	sf_code;
+	struct	freebsd_sigcontext *sf_scp;
+	char	*sf_addr;
+	sig_t	sf_handler;
+	struct	freebsd_sigcontext sf_sc;
+};
+
+/* sys/i386/include/exec.h */
+#define FREEBSD___LDPGSZ	4096
+
+void freebsd_syscall_intern(struct proc *);
+
+#endif /* _FREEBSD_MACHDEP_H */

sys/arch/i386/include/gdt.h

@@ -0,0 +1,51 @@
+/*	$NetBSD: gdt.h,v 1.13 2008/04/28 20:23:24 martin Exp $	*/
+
+/*-
+ * Copyright (c) 1996, 1997 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by John T. Kohl and Charles M. Hannum.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(_LOCORE)
+
+struct proc;
+struct pmap;
+
+void gdt_init(void);
+void gdt_init_cpu(struct cpu_info *);
+void gdt_reload_cpu(struct cpu_info *);
+int gdt_get_slot(void);
+void gdt_put_slot(int);
+void gdt_alloc_cpu(struct cpu_info *);
+int tss_alloc(const struct i386tss *);
+void tss_free(int);
+int ldt_alloc(union descriptor *, size_t);
+void ldt_free(int);
+
+#endif /* LOCORE */
+
+#define	MINGDTSIZ	512
+#define	MAXGDTSIZ	8192

sys/arch/i386/include/i82093reg.h

@@ -0,0 +1,74 @@
+/*	 $NetBSD: i82093reg.h,v 1.8 2008/07/03 14:02:25 drochner Exp $ */
+
+#include <x86/i82093reg.h>
+
+#ifdef _KERNEL
+
+#if defined(_KERNEL_OPT)
+#include "opt_multiprocessor.h"
+#endif
+
+#define ioapic_asm_ack(num) \
+	movl	$0,_C_LABEL(local_apic)+LAPIC_EOI
+
+#ifdef MULTIPROCESSOR
+
+#define ioapic_asm_lock(num) \
+	movl	$1,%esi						;\
+77:								\
+	xchgl	%esi,PIC_LOCK(%edi)				;\
+	testl	%esi,%esi					;\
+	jne	77b
+
+#define ioapic_asm_unlock(num) \
+	movl	$0,PIC_LOCK(%edi)
+	
+#else
+
+#define ioapic_asm_lock(num)
+#define ioapic_asm_unlock(num)
+
+#endif	/* MULTIPROCESSOR */
+
+#define ioapic_mask(num) \
+	movl	IS_PIC(%ebp),%edi				;\
+	ioapic_asm_lock(num)					;\
+	movl	IS_PIN(%ebp),%esi				;\
+	leal	0x10(%esi,%esi,1),%esi				;\
+	movl	PIC_IOAPIC(%edi),%edi				;\
+	movl	IOAPIC_SC_REG(%edi),%ebx			;\
+	movl	%esi, (%ebx)					;\
+	movl	IOAPIC_SC_DATA(%edi),%ebx			;\
+	movl	(%ebx),%esi					;\
+	orl	$IOAPIC_REDLO_MASK,%esi				;\
+	movl	%esi,(%ebx)					;\
+	movl	IS_PIC(%ebp),%edi				;\
+	ioapic_asm_unlock(num)
+
+/*
+ * Since this is called just before the interrupt stub exits, AND
+ * because the apic ACK doesn't use any registers, all registers
+ * can be used here.
+ * XXX this is not obvious
+ */
+#define ioapic_unmask(num) \
+	movl    (%esp),%eax					;\
+	cmpl    $IREENT_MAGIC,(TF_ERR+4)(%eax)			;\
+	jne     79f						;\
+	movl	IS_PIC(%ebp),%edi				;\
+	ioapic_asm_lock(num)					;\
+	movl	IS_PIN(%ebp),%esi				;\
+	leal	0x10(%esi,%esi,1),%esi				;\
+	movl	PIC_IOAPIC(%edi),%edi				;\
+	movl	IOAPIC_SC_REG(%edi),%ebx			;\
+	movl	IOAPIC_SC_DATA(%edi),%eax			;\
+	movl	%esi, (%ebx)					;\
+	movl	(%eax),%edx					;\
+	andl	$~IOAPIC_REDLO_MASK,%edx			;\
+	movl	%esi, (%ebx)					;\
+	movl	%edx,(%eax)					;\
+	movl	IS_PIC(%ebp),%edi				;\
+	ioapic_asm_unlock(num)					;\
+79:
+
+#endif

sys/arch/i386/include/i82093var.h

@@ -0,0 +1,3 @@
+/*	 $NetBSD: i82093var.h,v 1.7 2003/02/26 21:29:00 fvdl Exp $ */
+
+#include <x86/i82093var.h>

sys/arch/i386/include/i82489reg.h

@@ -0,0 +1,3 @@
+/*	$NetBSD: i82489reg.h,v 1.3 2003/02/26 21:29:00 fvdl Exp $	*/
+
+#include <x86/i82489reg.h>

sys/arch/i386/include/i82489var.h

@@ -0,0 +1,3 @@
+/*	$NetBSD: i82489var.h,v 1.5 2003/02/26 21:29:00 fvdl Exp $	*/
+
+#include <x86/i82489var.h>