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arm:make the MMU fetch pagetable data through the caches.

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Change-Id: Ibd7b66558c369d0c0792c02801562580d255fa1f
This commit is contained in:
Kees Jongenburger
2013-09-25 11:12:46 +02:00
parent 827378c57f
commit 0d02dc9d54
3 changed files with 23 additions and 4 deletions
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15
include/arch/earm/include/vm.h
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@@ -163,6 +163,21 @@ arm/vm.h
#define ARM_VM_PFE_FS4 (1<<10) /* Fault status (bit 4) */
#define ARM_VM_PFE_FS3_0 0xf /* Fault status (bits 3:0) */
/* Translation table base register specfic flags */
#define ARM_TTBR_C (0x01) /* Cacheable bit. Indicates whether the translation table walk is to Inner Cacheable memory. */
/* RGN bits[4:3] indicates the Outer cacheability attributes
for the memory associated with the translation table walks */
#define ARM_TTBR_OUTER_NC (0x0 << 3) /* Non-cacheable*/
#define ARM_TTBR_OUTER_WBWA (0x1 << 3) /* Outer Write-Back Write-Allocate Cacheable. */
#define ARM_TTBR_OUTER_WT (0x2 << 3) /* Outer Write-Through Cacheable. */
#define ARM_TTBR_OUTER_WBNWA (0x3 << 3) /* Outer Write-Back no Write-Allocate Cacheable. */
#define ARM_TTBR_ADDR_MASK (0xffffc000) /* only the 18 upper bits are to be used as address */
#define ARM_TTBR_FLAGS_CACHED ARM_TTBR_OUTER_WBWA
/* Fault status */
#define ARM_VM_PFE_FS(s) \
((((s) & ARM_VM_PFE_FS4) >> 6) | ((s) & ARM_VM_PFE_FS3_0))