i2c: initial bus drivers for am335x and dm37xx
Change-Id: I478704fbf30dbf6d3382bcbfb11e75b512c032a1
This commit is contained in:
Thomas Cort
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# Makefile for I2C support
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PROG= i2c
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.include "arch/${MACHINE_ARCH}/Makefile.inc"
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SRCS+= i2c.c
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DPADD+= ${LIBCHARDRIVER} ${LIBSYS} ${LIBTIMERS} ${CLKCONF} ${PADCONF}
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LDADD+= -lchardriver -lsys -ltimers -lclkconf -lpadconf
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MAN=
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BINDIR?= /usr/sbin
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CPPFLAGS+= -I${.CURDIR} -I${.CURDIR}/arch/${MACHINE_ARCH}
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.include <minix.service.mk>
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.include <bsd.subdir.mk>
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@@ -0,0 +1,64 @@
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Minix i2c Driver
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================
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TODO: this probably belongs on the wiki
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Overview
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--------
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This is the driver for the i2c bus. It provides the same /dev interface as
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NetBSD and OpenBSD (see dev/i2c/i2c_io.h). It also provides an interface for
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other drivers to access the I2C bus using Minix IPC.
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Organization and Layout
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-----------------------
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i2c.c generic i2c bus driver
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arch/ arch specific code
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earm/ earm specific code
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omap_i2c.c AM335X/DM37XX i2c bus driver
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omap_i2c.h AM335X/DM37XX function prototypes
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omap_i2c_registers.h AM335X/DM37XX register offsets, etc.
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Testing the Code
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----------------
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Below are the steps needed to start up the i2c driver instances. Though,
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now they get started at boot in /usr/etc/rc, it's still useful to know if
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you take down the service and need to start it again.
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Creating the device files (this is already done automatically, but if not):
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cd /dev && MAKEDEV i2c-1 && MAKEDEV i2c-2 && MAKEDEV i2c-3
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Starting up the instances:
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/bin/service up /usr/sbin/i2c -dev /dev/i2c-1 -label i2c.1 -args instance=1
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/bin/service up /usr/sbin/i2c -dev /dev/i2c-2 -label i2c.2 -args instance=2
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/bin/service up /usr/sbin/i2c -dev /dev/i2c-3 -label i2c.3 -args instance=3
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There is an i2cscan program from NetBSD which can detect devices on the bus:
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i2cscan -r /dev/i2c-1
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i2cscan -r /dev/i2c-2
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i2cscan -r /dev/i2c-3
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Limitations
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-----------
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The i2c controllers used in the am335x and the dm37xx do not support zero
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byte transfers. Writing 0 bytes is a common method used to probe the bus
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for devices. Most of the address ranges i2cscan scans are done by this
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method. Therefore, only a subset of devices on the bus will be detected by
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i2cscan (i.e. the devices it detects using the 1 byte read method). See
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the register description for I2C_CNT in the technical reference manuals
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for details about why 0 byte transfers are not allowed.
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Developing I2C Device Drivers
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-----------------------------
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The driver for the EEPROM (a.k.a. drivers/cat24c256) is the hello world of
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Minix i2c device drivers. It shows how to use the i2cdriver library and
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how to use the bus for reads and writes. commands/eepromread is another
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place to look if you're interested in accessing devices through the /dev
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interface.
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@@ -0,0 +1,7 @@
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# Makefile for arch-dependent i2c code
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.include <bsd.own.mk>
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HERE=${.CURDIR}/arch/${MACHINE_ARCH}
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.PATH: ${HERE}
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SRCS += omap_i2c.c omap_i2c.h omap_i2c_registers.h
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@@ -0,0 +1,855 @@
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/*
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* This file implements support for i2c on the BeagleBone and BeagleBoard-xM
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*/
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/* kernel headers */
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#include <minix/chardriver.h>
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#include <minix/clkconf.h>
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#include <minix/drivers.h>
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#include <minix/ds.h>
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#include <minix/log.h>
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#include <minix/mmio.h>
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#include <minix/padconf.h>
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#include <minix/sysutil.h>
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#include <minix/type.h>
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/* device headers */
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#include <minix/i2c.h>
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/* system headers */
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#include <sys/ioctl.h>
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#include <sys/mman.h>
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#include <sys/types.h>
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/* usr headers */
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#include <string.h>
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#include <stdio.h>
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#include <stdlib.h>
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/* local headers */
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#include "omap_i2c.h"
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/* defines the set of register */
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typedef struct omap_i2c_registers
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{
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vir_bytes I2C_REVNB_LO; /* AM335X Only */
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vir_bytes I2C_REVNB_HI; /* AM335X Only */
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vir_bytes I2C_REV; /* DM37XX Only */
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vir_bytes I2C_IE; /* DM37XX Only */
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vir_bytes I2C_STAT; /* DM37XX Only */
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vir_bytes I2C_SYSC;
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vir_bytes I2C_IRQSTATUS_RAW; /* AM335X Only */
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vir_bytes I2C_IRQSTATUS; /* AM335X Only */
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vir_bytes I2C_IRQENABLE_SET; /* AM335X Only */
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vir_bytes I2C_IRQENABLE_CLR; /* AM335X Only */
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vir_bytes I2C_WE;
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vir_bytes I2C_DMARXENABLE_SET; /* AM335X Only */
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vir_bytes I2C_DMATXENABLE_SET; /* AM335X Only */
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vir_bytes I2C_DMARXENABLE_CLR; /* AM335X Only */
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vir_bytes I2C_DMATXENABLE_CLR; /* AM335X Only */
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vir_bytes I2C_DMARXWAKE_EN; /* AM335X Only */
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vir_bytes I2C_DMATXWAKE_EN; /* AM335X Only */
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vir_bytes I2C_SYSS;
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vir_bytes I2C_BUF;
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vir_bytes I2C_CNT;
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vir_bytes I2C_DATA;
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vir_bytes I2C_CON;
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vir_bytes I2C_OA; /* AM335X Only */
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vir_bytes I2C_OA0; /* DM37XX Only */
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vir_bytes I2C_SA;
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vir_bytes I2C_PSC;
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vir_bytes I2C_SCLL;
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vir_bytes I2C_SCLH;
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vir_bytes I2C_SYSTEST;
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vir_bytes I2C_BUFSTAT;
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vir_bytes I2C_OA1;
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vir_bytes I2C_OA2;
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vir_bytes I2C_OA3;
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vir_bytes I2C_ACTOA;
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vir_bytes I2C_SBLOCK;
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} omap_i2c_regs_t;
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/* generic definition an i2c bus */
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typedef struct omap_i2c_bus
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{
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enum bus_types
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{ am335x, dm37xx } bus_type;
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phys_bytes mr_base;
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phys_bytes mr_size;
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vir_bytes mapped_addr;
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omap_i2c_regs_t *regs;
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uint32_t functional_clock;
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uint32_t module_clock;
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uint32_t bus_speed;
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uint16_t major;
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uint16_t minor;
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int irq;
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int irq_hook_id;
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int irq_hook_kernel_id;
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} omap_i2c_bus_t;
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/* Define the registers for each chip */
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static omap_i2c_regs_t am335x_i2c_regs = {
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.I2C_REVNB_LO = AM335X_I2C_REVNB_LO,
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.I2C_REVNB_HI = AM335X_I2C_REVNB_HI,
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.I2C_SYSC = AM335X_I2C_SYSC,
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.I2C_IRQSTATUS_RAW = AM335X_I2C_IRQSTATUS_RAW,
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.I2C_IRQSTATUS = AM335X_I2C_IRQSTATUS,
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.I2C_IRQENABLE_SET = AM335X_I2C_IRQENABLE_SET,
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.I2C_IRQENABLE_CLR = AM335X_I2C_IRQENABLE_CLR,
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.I2C_WE = AM335X_I2C_WE,
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.I2C_DMARXENABLE_SET = AM335X_I2C_DMARXENABLE_SET,
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.I2C_DMATXENABLE_SET = AM335X_I2C_DMATXENABLE_SET,
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.I2C_DMARXENABLE_CLR = AM335X_I2C_DMARXENABLE_CLR,
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.I2C_DMATXENABLE_CLR = AM335X_I2C_DMATXENABLE_CLR,
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.I2C_DMARXWAKE_EN = AM335X_I2C_DMARXWAKE_EN,
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.I2C_DMATXWAKE_EN = AM335X_I2C_DMATXWAKE_EN,
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.I2C_SYSS = AM335X_I2C_SYSS,
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.I2C_BUF = AM335X_I2C_BUF,
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.I2C_CNT = AM335X_I2C_CNT,
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.I2C_DATA = AM335X_I2C_DATA,
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.I2C_CON = AM335X_I2C_CON,
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.I2C_OA = AM335X_I2C_OA,
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.I2C_SA = AM335X_I2C_SA,
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.I2C_PSC = AM335X_I2C_PSC,
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.I2C_SCLL = AM335X_I2C_SCLL,
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.I2C_SCLH = AM335X_I2C_SCLH,
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.I2C_SYSTEST = AM335X_I2C_SYSTEST,
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.I2C_BUFSTAT = AM335X_I2C_BUFSTAT,
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.I2C_OA1 = AM335X_I2C_OA1,
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.I2C_OA2 = AM335X_I2C_OA2,
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.I2C_OA3 = AM335X_I2C_OA3,
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.I2C_ACTOA = AM335X_I2C_ACTOA,
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.I2C_SBLOCK = AM335X_I2C_SBLOCK
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};
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static omap_i2c_regs_t dm37xx_i2c_regs = {
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.I2C_REV = DM37XX_I2C_REV,
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.I2C_IE = DM37XX_I2C_IE,
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.I2C_STAT = DM37XX_I2C_STAT,
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.I2C_WE = DM37XX_I2C_WE,
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.I2C_SYSS = DM37XX_I2C_SYSS,
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.I2C_BUF = DM37XX_I2C_BUF,
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.I2C_CNT = DM37XX_I2C_CNT,
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.I2C_DATA = DM37XX_I2C_DATA,
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.I2C_SYSC = DM37XX_I2C_SYSC,
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.I2C_CON = DM37XX_I2C_CON,
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.I2C_OA0 = DM37XX_I2C_OA0,
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.I2C_SA = DM37XX_I2C_SA,
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.I2C_PSC = DM37XX_I2C_PSC,
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.I2C_SCLL = DM37XX_I2C_SCLL,
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.I2C_SCLH = DM37XX_I2C_SCLH,
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.I2C_SYSTEST = DM37XX_I2C_SYSTEST,
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.I2C_BUFSTAT = DM37XX_I2C_BUFSTAT,
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.I2C_OA1 = DM37XX_I2C_OA1,
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.I2C_OA2 = DM37XX_I2C_OA2,
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.I2C_OA3 = DM37XX_I2C_OA3,
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.I2C_ACTOA = DM37XX_I2C_ACTOA,
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.I2C_SBLOCK = DM37XX_I2C_SBLOCK
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};
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/* Define the buses available on each chip */
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static omap_i2c_bus_t am335x_i2c_buses[] = {
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{am335x, AM335X_I2C0_BASE, AM335X_I2C0_SIZE, 0, &am335x_i2c_regs,
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AM335X_FUNCTIONAL_CLOCK, AM335X_MODULE_CLOCK,
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BUS_SPEED_400KHz, AM335X_REV_MAJOR, AM335X_REV_MINOR,
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AM335X_I2C0_IRQ, 1, 1},
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{am335x, AM335X_I2C1_BASE, AM335X_I2C1_SIZE, 0, &am335x_i2c_regs,
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AM335X_FUNCTIONAL_CLOCK, AM335X_MODULE_CLOCK,
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BUS_SPEED_100KHz, AM335X_REV_MAJOR, AM335X_REV_MINOR,
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AM335X_I2C1_IRQ, 2, 3},
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{am335x, AM335X_I2C2_BASE, AM335X_I2C2_SIZE, 0, &am335x_i2c_regs,
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AM335X_FUNCTIONAL_CLOCK, AM335X_MODULE_CLOCK,
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BUS_SPEED_100KHz, AM335X_REV_MAJOR, AM335X_REV_MINOR,
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AM335X_I2C2_IRQ, 3, 3}
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};
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#define AM335X_OMAP_NBUSES (sizeof(am335x_i2c_buses) / sizeof(omap_i2c_bus_t))
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static omap_i2c_bus_t dm37xx_i2c_buses[] = {
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{dm37xx, DM37XX_I2C0_BASE, DM37XX_I2C0_SIZE, 0, &dm37xx_i2c_regs,
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DM37XX_FUNCTIONAL_CLOCK, DM37XX_MODULE_CLOCK,
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BUS_SPEED_100KHz, DM37XX_REV_MAJOR, DM37XX_REV_MINOR,
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DM37XX_I2C0_IRQ, 1, 1},
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{dm37xx, DM37XX_I2C1_BASE, DM37XX_I2C1_SIZE, 0, &dm37xx_i2c_regs,
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DM37XX_FUNCTIONAL_CLOCK, DM37XX_MODULE_CLOCK,
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BUS_SPEED_100KHz, DM37XX_REV_MAJOR, DM37XX_REV_MINOR,
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DM37XX_I2C1_IRQ, 2, 2},
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{dm37xx, DM37XX_I2C2_BASE, DM37XX_I2C2_SIZE, 0, &dm37xx_i2c_regs,
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DM37XX_FUNCTIONAL_CLOCK, DM37XX_MODULE_CLOCK,
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BUS_SPEED_100KHz, DM37XX_REV_MAJOR, DM37XX_REV_MINOR,
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DM37XX_I2C2_IRQ, 3, 3}
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};
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#define DM37XX_OMAP_NBUSES (sizeof(dm37xx_i2c_buses) / sizeof(omap_i2c_bus_t))
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/* Globals */
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static omap_i2c_bus_t *omap_i2c_buses; /* all available buses for this SoC */
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static omap_i2c_bus_t *omap_i2c_bus; /* the bus selected at start-up */
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static int omap_i2c_nbuses; /* number of buses supported by SoC */
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/* logging - use with log_warn(), log_info(), log_debug(), log_trace() */
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static struct log log = {
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.name = "i2c",
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.log_level = LEVEL_INFO,
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.log_func = default_log
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};
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/* Local Function Prototypes */
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/* Implementation of Generic I2C Interface using Bus Specific Code */
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static int omap_i2c_process(minix_i2c_ioctl_exec_t * m);
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/* Bus Specific Code */
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static void omap_i2c_flush(void);
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static uint16_t omap_i2c_poll(uint16_t mask);
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static int omap_i2c_claim_bus(void);
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static int omap_i2c_release_bus(void);
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static int omap_i2c_soft_reset(void);
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static void omap_i2c_bus_init(void);
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#if 0
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static void omap_i2c_padconf(int i2c_bus_id);
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#endif /* disable until libpadconf is fixed */
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static void omap_i2c_clkconf(int i2c_bus_id);
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static void omap_i2c_intr_enable(void);
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static uint16_t omap_i2c_read_status(void);
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static void omap_i2c_write_status(uint16_t mask);
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static int omap_i2c_read(i2c_addr_t addr, uint8_t * buf, size_t buflen,
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int dostop);
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static int omap_i2c_write(i2c_addr_t addr, const uint8_t * buf, size_t buflen,
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int dostop);
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/* Helpers for register access */
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#define reg_read(a) (*(volatile uint16_t *)(omap_i2c_bus->mapped_addr + a))
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#define reg_write(a,v) (*(volatile uint16_t *)(omap_i2c_bus->mapped_addr + a) = (v))
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#define reg_set_bit(a,v) reg_write((a), reg_read((a)) | (1<<v))
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#define reg_clear_bit(a,v) reg_write((a), reg_read((a)) & ~(1<<v))
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/*
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* Performs the action in minix_i2c_ioctl_exec_t.
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*/
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static int
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omap_i2c_process(minix_i2c_ioctl_exec_t * ioctl_exec)
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{
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int r;
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/*
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* Zero data bytes transfers are not allowed. The controller treats
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* I2C_CNT register value of 0x0 as 65536. This is true for both the
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* am335x and dm37xx. Full details in the TRM on the I2C_CNT page.
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*/
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if (ioctl_exec->iie_buflen == 0) {
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return EINVAL;
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}
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omap_i2c_flush(); /* clear any garbage in the fifo */
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/* Check bus busy flag before using the bus */
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r = omap_i2c_claim_bus();
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if (r == -1) {
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log_warn(&log, "Can't Claim Bus\n");
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return EBUSY;
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}
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if (ioctl_exec->iie_cmdlen > 0) {
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r = omap_i2c_write(ioctl_exec->iie_addr, ioctl_exec->iie_cmd,
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ioctl_exec->iie_cmdlen,
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!(I2C_OP_READ_P(ioctl_exec->iie_op)));
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if (r != OK) {
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omap_i2c_soft_reset();
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omap_i2c_bus_init();
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return r;
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}
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}
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if (I2C_OP_READ_P(ioctl_exec->iie_op)) {
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r = omap_i2c_read(ioctl_exec->iie_addr, ioctl_exec->iie_buf,
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ioctl_exec->iie_buflen, I2C_OP_STOP_P(ioctl_exec->iie_op));
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} else {
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r = omap_i2c_write(ioctl_exec->iie_addr, ioctl_exec->iie_buf,
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ioctl_exec->iie_buflen, I2C_OP_STOP_P(ioctl_exec->iie_op));
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}
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if (r != OK) {
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omap_i2c_soft_reset();
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omap_i2c_bus_init();
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return r;
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}
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omap_i2c_release_bus();
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return OK;
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}
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/*
|
||||
* Drain the incoming FIFO.
|
||||
*
|
||||
* Usually called to clear any garbage that may be in the buffer before
|
||||
* doing a read.
|
||||
*/
|
||||
static void
|
||||
omap_i2c_flush(void)
|
||||
{
|
||||
int tries;
|
||||
int status;
|
||||
|
||||
for (tries = 0; tries < 1000; tries++) {
|
||||
status = omap_i2c_poll(1 << RRDY);
|
||||
if ((status & (1 << RRDY)) != 0) { /* bytes available for reading */
|
||||
|
||||
/* consume the byte and throw it away */
|
||||
(void) reg_read(omap_i2c_bus->regs->I2C_DATA);
|
||||
|
||||
/* clear the read ready flag */
|
||||
omap_i2c_write_status(1 << RRDY);
|
||||
|
||||
micro_delay(250);
|
||||
|
||||
} else {
|
||||
break; /* buffer drained */
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Poll the status register checking the bits set in 'mask'.
|
||||
* Returns the status if any bits set or 0x0000 when the timeout is reached.
|
||||
*/
|
||||
static uint16_t
|
||||
omap_i2c_poll(uint16_t mask)
|
||||
{
|
||||
int tries;
|
||||
uint16_t status;
|
||||
|
||||
for (tries = 0; tries < 1000; tries++) {
|
||||
|
||||
status = omap_i2c_read_status();
|
||||
if ((status & mask) != 0) { /* any bits in mask set */
|
||||
return status;
|
||||
}
|
||||
|
||||
micro_delay(250); /* else wait and try again */
|
||||
}
|
||||
|
||||
return status; /* timeout reached, abort */
|
||||
}
|
||||
|
||||
/*
|
||||
* Poll Bus Busy Flag until the bus becomes free (return 0) or the timeout
|
||||
* expires (return -1).
|
||||
*/
|
||||
static int
|
||||
omap_i2c_claim_bus(void)
|
||||
{
|
||||
int tries;
|
||||
uint16_t status;
|
||||
|
||||
for (tries = 0; tries < 1000; tries++) {
|
||||
|
||||
status = omap_i2c_read_status();
|
||||
if ((status & (1 << BB)) == 0) {
|
||||
return 0; /* bus is free */
|
||||
}
|
||||
|
||||
micro_delay(1000);
|
||||
}
|
||||
|
||||
return -1; /* timeout expired */
|
||||
}
|
||||
|
||||
/*
|
||||
* Clean up after a transfer
|
||||
*/
|
||||
static int
|
||||
omap_i2c_release_bus(void)
|
||||
{
|
||||
omap_i2c_write_status(0x7fff);
|
||||
micro_delay(50000);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void
|
||||
omap_i2c_clkconf(int i2c_bus_id)
|
||||
{
|
||||
clkconf_init();
|
||||
|
||||
if (omap_i2c_bus->bus_type == dm37xx) {
|
||||
|
||||
clkconf_set(CM_ICLKEN1_CORE, BIT((15 + i2c_bus_id)),
|
||||
0xffffffff);
|
||||
clkconf_set(CM_FCLKEN1_CORE, BIT((15 + i2c_bus_id)),
|
||||
0xffffffff);
|
||||
|
||||
} else if (omap_i2c_bus->bus_type == am335x) {
|
||||
|
||||
switch (i2c_bus_id) {
|
||||
case 0:
|
||||
clkconf_set(CM_WKUP_I2C0_CLKCTRL, BIT(1), 0xffffffff);
|
||||
break;
|
||||
case 1:
|
||||
clkconf_set(CM_PER_I2C1_CLKCTRL, BIT(1), 0xffffffff);
|
||||
break;
|
||||
case 2:
|
||||
clkconf_set(CM_PER_I2C2_CLKCTRL, BIT(1), 0xffffffff);
|
||||
break;
|
||||
default:
|
||||
log_warn(&log, "Invalid i2c_bus_id\n");
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
clkconf_release();
|
||||
}
|
||||
|
||||
#if 0
|
||||
/* re-enable this code when libpadconf is working */
|
||||
static void
|
||||
omap_i2c_padconf(int i2c_bus_id)
|
||||
{
|
||||
u32_t pinopts;
|
||||
|
||||
padconf_init();
|
||||
|
||||
if (omap_i2c_bus->bus_type == am335x) {
|
||||
|
||||
/* use the options suggested in starterware driver */
|
||||
pinopts =
|
||||
CONTROL_CONF_SLEWCTRL | CONTROL_CONF_RXACTIVE |
|
||||
CONTROL_CONF_PUTYPESEL;
|
||||
|
||||
switch (i2c_bus_id) {
|
||||
case 0:
|
||||
pinopts |= CONTROL_CONF_MUXMODE(0);
|
||||
padconf_set(CONTROL_CONF_I2C0_SDA, 0xffffffff,
|
||||
pinopts);
|
||||
padconf_set(CONTROL_CONF_I2C0_SCL, 0xffffffff,
|
||||
pinopts);
|
||||
log_info(&log, "pinopts=%x\n", pinopts);
|
||||
break;
|
||||
|
||||
case 1:
|
||||
pinopts |= CONTROL_CONF_MUXMODE(2);
|
||||
padconf_set(CONTROL_CONF_SPI0_CS0, 0xffffffff,
|
||||
pinopts);
|
||||
padconf_set(CONTROL_CONF_SPI0_D1, 0xffffffff, pinopts);
|
||||
log_info(&log, "pinopts=%x\n", pinopts);
|
||||
break;
|
||||
|
||||
case 2:
|
||||
pinopts |= CONTROL_CONF_MUXMODE(3);
|
||||
padconf_set(CONTROL_CONF_UART1_CTSN,
|
||||
0xffffffff, pinopts);
|
||||
padconf_set(CONTROL_CONF_UART1_RTSN,
|
||||
0xffffffff, pinopts);
|
||||
log_info(&log, "pinopts=%x\n", pinopts);
|
||||
break;
|
||||
|
||||
default:
|
||||
log_warn(&log, "Invalid i2c_bus_id\n");
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* nothing to do for the DM37XX */
|
||||
|
||||
padconf_release();
|
||||
}
|
||||
#endif
|
||||
|
||||
static int
|
||||
omap_i2c_soft_reset(void)
|
||||
{
|
||||
int tries;
|
||||
|
||||
/* Disable to do soft reset */
|
||||
reg_write(omap_i2c_bus->regs->I2C_CON, 0);
|
||||
micro_delay(50000);
|
||||
|
||||
/* Do a soft reset */
|
||||
reg_write(omap_i2c_bus->regs->I2C_SYSC, (1 << SRST));
|
||||
|
||||
/* Have to temporarily enable I2C to read RDONE */
|
||||
reg_set_bit(omap_i2c_bus->regs->I2C_CON, I2C_EN);
|
||||
micro_delay(50000);
|
||||
|
||||
/* wait for reset to complete */
|
||||
for (tries = 0; tries < 10000; tries++) {
|
||||
|
||||
if (reg_read(omap_i2c_bus->regs->I2C_SYSS) & (1 << RDONE)) {
|
||||
return OK;
|
||||
}
|
||||
micro_delay(1000);
|
||||
}
|
||||
|
||||
log_warn(&log, "Tried soft reset, but bus never came back.\n");
|
||||
return EIO;
|
||||
}
|
||||
|
||||
static void
|
||||
omap_i2c_intr_enable(void)
|
||||
{
|
||||
int r;
|
||||
uint16_t intmask;
|
||||
static int policy_set = 0;
|
||||
static int enabled = 0;
|
||||
|
||||
if (!policy_set) {
|
||||
r = sys_irqsetpolicy(omap_i2c_bus->irq, 0,
|
||||
&omap_i2c_bus->irq_hook_kernel_id);
|
||||
if (r == OK) {
|
||||
policy_set = 1;
|
||||
} else {
|
||||
log_warn(&log, "Couldn't set irq policy\n");
|
||||
}
|
||||
}
|
||||
|
||||
if (policy_set && !enabled) {
|
||||
r = sys_irqenable(&omap_i2c_bus->irq_hook_kernel_id);
|
||||
if (r == OK) {
|
||||
enabled = 1;
|
||||
} else {
|
||||
log_warn(&log, "Couldn't enable irq %d (hooked)\n",
|
||||
omap_i2c_bus->irq);
|
||||
}
|
||||
}
|
||||
|
||||
/* According to NetBSD driver and u-boot, these are needed even
|
||||
* if just using polling (i.e. non-interrupt driver programming).
|
||||
*/
|
||||
intmask = 0;
|
||||
intmask |= (1 << ROVR);
|
||||
intmask |= (1 << AERR);
|
||||
intmask |= (1 << XRDY);
|
||||
intmask |= (1 << RRDY);
|
||||
intmask |= (1 << ARDY);
|
||||
intmask |= (1 << NACK);
|
||||
intmask |= (1 << AL);
|
||||
|
||||
if (omap_i2c_bus->bus_type == am335x) {
|
||||
reg_write(omap_i2c_bus->regs->I2C_IRQENABLE_SET, intmask);
|
||||
} else if (omap_i2c_bus->bus_type == dm37xx) {
|
||||
reg_write(omap_i2c_bus->regs->I2C_IE, intmask);
|
||||
} else {
|
||||
log_warn(&log, "Don't know how to enable interrupts.\n");
|
||||
}
|
||||
}
|
||||
|
||||
static void
|
||||
omap_i2c_bus_init(void)
|
||||
{
|
||||
|
||||
/* Ensure i2c module is disabled before setting prescalar & bus speed */
|
||||
reg_write(omap_i2c_bus->regs->I2C_CON, 0);
|
||||
micro_delay(50000);
|
||||
|
||||
/* Disable autoidle */
|
||||
reg_clear_bit(omap_i2c_bus->regs->I2C_SYSC, AUTOIDLE);
|
||||
|
||||
/* Set prescalar to obtain 12 MHz i2c module clock */
|
||||
reg_write(omap_i2c_bus->regs->I2C_PSC,
|
||||
((omap_i2c_bus->functional_clock / omap_i2c_bus->module_clock) -
|
||||
1));
|
||||
|
||||
/* Set the bus speed */
|
||||
reg_write(omap_i2c_bus->regs->I2C_SCLL,
|
||||
((omap_i2c_bus->module_clock / (2 * omap_i2c_bus->bus_speed)) -
|
||||
7));
|
||||
reg_write(omap_i2c_bus->regs->I2C_SCLH,
|
||||
((omap_i2c_bus->module_clock / (2 * omap_i2c_bus->bus_speed)) -
|
||||
5));
|
||||
|
||||
/* Set own I2C address */
|
||||
if (omap_i2c_bus->bus_type == am335x) {
|
||||
reg_write(omap_i2c_bus->regs->I2C_OA, I2C_OWN_ADDRESS);
|
||||
} else if (omap_i2c_bus->bus_type == dm37xx) {
|
||||
reg_write(omap_i2c_bus->regs->I2C_OA0, I2C_OWN_ADDRESS);
|
||||
} else {
|
||||
log_warn(&log, "Don't know how to set own address.\n");
|
||||
}
|
||||
|
||||
/* Set TX/RX Threshold to 1 and disable I2C DMA */
|
||||
reg_write(omap_i2c_bus->regs->I2C_BUF, 0x0000);
|
||||
|
||||
/* Bring the i2c module out of reset */
|
||||
reg_set_bit(omap_i2c_bus->regs->I2C_CON, I2C_EN);
|
||||
micro_delay(50000);
|
||||
|
||||
/*
|
||||
* Enable interrupts
|
||||
*/
|
||||
omap_i2c_intr_enable();
|
||||
}
|
||||
|
||||
static uint16_t
|
||||
omap_i2c_read_status(void)
|
||||
{
|
||||
uint16_t status = 0x0000;
|
||||
|
||||
if (omap_i2c_bus->bus_type == am335x) {
|
||||
/* TRM says to use RAW for polling for events */
|
||||
status = reg_read(omap_i2c_bus->regs->I2C_IRQSTATUS_RAW);
|
||||
} else if (omap_i2c_bus->bus_type == dm37xx) {
|
||||
status = reg_read(omap_i2c_bus->regs->I2C_STAT);
|
||||
} else {
|
||||
log_warn(&log, "Don't know how to read i2c bus status.\n");
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
static void
|
||||
omap_i2c_write_status(uint16_t mask)
|
||||
{
|
||||
if (omap_i2c_bus->bus_type == am335x) {
|
||||
/* write 1's to IRQSTATUS (not RAW) to clear the bits */
|
||||
reg_write(omap_i2c_bus->regs->I2C_IRQSTATUS, mask);
|
||||
} else if (omap_i2c_bus->bus_type == dm37xx) {
|
||||
reg_write(omap_i2c_bus->regs->I2C_STAT, mask);
|
||||
} else {
|
||||
log_warn(&log, "Don't know how to clear i2c bus status.\n");
|
||||
}
|
||||
}
|
||||
|
||||
static int
|
||||
omap_i2c_read(i2c_addr_t addr, uint8_t * buf, size_t buflen, int dostop)
|
||||
{
|
||||
int r, i;
|
||||
uint16_t conopts = 0;
|
||||
uint16_t pollmask = 0;
|
||||
uint16_t errmask = 0;
|
||||
|
||||
/* Set address of slave device */
|
||||
addr &= ADDRESS_MASK; /* sanitize address (10-bit max) */
|
||||
if (addr > 0x7f) {
|
||||
/* 10-bit extended address in use, need to set XSA */
|
||||
conopts |= (1 << XSA);
|
||||
}
|
||||
|
||||
errmask |= (1 << ROVR);
|
||||
errmask |= (1 << AERR);
|
||||
errmask |= (1 << NACK);
|
||||
errmask |= (1 << AL);
|
||||
|
||||
pollmask |= (1 << RRDY);
|
||||
|
||||
/* Set bytes to read and slave address */
|
||||
reg_write(omap_i2c_bus->regs->I2C_CNT, buflen);
|
||||
reg_write(omap_i2c_bus->regs->I2C_SA, addr);
|
||||
|
||||
/* Set control register */
|
||||
conopts |= (1 << I2C_EN); /* enabled */
|
||||
conopts |= (1 << MST); /* master mode */
|
||||
conopts |= (1 << STT); /* start condition */
|
||||
|
||||
if (dostop != 0) {
|
||||
conopts |= (1 << STP); /* stop condition */
|
||||
}
|
||||
|
||||
reg_write(omap_i2c_bus->regs->I2C_CON, conopts);
|
||||
|
||||
for (i = 0; i < buflen; i++) {
|
||||
/* Data to read? */
|
||||
r = omap_i2c_poll(pollmask | errmask);
|
||||
if ((r & errmask) != 0) {
|
||||
/* only debug log level because i2cscan trigers this */
|
||||
log_debug(&log, "Read Error! Status=%x\n", r);
|
||||
return EIO;
|
||||
} else if ((r & pollmask) == 0) {
|
||||
log_warn(&log, "No RRDY Interrupt. Status=%x\n", r);
|
||||
log_warn(&log,
|
||||
"Likely cause: bad pinmux or no devices on bus\n");
|
||||
return EBUSY;
|
||||
}
|
||||
|
||||
/* read a byte */
|
||||
buf[i] = reg_read(omap_i2c_bus->regs->I2C_DATA) & 0xff;
|
||||
|
||||
/* clear the read ready flag */
|
||||
omap_i2c_write_status(pollmask);
|
||||
}
|
||||
|
||||
r = omap_i2c_read_status();
|
||||
if ((r & (1 << NACK)) != 0) {
|
||||
log_warn(&log, "NACK\n");
|
||||
return EIO;
|
||||
}
|
||||
|
||||
omap_i2c_write_status(0x7fff);
|
||||
micro_delay(50000);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
omap_i2c_write(i2c_addr_t addr, const uint8_t * buf, size_t buflen, int dostop)
|
||||
{
|
||||
int r, i;
|
||||
uint16_t conopts = 0;
|
||||
uint16_t pollmask = 0;
|
||||
uint16_t errmask = 0;
|
||||
|
||||
/* Set address of slave device */
|
||||
addr &= ADDRESS_MASK; /* sanitize address (10-bit max) */
|
||||
if (addr > 0x7f) {
|
||||
/* 10-bit extended address in use, need to set XSA */
|
||||
conopts |= (1 << XSA);
|
||||
}
|
||||
|
||||
pollmask |= (1 << XRDY);
|
||||
|
||||
errmask |= (1 << ROVR);
|
||||
errmask |= (1 << AERR);
|
||||
errmask |= (1 << NACK);
|
||||
errmask |= (1 << AL);
|
||||
|
||||
reg_write(omap_i2c_bus->regs->I2C_CNT, buflen);
|
||||
reg_write(omap_i2c_bus->regs->I2C_SA, addr);
|
||||
|
||||
/* Set control register */
|
||||
conopts |= (1 << I2C_EN); /* enabled */
|
||||
conopts |= (1 << MST); /* master mode */
|
||||
conopts |= (1 << TRX); /* TRX mode */
|
||||
conopts |= (1 << STT); /* start condition */
|
||||
|
||||
if (dostop != 0) {
|
||||
conopts |= (1 << STP); /* stop condition */
|
||||
}
|
||||
|
||||
omap_i2c_write_status(0x7fff);
|
||||
reg_write(omap_i2c_bus->regs->I2C_CON, conopts);
|
||||
|
||||
for (i = 0; i < buflen; i++) {
|
||||
|
||||
/* Ready to write? */
|
||||
r = omap_i2c_poll(pollmask | errmask);
|
||||
if ((r & errmask) != 0) {
|
||||
log_warn(&log, "Write Error! Status=%x\n", r);
|
||||
return EIO;
|
||||
} else if ((r & pollmask) == 0) {
|
||||
log_warn(&log, "Not ready for write? Status=%x\n", r);
|
||||
return EBUSY;
|
||||
}
|
||||
|
||||
reg_write(omap_i2c_bus->regs->I2C_DATA, buf[i]);
|
||||
|
||||
/* clear the write ready flag */
|
||||
omap_i2c_write_status(pollmask);
|
||||
}
|
||||
|
||||
r = omap_i2c_read_status();
|
||||
if ((r & (1 << NACK)) != 0) {
|
||||
return EIO;
|
||||
}
|
||||
|
||||
omap_i2c_write_status(0x7fff);
|
||||
micro_delay(50000);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int
|
||||
omap_interface_setup(int (**process) (minix_i2c_ioctl_exec_t * ioctl_exec),
|
||||
int i2c_bus_id)
|
||||
{
|
||||
int r;
|
||||
int i2c_rev, major, minor;
|
||||
struct minix_mem_range mr;
|
||||
|
||||
/* Fill in the function pointer */
|
||||
|
||||
*process = omap_i2c_process;
|
||||
|
||||
/* Select the correct i2c definition for this SoC */
|
||||
|
||||
#if defined(AM335X)
|
||||
omap_i2c_buses = am335x_i2c_buses;
|
||||
omap_i2c_nbuses = AM335X_OMAP_NBUSES;
|
||||
#elif defined(DM37XX)
|
||||
omap_i2c_buses = dm37xx_i2c_buses;
|
||||
omap_i2c_nbuses = DM37XX_OMAP_NBUSES;
|
||||
#else
|
||||
#error /* Unsupported SoC */
|
||||
#endif
|
||||
|
||||
if (i2c_bus_id < 0 || i2c_bus_id >= omap_i2c_nbuses) {
|
||||
return EINVAL;
|
||||
}
|
||||
|
||||
/* select the bus to operate on */
|
||||
omap_i2c_bus = &omap_i2c_buses[i2c_bus_id];
|
||||
|
||||
/*
|
||||
* Map I2C Registers
|
||||
*/
|
||||
|
||||
/* Configure memory access */
|
||||
mr.mr_base = omap_i2c_bus->mr_base; /* start addr */
|
||||
mr.mr_limit = mr.mr_base + omap_i2c_bus->mr_size; /* end addr */
|
||||
|
||||
/* ask for privileges to access the I2C memory range */
|
||||
if (sys_privctl(SELF, SYS_PRIV_ADD_MEM, &mr) != OK) {
|
||||
panic("Unable to obtain i2c memory range privileges");
|
||||
}
|
||||
|
||||
/* map the memory into this process */
|
||||
omap_i2c_bus->mapped_addr = (vir_bytes) vm_map_phys(SELF,
|
||||
(void *) omap_i2c_bus->mr_base, omap_i2c_bus->mr_size);
|
||||
|
||||
if (omap_i2c_bus->mapped_addr == (vir_bytes) MAP_FAILED) {
|
||||
panic("Unable to map i2c registers");
|
||||
}
|
||||
|
||||
/* Enable Clocks */
|
||||
omap_i2c_clkconf(i2c_bus_id);
|
||||
|
||||
#if 0
|
||||
/* disable until libpadconf is fixed */
|
||||
/* Configure Pins */
|
||||
omap_i2c_padconf(i2c_bus_id);
|
||||
#endif
|
||||
|
||||
/* Perform a soft reset of the I2C module to ensure a fresh start */
|
||||
r = omap_i2c_soft_reset();
|
||||
if (r != OK) {
|
||||
/* module didn't come back up :( */
|
||||
return r;
|
||||
}
|
||||
|
||||
/* Bring up I2C module */
|
||||
omap_i2c_bus_init();
|
||||
|
||||
/* Get I2C Revision */
|
||||
if (omap_i2c_bus->bus_type == am335x) {
|
||||
/* I2C_REVLO revision: major (bits 10-8), minor (bits 5-0) */
|
||||
i2c_rev = reg_read(omap_i2c_bus->regs->I2C_REVNB_LO);
|
||||
major = (i2c_rev >> 8) & 0x07;
|
||||
minor = i2c_rev & 0x3f;
|
||||
|
||||
} else if (omap_i2c_bus->bus_type == dm37xx) {
|
||||
/* I2C_REV revision: major (bits 7-4), minor (bits 3-0) */
|
||||
i2c_rev = reg_read(omap_i2c_bus->regs->I2C_REV);
|
||||
major = (i2c_rev >> 4) & 0x0f;
|
||||
minor = i2c_rev & 0x0f;
|
||||
} else {
|
||||
panic("Don't know how to read i2c revision.");
|
||||
}
|
||||
|
||||
if (major != omap_i2c_bus->major || minor != omap_i2c_bus->minor) {
|
||||
log_warn(&log, "Unrecognized value in I2C_REV register.\n");
|
||||
log_warn(&log, "Read: 0x%x.0x%x | Expected: 0x%x.0x%x\n",
|
||||
major, minor, omap_i2c_bus->major, omap_i2c_bus->minor);
|
||||
}
|
||||
|
||||
/* display i2c revision information for debugging purposes */
|
||||
log_debug(&log, "i2c_%d: I2C rev 0x%x.0x%x\n", (i2c_bus_id + 1),
|
||||
major, minor);
|
||||
|
||||
return OK;
|
||||
}
|
||||
@@ -0,0 +1,10 @@
|
||||
#ifndef _OMAP_I2C_H
|
||||
#define _OMAP_I2C_H
|
||||
|
||||
#include <minix/chardriver.h>
|
||||
#include <minix/i2c.h>
|
||||
#include "omap_i2c_registers.h"
|
||||
|
||||
int omap_interface_setup(int (**process)(minix_i2c_ioctl_exec_t *ioctl_exec), int i2c_bus_id);
|
||||
|
||||
#endif /* _OMAP_I2C_H */
|
||||
@@ -0,0 +1,152 @@
|
||||
#ifndef _OMAP_I2C_REGISTERS_H
|
||||
#define _OMAP_I2C_REGISTERS_H
|
||||
|
||||
/* I2C Addresses for am335x (BeagleBone White / BeagleBone Black) */
|
||||
|
||||
/* IRQ Numbers */
|
||||
#define AM335X_I2C0_IRQ 70
|
||||
#define AM335X_I2C1_IRQ 71
|
||||
#define AM335X_I2C2_IRQ 30
|
||||
|
||||
/* Base Addresses */
|
||||
#define AM335X_I2C0_BASE 0x44e0b000
|
||||
#define AM335X_I2C1_BASE 0x4802a000
|
||||
#define AM335X_I2C2_BASE 0x4819c000
|
||||
|
||||
/* Size of I2C Register Address Range */
|
||||
#define AM335X_I2C0_SIZE 0x1000
|
||||
#define AM335X_I2C1_SIZE 0x1000
|
||||
#define AM335X_I2C2_SIZE 0x1000
|
||||
|
||||
/* Register Offsets */
|
||||
#define AM335X_I2C_REVNB_LO 0x00
|
||||
#define AM335X_I2C_REVNB_HI 0x04
|
||||
#define AM335X_I2C_SYSC 0x10
|
||||
#define AM335X_I2C_IRQSTATUS_RAW 0x24
|
||||
#define AM335X_I2C_IRQSTATUS 0x28
|
||||
#define AM335X_I2C_IRQENABLE_SET 0x2c
|
||||
#define AM335X_I2C_IRQENABLE_CLR 0x30
|
||||
#define AM335X_I2C_WE 0x34
|
||||
#define AM335X_I2C_DMARXENABLE_SET 0x38
|
||||
#define AM335X_I2C_DMATXENABLE_SET 0x3c
|
||||
#define AM335X_I2C_DMARXENABLE_CLR 0x40
|
||||
#define AM335X_I2C_DMATXENABLE_CLR 0x44
|
||||
#define AM335X_I2C_DMARXWAKE_EN 0x48
|
||||
#define AM335X_I2C_DMATXWAKE_EN 0x4c
|
||||
#define AM335X_I2C_SYSS 0x90
|
||||
#define AM335X_I2C_BUF 0x94
|
||||
#define AM335X_I2C_CNT 0x98
|
||||
#define AM335X_I2C_DATA 0x9c
|
||||
#define AM335X_I2C_CON 0xa4
|
||||
#define AM335X_I2C_OA 0xa8
|
||||
#define AM335X_I2C_SA 0xac
|
||||
#define AM335X_I2C_PSC 0xb0
|
||||
#define AM335X_I2C_SCLL 0xb4
|
||||
#define AM335X_I2C_SCLH 0xb8
|
||||
#define AM335X_I2C_SYSTEST 0xbc
|
||||
#define AM335X_I2C_BUFSTAT 0xc0
|
||||
#define AM335X_I2C_OA1 0xc4
|
||||
#define AM335X_I2C_OA2 0xc8
|
||||
#define AM335X_I2C_OA3 0xcc
|
||||
#define AM335X_I2C_ACTOA 0xd0
|
||||
#define AM335X_I2C_SBLOCK 0xd4
|
||||
|
||||
/* Constants */
|
||||
#define AM335X_FUNCTIONAL_CLOCK 96000000 /* 96 MHz */
|
||||
#define AM335X_MODULE_CLOCK 12000000 /* 12 MHz */
|
||||
|
||||
/* I2C_REV value found on the BeagleBone / BeagleBone Black */
|
||||
#define AM335X_REV_MAJOR 0x00
|
||||
#define AM335X_REV_MINOR 0x0b
|
||||
|
||||
/* I2C Addresses for dm37xx (BeagleBoard-xM) */
|
||||
|
||||
/* IRQ Numbers */
|
||||
#define DM37XX_I2C0_IRQ 56
|
||||
#define DM37XX_I2C1_IRQ 57
|
||||
#define DM37XX_I2C2_IRQ 61
|
||||
|
||||
/* Base Addresses */
|
||||
#define DM37XX_I2C0_BASE 0x48070000
|
||||
#define DM37XX_I2C1_BASE 0x48072000
|
||||
#define DM37XX_I2C2_BASE 0x48060000
|
||||
|
||||
/* Size of I2C Register Address Range */
|
||||
#define DM37XX_I2C0_SIZE 0x1000
|
||||
#define DM37XX_I2C1_SIZE 0x1000
|
||||
#define DM37XX_I2C2_SIZE 0x1000
|
||||
|
||||
/* Register Offsets */
|
||||
#define DM37XX_I2C_REV 0x00
|
||||
#define DM37XX_I2C_IE 0x04
|
||||
#define DM37XX_I2C_STAT 0x08
|
||||
#define DM37XX_I2C_WE 0x0C
|
||||
#define DM37XX_I2C_SYSS 0x10
|
||||
#define DM37XX_I2C_BUF 0x14
|
||||
#define DM37XX_I2C_CNT 0x18
|
||||
#define DM37XX_I2C_DATA 0x1c
|
||||
#define DM37XX_I2C_SYSC 0x20
|
||||
#define DM37XX_I2C_CON 0x24
|
||||
#define DM37XX_I2C_OA0 0x28
|
||||
#define DM37XX_I2C_SA 0x2c
|
||||
#define DM37XX_I2C_PSC 0x30
|
||||
#define DM37XX_I2C_SCLL 0x34
|
||||
#define DM37XX_I2C_SCLH 0x38
|
||||
#define DM37XX_I2C_SYSTEST 0x3c
|
||||
#define DM37XX_I2C_BUFSTAT 0x40
|
||||
#define DM37XX_I2C_OA1 0x44
|
||||
#define DM37XX_I2C_OA2 0x48
|
||||
#define DM37XX_I2C_OA3 0x4c
|
||||
#define DM37XX_I2C_ACTOA 0x50
|
||||
#define DM37XX_I2C_SBLOCK 0x54
|
||||
|
||||
/* Constants */
|
||||
#define DM37XX_FUNCTIONAL_CLOCK 96000000 /* 96 MHz */
|
||||
#define DM37XX_MODULE_CLOCK 19200000 /* 19.2 MHz */
|
||||
|
||||
#define DM37XX_REV_MAJOR 0x04
|
||||
#define DM37XX_REV_MINOR 0x00
|
||||
|
||||
/* Shared Values */
|
||||
|
||||
#define BUS_SPEED_100KHz 100000 /* 100 KHz */
|
||||
#define BUS_SPEED_400KHz 400000 /* 400 KHz */
|
||||
#define I2C_OWN_ADDRESS 0x01
|
||||
|
||||
/* Masks */
|
||||
|
||||
#define ADDRESS_MASK (0x3ff) /* Highest 10 bit address -- 9..0 */
|
||||
|
||||
/* Bit Offsets within Registers (only those used are listed) */
|
||||
|
||||
/* Same offsets for both dm37xx and am335x */
|
||||
|
||||
#define I2C_EN 15 /* I2C_CON */
|
||||
#define MST 10 /* I2C_CON */
|
||||
#define TRX 9 /* I2C_CON */
|
||||
#define XSA 8 /* I2C_CON */
|
||||
#define STP 1 /* I2C_CON */
|
||||
#define STT 0 /* I2C_CON */
|
||||
|
||||
#define CLKACTIVITY_S 9 /* I2C_SYSC */
|
||||
#define CLKACTIVITY_I 8 /* I2C_SYSC */
|
||||
#define SMART_WAKE_UP 4 /* I2C_SYSC */
|
||||
#define NO_IDLE_MODE 3 /* I2C_SYSC */
|
||||
#define SRST 1 /* I2C_SYSC */
|
||||
#define AUTOIDLE 0 /* I2C_SYSC */
|
||||
|
||||
#define RDONE 0 /* I2C_SYSS */
|
||||
|
||||
#define RXFIFO_CLR 14 /* I2C_BUF */
|
||||
#define TXFIFO_CLR 6 /* I2C_BUF */
|
||||
|
||||
#define BB 12 /* I2C_IRQSTATUS / I2C_STAT / I2C_IRQENABLE_SET / I2C_IE */
|
||||
#define ROVR 11 /* I2C_IRQSTATUS / I2C_STAT / I2C_IRQENABLE_SET / I2C_IE */
|
||||
#define AERR 7 /* I2C_IRQSTATUS / I2C_STAT / I2C_IRQENABLE_SET / I2C_IE */
|
||||
#define XRDY 4 /* I2C_IRQSTATUS / I2C_STAT / I2C_IRQENABLE_SET / I2C_IE */
|
||||
#define RRDY 3 /* I2C_IRQSTATUS / I2C_STAT / I2C_IRQENABLE_SET / I2C_IE */
|
||||
#define ARDY 2 /* I2C_IRQSTATUS / I2C_STAT / I2C_IRQENABLE_SET / I2C_IE */
|
||||
#define NACK 1 /* I2C_IRQSTATUS / I2C_STAT / I2C_IRQENABLE_SET / I2C_IE */
|
||||
#define AL 0 /* I2C_IRQSTATUS / I2C_STAT / I2C_IRQENABLE_SET / I2C_IE */
|
||||
|
||||
#endif /* _OMAP_I2C_REGISTERS_H */
|
||||
@@ -0,0 +1,555 @@
|
||||
/*
|
||||
* i2c - generic driver for Inter-Integrated Circuit bus (I2C).
|
||||
*/
|
||||
|
||||
/* kernel headers */
|
||||
#include <minix/chardriver.h>
|
||||
#include <minix/drivers.h>
|
||||
#include <minix/ds.h>
|
||||
#include <minix/i2c.h>
|
||||
#include <minix/log.h>
|
||||
#include <minix/type.h>
|
||||
|
||||
/* system headers */
|
||||
#include <sys/mman.h>
|
||||
|
||||
/* usr headers */
|
||||
#include <string.h>
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
|
||||
/* SoC specific headers - 1 for each SoC */
|
||||
#include "omap_i2c.h"
|
||||
|
||||
/* local definitions */
|
||||
|
||||
/* i2c slave addresses can be up to 10 bits */
|
||||
#define NR_I2CDEV (0x3ff)
|
||||
|
||||
/* local function prototypes */
|
||||
static int do_reserve(endpoint_t endpt, int slave_addr);
|
||||
static int check_reservation(endpoint_t endpt, int slave_addr);
|
||||
static void update_reservation(endpoint_t endpt, char *key);
|
||||
static void ds_event(void);
|
||||
|
||||
static int validate_ioctl_exec(minix_i2c_ioctl_exec_t * ioctl_exec);
|
||||
static int do_i2c_ioctl_exec(message * m);
|
||||
|
||||
static int env_parse_instance(void);
|
||||
|
||||
/* libchardriver callbacks */
|
||||
int i2c_ioctl(message * m);
|
||||
struct device *i2c_prepare(dev_t dev);
|
||||
int i2c_transfer(endpoint_t endpt, int opcode, u64_t position,
|
||||
iovec_t * iov, unsigned nr_req, endpoint_t user_endpt, unsigned int flags);
|
||||
int i2c_other(message * m);
|
||||
|
||||
/* SEF callbacks and driver state management */
|
||||
static int sef_cb_lu_state_save(int);
|
||||
static int lu_state_restore(void);
|
||||
static int sef_cb_init(int type, sef_init_info_t * info);
|
||||
static void sef_local_startup(void);
|
||||
|
||||
/* Globals */
|
||||
|
||||
/* the bus that this instance of the driver is responsible for */
|
||||
uint32_t i2c_bus_id;
|
||||
|
||||
/* Table of i2c device reservations. */
|
||||
static struct i2cdev
|
||||
{
|
||||
uint8_t inuse;
|
||||
endpoint_t endpt;
|
||||
char key[DS_MAX_KEYLEN];
|
||||
} i2cdev[NR_I2CDEV];
|
||||
|
||||
/* Process a request for an i2c operation.
|
||||
* This is the interface that all hardware specific code must implement.
|
||||
*/
|
||||
int (*process) (minix_i2c_ioctl_exec_t * ioctl_exec);
|
||||
|
||||
struct device i2c_device;
|
||||
|
||||
/* logging - use with log_warn(), log_info(), log_debug(), log_trace() */
|
||||
static struct log log = {
|
||||
.name = "i2c",
|
||||
.log_level = LEVEL_INFO,
|
||||
.log_func = default_log
|
||||
};
|
||||
|
||||
/* Entry points to the i2c driver from libchardriver.
|
||||
* Only i2c_ioctl() and i2c_other() are implemented. The rest are no-op.
|
||||
*/
|
||||
static struct chardriver i2c_tab = {
|
||||
.cdr_open = do_nop,
|
||||
.cdr_close = do_nop,
|
||||
.cdr_ioctl = i2c_ioctl,
|
||||
.cdr_prepare = i2c_prepare,
|
||||
.cdr_transfer = i2c_transfer,
|
||||
.cdr_cleanup = nop_cleanup,
|
||||
.cdr_alarm = nop_alarm,
|
||||
.cdr_cancel = nop_cancel,
|
||||
.cdr_select = nop_select,
|
||||
.cdr_other = i2c_other
|
||||
};
|
||||
|
||||
/*
|
||||
* Claim an unclaimed device for exclusive use by endpt. This function can
|
||||
* also be used to update the endpt if the endpt's label matches the label
|
||||
* already associated with the slave address. This is useful if a driver
|
||||
* shuts down unexpectedly and starts up with a new endpt and wants to reserve
|
||||
* the same device it reserved before.
|
||||
*/
|
||||
static int
|
||||
do_reserve(endpoint_t endpt, int slave_addr)
|
||||
{
|
||||
int r;
|
||||
char key[DS_MAX_KEYLEN];
|
||||
char label[DS_MAX_KEYLEN];
|
||||
|
||||
/* find the label for the endpoint */
|
||||
r = ds_retrieve_label_name(label, endpt);
|
||||
if (r != OK) {
|
||||
log_warn(&log, "Couldn't find label for endpt='0x%x'\n",
|
||||
endpt);
|
||||
return r;
|
||||
}
|
||||
|
||||
/* construct the key i2cdriver_announce published (saves an IPC call) */
|
||||
snprintf(key, DS_MAX_KEYLEN, "drv.i2c.%d.%s", i2c_bus_id + 1, label);
|
||||
|
||||
if (slave_addr < 0 || slave_addr >= NR_I2CDEV) {
|
||||
log_debug(&log,
|
||||
"slave address must be positive & no more than 10 bits\n");
|
||||
return EINVAL;
|
||||
}
|
||||
|
||||
/* check if device is in use by another driver */
|
||||
if (i2cdev[slave_addr].inuse != 0
|
||||
&& strncmp(i2cdev[slave_addr].key, key, DS_MAX_KEYLEN) != 0) {
|
||||
log_debug(&log, "address in use by '%s'/0x%x\n",
|
||||
i2cdev[slave_addr].key, i2cdev[slave_addr].endpt);
|
||||
return EBUSY;
|
||||
}
|
||||
|
||||
/* device is free or already owned by us, claim it */
|
||||
i2cdev[slave_addr].inuse = 1;
|
||||
i2cdev[slave_addr].endpt = endpt;
|
||||
memcpy(i2cdev[slave_addr].key, key, DS_MAX_KEYLEN);
|
||||
|
||||
sef_cb_lu_state_save(0); /* save reservations */
|
||||
|
||||
log_debug(&log, "Device 0x%x claimed by 0x%x key='%s'\n",
|
||||
slave_addr, endpt, key);
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
/*
|
||||
* All drivers must reserve their device(s) before doing operations on them
|
||||
* (read/write, etc). ioctl()'s from VFS (i.e. user programs) can only use
|
||||
* devices that haven't been reserved. A driver isn't allowed to access a
|
||||
* device that another driver has reserved (not even other instances of the
|
||||
* same driver).
|
||||
*/
|
||||
static int
|
||||
check_reservation(endpoint_t endpt, int slave_addr)
|
||||
{
|
||||
if (slave_addr < 0 || slave_addr >= NR_I2CDEV) {
|
||||
log_debug(&log,
|
||||
"slave address must be positive & no more than 10 bits\n");
|
||||
return EINVAL;
|
||||
}
|
||||
|
||||
if (endpt == VFS_PROC_NR && i2cdev[slave_addr].inuse == 0) {
|
||||
log_debug(&log,
|
||||
"allowing ioctl() from VFS to access unclaimed device\n");
|
||||
return OK;
|
||||
}
|
||||
|
||||
if (i2cdev[slave_addr].inuse && i2cdev[slave_addr].endpt != endpt) {
|
||||
log_debug(&log, "device reserved by another endpoint\n");
|
||||
return EBUSY;
|
||||
} else if (i2cdev[slave_addr].inuse == 0) {
|
||||
log_debug(&log,
|
||||
"all drivers sending messages directly to this driver must reserve\n");
|
||||
return EPERM;
|
||||
} else {
|
||||
log_debug(&log, "allowing access to registered device\n");
|
||||
return OK;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* i2c listens to updates from ds about i2c device drivers starting up.
|
||||
* When a driver comes back up with the same label, the endpt associated
|
||||
* with the reservation needs to be updated. This function does the updating.
|
||||
*/
|
||||
static void
|
||||
update_reservation(endpoint_t endpt, char *key)
|
||||
{
|
||||
int i;
|
||||
|
||||
log_debug(&log, "Updating reservation for '%s' endpt=0x%x\n", key,
|
||||
endpt);
|
||||
|
||||
for (i = 0; i < NR_I2CDEV; i++) {
|
||||
|
||||
/* find devices in use that the driver owns */
|
||||
if (i2cdev[i].inuse != 0
|
||||
&& strncmp(i2cdev[i].key, key, DS_MAX_KEYLEN) == 0) {
|
||||
/* update reservation with new endpoint */
|
||||
do_reserve(endpt, i);
|
||||
log_debug(&log, "Found device to update 0x%x\n", i);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Checks a minix_i2c_ioctl_exec_t to see if the fields make sense.
|
||||
*/
|
||||
static int
|
||||
validate_ioctl_exec(minix_i2c_ioctl_exec_t * ioctl_exec)
|
||||
{
|
||||
i2c_op_t op;
|
||||
i2c_addr_t addr;
|
||||
size_t len;
|
||||
|
||||
op = ioctl_exec->iie_op;
|
||||
if (op != I2C_OP_READ &&
|
||||
op != I2C_OP_READ_WITH_STOP &&
|
||||
op != I2C_OP_WRITE &&
|
||||
op != I2C_OP_WRITE_WITH_STOP &&
|
||||
op != I2C_OP_READ_BLOCK && op != I2C_OP_WRITE_BLOCK) {
|
||||
log_warn(&log, "iie_op value not valid\n");
|
||||
return EINVAL;
|
||||
}
|
||||
|
||||
addr = ioctl_exec->iie_addr;
|
||||
if (addr < 0 || addr >= NR_I2CDEV) {
|
||||
log_warn(&log, "iie_addr out of range 0x0-0x%x\n", NR_I2CDEV);
|
||||
return EINVAL;
|
||||
}
|
||||
|
||||
len = ioctl_exec->iie_cmdlen;
|
||||
if (len < 0 || len > I2C_EXEC_MAX_CMDLEN) {
|
||||
log_warn(&log,
|
||||
"iie_cmdlen out of range 0-I2C_EXEC_MAX_CMDLEN\n");
|
||||
return EINVAL;
|
||||
}
|
||||
|
||||
len = ioctl_exec->iie_buflen;
|
||||
if (len < 0 || len > I2C_EXEC_MAX_BUFLEN) {
|
||||
log_warn(&log,
|
||||
"iie_buflen out of range 0-I2C_EXEC_MAX_BUFLEN\n");
|
||||
return EINVAL;
|
||||
}
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
/*
|
||||
* Performs the action in minix_i2c_ioctl_exec_t.
|
||||
*/
|
||||
static int
|
||||
do_i2c_ioctl_exec(message * m)
|
||||
{
|
||||
int r;
|
||||
endpoint_t caller;
|
||||
cp_grant_id_t grant_nr;
|
||||
minix_i2c_ioctl_exec_t ioctl_exec;
|
||||
|
||||
caller = (endpoint_t) m->m_source;
|
||||
grant_nr = (cp_grant_id_t) m->IO_GRANT;
|
||||
|
||||
/* Copy the requested exection into the driver */
|
||||
r = sys_safecopyfrom(caller, grant_nr, (vir_bytes) 0,
|
||||
(vir_bytes) & ioctl_exec, sizeof(ioctl_exec));
|
||||
if (r != OK) {
|
||||
log_warn(&log, "sys_safecopyfrom() failed\n");
|
||||
return r;
|
||||
}
|
||||
|
||||
/* input validation */
|
||||
r = validate_ioctl_exec(&ioctl_exec);
|
||||
if (r != OK) {
|
||||
log_debug(&log, "Message validation failed\n");
|
||||
return r;
|
||||
}
|
||||
|
||||
/* permission check */
|
||||
r = check_reservation(caller, ioctl_exec.iie_addr);
|
||||
if (r != OK) {
|
||||
log_debug(&log, "check_reservation() denied the request\n");
|
||||
return r;
|
||||
}
|
||||
|
||||
/* Call the device specific code to execute the action */
|
||||
r = process(&ioctl_exec);
|
||||
if (r != OK) {
|
||||
log_debug(&log, "process() failed\n");
|
||||
return r;
|
||||
}
|
||||
|
||||
/* Copy the results of the execution back to the calling process */
|
||||
r = sys_safecopyto(caller, grant_nr, (vir_bytes) 0,
|
||||
(vir_bytes) & ioctl_exec, sizeof(ioctl_exec));
|
||||
if (r != OK) {
|
||||
log_warn(&log, "sys_safecopyto() failed\n");
|
||||
return r;
|
||||
}
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
int
|
||||
i2c_ioctl(message * m)
|
||||
{
|
||||
int r;
|
||||
|
||||
switch (m->COUNT) {
|
||||
case MINIX_I2C_IOCTL_EXEC:
|
||||
r = do_i2c_ioctl_exec(m);
|
||||
break;
|
||||
default:
|
||||
log_warn(&log, "Invalid ioctl() 0x%x\n", m->COUNT);
|
||||
r = EINVAL;
|
||||
break;
|
||||
}
|
||||
|
||||
return r;
|
||||
}
|
||||
|
||||
int
|
||||
i2c_other(message * m)
|
||||
{
|
||||
int r;
|
||||
|
||||
switch (m->m_type) {
|
||||
case BUSC_I2C_RESERVE:
|
||||
/* reserve a device on the bus for exclusive access */
|
||||
r = do_reserve((endpoint_t) m->m_source, m->DEVICE);
|
||||
break;
|
||||
case BUSC_I2C_EXEC:
|
||||
/* handle request from another driver */
|
||||
m->COUNT = MINIX_I2C_IOCTL_EXEC;
|
||||
r = do_i2c_ioctl_exec(m);
|
||||
break;
|
||||
case NOTIFY_MESSAGE:
|
||||
/* handle notifications about drivers changing state */
|
||||
if (m->m_source == DS_PROC_NR) {
|
||||
ds_event();
|
||||
}
|
||||
r = OK;
|
||||
break;
|
||||
default:
|
||||
log_warn(&log, "Invalid message type (0x%x)\n", m->m_type);
|
||||
r = EINVAL;
|
||||
break;
|
||||
}
|
||||
|
||||
log_trace(&log, "i2c_other() returning r=%d\n", r);
|
||||
|
||||
return r;
|
||||
}
|
||||
|
||||
struct device *
|
||||
i2c_prepare(dev_t dev)
|
||||
{
|
||||
/* NOP */
|
||||
i2c_device.dv_base = make64(0, 0);
|
||||
i2c_device.dv_size = make64(0, 0);
|
||||
|
||||
return &i2c_device;
|
||||
}
|
||||
|
||||
int
|
||||
i2c_transfer(endpoint_t endpt, int opcode, u64_t position,
|
||||
iovec_t * iov, unsigned nr_req, endpoint_t user_endpt, unsigned int flags)
|
||||
{
|
||||
/* NOP */
|
||||
return OK;
|
||||
}
|
||||
|
||||
/*
|
||||
* The bus drivers are subscribed to DS events about device drivers on their
|
||||
* bus. When the device drivers restart, DS sends a notification and this
|
||||
* function updates the reservation table with the device driver's new
|
||||
* endpoint.
|
||||
*/
|
||||
static void
|
||||
ds_event(void)
|
||||
{
|
||||
char key[DS_MAX_KEYLEN];
|
||||
u32_t value;
|
||||
int type;
|
||||
endpoint_t owner_endpoint;
|
||||
int r;
|
||||
|
||||
/* check for pending events */
|
||||
while ((r = ds_check(key, &type, &owner_endpoint)) == OK) {
|
||||
|
||||
r = ds_retrieve_u32(key, &value);
|
||||
if (r != OK) {
|
||||
log_warn(&log, "ds_retrieve_u32() failed r=%d\n", r);
|
||||
return;
|
||||
}
|
||||
|
||||
log_debug(&log, "key='%s' owner_endpoint=0x%x\n", key,
|
||||
owner_endpoint);
|
||||
|
||||
if (value == DS_DRIVER_UP) {
|
||||
/* clean up any old reservations the driver had */
|
||||
log_debug(&log, "DS_DRIVER_UP\n");
|
||||
update_reservation(owner_endpoint, key);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static int
|
||||
sef_cb_lu_state_save(int UNUSED(state))
|
||||
{
|
||||
int r;
|
||||
char key[DS_MAX_KEYLEN];
|
||||
|
||||
memset(key, '\0', DS_MAX_KEYLEN);
|
||||
snprintf(key, DS_MAX_KEYLEN, "i2c.%d.i2cdev", i2c_bus_id + 1);
|
||||
r = ds_publish_mem(key, i2cdev, sizeof(i2cdev), DSF_OVERWRITE);
|
||||
if (r != OK) {
|
||||
log_warn(&log, "ds_publish_mem(%s) failed (r=%d)\n", key, r);
|
||||
return r;
|
||||
}
|
||||
|
||||
log_debug(&log, "State Saved\n");
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
static int
|
||||
lu_state_restore(void)
|
||||
{
|
||||
int r;
|
||||
char key[DS_MAX_KEYLEN];
|
||||
size_t size;
|
||||
|
||||
env_parse_instance();
|
||||
|
||||
size = sizeof(i2cdev);
|
||||
|
||||
memset(key, '\0', DS_MAX_KEYLEN);
|
||||
snprintf(key, DS_MAX_KEYLEN, "i2c.%d.i2cdev", i2c_bus_id + 1);
|
||||
|
||||
r = ds_retrieve_mem(key, (char *) i2cdev, &size);
|
||||
if (r != OK) {
|
||||
log_warn(&log, "ds_retrieve_mem(%s) failed (r=%d)\n", key, r);
|
||||
return r;
|
||||
}
|
||||
|
||||
log_debug(&log, "State Restored\n");
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
static int
|
||||
sef_cb_init(int type, sef_init_info_t * UNUSED(info))
|
||||
{
|
||||
int r;
|
||||
char regex[DS_MAX_KEYLEN];
|
||||
|
||||
if (type != SEF_INIT_FRESH) {
|
||||
/* Restore a prior state. */
|
||||
lu_state_restore();
|
||||
}
|
||||
#if defined(AM335X) || defined(DM37XX)
|
||||
/* Set callback and initialize the bus */
|
||||
r = omap_interface_setup(&process, i2c_bus_id);
|
||||
if (r != OK) {
|
||||
return r;
|
||||
}
|
||||
#else
|
||||
#error /* Unknown SoC or bad configuration */
|
||||
#endif
|
||||
|
||||
/* Announce we are up when necessary. */
|
||||
if (type != SEF_INIT_LU) {
|
||||
|
||||
/* only capture events for this particular bus */
|
||||
snprintf(regex, DS_MAX_KEYLEN, "drv\\.i2c\\.%d\\..*",
|
||||
i2c_bus_id + 1);
|
||||
|
||||
/* Subscribe to driver events for i2c drivers */
|
||||
r = ds_subscribe(regex, DSF_INITIAL | DSF_OVERWRITE);
|
||||
if (r != OK) {
|
||||
log_warn(&log, "ds_subscribe() failed\n");
|
||||
return r;
|
||||
}
|
||||
|
||||
chardriver_announce();
|
||||
}
|
||||
|
||||
/* Save state */
|
||||
sef_cb_lu_state_save(0);
|
||||
|
||||
/* Initialization completed successfully. */
|
||||
return OK;
|
||||
}
|
||||
|
||||
static void
|
||||
sef_local_startup()
|
||||
{
|
||||
/* Register init callbacks. */
|
||||
sef_setcb_init_fresh(sef_cb_init);
|
||||
sef_setcb_init_lu(sef_cb_init);
|
||||
sef_setcb_init_restart(sef_cb_init);
|
||||
|
||||
/* Register live update callbacks */
|
||||
/* Agree to update immediately when LU is requested in a valid state */
|
||||
sef_setcb_lu_prepare(sef_cb_lu_prepare_always_ready);
|
||||
/* - Support live update starting from any standard state */
|
||||
sef_setcb_lu_state_isvalid(sef_cb_lu_state_isvalid_standard);
|
||||
/* - Register a custom routine to save the state. */
|
||||
sef_setcb_lu_state_save(sef_cb_lu_state_save);
|
||||
|
||||
/* Let SEF perform startup. */
|
||||
sef_startup();
|
||||
}
|
||||
|
||||
static int
|
||||
env_parse_instance(void)
|
||||
{
|
||||
int r;
|
||||
long instance;
|
||||
|
||||
/* Parse the instance number passed to service */
|
||||
instance = 0;
|
||||
r = env_parse("instance", "d", 0, &instance, 1, 3);
|
||||
if (r == -1) {
|
||||
log_warn(&log,
|
||||
"Expecting '-arg instance=N' argument (N=1..3)\n");
|
||||
return EXIT_FAILURE;
|
||||
}
|
||||
|
||||
/* Device files count from 1, hardware starts counting from 0 */
|
||||
i2c_bus_id = instance - 1;
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
int
|
||||
main(int argc, char *argv[])
|
||||
{
|
||||
int r;
|
||||
|
||||
env_setargs(argc, argv);
|
||||
|
||||
r = env_parse_instance();
|
||||
if (r != OK) {
|
||||
return r;
|
||||
}
|
||||
|
||||
memset(i2cdev, '\0', sizeof(i2cdev));
|
||||
sef_local_startup();
|
||||
chardriver_task(&i2c_tab, CHARDRIVER_SYNC);
|
||||
|
||||
return OK;
|
||||
}
|
||||
Reference in New Issue
Block a user