From 7442558681c085e1265ca66d474d4d1ea122a63b Mon Sep 17 00:00:00 2001 From: Korobov Nikita Date: Wed, 12 Jul 2017 16:09:05 +0300 Subject: [PATCH] [CLEANUP] The tty constants updated --- minix/drivers/tty/tty/arch/earm/pl011.c | 30 ++-- .../drivers/tty/tty/arch/earm/pl011_serial.h | 142 +++--------------- 2 files changed, 35 insertions(+), 137 deletions(-) diff --git a/minix/drivers/tty/tty/arch/earm/pl011.c b/minix/drivers/tty/tty/arch/earm/pl011.c index 758c061a0..c38bad68b 100644 --- a/minix/drivers/tty/tty/arch/earm/pl011.c +++ b/minix/drivers/tty/tty/arch/earm/pl011.c @@ -51,10 +51,10 @@ typedef struct rs232 { #define ODONE 1 /* output completed (< output enable bits) */ #define ORAW 2 /* raw mode for xoff disable (< enab. bits) */ #define OWAKEUP 4 /* tty_wakeup() pending (asm code only) */ -#define ODEVREADY UART_MSR_CTS /* external device hardware ready (CTS) */ +#define ODEVREADY PL011_FR_CTS /* external device hardware ready (CTS) */ #define OQUEUED 0x20 /* output buffer not empty */ #define OSWREADY 0x40 /* external device software ready (no xoff) */ -#define ODEVHUP UART_MSR_DCD /* external device has dropped carrier */ +#define ODEVHUP 0x80 /* external device has dropped carrier */ #define OSOFTBITS (ODONE | ORAW | OWAKEUP | OQUEUED | OSWREADY) /* user-defined bits */ #if (OSOFTBITS | ODEVREADY | ODEVHUP) == OSOFTBITS @@ -148,7 +148,7 @@ rs_reset(rs232_t *rs) { unsigned int fr; - fr = PL011_RXFE | PL011_TXFE | PL011_CTS; + fr = PL011_FR_RXFE | PL011_FR_TXFE | PL011_FR_CTS; serial_out(rs, PL011_FR, fr); } @@ -276,12 +276,10 @@ static void rs_config(rs232_t *rs) tty_t *tp = rs->tty; rs->ostate = ODEVREADY | ORAW | OSWREADY; /* reads MSR */ - - /* - * XXX: Disable FIFO otherwise only half of every received character - * will trigger an interrupt. - */ + /* Enable FIFO */ serial_out(rs, PL011_LCR_H, serial_in(rs, PL011_LCR_H) | PL011_LCR_FEN); + /* Set level of FIFO filling in */ + serial_out(rs, PL011_IFLS, PL011_IFLS_TXIFLSEL12 | PL011_IFLS_RXIFLSEL12); /* Set interrupt levels */ serial_out(rs, PL011_IFLS, 0x0); @@ -388,7 +386,7 @@ rs_init(tty_t *tp) tp->tty_open = rs_open; tp->tty_close = rs_close; - serial_out(rs, PL011_IMSC, PL011_RXRIS); + serial_out(rs, PL011_IMSC, PL011_RIS_RXRIS); } void @@ -402,7 +400,7 @@ rs_interrupt(message *m) case CLOCK: for (line = 0, rs = rs_lines; line < NR_RS_LINES; line++, rs++) { if (rs->phys_base != 0) { - if ((serial_in(rs, PL011_FR) & PL011_RXFE) == 0) { + if ((serial_in(rs, PL011_FR) & PL011_FR_RXFE) == 0) { read_chars(rs); } if (sys_irqenable(&rs->irq_hook_kernel_id) != OK) @@ -488,7 +486,7 @@ rs_ostart(rs232_t *rs) rs->ostate |= OQUEUED; write_chars(rs); - serial_out(rs, PL011_IMSC, PL011_TXRIS|PL011_RXRIS); + serial_out(rs, PL011_IMSC, PL011_RIS_TXRIS | PL011_RIS_RXRIS); } static int @@ -530,12 +528,12 @@ rs232_handler(struct rs232 *rs) ris = serial_in(rs, PL011_RIS); - if (ris & PL011_RXRIS) { + if (ris & PL011_RIS_RXRIS) { /* Data ready interrupt */ read_chars(rs); } rs->ostate |= ODEVREADY; - if (ris & PL011_TXRIS) { + if (ris & PL011_RIS_TXRIS) { /* Ready to send and space available */ write_chars(rs); } @@ -549,7 +547,7 @@ read_chars(rs232_t *rs) unsigned char c; /* check the line status to know if there are more chars */ - while ((serial_in(rs, PL011_FR) & PL011_RXFE) == 0) { + while ((serial_in(rs, PL011_FR) & PL011_FR_RXFE) == 0) { c = serial_in(rs, PL011_DR); if (!(rs->ostate & ORAW)) { if (c == rs->oxoff) { @@ -585,13 +583,13 @@ write_chars(rs232_t *rs) * known ready). * Notify TTY when the buffer goes empty. */ - while ((rs->ostate >= (OQUEUED | OSWREADY)) && ((serial_in(rs, PL011_FR) & PL011_TXFF) == 0)) { + while ((rs->ostate >= (OQUEUED | OSWREADY)) && ((serial_in(rs, PL011_FR) & PL011_FR_TXFF) == 0)) { /* Bit test allows ORAW and requires the others. */ serial_out(rs, PL011_DR, *rs->otail); if (++rs->otail == bufend(rs->obuf)) rs->otail = rs->obuf; if (--rs->ocount == 0) { - serial_out(rs, PL011_IMSC, PL011_RXRIS); + serial_out(rs, PL011_IMSC, PL011_RIS_RXRIS); /* Turn on ODONE flag, turn off OQUEUED */ rs->ostate ^= (ODONE | OQUEUED); rs->tty->tty_events = 1; diff --git a/minix/drivers/tty/tty/arch/earm/pl011_serial.h b/minix/drivers/tty/tty/arch/earm/pl011_serial.h index a1459c98b..344f0d3fb 100644 --- a/minix/drivers/tty/tty/arch/earm/pl011_serial.h +++ b/minix/drivers/tty/tty/arch/earm/pl011_serial.h @@ -20,23 +20,20 @@ #define PL011_ICR 0x044 /* Interrupt clear register */ #define PL011_DMACR 0x048 /* DMA control register */ -#define PL011_RXRIS 0x10 -#define PL011_TXRIS 0x20 +/* Raw interrupt status register */ +#define PL011_RIS_RXRIS 0x10 /* receiver interrupt */ +#define PL011_RIS_TXRIS 0x20 /* transmiter interrupt */ +#define PL011_RIS_RTRIS 0x40 /* timeout interrupt */ /* Flag Register bits */ -#define PL011_RXFE 0x10 -#define PL011_TXFF 0x20 -#define PL011_TXFE 0x80 -#define PL011_CTS 0x00 - - -// Send break. If this bit is set to 1, a low-level is continually output on the UARTTXD output, after -// completing transmission of the current character. For the proper execution of the break command, the -// software must set this bit for at least two complete frames. -// For normal use, this bit must be cleared to 0 +#define PL011_FR_RXFE 0x10 /* receive fifo is empty */ +#define PL011_FR_TXFF 0x20 /* transmit fifo is full */ +#define PL011_FR_RXFF 0x40 /* receive fifo is full */ +#define PL011_FR_TXFE 0x80 /* transmit fifo is empty */ +#define PL011_FR_CTS 0x00 /* clear to send */ /* Line Control Register bits */ -#define PL011_LCR_BRK 0x00 /* Send break */ +#define PL011_LCR_BRK 0x01 /* Send break */ #define PL011_LCR_EPS 0x04 /* Even parity select */ #define PL011_LCR_SPS 0x80 /* Stick parity select */ #define PL011_LCR_FEN 0x10 /* Enable FIFO */ @@ -47,113 +44,16 @@ #define PL011_LCR_WLEN7 0x40 /* Wordlength 7 bits */ #define PL011_LCR_WLEN8 0x60 /* Wordlength 8 bits */ -//// PL011_IMSC /* Interrupt mask set/clear register */ -//// UARTIMSC - -//// #define UART_IER_MSI 0x08 /* Modem status interrupt */ -//// UARTMSINTR ?? /* Modem status interrupt */ - -/* UART register map */ -// #define OMAP3_UART1_BASE 0x4806A000 /* UART1 physical address */ -// #define OMAP3_UART2_BASE 0x4806C000 /* UART2 physical address */ -// #define OMAP3_UART3_BASE 0x49020000 /* UART3 physical address */ - -// /* UART registers */ -// #define OMAP3_THR 0 /* Transmit holding register */ -// #define OMAP3_RHR 0 /* Receive holding register */ -// #define OMAP3_DLL 0 /* Divisor latches low */ -// #define OMAP3_DLH 1 /* Divisor latches high */ -// #define OMAP3_IER 1 /* Interrupt enable register */ -// #define OMAP3_IIR 2 /* Interrupt identification register */ -// #define OMAP3_EFR 2 /* Extended features register */ -// #define OMAP3_FCR 2 /* FIFO control register */ -// #define OMAP3_LCR 3 /* Line control register */ -// #define OMAP3_MCR 4 /* Modem control register */ -// #define OMAP3_LSR 5 /* Line status register */ -// #define OMAP3_MSR 6 /* Modem status register */ -// #define OMAP3_TCR 6 -// #define OMAP3_MDR1 0x08 /* Mode definition register 1 */ -// #define OMAP3_MDR2 0x09 /* Mode definition register 2 */ -// #define OMAP3_SCR 0x10 /* Supplementary control register */ -// #define OMAP3_SSR 0x11 /* Supplementary status register */ -// #define OMAP3_SYSC 0x15 /* System configuration register */ -// #define OMAP3_SYSS 0x16 /* System status register */ - -/* Enhanced Features Register bits */ -#define UART_EFR_ECB (1 << 4)/* Enhanced control bit */ -#define UART_EFR_AUTO_CTS (1 << 6)/* auto cts enable */ -#define UART_EFR_AUTO_RTS (1 << 7)/* auto rts enable */ - -/* Interrupt Enable Register bits */ -#define UART_IER_MSI 0x08 /* Modem status interrupt */ -#define UART_IER_RLSI 0x04 /* Receiver line status interrupt */ -#define UART_IER_THRI 0x02 /* Transmitter holding register int. */ -#define UART_IER_RDI 0x01 /* Receiver data interrupt */ - -/* FIFO control register */ -// #define OMAP_UART_FCR_RX_FIFO_TRIG_SHIFT 6 -// #define OMAP_UART_FCR_RX_FIFO_TRIG_MASK (0x3 << 6) -// #define OMAP_UART_FCR_TX_FIFO_TRIG_SHIFT 4 -// #define OMAP_UART_FCR_TX_FIFO_TRIG_MASK (0x3 << 4) -#define UART_FCR_ENABLE_FIFO 0x01 /* Enable the fifo */ -#define UART_FCR_CLR_RCVR 0x02 /* Clear the RCVR FIFO */ -#define UART_FCR_CLR_XMIT 0x04 /* Clear the XMIT FIFO */ - -/* Interrupt Identification Register bits */ -#define UART_IIR_RDI 0x04 /* Data ready interrupt */ -#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ -#define UART_IIR_NO_INT 0x01 /* No interrupt is pending */ - -/* Line Control Register bits */ -// #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ -// #define UART_LCR_SBC 0x40 /* Set break control */ -// #define UART_LCR_EPAR 0x10 /* Even parity select */ -// #define UART_LCR_PARITY 0x08 /* Enable parity */ -// #define UART_LCR_STOP 0x04 /* Stop bits; 0=1 bit, 1=2 bits */ -// #define UART_LCR_WLEN5 0x00 /* Wordlength 5 bits */ -// #define UART_LCR_WLEN6 0x01 /* Wordlength 6 bits */ -// #define UART_LCR_WLEN7 0x02 /* Wordlength 7 bits */ -// #define UART_LCR_WLEN8 0x03 /* Wordlength 8 bits */ - -#define UART_LCR_CONF_MODE_A UART_LCR_DLAB /* Configuration Mode A */ -#define UART_LCR_CONF_MODE_B 0xBF /* Configuration Mode B */ - -/* Line Status Register bits */ -#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */ -#define UART_LSR_BI 0x10 /* Break condition */ -#define UART_LSR_DR 0x01 /* Data ready */ - -/* Modem Control Register bits */ -#define UART_MCR_TCRTLR 0x40 /* Access TCR/TLR */ -#define UART_MCR_OUT2 0x08 /* Out2 complement */ -#define UART_MCR_RTS 0x02 /* RTS complement */ -#define UART_MCR_DTR 0x01 /* DTR output low */ - -/* Mode Definition Register 1 bits */ -#define OMAP_MDR1_DISABLE 0x07 -#define OMAP_MDR1_MODE13X 0x03 -#define OMAP_MDR1_MODE16X 0x00 - -/* Modem Status Register bits */ -#define UART_MSR_DCD 0x80 /* Data Carrier Detect */ -#define UART_MSR_CTS 0x10 /* Clear to Send */ -#define UART_MSR_DDCD 0x08 /* Delta DCD */ - -/* Supplementary control Register bits */ -// #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7) - -/* System Control Register bits */ -#define UART_SYSC_SOFTRESET 0x02 - -/* System Status Register bits */ -#define UART_SYSS_RESETDONE 0x01 - -/* Line status register fields */ -// #define OMAP3_LSR_TX_FIFO_E (1 << 5) /* Transmit FIFO empty */ -// #define OMAP3_LSR_RX_FIFO_E (1 << 0) /* Receive FIFO empty */ -// #define OMAP3_LSR_RXOE (1 << 1) /* Overrun error.*/ - -/* Supplementary status register fields */ -// #define OMAP3_SSR_TX_FIFO_FULL (1 << 0) /* Transmit FIFO full */ +/* Interrupt FIFO Level Select */ +#define PL011_IFLS_RXIFLSEL18 0x00 /* receive fifo become 1/8 full */ +#define PL011_IFLS_RXIFLSEL14 0x08 /* receive fifo become 1/4 full */ +#define PL011_IFLS_RXIFLSEL12 0x10 /* receive fifo become 1/2 full */ +#define PL011_IFLS_RXIFLSEL34 0x18 /* receive fifo become 3/4 full */ +#define PL011_IFLS_RXIFLSEL78 0x20 /* receive fifo become 7/8 full */ +#define PL011_IFLS_TXIFLSEL18 0x00 /* receive fifo become 1/8 full */ +#define PL011_IFLS_TXIFLSEL14 0x01 /* receive fifo become 1/4 full */ +#define PL011_IFLS_TXIFLSEL12 0x02 /* receive fifo become 1/2 full */ +#define PL011_IFLS_TXIFLSEL34 0x03 /* receive fifo become 3/4 full */ +#define PL011_IFLS_TXIFLSEL78 0x04 /* receive fifo become 7/8 full */ #endif /* _PL011_SERIAL_H */