Importing lib/libpci

Change-Id: I21ae1e409286cec27c5e35677de3778a3f505d1e
2014-10-15 09:51:53 +02:00
parent 6e7bb62853
commit 7eb99bda90
26 changed files with 32368 additions and 24 deletions
--- a/sys/dev/Makefile
+++ b/sys/dev/Makefile
@@ -1,13 +1,9 @@
 #	$NetBSD: Makefile,v 1.35 2012/06/20 21:38:26 sjg Exp $

-.if defined(__MINIX)
-SUBDIR=	i2c
-.else
-SUBDIR=	apm ata bluetooth dec dm dmover dtv filemon hpc \
-	i2c i2o ic ieee1394 ir isa \
-	microcode ofw pci pckbport pcmcia pud putter raidframe sbus scsipi \
-	sun tc usb vme wscons
-.endif # defined(__MINIX)
+SUBDIR=	\
+	i2c \
+	pci \
+	

 .include <bsd.own.mk>

@@ -17,12 +13,8 @@ SUBDIR+= iscsi

 INCSDIR= /usr/include/dev

-.if !defined(__MINIX)
 # Only install includes which are used by userland
-INCS=	biovar.h ccdvar.h cgdvar.h fssvar.h keylock.h kttcpio.h lockstat.h \
-	md.h vndvar.h
-.else
-INCS=	vndvar.h
-.endif # !defined(__MINIX)
+INCS=	\
+	vndvar.h

 .include <bsd.kinc.mk>
--- a/sys/dev/pci/Makefile
+++ b/sys/dev/pci/Makefile
@@ -0,0 +1,15 @@
+#	$NetBSD: Makefile,v 1.13 2009/09/16 20:58:07 sborrill Exp $
+
+# use 'make -f Makefile.pcidevs' to make pcidevs.h and pcidevs_data.h
+
+#LSC: MINIX Not Yet imported
+#SUBDIR=       hdaudio
+
+INCSDIR= /usr/include/dev/pci
+
+# Only install includes which are used by userland
+INCS=	amrreg.h amrio.h if_lmc.h mlyio.h mlyreg.h \
+	pcidevs.h pcidevs_data.h pciio.h pcireg.h \
+	tgareg.h twereg.h tweio.h
+
+.include <bsd.kinc.mk>
--- a/sys/dev/pci/amrio.h
+++ b/sys/dev/pci/amrio.h
@@ -0,0 +1,124 @@
+/* $NetBSD: amrio.h,v 1.1 2006/07/23 12:01:26 bouyer Exp $ */
+
+/*-
+ * Copyright (c) 1999 Michael Smith
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * Copyright (c) 2002 Eric Moore
+ * Copyright (c) 2002 LSI Logic Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The party using or redistributing the source code and binary forms
+ *    agrees to the disclaimer below and the terms and conditions set forth
+ *    herein.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ *
+ *	FreeBSD: src/sys/dev/amr/amrio.h,v 1.7 2005/12/14 03:26:49 scottl Exp
+ */
+
+/*
+ * ioctl interface
+ */
+
+#include <sys/ioccom.h>
+#include <sys/param.h>
+
+/*
+ * Fetch the driver's interface version.
+ */
+#define AMR_IO_VERSION_NUMBER	153
+#define AMR_IO_VERSION	_IOR('A', 0x200, int)
+
+/*
+ * Pass a command from userspace through to the adapter.
+ *
+ * Note that in order to be code-compatible with the Linux
+ * interface where possible, the formatting of the au_cmd field is
+ * somewhat Interesting.
+ *
+ * For normal commands, the layout is (fields from struct amr_mailbox_ioctl):
+ *
+ * 0		mb_command
+ * 1		mb_channel
+ * 2		mb_param
+ * 3		mb_pad[0]
+ * 4		mb_drive
+ *
+ * For SCSI passthrough commands, the layout is:
+ *
+ * 0		AMR_CMD_PASS	(0x3)
+ * 1		reserved, 0
+ * 2		cdb length
+ * 3		cdb data
+ * 3+cdb_len	passthrough control byte (timeout, ars, islogical)
+ * 4+cdb_len	reserved, 0
+ * 5+cdb_len	channel
+ * 6+cdb_len	target
+ */
+
+struct amr_user_ioctl {
+    unsigned char	au_cmd[32];	/* command text from userspace */
+    void		*au_buffer;	/* data buffer in userspace */
+    unsigned long	au_length;	/* data buffer size (0 == no data) */
+    int			au_direction;	/* data transfer direction */
+#define AMR_IO_NODATA	0
+#define AMR_IO_READ	1
+#define AMR_IO_WRITE	2
+    int			au_status;	/* command status returned by adapter */
+};
+
+#define AMR_IO_COMMAND	_IOWR('A', 0x201, struct amr_user_ioctl)
+
+#if 0 /* defined(__amd64__) || defined(__ia64__) */
+
+struct amr_user_ioctl32 {
+    unsigned char	au_cmd[32];	/* command text from userspace */
+    u_int32_t		au_buffer;	/* 32-bit pointer to uspace buf */
+    u_int32_t		au_length;	/* length of the uspace buffer */
+    int32_t		au_direction;	/* data transfer direction */
+    int32_t		au_status;	/* command status returned by adapter */
+};
+
+#	define AMR_IO_COMMAND32	_IOWR('A', 0x201, struct amr_user_ioctl32)
+#endif
--- a/sys/dev/pci/amrreg.h
+++ b/sys/dev/pci/amrreg.h
@@ -0,0 +1,433 @@
+/*	$NetBSD: amrreg.h,v 1.5 2008/09/08 23:36:54 gmcgarry Exp $	*/
+
+/*-
+ * Copyright (c) 2002, 2003 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Andrew Doran.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*-
+ * Copyright (c) 1999,2000 Michael Smith
+ * Copyright (c) 2000 BSDi
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * from FreeBSD: amrreg.h,v 1.2 2000/08/30 07:52:40 msmith Exp
+ */
+
+#ifndef	_PCI_AMRREG_H_
+#define	_PCI_AMRREG_H_
+
+#ifdef AMR_CRASH_ME
+#define	AMR_MAX_CMDS		255		/* ident = 0 not allowed */
+#else
+#define	AMR_MAX_CMDS		120
+#endif
+#define	AMR_MAXLD      		40
+
+#define	AMR_MAX_CMDS_PU		63
+
+#define	AMR_MAX_SEGS		26
+#define	AMR_MAX_CHANNEL		3
+#define	AMR_MAX_TARGET		15
+#define	AMR_MAX_LUN		7
+
+#define	AMR_MAX_CDB_LEN		0x0a
+#define	AMR_MAX_REQ_SENSE_LEN	0x20
+
+#define	AMR_SECTOR_SIZE		512
+
+/* Mailbox commands.*/
+#define	AMR_CMD_LREAD		0x01
+#define	AMR_CMD_LWRITE		0x02
+#define	AMR_CMD_PASS		0x03
+#define	AMR_CMD_EXT_ENQUIRY	0x04
+#define	AMR_CMD_ENQUIRY		0x05
+#define	AMR_CMD_FLUSH		0x0a
+#define	AMR_CMD_EXT_ENQUIRY2	0x0c
+#define	AMR_CMD_GET_MACHINEID	0x36
+#define	AMR_CMD_GET_INITIATOR	0x7d	/* returns one byte */
+#define	AMR_CMD_CONFIG		0xa1
+#define	AMR_CONFIG_PRODUCT_INFO			0x0e
+#define	AMR_CONFIG_ENQ3				0x0f
+#define	AMR_CONFIG_ENQ3_SOLICITED_NOTIFY	0x01
+#define	AMR_CONFIG_ENQ3_SOLICITED_FULL		0x02
+#define	AMR_CONFIG_ENQ3_UNSOLICITED		0x03
+
+/* Command completion status. */
+#define	AMR_STATUS_SUCCESS	0x00
+#define	AMR_STATUS_ABORTED	0x02
+#define	AMR_STATUS_FAILED	0x80
+
+/* Physical/logical drive states. */
+#define	AMR_DRV_CURSTATE(x)	((x) & 0x0f)
+#define	AMR_DRV_PREVSTATE(x)	(((x) >> 4) & 0x0f)
+#define	AMR_DRV_OFFLINE		0x00
+#define	AMR_DRV_DEGRADED	0x01
+#define	AMR_DRV_OPTIMAL		0x02
+#define	AMR_DRV_ONLINE		0x03
+#define	AMR_DRV_FAILED		0x04
+#define	AMR_DRV_REBUILD		0x05
+#define	AMR_DRV_HOTSPARE	0x06
+
+/* Logical drive properties. */
+#define	AMR_DRV_RAID_MASK	0x0f	/* RAID level 0, 1, 3, 5, etc. */
+#define	AMR_DRV_WRITEBACK	0x10	/* write-back enabled */
+#define	AMR_DRV_READHEAD	0x20	/* readhead policy enabled */
+#define	AMR_DRV_ADAPTIVE	0x40	/* adaptive I/O policy enabled */
+
+/* Battery status. */
+#define	AMR_BATT_MODULE_MISSING		0x01
+#define	AMR_BATT_LOW_VOLTAGE		0x02
+#define	AMR_BATT_TEMP_HIGH		0x04
+#define	AMR_BATT_PACK_MISSING		0x08
+#define	AMR_BATT_CHARGE_MASK		0x30
+#define	AMR_BATT_CHARGE_DONE		0x00
+#define	AMR_BATT_CHARGE_INPROG		0x10
+#define	AMR_BATT_CHARGE_FAIL		0x20
+#define	AMR_BATT_CYCLES_EXCEEDED	0x40
+
+/*
+ * 8LD firmware interface.
+ */
+
+/* Array constraints. */
+#define	AMR_8LD_MAXDRIVES	8
+#define	AMR_8LD_MAXCHAN		5
+#define	AMR_8LD_MAXTARG		15
+#define	AMR_8LD_MAXPHYSDRIVES	(AMR_8LD_MAXCHAN * AMR_8LD_MAXTARG)
+
+/* Adapter information. */
+struct amr_adapter_info {
+	u_int8_t	aa_maxio;
+	u_int8_t	aa_rebuild_rate;
+	u_int8_t	aa_maxtargchan;
+	u_int8_t	aa_channels;
+	u_int8_t	aa_firmware[4];
+	u_int16_t	aa_flashage;
+	u_int8_t	aa_chipsetvalue;
+	u_int8_t	aa_memorysize;
+	u_int8_t	aa_cacheflush;
+	u_int8_t	aa_bios[4];
+	u_int8_t	aa_boardtype;
+	u_int8_t	aa_scsisensealert;
+	u_int8_t	aa_writeconfigcount;
+	u_int8_t	aa_driveinsertioncount;
+	u_int8_t	aa_inserteddrive;
+	u_int8_t	aa_batterystatus;
+	u_int8_t   	aa_res1;
+} __packed;
+
+/* Logical drive information. */
+struct amr_logdrive_info {
+	u_int8_t	al_numdrives;
+	u_int8_t	al_res1[3];
+	u_int32_t	al_size[AMR_8LD_MAXDRIVES];
+	u_int8_t	al_properties[AMR_8LD_MAXDRIVES];
+	u_int8_t	al_state[AMR_8LD_MAXDRIVES];
+} __packed;
+
+/* Physical drive information. */
+struct amr_physdrive_info {
+	/* Low nybble is current state, high nybble is previous state. */
+	u_int8_t	ap_state[AMR_8LD_MAXPHYSDRIVES];
+	u_int8_t	ap_predictivefailure;
+} __packed;
+
+/*
+ * Enquiry response structure for AMR_CMD_ENQUIRY (e), AMR_CMD_EXT_ENQUIRY (x)
+ * and AMR_CMD_EXT_ENQUIRY2 (2).
+ */
+struct amr_enquiry {
+	struct		amr_adapter_info ae_adapter;		/* e x 2 */
+	struct		amr_logdrive_info ae_ldrv;		/* e x 2 */
+	struct		amr_physdrive_info ae_pdrv;		/* e x 2 */
+	u_int8_t	ae_formatting[AMR_8LD_MAXDRIVES];	/*   x 2 */
+	u_int8_t	res1[AMR_8LD_MAXDRIVES];		/*   x 2 */
+	u_int32_t	ae_extlen;				/*     2 */
+	u_int16_t	ae_subsystem;				/*     2 */
+	u_int16_t	ae_subvendor;				/*     2 */
+	u_int32_t	ae_signature;				/*     2 */
+#define	AMR_SIG_431	0xfffe0001
+#define	AMR_SIG_438	0xfffd0002
+#define	AMR_SIG_762	0xfffc0003
+#define	AMR_SIG_T5	0xfffb0004
+#define	AMR_SIG_466	0xfffa0005
+#define	AMR_SIG_467	0xfff90006
+#define	AMR_SIG_T7	0xfff80007
+#define	AMR_SIG_490	0xfff70008
+	u_int8_t	res2[844];				/*     2 */
+} __packed;
+
+/*
+ * 40LD firmware interface.
+ */
+
+/* Array constraints. */
+#define	AMR_40LD_MAXDRIVES	40
+#define	AMR_40LD_MAXCHAN	16
+#define	AMR_40LD_MAXTARG	16
+#define	AMR_40LD_MAXPHYSDRIVES	256
+
+/* Product information structure. */
+struct amr_prodinfo {
+	u_int32_t	ap_size;		/* current size in bytes (not including resvd) */
+	u_int32_t	ap_configsig;		/* default is 0x00282008, indicating 0x28 maximum
+					 * logical drives, 0x20 maximum stripes and 0x08
+					 * maximum spans */
+	u_int8_t	ap_firmware[16];	/* printable identifiers */
+	u_int8_t	ap_bios[16];
+	u_int8_t	ap_product[80];
+	u_int8_t	ap_maxio;		/* maximum number of concurrent commands supported */
+	u_int8_t	ap_nschan;		/* number of SCSI channels present */
+	u_int8_t	ap_fcloops;		/* number of fibre loops present */
+	u_int8_t	ap_memtype;		/* memory type */
+	u_int32_t	ap_signature;
+	u_int16_t	ap_memsize;		/* onboard memory in MB */
+	u_int16_t	ap_subsystem;		/* subsystem identifier */
+	u_int16_t	ap_subvendor;		/* subsystem vendor ID */
+	u_int8_t	ap_numnotifyctr;	/* number of notify counters */
+} __packed;
+
+/* Notify structure. */
+struct amr_notify {
+	u_int32_t	an_globalcounter;	/* change counter */
+
+	u_int8_t	an_paramcounter;	/* parameter change counter */
+	u_int8_t	an_paramid;
+#define	AMR_PARAM_REBUILD_RATE		0x01	/* value = new rebuild rate */
+#define	AMR_PARAM_FLUSH_INTERVAL	0x02	/* value = new flush interval */
+#define	AMR_PARAM_SENSE_ALERT		0x03	/* value = last physical drive with check condition set */
+#define	AMR_PARAM_DRIVE_INSERTED	0x04	/* value = last physical drive inserted */
+#define	AMR_PARAM_BATTERY_STATUS	0x05	/* value = battery status */
+	u_int16_t	an_paramval;
+
+	u_int8_t	an_writeconfigcounter;	/* write config occurred */
+	u_int8_t	res1[3];
+
+	u_int8_t	an_ldrvopcounter;	/* logical drive operation started/completed */
+	u_int8_t	an_ldrvopid;
+	u_int8_t	an_ldrvopcmd;
+#define	AMR_LDRVOP_CHECK	0x01
+#define	AMR_LDRVOP_INIT		0x02
+#define	AMR_LDRVOP_REBUILD	0x03
+	u_int8_t	an_ldrvopstatus;
+#define	AMR_LDRVOP_SUCCESS	0x00
+#define	AMR_LDRVOP_FAILED	0x01
+#define	AMR_LDRVOP_ABORTED	0x02
+#define	AMR_LDRVOP_CORRECTED	0x03
+#define	AMR_LDRVOP_STARTED	0x04
+
+	u_int8_t	an_ldrvstatecounter;	/* logical drive state change occurred */
+	u_int8_t	an_ldrvstateid;
+	u_int8_t	an_ldrvstatenew;
+	u_int8_t	an_ldrvstateold;
+
+	u_int8_t	an_pdrvstatecounter;	/* physical drive state change occurred */
+	u_int8_t	an_pdrvstateid;
+	u_int8_t	an_pdrvstatenew;
+	u_int8_t	an_pdrvstateold;
+
+	u_int8_t	an_pdrvfmtcounter;
+	u_int8_t	an_pdrvfmtid;
+	u_int8_t	an_pdrvfmtval;
+#define	AMR_FORMAT_START	0x01
+#define	AMR_FORMAT_COMPLETE	0x02
+	u_int8_t	res2;
+
+	u_int8_t	an_targxfercounter;	/* scsi xfer rate change */
+	u_int8_t	an_targxferid;
+	u_int8_t	an_targxferval;
+	u_int8_t	res3;
+
+	u_int8_t	an_fcloopidcounter;	/* FC/AL loop ID changed */
+	u_int8_t	an_fcloopidpdrvid;
+	u_int8_t	an_fcloopid0;
+	u_int8_t	an_fcloopid1;
+
+	u_int8_t	an_fcloopstatecounter;	/* FC/AL loop status changed */
+	u_int8_t	an_fcloopstate0;
+	u_int8_t	an_fcloopstate1;
+	u_int8_t	res4;
+} __packed;
+
+/* Enquiry3 structure. */
+struct amr_enquiry3 {
+	u_int32_t	ae_datasize;		/* valid data size in this structure */
+	union {				/* event notify structure */
+	struct amr_notify	n;
+	u_int8_t		pad[0x80];
+	} 		ae_notify;
+	u_int8_t	ae_rebuildrate;		/* current rebuild rate in % */
+	u_int8_t	ae_cacheflush;		/* flush interval in seconds */
+	u_int8_t	ae_sensealert;
+	u_int8_t	ae_driveinsertcount;	/* count of inserted drives */
+	u_int8_t	ae_batterystatus;
+	u_int8_t	ae_numldrives;
+	u_int8_t	ae_reconstate[AMR_40LD_MAXDRIVES / 8];	/* reconstruction state */
+	u_int16_t	ae_opstatus[AMR_40LD_MAXDRIVES / 8];	/* operation status per drive */
+	u_int32_t	ae_drivesize[AMR_40LD_MAXDRIVES];	/* logical drive size */
+	u_int8_t	ae_driveprop[AMR_40LD_MAXDRIVES];	/* logical drive properties */
+	u_int8_t	ae_drivestate[AMR_40LD_MAXDRIVES];	/* physical drive state */
+	u_int8_t	ae_pdrivestate[AMR_40LD_MAXPHYSDRIVES]; /* physical drive state */
+	u_int16_t	ae_driveformat[AMR_40LD_MAXPHYSDRIVES];
+	u_int8_t	ae_targxfer[80];			/* physical drive transfer rates */
+
+	u_int8_t	res1[263];		/* pad to 1024 bytes */
+} __packed;
+
+/*
+ * Mailbox and command structures.
+ */
+
+struct amr_mailbox_cmd {
+	u_int8_t	mb_command;
+	u_int8_t	mb_ident;
+	u_int16_t	mb_blkcount;
+	u_int32_t	mb_lba;
+	u_int32_t	mb_physaddr;
+	u_int8_t	mb_drive;
+	u_int8_t	mb_nsgelem;
+	u_int8_t	res1;
+	u_int8_t	mb_busy;
+} __packed;
+
+struct amr_mailbox_resp {
+	u_int8_t	mb_nstatus;
+	u_int8_t	mb_status;
+	u_int8_t	mb_completed[46];
+}  __packed;
+
+struct amr_mailbox {
+	u_int32_t	mb_res1[3];
+	u_int32_t	mb_segment;
+	struct		amr_mailbox_cmd mb_cmd;
+	struct		amr_mailbox_resp mb_resp;
+	u_int8_t	mb_poll;
+	u_int8_t	mb_ack;
+	u_int8_t	res2[62];		/* Pad to 128+16 bytes. */
+} __packed;
+
+struct amr_mailbox_ioctl {
+	u_int8_t	mb_command;
+	u_int8_t	mb_ident;
+	u_int8_t	mb_channel;
+	u_int8_t	mb_param;
+	u_int8_t	mb_pad[4];
+	u_int32_t	mb_physaddr;
+	u_int8_t	mb_drive;
+	u_int8_t	mb_nsgelem;
+	u_int8_t	res1;
+	u_int8_t	mb_busy;
+	u_int8_t	mb_nstatus;
+	u_int8_t	mb_completed[46];
+	u_int8_t	mb_poll;
+	u_int8_t	mb_ack;
+	u_int8_t	res4[16];
+} __packed;
+
+struct amr_sgentry {
+	u_int32_t	sge_addr;
+	u_int32_t	sge_count;
+} __packed;
+
+struct amr_passthrough {
+	u_int8_t	ap_timeout:3;
+	u_int8_t	ap_ars:1;
+	u_int8_t	ap_dummy:3;
+	u_int8_t	ap_islogical:1;
+	u_int8_t	ap_logical_drive_no;
+	u_int8_t	ap_channel;
+	u_int8_t	ap_scsi_id;
+	u_int8_t	ap_queue_tag;
+	u_int8_t	ap_queue_action;
+	u_int8_t	ap_cdb[AMR_MAX_CDB_LEN];
+	u_int8_t	ap_cdb_length;
+	u_int8_t	ap_request_sense_length;
+	u_int8_t	ap_request_sense_area[AMR_MAX_REQ_SENSE_LEN];
+	u_int8_t	ap_no_sg_elements;
+	u_int8_t	ap_scsi_status;
+	u_int32_t	ap_data_transfer_address;
+	u_int32_t	ap_data_transfer_length;
+} __packed;
+
+/*
+ * "Quartz" i960 PCI bridge interface.
+ */
+
+#define	AMR_QUARTZ_SIG_REG	0xa0
+#define	AMR_QUARTZ_SIG0		0xcccc
+#define	AMR_QUARTZ_SIG1		0x3344
+
+/* Doorbell registers. */
+#define	AMR_QREG_IDB		0x20
+#define	AMR_QREG_ODB		0x2c
+
+#define	AMR_QIDB_SUBMIT		0x00000001	/* mailbox ready for work */
+#define	AMR_QIDB_ACK		0x00000002	/* mailbox done */
+#define	AMR_QODB_READY		0x10001234	/* work ready to be processed */
+
+/*
+ * Old-style ("standard") ASIC bridge interface.
+ */
+
+/* I/O registers. */
+#define	AMR_SREG_CMD		0x10	/* Command/ack register (w) */
+#define	AMR_SREG_MBOX_BUSY	0x10	/* Mailbox status (r) */
+#define	AMR_SREG_TOGL		0x11	/* Interrupt enable */
+#define	AMR_SREG_MBOX		0x14	/* Mailbox physical address */
+#define	AMR_SREG_MBOX_ENABLE	0x18	/* Atomic mailbox address enable */
+#define	AMR_SREG_INTR		0x1a	/* Interrupt status */
+
+/* I/O magic numbers. */
+#define	AMR_SCMD_POST		0x10	/* in SCMD to initiate action on mailbox */
+#define	AMR_SCMD_ACKINTR	0x08	/* in SCMD to ack mailbox retrieved */
+#define	AMR_STOGL_ENABLE	0xc0	/* in STOGL */
+#define	AMR_SINTR_VALID		0x40	/* in SINTR */
+#define	AMR_SMBOX_BUSY_FLAG	0x10	/* in SMBOX_BUSY */
+#define	AMR_SMBOX_ENABLE_ADDR	0x00	/* in SMBOX_ENABLE */
+
+#endif	/* !_PCI_AMRREG_H_ */
--- a/sys/dev/pci/if_lmc.h
+++ b/sys/dev/pci/if_lmc.h
--- a/sys/dev/pci/mlyio.h
+++ b/sys/dev/pci/mlyio.h
@@ -0,0 +1,104 @@
+/*	$NetBSD: mlyio.h,v 1.4 2008/04/28 20:23:55 martin Exp $	*/
+
+/*-
+ * Copyright (c) 2001 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Andrew Doran, Thor Lancelot Simon, and Eric Haszlakiewicz.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*-
+ * Copyright (c) 2001 Michael Smith
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * from FreeBSD: mlyio.h,v 1.2 2001/07/14 00:12:22 msmith Exp
+ */
+
+/*
+ * Control structures exchanged through the GAM interface with userland
+ * management tools.
+ *
+ * The member naming here is consistent with the Linux driver, with which this
+ * interface is basically compatible.
+ */
+
+#ifndef _PCI_MLYIO_H_
+#define	_PCI_MLYIO_H_
+
+struct mly_user_command {
+	unsigned char	ControllerNumber;
+	union mly_cmd_packet	CommandMailbox;
+	int		DataTransferLength;
+	int		RequestSenseLength;
+	void		*DataTransferBuffer;
+	void		*RequestSenseBuffer;
+	int		CommandStatus;	/* not in the Linux structure */
+};
+
+#define	MLYIO_COMMAND	_IOWR('M', 200, struct mly_user_command)
+
+struct mly_user_health {
+	unsigned char	ControllerNumber;
+	void		*HealthStatusBuffer;
+};
+
+#define	MLYIO_HEALTH	_IOW('M', 201, struct mly_user_health)
+
+/*
+ * Command queue statistics
+ */
+
+#define	MLYQ_FREE	0
+#define	MLYQ_BUSY	1
+#define	MLYQ_COMPLETE	2
+#define	MLYQ_COUNT	3
+
+struct mly_qstat {
+	u_int32_t	q_length;
+	u_int32_t	q_max;
+};
+
+#endif	/* !defined _PCI_MLYIO_ */
--- a/sys/dev/pci/mlyreg.h
+++ b/sys/dev/pci/mlyreg.h
--- a/sys/dev/pci/pci_subr.c
+++ b/sys/dev/pci/pci_subr.c
--- a/sys/dev/pci/pci_verbose.c
+++ b/sys/dev/pci/pci_verbose.c
@@ -0,0 +1,158 @@
+/*	$NetBSD: pci_verbose.c,v 1.8 2011/08/29 14:47:08 jmcneill Exp $	*/
+
+/*
+ * Copyright (c) 1997 Zubin D. Dittia.  All rights reserved.
+ * Copyright (c) 1995, 1996, 1998, 2000
+ *	Christopher G. Demetriou.  All rights reserved.
+ * Copyright (c) 1994 Charles M. Hannum.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by Charles M. Hannum.
+ * 4. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * PCI autoconfiguration support functions.
+ *
+ * Note: This file is also built into a userland library (libpci).
+ * Pay attention to this when you make modifications.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: pci_verbose.c,v 1.8 2011/08/29 14:47:08 jmcneill Exp $");
+
+#include <sys/param.h>
+
+#ifdef _KERNEL
+#include <sys/module.h>
+#else
+#include <pci.h>
+#endif
+
+#include <dev/pci/pcireg.h>
+#include <dev/pci/pcidevs.h>
+#ifdef _KERNEL
+#include <dev/pci/pci_verbose.h>
+#endif
+
+/*
+ * Descriptions of of known vendors and devices ("products").
+ */
+
+#include <dev/pci/pcidevs_data.h>
+
+#ifndef _KERNEL
+#include <string.h>
+#endif
+
+#ifdef _KERNEL
+static int pciverbose_modcmd(modcmd_t, void *);
+
+MODULE(MODULE_CLASS_MISC, pciverbose, "pci");
+
+static int
+pciverbose_modcmd(modcmd_t cmd, void *arg)
+{
+	static const char *(*saved_findvendor)(pcireg_t);
+	static const char *(*saved_findproduct)(pcireg_t);
+	static const char *saved_unmatched;
+
+	switch (cmd) {
+	case MODULE_CMD_INIT:
+		saved_findvendor = pci_findvendor;
+		saved_findproduct = pci_findproduct;
+		saved_unmatched = pci_unmatched;
+		pci_findvendor = pci_findvendor_real;
+		pci_findproduct = pci_findproduct_real;
+		pci_unmatched = "unmatched ";
+		pciverbose_loaded = 1;
+		return 0;
+	case MODULE_CMD_FINI:
+		pci_findvendor = saved_findvendor;
+		pci_findproduct = saved_findproduct;
+		pci_unmatched = saved_unmatched;
+		pciverbose_loaded = 0;
+		return 0;
+	default:
+		return ENOTTY;
+	}
+}
+#endif /* KERNEL */
+
+static const char *
+pci_untokenstring(const uint16_t *token, char *buf, size_t len)
+{
+	char *cp = buf;
+
+	buf[0] = '\0';
+	for (; *token != 0; token++) {
+		cp = buf + strlcat(buf, pci_words + *token, len - 2);
+		cp[0] = ' ';
+		cp[1] = '\0';
+	}
+	*cp = '\0';
+	return cp != buf ? buf : NULL;
+}
+
+const char *
+pci_findvendor_real(pcireg_t id_reg)
+{
+	static char buf[256];
+	pci_vendor_id_t vendor = PCI_VENDOR(id_reg);
+	size_t n;
+
+	for (n = 0; n < __arraycount(pci_vendors); n++) {
+		if (pci_vendors[n] == vendor)
+			return pci_untokenstring(&pci_vendors[n+1], buf,
+			    sizeof(buf));
+
+		/* Skip Tokens */
+		n++;
+		while (pci_vendors[n] != 0 && n < __arraycount(pci_vendors))
+			n++;
+	}
+	return (NULL);
+}
+
+const char *
+pci_findproduct_real(pcireg_t id_reg)
+{
+	static char buf[256];
+	pci_vendor_id_t vendor = PCI_VENDOR(id_reg);
+	pci_product_id_t product = PCI_PRODUCT(id_reg);
+	size_t n;
+
+	for (n = 0; n < __arraycount(pci_products); n++) {
+		if (pci_products[n] == vendor && pci_products[n+1] == product)
+			return pci_untokenstring(&pci_products[n+2], buf,
+			    sizeof(buf));
+
+		/* Skip Tokens */
+		n += 2;
+		while (pci_products[n] != 0 && n < __arraycount(pci_products))
+			n++;
+	}
+	return (NULL);
+}
+
--- a/sys/dev/pci/pcidevs
+++ b/sys/dev/pci/pcidevs
--- a/sys/dev/pci/pcidevs.h
+++ b/sys/dev/pci/pcidevs.h
--- a/sys/dev/pci/pcidevs_data.h
+++ b/sys/dev/pci/pcidevs_data.h
--- a/sys/dev/pci/pciio.h
+++ b/sys/dev/pci/pciio.h
@@ -0,0 +1,96 @@
+/*	$NetBSD: pciio.h,v 1.3 2009/06/06 12:56:43 cegger Exp $	*/
+
+/*
+ * Copyright 2001 Wasabi Systems, Inc.
+ * All rights reserved.
+ *
+ * Written by Jason R. Thorpe for Wasabi Systems, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed for the NetBSD Project by
+ *	Wasabi Systems, Inc.
+ * 4. The name of Wasabi Systems, Inc. may not be used to endorse
+ *    or promote products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _DEV_PCI_PCIIO_H_
+#define	_DEV_PCI_PCIIO_H_
+
+/*
+ * User -> kernel interface for PCI bus access.
+ */
+
+#include <sys/ioccom.h>
+
+/*
+ * pciio_cfgreg:
+ *
+ *	Representation of a PCI config space register.
+ */
+struct pciio_cfgreg {
+	u_int	 reg;	/* offset into PCI configuration space */
+	uint32_t val;	/* value of the register */
+};
+
+/*
+ * Read and write PCI configuration space registers on a
+ * specific device.
+ */
+#define	PCI_IOC_CFGREAD		_IOWR('P', 0, struct pciio_cfgreg)
+#define	PCI_IOC_CFGWRITE	 _IOW('P', 1, struct pciio_cfgreg)
+
+/*
+ * pciio_bdf_cfgreg:
+ *
+ *	Like pciio_cfgreg, except for any bus/dev/func within
+ *	a given PCI domain.
+ */
+struct pciio_bdf_cfgreg {
+	u_int	bus;
+	u_int	device;
+	u_int	function;
+	struct pciio_cfgreg cfgreg;
+};
+
+/*
+ * Read and write PCI configuration space registers on any
+ * device within a given PCI domain.
+ */
+#define	PCI_IOC_BDF_CFGREAD	_IOWR('P', 2, struct pciio_bdf_cfgreg)
+#define	PCI_IOC_BDF_CFGWRITE	 _IOW('P', 3, struct pciio_bdf_cfgreg)
+
+/*
+ * pciio_businfo:
+ *
+ *	Information for a PCI bus (autoconfiguration node) instance.
+ */
+struct pciio_businfo {
+	u_int	busno;		/* bus number */
+	u_int	maxdevs;	/* max devices on bus */
+};
+
+#define	PCI_IOC_BUSINFO		 _IOR('P', 4, struct pciio_businfo)
+
+#endif /* _DEV_PCI_PCIIO_H_ */
--- a/sys/dev/pci/pcireg.h
+++ b/sys/dev/pci/pcireg.h
--- a/sys/dev/pci/tgareg.h
+++ b/sys/dev/pci/tgareg.h
@@ -0,0 +1,182 @@
+/* $NetBSD: tgareg.h,v 1.6 2005/12/11 12:22:50 christos Exp $ */
+
+/*
+ * Copyright (c) 1995, 1996 Carnegie-Mellon University.
+ * All rights reserved.
+ *
+ * Author: Chris G. Demetriou
+ *
+ * Permission to use, copy, modify and distribute this software and
+ * its documentation is hereby granted, provided that both the copyright
+ * notice and this permission notice appear in all copies of the
+ * software, derivative works or modified versions, and any portions
+ * thereof, and that both notices appear in supporting documentation.
+ *
+ * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
+ * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
+ * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
+ *
+ * Carnegie Mellon requests users of this software to return to
+ *
+ *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
+ *  School of Computer Science
+ *  Carnegie Mellon University
+ *  Pittsburgh PA 15213-3890
+ *
+ * any improvements or extensions that they make and grant Carnegie the
+ * rights to redistribute these changes.
+ */
+
+#ifndef _ALPHA_INCLUDE_TGAREG_H_
+#define _ALPHA_INCLUDE_TGAREG_H_
+
+/*
+ * Device-specific PCI register offsets and contents.
+ */
+
+#define	TGA_PCIREG_PVRR	0x40		/* PCI Address Extension Register */
+
+#define	TGA_PCIREG_PAER	0x44		/* PCI VGA Redirect Register */
+
+/*
+ * TGA Memory Space offsets
+ */
+
+#define	TGA_MEM_ALTROM	0x0000000	/* 0MB -- Alternate ROM space */
+#define TGA2_MEM_EXTDEV	0x0000000	/* 0MB -- External Device Access */
+#define	TGA_MEM_CREGS	0x0100000	/* 1MB -- Core Registers */
+#define TGA_CREGS_SIZE	0x0100000 	/* Core registers occupy 1MB */
+#define TGA_CREGS_ALIAS	0x0000400	/* Register copies every 1kB */
+
+#define TGA2_MEM_CLOCK	0x0060000	/* TGA2 Clock access */
+#define TGA2_MEM_RAMDAC	0x0080000	/* TGA2 RAMDAC access */
+
+/* Display and Back Buffers mapped at config-dependent addresses */
+
+/*
+ * TGA Core Space register numbers and contents.
+ */
+
+typedef u_int32_t tga_reg_t;
+
+#define	TGA_REG_GCBR0	0x000		/* Copy buffer 0 */
+#define	TGA_REG_GCBR1	0x001		/* Copy buffer 1 */
+#define	TGA_REG_GCBR2	0x002		/* Copy buffer 2 */
+#define	TGA_REG_GCBR3	0x003		/* Copy buffer 3 */
+#define	TGA_REG_GCBR4	0x004		/* Copy buffer 4 */
+#define	TGA_REG_GCBR5	0x005		/* Copy buffer 5 */
+#define	TGA_REG_GCBR6	0x006		/* Copy buffer 6 */
+#define	TGA_REG_GCBR7	0x007		/* Copy buffer 7 */
+
+#define	TGA_REG_GFGR	0x008		/* Foreground */
+#define	TGA_REG_GBGR	0x009		/* Background */
+#define	TGA_REG_GPMR	0x00a		/* Plane Mask */
+#define	TGA_REG_GPXR_S	0x00b		/* Pixel Mask (one-shot) */
+#define	TGA_REG_GMOR	0x00c		/* Mode */
+#define	TGA_REG_GOPR	0x00d		/* Raster Operation */
+#define	TGA_REG_GPSR	0x00e		/* Pixel Shift */
+#define	TGA_REG_GADR	0x00f		/* Address */
+
+#define	TGA_REG_GB1R	0x010		/* Bresenham 1 */
+#define	TGA_REG_GB2R	0x011		/* Bresenham 2 */
+#define	TGA_REG_GB3R	0x012		/* Bresenham 3 */
+
+#define	TGA_REG_GCTR	0x013		/* Continue */
+#define	TGA_REG_GDER	0x014		/* Deep */
+#define TGA_REG_GREV	0x015		/* Start/Version on TGA,
+					 * Revision on TGA2 */
+#define	TGA_REG_GSMR	0x016		/* Stencil Mode */
+#define	TGA_REG_GPXR_P	0x017		/* Pixel Mask (persistent) */
+#define	TGA_REG_CCBR	0x018		/* Cursor Base Address */
+#define	TGA_REG_VHCR	0x019		/* Horizontal Control */
+#define	TGA_REG_VVCR	0x01a		/* Vertical Control */
+#define	TGA_REG_VVBR	0x01b		/* Video Base Address */
+#define	TGA_REG_VVVR	0x01c		/* Video Valid */
+#define	TGA_REG_CXYR	0x01d		/* Cursor XY */
+#define	TGA_REG_VSAR	0x01e		/* Video Shift Address */
+#define	TGA_REG_SISR	0x01f		/* Interrupt Status */
+#define	TGA_REG_GDAR	0x020		/* Data */
+#define	TGA_REG_GRIR	0x021		/* Red Increment */
+#define	TGA_REG_GGIR	0x022		/* Green Increment */
+#define	TGA_REG_GBIR	0x023		/* Blue Increment */
+#define	TGA_REG_GZIR_L	0x024		/* Z-increment Low */
+#define	TGA_REG_GZIR_H	0x025		/* Z-Increment High */
+#define	TGA_REG_GDBR	0x026		/* DMA Base Address */
+#define	TGA_REG_GBWR	0x027		/* Bresenham Width */
+#define	TGA_REG_GZVR_L	0x028		/* Z-value Low */
+#define	TGA_REG_GZVR_H	0x029		/* Z-value High */
+#define	TGA_REG_GZBR	0x02a		/* Z-base address */
+/*	GADR alias	0x02b */
+#define	TGA_REG_GRVR	0x02c		/* Red Value */
+#define	TGA_REG_GGVR	0x02d		/* Green Value */
+#define	TGA_REG_GBVR	0x02e		/* Blue Value */
+#define	TGA_REG_GSWR	0x02f		/* Span Width */
+#define	TGA_REG_EPSR	0x030		/* Pallete and DAC Setup */
+
+/*	reserved	0x031 - 0x3f */
+
+#define	TGA_REG_GSNR0	0x040		/* Slope-no-go 0 */
+#define	TGA_REG_GSNR1	0x041		/* Slope-no-go 1 */
+#define	TGA_REG_GSNR2	0x042		/* Slope-no-go 2 */
+#define	TGA_REG_GSNR3	0x043		/* Slope-no-go 3 */
+#define	TGA_REG_GSNR4	0x044		/* Slope-no-go 4 */
+#define	TGA_REG_GSNR5	0x045		/* Slope-no-go 5 */
+#define	TGA_REG_GSNR6	0x046		/* Slope-no-go 6 */
+#define	TGA_REG_GSNR7	0x047		/* Slope-no-go 7 */
+
+#define	TGA_REG_GSLR0	0x048		/* Slope 0 */
+#define	TGA_REG_GSLR1	0x049		/* Slope 1 */
+#define	TGA_REG_GSLR2	0x04a		/* Slope 2 */
+#define	TGA_REG_GSLR3	0x04b		/* Slope 3 */
+#define	TGA_REG_GSLR4	0x04c		/* Slope 4 */
+#define	TGA_REG_GSLR5	0x04d		/* Slope 5 */
+#define	TGA_REG_GSLR6	0x04e		/* Slope 6 */
+#define	TGA_REG_GSLR7	0x04f		/* Slope 7 */
+
+#define	TGA_REG_GBCR0	0x050		/* Block Color 0 */
+#define	TGA_REG_GBCR1	0x051		/* Block Color 1 */
+#define	TGA_REG_GBCR2	0x052		/* Block Color 2 */
+#define	TGA_REG_GBCR3	0x053		/* Block Color 3 */
+#define	TGA_REG_GBCR4	0x054		/* Block Color 4 */
+#define	TGA_REG_GBCR5	0x055		/* Block Color 5 */
+#define	TGA_REG_GBCR6	0x056		/* Block Color 6 */
+#define	TGA_REG_GBCR7	0x057		/* Block Color 7 */
+
+#define	TGA_REG_GCSR	0x058		/* Copy 64 Source */
+#define	TGA_REG_GCDR	0x059		/* Copy 64 Destination */
+/*	GC[SD]R aliases 0x05a - 0x05f */
+
+/*	reserved	0x060 - 0x077 */
+
+#define	TGA_REG_ERWR	0x078		/* EEPROM write */
+
+/*	reserved	0x079 */
+
+#define	TGA_REG_ECGR	0x07a		/* Clock */
+
+/*	reserved	0x07b */
+
+#define	TGA_REG_EPDR	0x07c		/* Pallete and DAC Data */
+
+/*	reserved	0x07d */
+
+#define	TGA_REG_SCSR	0x07e		/* Command Status */
+
+/*	reserved	0x07f */
+
+/*
+ * Video Valid Register
+ */
+#define	VVR_VIDEOVALID	0x00000001	/* 0 VGA, 1 TGA2 (TGA2 only) */
+#define	VVR_BLANK	0x00000002	/* 0 active, 1 blank */
+#define	VVR_CURSOR	0x00000004	/* 0 disable, 1 enable (TGA2 R/O) */
+#define	VVR_INTERLACE	0x00000008	/* 0 N/Int, 1 Int. (TGA2 R/O) */
+#define	VVR_DPMS_MASK	0x00000030	/* See "DMPS mask" below */
+#define	VVR_DPMS_SHIFT	4
+#define	VVR_DDC		0x00000040	/* DDC-in pin value (R/O) */
+#define	VVR_TILED	0x00000400	/* 0 linear, 1 tiled (not on TGA2) */
+#define	VVR_LDDLY_MASK	0x01ff0000	/* load delay in quad pixel clock ticks
+					   (not on TGA2) */
+#define	VVR_LDDLY_SHIFT	16
+
+#endif /* _ALPHA_INCLUDE_TGAREG_H_ */
--- a/sys/dev/pci/tweio.h
+++ b/sys/dev/pci/tweio.h
@@ -0,0 +1,110 @@
+/*	$NetBSD: tweio.h,v 1.5 2005/12/11 12:22:51 christos Exp $	*/
+
+/*-
+ * Copyright (c) 2000 Michael Smith
+ * Copyright (c) 2000 BSDi
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * from FreeBSD: tweio.h,v 1.1 2000/10/25 06:59:05 msmith Exp
+ */
+
+#ifndef _DEV_PCI_TWEIO_H_
+#define	_DEV_PCI_TWEIO_H_
+
+#include <sys/ioccom.h>
+#include <dev/pci/twereg.h>
+
+/*
+ * User-space command
+ *
+ * Note that the command's scatter/gather list will be computed by the
+ * driver, and cannot be filled in by the consumer.
+ */
+struct twe_usercommand {
+	struct twe_cmd	tu_cmd;		/* command ready for the controller */
+	void		*tu_data;	/* pointer to data in userspace */
+	size_t		tu_size;	/* userspace data length */
+};
+
+#define TWEIO_COMMAND	_IOWR('T', 100, struct twe_usercommand)
+
+/*
+ * Command queue statistics
+ */
+#define	TWEQ_FREE	0
+#define	TWEQ_BIO	1
+#define	TWEQ_READY	2
+#define	TWEQ_BUSY	3
+#define	TWEQ_COMPLETE	4
+#define	TWEQ_COUNT	5	/* total number of queues */
+
+struct twe_qstat {
+	u_int32_t	q_length;
+	u_int32_t	q_max;
+};
+
+/*
+ * Statistics request
+ */
+union twe_statrequest {
+	u_int32_t		ts_item;
+	struct twe_qstat	ts_qstat;
+};
+
+#define	TWEIO_STATS	_IOWR('T', 101, union twe_statrequest)
+
+/*
+ * AEN listen
+ */
+#define	TWEIO_AEN_POLL	_IOR('T', 102, int)
+#define	TWEIO_AEN_WAIT	_IOR('T', 103, int)
+
+/*
+ * Controller parameter access
+ */
+struct twe_paramcommand {
+	u_int16_t	tp_table_id;
+	u_int8_t	tp_param_id;
+	void		*tp_data;
+	u_int8_t	tp_size;
+};
+
+#define	TWEIO_SET_PARAM	_IOW('T', 104, struct twe_paramcommand)
+#define	TWEIO_GET_PARAM	_IOW('T', 105, struct twe_paramcommand)
+
+/*
+ * Request a controller soft-reset
+ */
+#define	TWEIO_RESET	_IO('T', 106)
+
+/*
+ * Request a drive addition or deletion
+ */
+struct twe_drivecommand {
+	int		td_unit;
+};
+#define	TWEIO_ADD_UNIT	_IOW('U', 107, struct twe_drivecommand)
+#define	TWEIO_DEL_UNIT	_IOW('U', 108, struct twe_drivecommand)
+
+#endif /* _DEV_PCI_TWEIO_H_ */
--- a/sys/dev/pci/twereg.h
+++ b/sys/dev/pci/twereg.h
@@ -0,0 +1,342 @@
+/*	$NetBSD: twereg.h,v 1.15 2008/09/08 23:36:54 gmcgarry Exp $	*/
+
+/*-
+ * Copyright (c) 2000 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Andrew Doran.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*-
+ * Copyright (c) 2000 Michael Smith
+ * Copyright (c) 2000 BSDi
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * from FreeBSD: twereg.h,v 1.1 2000/05/24 23:35:23 msmith Exp
+ */
+
+#ifndef _PCI_TWEREG_H_
+#define	_PCI_TWEREG_H_
+
+/* Board registers. */
+#define	TWE_REG_CTL			0x00
+#define	TWE_REG_STS			0x04
+#define	TWE_REG_CMD_QUEUE		0x08
+#define	TWE_REG_RESP_QUEUE		0x0c
+
+/* Control register bit definitions. */
+#define	TWE_CTL_CLEAR_HOST_INTR		0x00080000
+#define	TWE_CTL_CLEAR_ATTN_INTR		0x00040000
+#define	TWE_CTL_MASK_CMD_INTR		0x00020000
+#define	TWE_CTL_MASK_RESP_INTR		0x00010000
+#define	TWE_CTL_UNMASK_CMD_INTR		0x00008000
+#define	TWE_CTL_UNMASK_RESP_INTR	0x00004000
+#define	TWE_CTL_CLEAR_ERROR_STS		0x00000200
+#define	TWE_CTL_ISSUE_SOFT_RESET	0x00000100
+#define	TWE_CTL_ENABLE_INTRS		0x00000080
+#define	TWE_CTL_DISABLE_INTRS		0x00000040
+#define	TWE_CTL_ISSUE_HOST_INTR		0x00000020
+#define	TWE_CTL_CLEAR_PARITY_ERROR	0x00800000
+#define	TWE_CTL_CLEAR_PCI_ABORT		0x00100000
+
+/* Status register bit definitions. */
+#define	TWE_STS_MAJOR_VERSION_MASK	0xf0000000
+#define	TWE_STS_MINOR_VERSION_MASK	0x0f000000
+#define	TWE_STS_PCI_PARITY_ERROR	0x00800000
+#define	TWE_STS_QUEUE_ERROR		0x00400000
+#define	TWE_STS_MICROCONTROLLER_ERROR	0x00200000
+#define	TWE_STS_PCI_ABORT		0x00100000
+#define	TWE_STS_HOST_INTR		0x00080000
+#define	TWE_STS_ATTN_INTR		0x00040000
+#define	TWE_STS_CMD_INTR		0x00020000
+#define	TWE_STS_RESP_INTR		0x00010000
+#define	TWE_STS_CMD_QUEUE_FULL		0x00008000
+#define	TWE_STS_RESP_QUEUE_EMPTY	0x00004000
+#define	TWE_STS_MICROCONTROLLER_READY	0x00002000
+#define	TWE_STS_CMD_QUEUE_EMPTY		0x00001000
+
+#define	TWE_STS_ALL_INTRS		0x000f0000
+#define	TWE_STS_CLEARABLE_BITS		0x00d00000
+#define	TWE_STS_EXPECTED_BITS		0x00002000
+#define	TWE_STS_UNEXPECTED_BITS		0x00f80000
+
+/* Command packet opcodes. */
+#define TWE_OP_NOP			0x00
+#define TWE_OP_INIT_CONNECTION		0x01
+#define TWE_OP_READ			0x02
+#define TWE_OP_WRITE			0x03
+#define TWE_OP_READVERIFY		0x04
+#define TWE_OP_VERIFY			0x05
+#define TWE_OP_PROBE			0x06
+#define TWE_OP_PROBEUNIT		0x07
+#define TWE_OP_ZEROUNIT			0x08
+#define TWE_OP_REPLACEUNIT		0x09
+#define TWE_OP_HOTSWAP			0x0a
+#define TWE_OP_SETATAFEATURE		0x0c
+#define TWE_OP_FLUSH			0x0e
+#define TWE_OP_ABORT			0x0f
+#define TWE_OP_CHECKSTATUS		0x10
+#define	TWE_OP_ATA_PASSTHROUGH		0x11
+#define TWE_OP_GET_PARAM		0x12
+#define TWE_OP_SET_PARAM		0x13
+#define TWE_OP_CREATEUNIT		0x14
+#define TWE_OP_DELETEUNIT		0x15
+#define TWE_OP_REBUILDUNIT		0x17
+#define TWE_OP_SECTOR_INFO		0x1a
+#define TWE_OP_AEN_LISTEN		0x1c
+#define TWE_OP_CMD_PACKET		0x1d
+#define	TWE_OP_CMD_WITH_DATA		0x1f
+
+/* Response queue entries.  Masking and shifting yields request ID. */
+#define	TWE_RESP_MASK			0x00000ff0
+#define	TWE_RESP_SHIFT			4
+
+/* Miscellenous constants. */
+#define	TWE_ALIGNMENT			512
+#define	TWE_MAX_UNITS			16
+#define	TWE_INIT_CMD_PACKET_SIZE	0x3
+#define	TWE_SG_SIZE			62
+#define	TWE_MAX_CMDS			255
+#define	TWE_Q_START			0
+#define	TWE_UNIT_INFORMATION_TABLE_BASE	0x300
+#define	TWE_IOCTL			0x80
+#define	TWE_SECTOR_SIZE			512
+
+/* Scatter/gather block. */
+struct twe_sgb {
+	u_int32_t	tsg_address;
+	u_int32_t	tsg_length;
+} __packed;
+
+/*
+ * Command block.  This is 512 (really 508) bytes in size, and must be
+ * aligned on a 512 byte boundary.
+ */
+struct twe_cmd {
+	u_int8_t	tc_opcode;	/* high 3 bits is S/G list offset */
+	u_int8_t	tc_size;
+	u_int8_t	tc_cmdid;
+	u_int8_t	tc_unit;	/* high nybble is host ID */
+	u_int8_t	tc_status;
+	u_int8_t	tc_flags;
+	u_int16_t	tc_count;	/* block & param count, msg credits */
+	union {
+		struct {
+			u_int32_t	lba;
+			struct	twe_sgb sgl[TWE_SG_SIZE];
+		} io __packed;
+		struct {
+			struct	twe_sgb sgl[TWE_SG_SIZE];
+		} param;
+		struct {
+			u_int32_t	response_queue_pointer;
+		} init_connection  __packed;
+	} tc_args;
+	int32_t		tc_pad;
+} __packed;
+
+/* Get/set parameter block. */
+struct twe_param {
+	u_int16_t	tp_table_id;
+	u_int8_t	tp_param_id;
+	u_int8_t	tp_param_size;
+	u_int8_t	tp_data[1];
+} __packed;
+
+/*
+ * From 3ware's documentation:
+ *
+ *   All parameters maintained by the controller are grouped into related
+ *   tables.  Tables are are accessed indirectly via get and set parameter
+ *   commands.  To access a specific parameter in a table, the table ID and
+ *   parameter index are used to uniquely identify a parameter.  Table
+ *   0xffff is the directory table and provides a list of the table IDs and
+ *   sizes of all other tables.  Index zero in each table specifies the
+ *   entire table, and index one specifies the size of the table.  An entire
+ *   table can be read or set by using index zero.
+ */
+
+#define TWE_PARAM_PARAM_ALL	0
+#define TWE_PARAM_PARAM_SIZE	1
+
+#define TWE_PARAM_DIRECTORY			0xffff	/* size is 4 * number of tables */
+#define TWE_PARAM_DIRECTORY_TABLES		2	/* 16 bits * number of tables */
+#define TWE_PARAM_DIRECTORY_SIZES		3	/* 16 bits * number of tables */
+
+#define TWE_PARAM_DRIVESUMMARY			0x0002
+#define TWE_PARAM_DRIVESUMMARY_Num		2	/* number of physical drives [2] */
+#define TWE_PARAM_DRIVESUMMARY_Status		3	/* array giving drive status per aport */
+#define TWE_PARAM_DRIVESTATUS_Missing		0x00
+#define TWE_PARAM_DRIVESTATUS_NotSupp		0xfe
+#define TWE_PARAM_DRIVESTATUS_Present		0xff
+
+#define TWE_PARAM_UNITSUMMARY			0x0003
+#define TWE_PARAM_UNITSUMMARY_Num		2	/* number of logical units [2] */
+#define TWE_PARAM_UNITSUMMARY_Status		3	/* array giving unit status [16] */
+#define TWE_PARAM_UNITSTATUS_Online		(1<<0)
+#define TWE_PARAM_UNITSTATUS_Complete		(1<<1)
+#define TWE_PARAM_UNITSTATUS_MASK		0xfc
+#define TWE_PARAM_UNITSTATUS_Normal		0xfc
+#define TWE_PARAM_UNITSTATUS_Initialising	0xf4	/* cannot be incomplete */
+#define TWE_PARAM_UNITSTATUS_Degraded		0xec
+#define TWE_PARAM_UNITSTATUS_Rebuilding		0xdc	/* cannot be incomplete */
+#define TWE_PARAM_UNITSTATUS_Verifying		0xcc	/* cannot be incomplete */
+#define TWE_PARAM_UNITSTATUS_Corrupt		0xbc	/* cannot be complete */
+#define TWE_PARAM_UNITSTATUS_Missing		0x00	/* cannot be complete or online */
+
+#define TWE_PARAM_DRIVEINFO			0x0200	/* add drive number 0x00-0x0f XXX docco confused 0x0100 vs 0x0200 */
+#define TWE_PARAM_DRIVEINFO_Size		2	/* size in blocks [4] */
+#define TWE_PARAM_DRIVEINFO_Model		3	/* drive model string [40] */
+#define TWE_PARAM_DRIVEINFO_Serial		4	/* drive serial number [20] */
+#define TWE_PARAM_DRIVEINFO_PhysCylNum		5	/* physical geometry [2] */
+#define TWE_PARAM_DRIVEINFO_PhysHeadNum		6	/* [2] */
+#define TWE_PARAM_DRIVEINFO_PhysSectorNum	7	/* [2] */
+#define TWE_PARAM_DRIVEINFO_LogCylNum		8	/* logical geometry [2] */
+#define TWE_PARAM_DRIVEINFO_LogHeadNum		9	/* [2] */
+#define TWE_PARAM_DRIVEINFO_LogSectorNum	10	/* [2] */
+#define TWE_PARAM_DRIVEINFO_UnitNum		11	/* unit number this drive is associated with or 0xff [1] */
+#define TWE_PARAM_DRIVEINFO_DriveFlags		12	/* N/A [1] */
+
+#define TWE_PARAM_APORTTIMEOUT			0x02c0	/* add (aport_number * 3) to parameter index */
+#define TWE_PARAM_APORTTIMEOUT_READ		2	/* read timeouts last 24hrs [2] */
+#define TWE_PARAM_APORTTIMEOUT_WRITE		3	/* write timeouts last 24hrs [2] */
+#define TWE_PARAM_APORTTIMEOUT_DEGRADE		4	/* degrade threshold [2] */
+
+#define TWE_PARAM_UNITINFO			0x0300	/* add unit number 0x00-0x0f */
+#define TWE_PARAM_UNITINFO_Number		2	/* unit number [1] */
+#define TWE_PARAM_UNITINFO_Status		3	/* unit status [1] */
+#define TWE_PARAM_UNITINFO_Capacity		4	/* unit capacity in blocks [4] */
+#define TWE_PARAM_UNITINFO_DescriptorSize	5	/* unit descriptor size + 3 bytes [2] */
+#define TWE_PARAM_UNITINFO_Descriptor		6	/* unit descriptor, TWE_UnitDescriptor or TWE_Array_Descriptor */
+#define TWE_PARAM_UNITINFO_Flags		7	/* unit flags [1] */
+#define TWE_PARAM_UNITFLAGS_WCE			(1<<0)
+
+#define TWE_PARAM_AEN				0x0401
+#define TWE_PARAM_AEN_UnitCode			2	/* (unit number << 8) | AEN code [2] */
+#define TWE_AEN_QUEUE_EMPTY			0x00
+#define TWE_AEN_SOFT_RESET			0x01
+#define TWE_AEN_DEGRADED_MIRROR			0x02	/* reports unit */
+#define TWE_AEN_CONTROLLER_ERROR		0x03
+#define TWE_AEN_REBUILD_FAIL			0x04	/* reports unit */
+#define TWE_AEN_REBUILD_DONE			0x05	/* reports unit */
+#define TWE_AEN_INCOMP_UNIT			0x06	/* reports unit */
+#define TWE_AEN_INIT_DONE			0x07	/* reports unit */
+#define TWE_AEN_UNCLEAN_SHUTDOWN		0x08	/* reports unit */
+#define TWE_AEN_APORT_TIMEOUT			0x09	/* reports unit, rate limited to 1 per 2^16 errors */
+#define TWE_AEN_DRIVE_ERROR			0x0a	/* reports unit */
+#define TWE_AEN_REBUILD_STARTED			0x0b	/* reports unit */
+#define TWE_AEN_QUEUE_FULL			0xff
+#define TWE_AEN_TABLE_UNDEFINED			0x15
+#define TWE_AEN_CODE(x)				((x) & 0xff)
+#define TWE_AEN_UNIT(x)				((x) >> 8)
+
+#define TWE_PARAM_VERSION			0x0402
+#define TWE_PARAM_VERSION_Mon			2	/* monitor version [16] */
+#define TWE_PARAM_VERSION_FW			3	/* firmware version [16] */
+#define TWE_PARAM_VERSION_BIOS			4	/* BIOSs version [16] */
+#define TWE_PARAM_VERSION_PCB			5	/* PCB version [8] */
+#define TWE_PARAM_VERSION_ATA			6	/* A-chip version [8] */
+#define TWE_PARAM_VERSION_PCI			7	/* P-chip version [8] */
+#define TWE_PARAM_VERSION_CtrlModel		8	/* N/A */
+#define TWE_PARAM_VERSION_CtrlSerial		9	/* N/A */
+#define TWE_PARAM_VERSION_SBufSize		10	/* N/A */
+#define TWE_PARAM_VERSION_CompCode		11	/* compatibility code [4] */
+
+#define TWE_PARAM_CONTROLLER			0x0403
+#define TWE_PARAM_CONTROLLER_DCBSectors		2	/* # sectors reserved for DCB per drive [2] */
+#define TWE_PARAM_CONTROLLER_PortCount		3	/* number of drive ports [1] */
+
+#define TWE_PARAM_FEATURES			0x404
+#define TWE_PARAM_FEATURES_DriverShutdown	2	/* set to 1 if driver supports shutdown notification [1] */
+
+#define TWE_PARAM_PROC				0x406
+#define TWE_PARAM_PROC_PERCENT			2	/* Per-sub-unit % complete of init/verify/rebuild or 0xff [16] */
+
+struct twe_unit_descriptor {
+	u_int8_t	num_subunits;	/* must be zero */
+	u_int8_t	configuration;
+#define TWE_UD_CONFIG_CBOD	0x0c	/* JBOD with DCB, used for mirrors */
+#define TWE_UD_CONFIG_SPARE	0x0d	/* same as CBOD, but firmware will use as spare */
+#define TWE_UD_CONFIG_SUBUNIT	0x0e	/* drive is a subunit in an array */
+#define TWE_UD_CONFIG_JBOD	0x0f	/* plain drive */
+	u_int8_t	phys_drv_num;	/* may be 0xff if port can't be determined at runtime */
+	u_int8_t	log_drv_num;	/* must be zero for configuration == 0x0f */
+	u_int32_t	start_lba;
+	u_int32_t	block_count;	/* actual drive size if configuration == 0x0f, otherwise less DCB size */
+} __packed;
+
+struct twe_mirror_descriptor {
+	u_int8_t	flag;			/* must be 0xff */
+	u_int8_t	res1;
+	u_int8_t	mirunit_status[4];	/* bitmap of functional subunits in each mirror */
+	u_int8_t	res2[6];
+} __packed;
+
+struct twe_array_descriptor {
+	u_int8_t	num_subunits;	/* number of subunits, or number of mirror units in RAID10 */
+	u_int8_t	configuration;
+#define TWE_AD_CONFIG_RAID0	0x00
+#define TWE_AD_CONFIG_RAID1	0x01
+#define TWE_AD_CONFIG_TwinStor	0x02
+#define TWE_AD_CONFIG_RAID5	0x05
+#define TWE_AD_CONFIG_RAID10	0x06
+	u_int8_t		stripe_size;
+#define TWE_AD_STRIPE_4k	0x03
+#define TWE_AD_STRIPE_8k	0x04
+#define TWE_AD_STRIPE_16k	0x05
+#define TWE_AD_STRIPE_32k	0x06
+#define TWE_AD_STRIPE_64k	0x07
+#define TWE_AD_STRIPE_128k	0x08
+#define TWE_AD_STRIPE_256k	0x09
+#define TWE_AD_STRIPE_512k	0x0a
+#define TWE_AD_STRIPE_1024k	0x0b
+	u_int8_t		log_drv_status;	/* bitmap of functional subunits, or mirror units in RAID10 */
+	u_int32_t		start_lba;
+	u_int32_t		block_count;	/* actual drive size if configuration == 0x0f, otherwise less DCB size */
+	struct twe_unit_descriptor	subunit[1];
+} __packed;
+
+#endif	/* !_PCI_TWEREG_H_ */