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Synchronize on NetBSD-CVS (2013/12/1 12:00:00 UTC)

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- Fix for possible unset uid/gid in toproto
 - Fix for default mtree style
 - Update libelf
 - Importing libexecinfo
 - Resynchronize GCC, mpc, gmp, mpfr
 - build.sh: Replace params with show-params.
     This has been done as the make target has been renamed in the same
     way, while a new target named params has been added. This new
     target generates a file containing all the parameters, instead of
     printing it on the console.
 - Update test48 with new etc/services (Fix by Ben Gras <ben@minix3.org)
     get getservbyport() out of the inner loop

Change-Id: Ie6ad5226fa2621ff9f0dee8782ea48f9443d2091
This commit is contained in:
Lionel Sambuc
2013-12-06 12:04:52 +01:00
parent ff10274392
commit 84d9c625bf
4655 changed files with 379317 additions and 151059 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
sys/arch/arm/include/Makefile
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@@ -1,4 +1,4 @@
# $NetBSD: Makefile,v 1.43 2012/08/15 20:38:49 matt Exp $
# $NetBSD: Makefile,v 1.47 2013/05/02 03:56:40 matt Exp $
INCSDIR= /usr/include/arm
@@ -7,9 +7,10 @@ INCS= aeabi.h ansi.h aout_machdep.h armreg.h asm.h atomic.h \
cdefs.h cpu.h cpuconf.h \
disklabel.h \
elf_machdep.h endian.h endian_machdep.h \
float.h fp.h frame.h \
fenv.h float.h frame.h \
ieee.h ieeefp.h \
int_const.h int_fmtio.h int_limits.h int_mwgwtypes.h int_types.h \
\
kcore.h \
limits.h lock.h \
math.h mcontext.h mutex.h \
@@ -18,7 +19,7 @@ INCS= aeabi.h ansi.h aout_machdep.h armreg.h asm.h atomic.h \
reg.h rwlock.h \
setjmp.h signal.h swi.h sysarch.h \
trap.h types.h \
vfpreg.h \
vfpreg.h vmparam.h \
wchar_limits.h
.include <bsd.kinc.mk>

26
sys/arch/arm/include/Makefile.common Normal file
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@@ -0,0 +1,26 @@
# $NetBSD: Makefile.common,v 1.2 2013/05/02 03:56:40 matt Exp $
.PATH: ../../arm/include/common
.if 0
INCS+= ansi.h aout_machdep.h asm.h \
bswap.h \
cdefs.h cpu.h \
elf_machdep.h endian.h endian_machdep.h \
fenv.h float.h frame.h \
ieee.h ieeefp.h \
int_const.h int_fmtio.h int_limits.h int_mwgwtypes.h int_types.h \
limits.h lock.h \
math.h mcontext.h mutex.h \
param.h pcb.h pmap.h pmc.h proc.h profile.h ptrace.h \
reg.h rwlock.h \
setjmp.h signal.h sysarch.h \
trap.h types.h \
vmparam.h \
wchar_limits.h
.else
INCS+= disklabel.h \
.endif
.include <bsd.kinc.mk>

113
sys/arch/arm/include/aeabi.h
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@@ -1,4 +1,4 @@
/* $NetBSD: aeabi.h,v 1.2 2012/08/11 16:21:26 matt Exp $ */
/* $NetBSD: aeabi.h,v 1.5 2013/08/01 22:20:40 matt Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
@@ -31,89 +31,94 @@
#ifndef _ARM_AEABI_H_
#define _ARM_AEABI_H_
#if defined(_KERNEL) || defined(_STANDALONE)
#include <sys/types.h>
#else
#include <stddef.h>
#endif
#define __value_in_regs /* nothing */
#define __aapcs __attribute__((__pcs__("aapcs")))
/*
* Standard double precision floating-point arithmetic helper functions
*/
double __aeabi_dadd(double, double); // double-precision addition
double __aeabi_ddiv(double n, double d); // double-precision division, n / d
double __aeabi_dmul(double, double); // double-precision multiplication
double __aeabi_drsub(double x, double y); // double-precision reverse subtraction, y - x
double __aeabi_dsub(double x, double y); // double-precision subtraction, x - y
double __aeabi_dneg(double); // double-precision negation (obsolete, to be removed in r2.09)
double __aeabi_dadd(double, double) __aapcs; // double-precision addition
double __aeabi_ddiv(double n, double d) __aapcs; // double-precision division, n / d
double __aeabi_dmul(double, double) __aapcs; // double-precision multiplication
double __aeabi_drsub(double x, double y) __aapcs; // double-precision reverse subtraction, y - x
double __aeabi_dsub(double x, double y) __aapcs; // double-precision subtraction, x - y
double __aeabi_dneg(double) __aapcs; // double-precision negation (obsolete, to be removed in r2.09)
/*
* Double precision floating-point comparison helper functions
*/
void __aeabi_cdcmpeq(double, double); // non-excepting equality comparison [1], result in PSR ZC flags
void __aeabi_cdcmple(double, double); // 3-way (<, =, >) compare [1], result in PSR ZC flags
void __aeabi_cdrcmple(double, double); // reversed 3-way (<, =, >) compare [1], result in PSR ZC flags
int __aeabi_dcmpeq(double, double); // result (1, 0) denotes (=, <>) [2], use for C == and !=
int __aeabi_dcmplt(double, double); // result (1, 0) denotes (<, >=) [2], use for C <
int __aeabi_dcmple(double, double); // result (1, 0) denotes (<=, >) [2], use for C <=
int __aeabi_dcmpge(double, double); // result (1, 0) denotes (>=, <) [2], use for C >=
int __aeabi_dcmpgt(double, double); // result (1, 0) denotes (>, <=) [2], use for C >
int __aeabi_dcmpun(double, double); // result (1, 0) denotes (?, <=>) [2], use for C99 isunordered()
void __aeabi_cdcmpeq(double, double) __aapcs; // non-excepting equality comparison [1], result in PSR ZC flags
void __aeabi_cdcmple(double, double) __aapcs; // 3-way (<, =, >) compare [1], result in PSR ZC flags
void __aeabi_cdrcmple(double, double) __aapcs; // reversed 3-way (<, =, >) compare [1], result in PSR ZC flags
int __aeabi_dcmpeq(double, double) __aapcs; // result (1, 0) denotes (=, <>) [2], use for C == and !=
int __aeabi_dcmplt(double, double) __aapcs; // result (1, 0) denotes (<, >=) [2], use for C <
int __aeabi_dcmple(double, double) __aapcs; // result (1, 0) denotes (<=, >) [2], use for C <=
int __aeabi_dcmpge(double, double) __aapcs; // result (1, 0) denotes (>=, <) [2], use for C >=
int __aeabi_dcmpgt(double, double) __aapcs; // result (1, 0) denotes (>, <=) [2], use for C >
int __aeabi_dcmpun(double, double) __aapcs; // result (1, 0) denotes (?, <=>) [2], use for C99 isunordered()
/*
* Standard single precision floating-point arithmetic helper functions
*/
float __aeabi_fadd(float, float); // single-precision addition
float __aeabi_fdiv(float n, float d); // single-precision division, n / d
float __aeabi_fmul(float, float); // single-precision multiplication
float __aeabi_frsub(float x, float y); // single-precision reverse subtraction, y - x
float __aeabi_fsub(float x, float y); // single-precision subtraction, x - y
float __aeabi_fneg(float); // single-precision negation (obsolete, to be removed in r2.09)
float __aeabi_fadd(float, float) __aapcs; // single-precision addition
float __aeabi_fdiv(float n, float d) __aapcs; // single-precision division, n / d
float __aeabi_fmul(float, float) __aapcs; // single-precision multiplication
float __aeabi_frsub(float x, float y) __aapcs; // single-precision reverse subtraction, y - x
float __aeabi_fsub(float x, float y) __aapcs; // single-precision subtraction, x - y
float __aeabi_fneg(float) __aapcs; // single-precision negation (obsolete, to be removed in r2.09)
/*
* Standard single precision floating-point comparison helper functions
*/
void __aeabi_cfcmpeq(float, float); // non-excepting equality comparison [1], result in PSR ZC flags
void __aeabi_cfcmple(float, float); // 3-way (<, =, ?>) compare [1], result in PSR ZC flags
void __aeabi_cfrcmple(float, float); // reversed 3-way (<, =, ?>) compare [1], result in PSR ZC flags
int __aeabi_fcmpeq(float, float); // result (1, 0) denotes (=, <>) [2], use for C == and !=
int __aeabi_fcmplt(float, float); // result (1, 0) denotes (<, >=) [2], use for C <
int __aeabi_fcmple(float, float); // result (1, 0) denotes (<=, >) [2], use for C <=
int __aeabi_fcmpge(float, float); // result (1, 0) denotes (>=, <) [2], use for C >=
int __aeabi_fcmpgt(float, float); // result (1, 0) denotes (>, <=) [2], use for C >
int __aeabi_fcmpun(float, float); // result (1, 0) denotes (?, <=>) [2], use for C99 isunordered()
void __aeabi_cfcmpeq(float, float) __aapcs; // non-excepting equality comparison [1], result in PSR ZC flags
void __aeabi_cfcmple(float, float) __aapcs; // 3-way (<, =, ?>) compare [1], result in PSR ZC flags
void __aeabi_cfrcmple(float, float) __aapcs; // reversed 3-way (<, =, ?>) compare [1], result in PSR ZC flags
int __aeabi_fcmpeq(float, float) __aapcs; // result (1, 0) denotes (=, <>) [2], use for C == and !=
int __aeabi_fcmplt(float, float) __aapcs; // result (1, 0) denotes (<, >=) [2], use for C <
int __aeabi_fcmple(float, float) __aapcs; // result (1, 0) denotes (<=, >) [2], use for C <=
int __aeabi_fcmpge(float, float) __aapcs; // result (1, 0) denotes (>=, <) [2], use for C >=
int __aeabi_fcmpgt(float, float) __aapcs; // result (1, 0) denotes (>, <=) [2], use for C >
int __aeabi_fcmpun(float, float) __aapcs; // result (1, 0) denotes (?, <=>) [2], use for C99 isunordered()
/*
* Standard conversions between floating types
*/
float __aeabi_d2f(double); // double to float (single precision) conversion
double __aeabi_f2d(float); // float (single precision) to double conversion
float __aeabi_h2f(short hf); // IEEE 754 binary16 storage format (VFP half precision) to binary32 (float) conversion [4, 5]
short __aeabi_f2h(float f); // IEEE 754 binary32 (float) to binary16 storage format (VFP half precision) conversion [4, 6]
float __aeabi_h2f_alt(short hf); // __aeabi_h2f_alt converts from VFP alternative format [7].
short __aeabi_f2h_alt(float f); // __aeabi_f2h_alt converts to VFP alternative format [8].
float __aeabi_d2f(double) __aapcs; // double to float (single precision) conversion
double __aeabi_f2d(float) __aapcs; // float (single precision) to double conversion
float __aeabi_h2f(short hf) __aapcs; // IEEE 754 binary16 storage format (VFP half precision) to binary32 (float) conversion [4, 5]
short __aeabi_f2h(float f) __aapcs; // IEEE 754 binary32 (float) to binary16 storage format (VFP half precision) conversion [4, 6]
float __aeabi_h2f_alt(short hf) __aapcs; // __aeabi_h2f_alt converts from VFP alternative format [7].
short __aeabi_f2h_alt(float f) __aapcs; // __aeabi_f2h_alt converts to VFP alternative format [8].
/*
* Standard floating-point to integer conversions
*/
int __aeabi_d2iz(double); // double to integer C-style conversion [3]
unsigned __aeabi_d2uiz(double); // double to unsigned C-style conversion [3]
long long __aeabi_d2lz(double); // double to long long C-style conversion [3]
unsigned long long __aeabi_d2ulz(double); // double to unsigned long long C-style conversion [3]
int __aeabi_f2iz(float); // float (single precision) to integer C-style conversion [3]
unsigned __aeabi_f2uiz(float); // float (single precision) to unsigned C-style conversion [3]
long long __aeabi_f2lz(float); // float (single precision) to long long C-style conversion [3]
unsigned long long __aeabi_f2ulz(float); // float to unsigned long long C-style conversion [3]
int __aeabi_d2iz(double) __aapcs; // double to integer C-style conversion [3]
unsigned __aeabi_d2uiz(double) __aapcs; // double to unsigned C-style conversion [3]
long long __aeabi_d2lz(double) __aapcs; // double to long long C-style conversion [3]
unsigned long long __aeabi_d2ulz(double) __aapcs; // double to unsigned long long C-style conversion [3]
int __aeabi_f2iz(float) __aapcs; // float (single precision) to integer C-style conversion [3]
unsigned __aeabi_f2uiz(float) __aapcs; // float (single precision) to unsigned C-style conversion [3]
long long __aeabi_f2lz(float) __aapcs; // float (single precision) to long long C-style conversion [3]
unsigned long long __aeabi_f2ulz(float) __aapcs; // float to unsigned long long C-style conversion [3]
/*
* Standard integer to floating-point conversions
*/
double __aeabi_i2d(int); // integer to double conversion
double __aeabi_ui2d(unsigned); // unsigned to double conversion
double __aeabi_l2d(long long); // long long to double conversion
double __aeabi_ul2d(unsigned long long); // unsigned long long to double conversion
float __aeabi_i2f(int); // integer to float (single precision) conversion
float __aeabi_ui2f(unsigned); // unsigned to float (single precision) conversion
float __aeabi_l2f(long long); // long long to float (single precision) conversion
float __aeabi_ul2f(unsigned long long); // unsigned long long to float (single precision) conversion
double __aeabi_i2d(int) __aapcs; // integer to double conversion
double __aeabi_ui2d(unsigned) __aapcs; // unsigned to double conversion
double __aeabi_l2d(long long) __aapcs; // long long to double conversion
double __aeabi_ul2d(unsigned long long) __aapcs; // unsigned long long to double conversion
float __aeabi_i2f(int) __aapcs; // integer to float (single precision) conversion
float __aeabi_ui2f(unsigned) __aapcs; // unsigned to float (single precision) conversion
float __aeabi_l2f(long long) __aapcs; // long long to float (single precision) conversion
float __aeabi_ul2f(unsigned long long) __aapcs; // unsigned long long to float (single precision) conversion
/*
* Long long functions
@@ -197,4 +202,6 @@ void __aeabi_memclr(void *, size_t);
void *__aeabi_read_tp(void); // return the value of $tp
#undef __aapcs
#endif /* _ARM_AEABI_H_ */

27
sys/arch/arm/include/ansi.h
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@@ -1,4 +1,4 @@
/* $NetBSD: ansi.h,v 1.13 2011/07/17 20:54:37 joerg Exp $ */
/* $NetBSD: ansi.h,v 1.15 2013/01/27 17:43:20 matt Exp $ */
/*
* Copyright (c) 1990, 1993
@@ -51,20 +51,37 @@
#if defined(__minix)
/* To change this, this require also changing the defintion of size_t in GCC,
* and to adapt the following headers: int_fmt.h, int_types.h */
#define _BSD_PTRDIFF_T_ int /* ptr1 - ptr2 */
#define _BSD_SIZE_T_ unsigned int /* sizeof() */
#define _BSD_SSIZE_T_ int /* byte count or error */
#define _BSD_PTRDIFF_T_ int /* ptr1 - ptr2 */
#define _BSD_SIZE_T_ unsigned int /* sizeof() */
#define _BSD_SSIZE_T_ int /* byte count or error */
#else
#ifdef __PTRDIFF_TYPE__
#define _BSD_PTRDIFF_T_ __PTRDIFF_TYPE__ /* ptr1 - ptr2 */
#define _BSD_SSIZE_T_ __PTRDIFF_TYPE__ /* byte count or error */
#else
#define _BSD_PTRDIFF_T_ long int /* ptr1 - ptr2 */
#define _BSD_SIZE_T_ unsigned long int /* sizeof() */
#define _BSD_SSIZE_T_ long int /* byte count or error */
#endif
#ifdef __SIZE_TYPE__
#define _BSD_SIZE_T_ __SIZE_TYPE__ /* sizeof() */
#else
#define _BSD_SIZE_T_ unsigned long int /* sizeof() */
#endif
#endif /* defined(__minix) */
#define _BSD_TIME_T_ __int64_t /* time() */
#define _BSD_CLOCKID_T_ int /* clockid_t */
#define _BSD_TIMER_T_ int /* timer_t */
#define _BSD_SUSECONDS_T_ int /* suseconds_t */
#define _BSD_USECONDS_T_ unsigned int /* useconds_t */
#ifdef __WCHAR_TYPE__
#define _BSD_WCHAR_T_ __WCHAR_TYPE__ /* wchar_t */
#else
#define _BSD_WCHAR_T_ int /* wchar_t */
#endif
#ifdef __WINT_TYPE__
#define _BSD_WINT_T_ __WINT_TYPE__ /* wint_t */
#else
#define _BSD_WINT_T_ int /* wint_t */
#endif
#endif /* _ANSI_H_ */

34
sys/arch/arm/include/apmvar.h Normal file
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@@ -0,0 +1,34 @@
/* $NetBSD: apmvar.h,v 1.1 2013/05/02 03:56:40 matt Exp $ */
/*-
* Copyright (c) 1995 The NetBSD Foundation, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ZAURUS_APMVAR_H__
#define __ZAURUS_APMVAR_H__
#include <dev/apm/apmbios.h>
#include <dev/apm/apmio.h>
#endif /* __ZAURUS_APMVAR_H__ */

3
sys/arch/arm/include/arm32/db_machdep.h
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@@ -1,11 +1,10 @@
/* $NetBSD: db_machdep.h,v 1.6 2012/09/21 22:12:36 matt Exp $ */
/* $NetBSD: db_machdep.h,v 1.7 2013/01/05 15:06:51 christos Exp $ */
#ifndef _ARM32_DB_MACHDEP_H_
#define _ARM32_DB_MACHDEP_H_
#include <arm/db_machdep.h>
void db_show_panic_cmd(db_expr_t, bool, db_expr_t, const char *);
void db_show_frame_cmd(db_expr_t, bool, db_expr_t, const char *);
void db_show_fault_cmd(db_expr_t, bool, db_expr_t, const char *);

125
sys/arch/arm/include/arm32/frame.h
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@@ -1,4 +1,4 @@
/* $NetBSD: frame.h,v 1.33 2012/08/29 07:09:12 matt Exp $ */
/* $NetBSD: frame.h,v 1.36 2013/08/18 06:37:02 matt Exp $ */
/*
* Copyright (c) 1994-1997 Mark Brinicombe.
@@ -50,14 +50,6 @@
#ifndef _LOCORE
/*
* System stack frames.
*/
struct clockframe {
struct trapframe cf_tf;
};
/*
* Switch frame.
*
@@ -73,6 +65,14 @@ struct switchframe {
u_int sf_pc;
};
/*
* System stack frames.
*/
struct clockframe {
struct trapframe cf_tf;
};
/*
* Stack frame. Used during stack traces (db_trace.c)
*/
@@ -96,16 +96,33 @@ void validate_trapframe(trapframe_t *, int);
#include "opt_arm_debug.h"
#include "opt_cputypes.h"
#include <machine/cpu.h>
#include <arm/locore.h>
/*
* This macro is used by DO_AST_AND_RESTORE_ALIGNMENT_FAULTS to process
* any pending softints.
*/
#ifdef _ARM_ARCH_4T
#define B_CF_CONTROL(rX) ;\
ldr ip, [rX, #CF_CONTROL] /* get function addr */ ;\
bx ip /* branch to cpu_control */
#else
#define B_CF_CONTROL(rX) ;\
ldr pc, [rX, #CF_CONTROL] /* branch to cpu_control */
#endif
#ifdef _ARM_ARCH_5T
#define BL_CF_CONTROL(rX) ;\
ldr ip, [rX, #CF_CONTROL] /* get function addr */ ;\
blx ip /* call cpu_control */
#else
#define BL_CF_CONTROL(rX) ;\
mov lr, pc ;\
ldr pc, [rX, #CF_CONTROL] /* call cpu_control */
#endif
#if defined(__HAVE_FAST_SOFTINTS) && !defined(__HAVE_PIC_FAST_SOFTINTS)
#define DO_PENDING_SOFTINTS \
ldr r0, [r4, #CI_INTR_DEPTH]/* Get current intr depth */ ;\
teq r0, #0 /* Test for 0. */ ;\
cmp r0, #0 /* Test for 0. */ ;\
bne 10f /* skip softints if != 0 */ ;\
ldr r0, [r4, #CI_CPL] /* Get current priority level */;\
ldr r1, [r4, #CI_SOFTINTS] /* Get pending softint mask */ ;\
@@ -183,8 +200,7 @@ void validate_trapframe(trapframe_t *, int);
ldr r2, .Laflt_cpufuncs ;\
ldr r1, [r4, #CI_CTRL] /* Fetch control register */ ;\
mov r0, #-1 ;\
mov lr, pc ;\
ldr pc, [r2, #CF_CONTROL] /* Enable alignment faults */ ;\
BL_CF_CONTROL(r2) /* Enable alignment faults */ ;\
1: KERNEL_LOCK
/*
@@ -211,7 +227,7 @@ void validate_trapframe(trapframe_t *, int);
mov r0, #-1 ;\
bic r1, r1, #CPU_CONTROL_AFLT_ENABLE /* Disable AFLTs */ ;\
adr lr, 3f ;\
ldr pc, [r2, #CF_CONTROL] /* Set new CTRL reg value */ ;\
B_CF_CONTROL(r2) /* Set new CTRL reg value */ ;\
/* NOTREACHED */ \
2: mov r1, #0x00000000 ;\
str r1, [r4, #CI_ASTPENDING] /* Clear astpending */ ;\
@@ -323,7 +339,7 @@ LOCK_CAS_DEBUG_LOCALS
*/
#define PUSHUSERREGS \
stmia sp, {r0-r12}; /* Push the user mode registers */ \
add r0, sp, #(4*13); /* Adjust the stack pointer */ \
add r0, sp, #(TF_USR_SP-TF_R0); /* Adjust the stack pointer */ \
stmia r0, {r13-r14}^ /* Push the user mode registers */
#else
#define PUSHUSERREGS \
@@ -332,11 +348,61 @@ LOCK_CAS_DEBUG_LOCALS
#define PUSHFRAME \
str lr, [sp, #-4]!; /* Push the return address */ \
sub sp, sp, #(4*17); /* Adjust the stack pointer */ \
sub sp, sp, #(TF_PC-TF_R0); /* Adjust the stack pointer */ \
PUSHUSERREGS; /* Push the user mode registers */ \
mov r0, r0; /* NOP for previous instruction */ \
mrs r0, spsr_all; /* Get the SPSR */ \
str r0, [sp, #-8]! /* Push the SPSR on the stack */
str r0, [sp, #-TF_R0]! /* Push the SPSR on the stack */
/*
* Push a minimal trapframe so we can dispatch an interrupt from the
* idle loop. The only reason the idle loop wakes up is to dispatch
* interrupts so why take the avoid of a full exception when we can do
* something minimal.
*/
#define PUSHIDLEFRAME \
str lr, [sp, #-4]!; /* save SVC32 lr */ \
str r6, [sp, #(TF_R6-TF_PC)]!; /* save callee-saved r6 */ \
str r4, [sp, #(TF_R4-TF_R6)]!; /* save callee-saved r4 */ \
mrs r0, cpsr_all; /* Get the CPSR */ \
str r0, [sp, #(-TF_R4)]! /* Push the CPSR on the stack */
/*
* Push a trapframe to be used by cpu_switchto
*/
#define PUSHSWITCHFRAME(rX) \
mov ip, sp; \
sub sp, sp, #(TRAPFRAMESIZE-TF_R12); /* Adjust the stack pointer */ \
push {r4-r11}; /* Push the callee saved registers */ \
sub sp, sp, #TF_R4; /* reserve rest of trapframe */ \
str ip, [sp, #TF_SVC_SP]; \
str lr, [sp, #TF_SVC_LR]; \
str lr, [sp, #TF_PC]; \
mrs rX, cpsr_all; /* Get the CPSR */ \
str rX, [sp, #TF_SPSR] /* save in trapframe */
#define PUSHSWITCHFRAME1 \
mov ip, sp; \
sub sp, sp, #(TRAPFRAMESIZE-TF_R8); /* Adjust the stack pointer */ \
push {r4-r7}; /* Push some of the callee saved registers */ \
sub sp, sp, #TF_R4; /* reserve rest of trapframe */ \
str ip, [sp, #TF_SVC_SP]; \
str lr, [sp, #TF_SVC_LR]; \
str lr, [sp, #TF_PC]
#if defined(_ARM_ARCH_DWORD_OK) && __ARM_EABI__
#define PUSHSWITCHFRAME2 \
strd r10, [sp, #TF_R10]; /* save r10 & r11 */ \
strd r8, [sp, #TF_R8]; /* save r8 & r9 */ \
mrs r0, cpsr_all; /* Get the CPSR */ \
str r0, [sp, #TF_SPSR] /* save in trapframe */
#else
#define PUSHSWITCHFRAME2 \
add r0, sp, #TF_R8; /* get ptr to r8 and above */ \
stmia r0, {r8-r11}; /* save rest of registers */ \
mrs r0, cpsr_all; /* Get the CPSR */ \
str r0, [sp, #TF_SPSR] /* save in trapframe */
#endif
/*
* PULLFRAME - macro to pull a trap frame from the stack in the current mode
@@ -344,13 +410,28 @@ LOCK_CAS_DEBUG_LOCALS
*/
#define PULLFRAME \
ldr r0, [sp], #0x0008; /* Pop the SPSR from stack */ \
ldr r0, [sp], #TF_R0; /* Pop the SPSR from stack */ \
msr spsr_all, r0; \
ldmia sp, {r0-r14}^; /* Restore registers (usr mode) */ \
mov r0, r0; /* NOP for previous instruction */ \
add sp, sp, #(4*17); /* Adjust the stack pointer */ \
add sp, sp, #(TF_PC-TF_R0); /* Adjust the stack pointer */ \
ldr lr, [sp], #0x0004 /* Pop the return address */
#define PULLIDLEFRAME \
add sp, sp, #TF_R4; /* Adjust the stack pointer */ \
ldr r4, [sp], #(TF_R6-TF_R4); /* restore callee-saved r4 */ \
ldr r6, [sp], #(TF_PC-TF_R6); /* restore callee-saved r6 */ \
ldr lr, [sp], #4 /* Pop the return address */
/*
* Pop a trapframe to be used by cpu_switchto (don't touch r0 & r1).
*/
#define PULLSWITCHFRAME \
add sp, sp, #TF_R4; /* Adjust the stack pointer */ \
pop {r4-r11}; /* pop the callee saved registers */ \
add sp, sp, #(TF_PC-TF_R12); /* Adjust the stack pointer */ \
ldr lr, [sp], #4; /* pop the return address */
/*
* PUSHFRAMEINSVC - macro to push a trap frame on the stack in SVC32 mode
* This should only be used if the processor is not currently in SVC32
@@ -385,11 +466,11 @@ LOCK_CAS_DEBUG_LOCALS
mov sp, r2; /* Keep stack aligned */ \
msr spsr_all, r3; /* Restore correct spsr */ \
ldmdb r1, {r0-r3}; /* Restore 4 regs from xxx mode */ \
sub sp, sp, #(4*15); /* Adjust the stack pointer */ \
sub sp, sp, #(TF_SVC_SP-TF_R0); /* Adjust the stack pointer */ \
PUSHUSERREGS; /* Push the user mode registers */ \
mov r0, r0; /* NOP for previous instruction */ \
mrs r0, spsr_all; /* Get the SPSR */ \
str r0, [sp, #-8]! /* Push the SPSR onto the stack */
str r0, [sp, #-TF_R0]! /* Push the SPSR onto the stack */
/*
* PULLFRAMEFROMSVCANDEXIT - macro to pull a trap frame from the stack
@@ -403,7 +484,7 @@ LOCK_CAS_DEBUG_LOCALS
msr spsr_all, r0; /* restore SPSR */ \
ldmia sp, {r0-r14}^; /* Restore registers (usr mode) */ \
mov r0, r0; /* NOP for previous instruction */ \
add sp, sp, #(4*15); /* Adjust the stack pointer */ \
add sp, sp, #(TF_SVC_SP-TF_R0); /* Adjust the stack pointer */ \
ldmia sp, {sp, lr, pc}^ /* Restore lr and exit */
#endif /* _LOCORE */

4
sys/arch/arm/include/arm32/machdep.h
View File

@@ -1,4 +1,4 @@
/* $NetBSD: machdep.h,v 1.16 2012/09/01 12:19:32 martin Exp $ */
/* $NetBSD: machdep.h,v 1.17 2012/10/20 14:42:20 matt Exp $ */
#ifndef _ARM32_BOOT_MACHDEP_H_
#define _ARM32_BOOT_MACHDEP_H_
@@ -43,7 +43,7 @@ struct bootmem_info {
*/
pv_addr_t bmi_vector_l2pt;
pv_addr_t bmi_io_l2pt;
pv_addr_t bmi_l2pts[16];
pv_addr_t bmi_l2pts[32]; // for large memory disks.
u_int bmi_freepages;
u_int bmi_nfreeblocks;
};

19
sys/arch/arm/include/arm32/param.h
View File

@@ -1,4 +1,4 @@
/* $NetBSD: param.h,v 1.17 2012/02/04 17:56:16 para Exp $ */
/* $NetBSD: param.h,v 1.20 2013/05/29 23:29:44 rkujawa Exp $ */
/*
* Copyright (c) 1994,1995 Mark Brinicombe.
@@ -57,7 +57,7 @@
#define USPACE (UPAGES * NBPG) /* total size of u-area */
#ifndef MSGBUFSIZE
#define MSGBUFSIZE NBPG /* default message buffer size */
#define MSGBUFSIZE 16384 /* default message buffer size */
#endif
/*
@@ -72,17 +72,13 @@
/*
* The USPACE area contains :
* 1. the pcb structure for the process
* 2. the fp context for FP emulation
* 3. the kernel (svc) stack
* 2. the kernel (svc) stack
*
* The layout of the area looks like this
*
* | uarea | FP context | kernel stack |
* | uarea | kernel stack |
*
* The size of the uarea is known.
* The size of the FP context is variable depending of the FP emulator
* in use and whether there is hardware FP support. However we can put
* an upper limit on it.
* The kernel stack should be at least 4K is size.
*
* The stack top addresses are used to set the stack pointers. The stack bottom
@@ -90,12 +86,11 @@
*
*/
#define FPCONTEXTSIZE (0x100)
#define USPACE_SVC_STACK_TOP (USPACE)
#define USPACE_SVC_STACK_BOTTOM (sizeof(struct pcb) + FPCONTEXTSIZE + 10)
#define USPACE_SVC_STACK_BOTTOM (sizeof(struct pcb))
#define arm_btop(x) ((x) >> PGSHIFT)
#define arm_ptob(x) ((x) << PGSHIFT)
#define arm_btop(x) ((unsigned)(x) >> PGSHIFT)
#define arm_ptob(x) ((unsigned)(x) << PGSHIFT)
#define arm_trunc_page(x) ((unsigned)(x) & ~PGOFSET)
#ifdef _KERNEL

61
sys/arch/arm/include/arm32/pmap.h
View File

@@ -1,4 +1,4 @@
/* $NetBSD: pmap.h,v 1.112 2012/09/22 00:33:38 matt Exp $ */
/* $NetBSD: pmap.h,v 1.122 2013/08/18 05:01:47 matt Exp $ */
/*
* Copyright (c) 2002, 2003 Wasabi Systems, Inc.
@@ -143,16 +143,16 @@ struct l2_dtable;
union pmap_cache_state {
struct {
union {
u_int8_t csu_cache_b[2];
u_int16_t csu_cache;
uint8_t csu_cache_b[2];
uint16_t csu_cache;
} cs_cache_u;
union {
u_int8_t csu_tlb_b[2];
u_int16_t csu_tlb;
uint8_t csu_tlb_b[2];
uint16_t csu_tlb;
} cs_tlb_u;
} cs_s;
u_int32_t cs_all;
uint32_t cs_all;
};
#define cs_cache_id cs_s.cs_cache_u.csu_cache_b[0]
#define cs_cache_d cs_s.cs_cache_u.csu_cache_b[1]
@@ -182,11 +182,13 @@ struct pmap_devmap {
* The pmap structure itself
*/
struct pmap {
u_int8_t pm_domain;
uint8_t pm_domain;
bool pm_remove_all;
bool pm_activated;
struct l1_ttable *pm_l1;
#ifndef ARM_HAS_VBAR
pd_entry_t *pm_pl1vec;
#endif
pd_entry_t pm_l1vec;
union pmap_cache_state pm_cstate;
struct uvm_object pm_obj;
@@ -269,6 +271,7 @@ extern pv_addr_t kernel_l1pt;
* Commonly referenced structures
*/
extern int pmap_debug_level; /* Only exists if PMAP_DEBUG */
extern int arm_poolpage_vmfreelist;
/*
* Macros that we need to export
@@ -321,6 +324,7 @@ void pmap_do_remove(pmap_t, vaddr_t, vaddr_t, int);
int pmap_fault_fixup(pmap_t, vaddr_t, vm_prot_t, int);
bool pmap_get_pde_pte(pmap_t, vaddr_t, pd_entry_t **, pt_entry_t **);
bool pmap_get_pde(pmap_t, vaddr_t, pd_entry_t **);
struct pcb;
void pmap_set_pcb_pagedir(pmap_t, struct pcb *);
void pmap_debug(int);
@@ -448,6 +452,27 @@ pmap_ptesync(pt_entry_t *ptep, size_t cnt)
(L2_B | L2_C | L2_XS_T_TEX(TEX_XSCALE_X)))\
== (L2_C | L2_XS_T_TEX(TEX_XSCALE_X)))
static inline void
l2pte_set(pt_entry_t *ptep, pt_entry_t pte, pt_entry_t opte)
{
KASSERT(*ptep == opte);
*ptep = pte;
for (vsize_t k = 1; k < PAGE_SIZE / L2_S_SIZE; k++) {
KASSERT(ptep[k] == opte ? opte + k * L2_S_SIZE : 0);
pte += L2_S_SIZE;
ptep[k] = pte;
}
}
static inline void
l2pte_reset(pt_entry_t *ptep)
{
*ptep = 0;
for (vsize_t k = 1; k < PAGE_SIZE / L2_S_SIZE; k++) {
ptep[k] = 0;
}
}
/* L1 and L2 page table macros */
#define pmap_pde_v(pde) l1pte_valid(*(pde))
#define pmap_pde_section(pde) l1pte_section_p(*(pde))
@@ -462,6 +487,14 @@ pmap_ptesync(pt_entry_t *ptep, size_t cnt)
#define KERNEL_PD_SIZE \
(L1_TABLE_SIZE - (KERNEL_BASE >> L1_S_SHIFT) * sizeof(pd_entry_t))
void bzero_page(vaddr_t);
void bcopy_page(vaddr_t, vaddr_t);
#ifdef FPU_VFP
void bzero_page_vfp(vaddr_t);
void bcopy_page_vfp(vaddr_t, vaddr_t);
#endif
/************************* ARM MMU configuration *****************************/
#if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0
@@ -881,12 +914,22 @@ extern void (*pmap_zero_page_func)(paddr_t);
#define L2_L_MAPPABLE_P(va, pa, size) \
((((va) | (pa)) & L2_L_OFFSET) == 0 && (size) >= L2_L_SIZE)
#ifndef _LOCORE
/*
* Hooks for the pool allocator.
*/
#define POOL_VTOPHYS(va) vtophys((vaddr_t) (va))
#ifndef _LOCORE
extern paddr_t physical_start, physical_end;
#ifdef PMAP_NEED_ALLOC_POOLPAGE
struct vm_page *arm_pmap_alloc_poolpage(int);
#define PMAP_ALLOC_POOLPAGE arm_pmap_alloc_poolpage
#endif
#if defined(PMAP_NEED_ALLOC_POOLPAGE) || defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS)
#define PMAP_MAP_POOLPAGE(pa) \
((vaddr_t)((paddr_t)(pa) - physical_start + KERNEL_BASE))
#define PMAP_UNMAP_POOLPAGE(va) \
((paddr_t)((vaddr_t)(va) - KERNEL_BASE + physical_start))
#endif
/*
* pmap-specific data store in the vm_page structure.

2
sys/arch/arm/include/arm32/types.h
View File

@@ -1,4 +1,4 @@
/* $NetBSD: types.h,v 1.9 2010/07/07 01:20:50 chs Exp $ */
/* $NetBSD: types.h,v 1.11 2013/05/07 23:01:55 matt Exp $ */
/*
* Copyright (c) 2001 Wasabi Systems, Inc.

10
sys/arch/arm/include/arm32/vmparam.h
View File

@@ -1,4 +1,4 @@
/* $NetBSD: vmparam.h,v 1.27 2012/08/16 07:25:37 matt Exp $ */
/* $NetBSD: vmparam.h,v 1.29 2013/02/27 17:50:07 matt Exp $ */
/*
* Copyright (c) 2001, 2002 Wasabi Systems, Inc.
@@ -55,25 +55,25 @@
* Note that MAXTSIZ can't be larger than 32M, otherwise the compiler
* would have to be changed to not generate "bl" instructions.
*/
#define MAXTSIZ (16*1024*1024) /* max text size */
#define MAXTSIZ (64*1024*1024) /* max text size */
#ifndef DFLDSIZ
#define DFLDSIZ (128*1024*1024) /* initial data size limit */
#endif
#ifndef MAXDSIZ
#define MAXDSIZ (512*1024*1024) /* max data size */
#define MAXDSIZ (1024*1024*1024) /* max data size */
#endif
#ifndef DFLSSIZ
#define DFLSSIZ (2*1024*1024) /* initial stack size limit */
#endif
#ifndef MAXSSIZ
#define MAXSSIZ (8*1024*1024) /* max stack size */
#define MAXSSIZ (32*1024*1024) /* max stack size */
#endif
/*
* While the ARM architecture defines Section mappings, large pages,
* and small pages, the standard page size is (and will always be) 4K.
*/
#define PAGE_SHIFT 12
#define PAGE_SHIFT PGSHIFT
#define PAGE_SIZE (1 << PAGE_SHIFT)
#define PAGE_MASK (PAGE_SIZE - 1)

188
sys/arch/arm/include/armreg.h
View File

@@ -1,4 +1,4 @@
/* $NetBSD: armreg.h,v 1.69 2012/09/27 21:48:17 matt Exp $ */
/* $NetBSD: armreg.h,v 1.83 2013/09/07 00:32:33 matt Exp $ */
/*
* Copyright (c) 1998, 2001 Ben Harris
@@ -185,7 +185,7 @@
#define CPU_ID_ARM700 0x41007000 /* XXX This is a guess. */
#define CPU_ID_ARM710 0x41007100
#define CPU_ID_ARM7500 0x41027100
#define CPU_ID_ARM710A 0x41047100 /* inc ARM7100 */
#define CPU_ID_ARM710A 0x41067100
#define CPU_ID_ARM7500FE 0x41077100
#define CPU_ID_ARM710T 0x41807100
#define CPU_ID_ARM720T 0x41807200
@@ -211,6 +211,7 @@
#define CPU_ID_ARM1176JZS 0x410fb760
#define CPU_ID_ARM11_P(n) ((n & 0xff07f000) == 0x4107b000)
#define CPU_ID_CORTEXA5R0 0x410fc050
#define CPU_ID_CORTEXA7R0 0x410fc070
#define CPU_ID_CORTEXA8R1 0x411fc080
#define CPU_ID_CORTEXA8R2 0x412fc080
#define CPU_ID_CORTEXA8R3 0x413fc080
@@ -220,8 +221,11 @@
#define CPU_ID_CORTEXA15R2 0x412fc0f0
#define CPU_ID_CORTEXA15R3 0x413fc0f0
#define CPU_ID_CORTEX_P(n) ((n & 0xff0ff000) == 0x410fc000)
#define CPU_ID_CORTEX_A5_P(n) ((n & 0xff0ff0f0) == 0x410fc050)
#define CPU_ID_CORTEX_A7_P(n) ((n & 0xff0ff0f0) == 0x410fc070)
#define CPU_ID_CORTEX_A8_P(n) ((n & 0xff0ff0f0) == 0x410fc080)
#define CPU_ID_CORTEX_A9_P(n) ((n & 0xff0ff0f0) == 0x410fc090)
#define CPU_ID_CORTEX_A15_P(n) ((n & 0xff0ff0f0) == 0x410fc0f0)
#define CPU_ID_SA110 0x4401a100
#define CPU_ID_SA1100 0x4401a110
#define CPU_ID_TI925T 0x54029250
@@ -249,6 +253,39 @@
#define CPU_ID_IXP425_533 0x690541c0
#define CPU_ID_IXP425_400 0x690541d0
#define CPU_ID_IXP425_266 0x690541f0
#define CPU_ID_MV88SV58XX_P(n) ((n & 0xff0fff00) == 0x560f5800)
#define CPU_ID_MV88SV581X_V6 0x560f5810 /* Marvell Sheeva 88SV581x v6 Core */
#define CPU_ID_MV88SV581X_V7 0x561f5810 /* Marvell Sheeva 88SV581x v7 Core */
#define CPU_ID_MV88SV584X_V6 0x561f5840 /* Marvell Sheeva 88SV584x v6 Core */
#define CPU_ID_MV88SV584X_V7 0x562f5840 /* Marvell Sheeva 88SV584x v7 Core */
/* Marvell's CPUIDs with ARM ID in implementor field */
#define CPU_ID_ARM_88SV581X_V6 0x410fb760 /* Marvell Sheeva 88SV581x v6 Core */
#define CPU_ID_ARM_88SV581X_V7 0x413fc080 /* Marvell Sheeva 88SV581x v7 Core */
#define CPU_ID_ARM_88SV584X_V6 0x410fb020 /* Marvell Sheeva 88SV584x v6 Core */
/* CPUID registers */
#define ARM_PFR0_THUMBEE_MASK 0x0000f000
#define ARM_PFR1_GTIMER_MASK 0x000f0000
#define ARM_PFR1_VIRT_MASK 0x0000f000
#define ARM_PFR1_SEC_MASK 0x000000f0
/* Media and VFP Feature registers */
#define ARM_MVFR0_ROUNDING_MASK 0xf0000000
#define ARM_MVFR0_SHORTVEC_MASK 0x0f000000
#define ARM_MVFR0_SQRT_MASK 0x00f00000
#define ARM_MVFR0_DIVIDE_MASK 0x000f0000
#define ARM_MVFR0_EXCEPT_MASK 0x0000f000
#define ARM_MVFR0_DFLOAT_MASK 0x00000f00
#define ARM_MVFR0_SFLOAT_MASK 0x000000f0
#define ARM_MVFR0_ASIMD_MASK 0x0000000f
#define ARM_MVFR1_ASIMD_FMACS_MASK 0xf0000000
#define ARM_MVFR1_VFP_HPFP_MASK 0x0f000000
#define ARM_MVFR1_ASIMD_HPFP_MASK 0x00f00000
#define ARM_MVFR1_ASIMD_SPFP_MASK 0x000f0000
#define ARM_MVFR1_ASIMD_INT_MASK 0x0000f000
#define ARM_MVFR1_ASIMD_LDST_MASK 0x00000f00
#define ARM_MVFR1_D_NAN_MASK 0x000000f0
#define ARM_MVFR1_FTZ_MASK 0x0000000f
/* ARM3-specific coprocessor 15 registers */
#define ARM3_CP15_FLUSH 1
@@ -386,6 +423,9 @@
#define MPCORE_AUXCTL_EX 0x00000010 /* exclusive L1/L2 cache */
#define MPCORE_AUXCTL_SA 0x00000020 /* SMP/AMP */
/* Marvell PJ4B Auxillary Control Register */
#define PJ4B_AUXCTL_SMPNAMP 0x00000040 /* SMP/AMP */
/* Cortex-A9 Auxiliary Control Register (CP15 register 1, opcode 1) */
#define CORTEXA9_AUXCTL_FW 0x00000001 /* Cache and TLB updates broadcast */
#define CORTEXA9_AUXCTL_L2_PLD 0x00000002 /* Prefetch hint enable */
@@ -452,6 +492,19 @@
#define CPU_CSSR_L1 0x00000000
#define CPU_CSSR_InD 0x00000001
/* ARMv7A CP15 Global Timer definitions */
#define CNTKCTL_PL0PTEN 0x00000200 /* PL0 Physical Timer Enable */
#define CNTKCTL_PL0VTEN 0x00000100 /* PL0 Virtual Timer Enable */
#define CNTKCTL_EVNTI 0x000000f0 /* CNTVCT Event Bit Select */
#define CNTKCTL_EVNTDIR 0x00000008 /* CNTVCT Event Dir (1->0) */
#define CNTKCTL_EVNTEN 0x00000004 /* CNTVCT Event Enable */
#define CNTKCTL_PL0PCTEN 0x00000200 /* PL0 Physical Counter Enable */
#define CNTKCTL_PL0VCTEN 0x00000100 /* PL0 Virtual Counter Enable */
#define CNT_CTL_ISTATUS 0x00000004 /* Timer is asserted */
#define CNT_CTL_IMASK 0x00000002 /* Timer output is masked */
#define CNT_CTL_ENABLE 0x00000001 /* Timer is enabled */
/* Fault status register definitions */
#define FAULT_TYPE_MASK 0x0f
@@ -550,7 +603,45 @@
#define CORTEX_CNTENC_C __BIT(31) /* Disables the cycle counter */
#define CORTEX_CNTOFL_C __BIT(31) /* Cycle counter overflow flag */
#if !defined(__ASSEMBLER__)
/* Translate Table Base Control Register */
#define TTBCR_S_EAE __BIT(31) // Extended Address Extension
#define TTBCR_S_PD1 __BIT(5) // Don't use TTBR1
#define TTBCR_S_PD0 __BIT(4) // Don't use TTBR0
#define TTBCR_S_N __BITS(2,0) // Width of base address in TTB0
#define TTBCR_L_EAE __BIT(31) // Extended Address Extension
#define TTBCR_L_SH1 __BITS(29,28) // TTBR1 Shareability
#define TTBCR_L_ORGN1 __BITS(27,26) // TTBR1 Outer cacheability
#define TTBCR_L_IRGN1 __BITS(25,24) // TTBR1 inner cacheability
#define TTBCR_L_EPD1 __BIT(23) // Don't use TTBR1
#define TTBCR_L_A1 __BIT(22) // ASID is in TTBR1
#define TTBCR_L_T1SZ __BITS(18,16) // TTBR1 size offset
#define TTBCR_L_SH0 __BITS(13,12) // TTBR0 Shareability
#define TTBCR_L_ORGN0 __BITS(11,10) // TTBR0 Outer cacheability
#define TTBCR_L_IRGN0 __BITS(9,8) // TTBR0 inner cacheability
#define TTBCR_L_EPD0 __BIT(7) // Don't use TTBR0
#define TTBCR_L_T0SZ __BITS(2,0) // TTBR0 size offset
/* Defines for ARM Generic Timer */
#define ARM_CNTCTL_ENABLE __BIT(0) // Timer Enabled
#define ARM_CNTCTL_IMASK __BIT(1) // Mask Interrupt
#define ARM_CNTCTL_ISTATUS __BIT(2) // Interrupt is pending
#define ARM_CNTKCTL_PL0PTEN __BIT(9)
#define ARM_CNTKCTL_PL0VTEN __BIT(8)
#define ARM_CNTKCTL_EVNTI __BITS(7,4)
#define ARM_CNTKCTL_EVNTDIR __BIT(3)
#define ARM_CNTKCTL_EVNTEN __BIT(2)
#define ARM_CNTKCTL_PL0PCTEN __BIT(1)
#define ARM_CNTKCTL_PL0VCTEN __BIT(0)
#define ARM_CNTHCTL_EVNTI __BITS(7,4)
#define ARM_CNTHCTL_EVNTDIR __BIT(3)
#define ARM_CNTHCTL_EVNTEN __BIT(2)
#define ARM_CNTHCTL_PL1PCTEN __BIT(1)
#define ARM_CNTHCTL_PL1VCTEN __BIT(0)
#if !defined(__ASSEMBLER__) && !defined(_RUMPKERNEL)
#define ARMREG_READ_INLINE(name, __insnstring) \
static inline uint32_t armreg_##name##_read(void) \
{ \
@@ -565,7 +656,34 @@ static inline void armreg_##name##_write(uint32_t __val) \
__asm __volatile("mcr " __insnstring :: "r"(__val)); \
}
/* c0 registers */
#define ARMREG_READ64_INLINE(name, __insnstring) \
static inline uint64_t armreg_##name##_read(void) \
{ \
uint64_t __rv; \
__asm __volatile("mrrc " __insnstring : "=r"(__rv)); \
return __rv; \
}
#define ARMREG_WRITE64_INLINE(name, __insnstring) \
static inline void armreg_##name##_write(uint64_t __val) \
{ \
__asm __volatile("mcrr " __insnstring :: "r"(__val)); \
}
/* cp10 registers */
ARMREG_READ_INLINE(fpsid, "p10,7,%0,c0,c0,0") /* VFP System ID */
ARMREG_READ_INLINE(fpscr, "p10,7,%0,c1,c0,0") /* VFP Status/Control Register */
ARMREG_WRITE_INLINE(fpscr, "p10,7,%0,c1,c0,0") /* VFP Status/Control Register */
ARMREG_READ_INLINE(mvfr1, "p10,7,%0,c6,c0,0") /* Media and VFP Feature Register 1 */
ARMREG_READ_INLINE(mvfr0, "p10,7,%0,c7,c0,0") /* Media and VFP Feature Register 0 */
ARMREG_READ_INLINE(fpexc, "p10,7,%0,c8,c0,0") /* VFP Exception Register */
ARMREG_WRITE_INLINE(fpexc, "p10,7,%0,c8,c0,0") /* VFP Exception Register */
ARMREG_READ_INLINE(fpinst, "p10,7,%0,c9,c0,0") /* VFP Exception Instruction */
ARMREG_WRITE_INLINE(fpinst, "p10,7,%0,c9,c0,0") /* VFP Exception Instruction */
ARMREG_READ_INLINE(fpinst2, "p10,7,%0,c10,c0,0") /* VFP Exception Instruction 2 */
ARMREG_WRITE_INLINE(fpinst2, "p10,7,%0,c10,c0,0") /* VFP Exception Instruction 2 */
/* cp15 c0 registers */
ARMREG_READ_INLINE(midr, "p15,0,%0,c0,c0,0") /* Main ID Register */
ARMREG_READ_INLINE(ctr, "p15,0,%0,c0,c0,1") /* Cache Type Register */
ARMREG_READ_INLINE(mpidr, "p15,0,%0,c0,c0,5") /* Multiprocess Affinity Register */
@@ -585,25 +703,27 @@ ARMREG_READ_INLINE(ccsidr, "p15,1,%0,c0,c0,0") /* Cache Size ID Register */
ARMREG_READ_INLINE(clidr, "p15,1,%0,c0,c0,1") /* Cache Level ID Register */
ARMREG_READ_INLINE(csselr, "p15,2,%0,c0,c0,0") /* Cache Size Selection Register */
ARMREG_WRITE_INLINE(csselr, "p15,2,%0,c0,c0,0") /* Cache Size Selection Register */
/* c1 registers */
/* cp15 c1 registers */
ARMREG_READ_INLINE(sctrl, "p15,0,%0,c1,c0,0") /* System Control Register */
ARMREG_WRITE_INLINE(sctrl, "p15,0,%0,c1,c0,0") /* System Control Register */
ARMREG_READ_INLINE(auxctl, "p15,0,%0,c1,c0,1") /* Auxiliary Control Register */
ARMREG_WRITE_INLINE(auxctl, "p15,0,%0,c1,c0,1") /* Auxiliary Control Register */
ARMREG_READ_INLINE(cpacr, "p15,0,%0,c1,c0,2") /* Co-Processor Access Control Register */
ARMREG_WRITE_INLINE(cpacr, "p15,0,%0,c1,c0,2") /* Co-Processor Access Control Register */
/* c2 registers */
/* cp15 c2 registers */
ARMREG_READ_INLINE(ttbr, "p15,0,%0,c2,c0,0") /* Translation Table Base Register 0 */
ARMREG_WRITE_INLINE(ttbr, "p15,0,%0,c2,c0,0") /* Translation Table Base Register 0 */
ARMREG_READ_INLINE(ttbr1, "p15,0,%0,c2,c0,1") /* Translation Table Base Register 1 */
ARMREG_WRITE_INLINE(ttbr1, "p15,0,%0,c2,c0,1") /* Translation Table Base Register 1 */
ARMREG_READ_INLINE(ttbcr, "p15,0,%0,c2,c0,2") /* Translation Table Base Register */
ARMREG_WRITE_INLINE(ttbcr, "p15,0,%0,c2,c0,2") /* Translation Table Base Register */
/* c5 registers */
/* cp15 c5 registers */
ARMREG_READ_INLINE(dfsr, "p15,0,%0,c5,c0,0") /* Data Fault Status Register */
ARMREG_READ_INLINE(ifsr, "p15,0,%0,c5,c0,1") /* Instruction Fault Status Register */
/* c6 registers */
/* cp15 c6 registers */
ARMREG_READ_INLINE(dfar, "p15,0,%0,c6,c0,0") /* Data Fault Address Register */
ARMREG_READ_INLINE(ifar, "p15,0,%0,c6,c0,2") /* Instruction Fault Address Register */
/* c7 registers */
/* cp15 c7 registers */
ARMREG_WRITE_INLINE(icialluis, "p15,0,%0,c7,c1,0") /* Instruction Inv All (IS) */
ARMREG_WRITE_INLINE(bpiallis, "p15,0,%0,c7,c1,6") /* Branch Invalidate All (IS) */
ARMREG_READ_INLINE(par, "p15,0,%0,c7,c4,0") /* Physical Address Register */
@@ -621,7 +741,22 @@ ARMREG_WRITE_INLINE(dmb, "p15,0,%0,c7,c10,5") /* Data Memory Barrier */
ARMREG_WRITE_INLINE(dccmvau, "p15,0,%0,c7,c14,1") /* Data Clean MVA to PoU */
ARMREG_WRITE_INLINE(dccimvac, "p15,0,%0,c7,c14,1") /* Data Clean&Inv MVA to PoC */
ARMREG_WRITE_INLINE(dccisw, "p15,0,%0,c7,c14,2") /* Data Clean&Inv Set/Way */
/* c9 registers */
/* cp15 c8 registers */
ARMREG_WRITE_INLINE(tlbiallis, "p15,0,%0,c8,c3,0") /* Invalidate entire unified TLB, inner shareable */
ARMREG_WRITE_INLINE(tlbimvais, "p15,0,%0,c8,c3,1") /* Invalidate unified TLB by MVA, inner shareable */
ARMREG_WRITE_INLINE(tlbiasidis, "p15,0,%0,c8,c3,2") /* Invalidate unified TLB by ASID, inner shareable */
ARMREG_WRITE_INLINE(tlbimvaais, "p15,0,%0,c8,c3,3") /* Invalidate unified TLB by MVA, all ASID, inner shareable */
ARMREG_WRITE_INLINE(itlbiall, "p15,0,%0,c8,c5,0") /* Invalidate entire instruction TLB */
ARMREG_WRITE_INLINE(itlbimva, "p15,0,%0,c8,c5,1") /* Invalidate instruction TLB by MVA */
ARMREG_WRITE_INLINE(itlbiasid, "p15,0,%0,c8,c5,2") /* Invalidate instruction TLB by ASID */
ARMREG_WRITE_INLINE(dtlbiall, "p15,0,%0,c8,c6,0") /* Invalidate entire data TLB */
ARMREG_WRITE_INLINE(dtlbimva, "p15,0,%0,c8,c6,1") /* Invalidate data TLB by MVA */
ARMREG_WRITE_INLINE(dtlbiasid, "p15,0,%0,c8,c6,2") /* Invalidate data TLB by ASID */
ARMREG_WRITE_INLINE(tlbiall, "p15,0,%0,c8,c7,0") /* Invalidate entire unified TLB */
ARMREG_WRITE_INLINE(tlbimva, "p15,0,%0,c8,c7,1") /* Invalidate unified TLB by MVA */
ARMREG_WRITE_INLINE(tlbiasid, "p15,0,%0,c8,c7,2") /* Invalidate unified TLB by ASID */
ARMREG_WRITE_INLINE(tlbimvaa, "p15,0,%0,c8,c7,3") /* Invalidate unified TLB by MVA, all ASID */
/* cp15 c9 registers */
ARMREG_READ_INLINE(pmcr, "p15,0,%0,c9,c12,0") /* PMC Control Register */
ARMREG_WRITE_INLINE(pmcr, "p15,0,%0,c9,c12,0") /* PMC Control Register */
ARMREG_READ_INLINE(pmcntenset, "p15,0,%0,c9,c12,1") /* PMC Count Enable Set */
@@ -632,11 +767,40 @@ ARMREG_READ_INLINE(pmovsr, "p15,0,%0,c9,c12,3") /* PMC Overflow Flag Status */
ARMREG_WRITE_INLINE(pmovsr, "p15,0,%0,c9,c12,3") /* PMC Overflow Flag Status */
ARMREG_READ_INLINE(pmccntr, "p15,0,%0,c9,c13,0") /* PMC Cycle Counter */
ARMREG_WRITE_INLINE(pmccntr, "p15,0,%0,c9,c13,0") /* PMC Cycle Counter */
/* c13 registers */
ARMREG_READ_INLINE(pmuserenr, "p15,0,%0,c9,c14,0") /* PMC User Enable */
ARMREG_WRITE_INLINE(pmuserenr, "p15,0,%0,c9,c14,0") /* PMC User Enable */
/* cp15 c13 registers */
ARMREG_READ_INLINE(contextidr, "p15,0,%0,c13,c0,1") /* Context ID Register */
ARMREG_WRITE_INLINE(contextidr, "p15,0,%0,c13,c0,1") /* Context ID Register */
ARMREG_READ_INLINE(tpidrprw, "p15,0,%0,c13,c0,4") /* PL1 only Thread ID Register */
ARMREG_WRITE_INLINE(tpidrprw, "p15,0,%0,c13,c0,4") /* PL1 only Thread ID Register */
/* cp14 c12 registers */
ARMREG_READ_INLINE(vbar, "p15,0,%0,c12,c0,0") /* Vector Base Address Register */
ARMREG_WRITE_INLINE(vbar, "p15,0,%0,c12,c0,0") /* Vector Base Address Register */
/* cp15 c14 registers */
/* cp15 Global Timer Registers */
ARMREG_READ_INLINE(cnt_frq, "p15,0,%0,c14,c0,0") /* Counter Frequency Register */
ARMREG_WRITE_INLINE(cnt_frq, "p15,0,%0,c14,c0,0") /* Counter Frequency Register */
ARMREG_READ_INLINE(cntk_ctl, "p15,0,%0,c14,c1,0") /* Timer PL1 Control Register */
ARMREG_WRITE_INLINE(cntk_ctl, "p15,0,%0,c14,c1,0") /* Timer PL1 Control Register */
ARMREG_READ_INLINE(cntp_tval, "p15,0,%0,c14,c2,0") /* PL1 Physical TimerValue Register */
ARMREG_WRITE_INLINE(cntp_tval, "p15,0,%0,c14,c2,0") /* PL1 Physical TimerValue Register */
ARMREG_READ_INLINE(cntp_ctl, "p15,0,%0,c14,c2,1") /* PL1 Physical Timer Control Register */
ARMREG_WRITE_INLINE(cntp_ctl, "p15,0,%0,c14,c2,1") /* PL1 Physical Timer Control Register */
ARMREG_READ_INLINE(cntv_tval, "p15,0,%0,c14,c3,0") /* Virtual TimerValue Register */
ARMREG_WRITE_INLINE(cntv_tval, "p15,0,%0,c14,c3,0") /* Virtual TimerValue Register */
ARMREG_READ_INLINE(cntv_ctl, "p15,0,%0,c14,c3,1") /* Virtual Timer Control Register */
ARMREG_WRITE_INLINE(cntv_ctl, "p15,0,%0,c14,c3,1") /* Virtual Timer Control Register */
ARMREG_READ64_INLINE(cntp_ct, "p15,0,%Q0,%R0,c14") /* Physical Count Register */
ARMREG_WRITE64_INLINE(cntp_ct, "p15,0,%Q0,%R0,c14") /* Physical Count Register */
ARMREG_READ64_INLINE(cntv_ct, "p15,1,%Q0,%R0,c14") /* Virtual Count Register */
ARMREG_WRITE64_INLINE(cntv_ct, "p15,1,%Q0,%R0,c14") /* Virtual Count Register */
ARMREG_READ64_INLINE(cntp_cval, "p15,2,%Q0,%R0,c14") /* PL1 Physical Timer CompareValue Register */
ARMREG_WRITE64_INLINE(cntp_cval, "p15,2,%Q0,%R0,c14") /* PL1 Physical Timer CompareValue Register */
ARMREG_READ64_INLINE(cntv_cval, "p15,3,%Q0,%R0,c14") /* PL1 Virtual Timer CompareValue Register */
ARMREG_WRITE64_INLINE(cntv_cval, "p15,3,%Q0,%R0,c14") /* PL1 Virtual Timer CompareValue Register */
/* cp15 c15 registers */
ARMREG_READ_INLINE(cbar, "p15,4,%0,c15,c0,0") /* Configuration Base Address Register */
/* c13 registers */
ARMREG_READ_INLINE(pmcrv6, "p15,0,%0,c15,c12,0") /* PMC Control Register (armv6) */
ARMREG_WRITE_INLINE(pmcrv6, "p15,0,%0,c15,c12,0") /* PMC Control Register (armv6) */
ARMREG_READ_INLINE(pmccntrv6, "p15,0,%0,c15,c12,1") /* PMC Cycle Counter (armv6) */

111
sys/arch/arm/include/asm.h
View File

@@ -1,4 +1,4 @@
/* $NetBSD: asm.h,v 1.16 2012/09/01 14:46:25 matt Exp $ */
/* $NetBSD: asm.h,v 1.25 2013/11/30 20:11:11 matt Exp $ */
/*
* Copyright (c) 1990 The Regents of the University of California.
@@ -39,6 +39,14 @@
#include <arm/cdefs.h>
.syntax unified
#ifdef __thumb__
#define THUMB_INSN(n) n
#else
#define THUMB_INSN(n)
#endif
#define __BIT(n) (1 << (n))
#define __BITS(hi,lo) ((~((~0)<<((hi)+1)))&((~0)<<(lo)))
@@ -54,9 +62,12 @@
#endif
#ifndef _ALIGN_TEXT
# define _ALIGN_TEXT .align 0
# define _ALIGN_TEXT .align 2
#endif
#ifndef _TEXT_SECTION
#define _TEXT_SECTION .text
#endif
/*
* gas/arm uses @ as a single comment character and thus cannot be used here
* Instead it recognised the # instead of an @ symbols in .type directives
@@ -65,12 +76,16 @@
*/
#define _ASM_TYPE_FUNCTION %function
#define _ASM_TYPE_OBJECT %object
#define _THUMB_ENTRY(x) \
_TEXT_SECTION; _ALIGN_TEXT; .globl x; .type x,_ASM_TYPE_FUNCTION; \
.thumb_func; .code 16; x:
#define _ARM_ENTRY(x) \
_TEXT_SECTION; _ALIGN_TEXT; .globl x; .type x,_ASM_TYPE_FUNCTION; \
.code 32; x:
#ifdef __thumb__
#define _ENTRY(x) \
.text; _ALIGN_TEXT; .globl x; .type x,_ASM_TYPE_FUNCTION; .thumb_func; x:
#define _ENTRY(x) _THUMB_ENTRY(x)
#else
#define _ENTRY(x) \
.text; _ALIGN_TEXT; .globl x; .type x,_ASM_TYPE_FUNCTION; x:
#define _ENTRY(x) _ARM_ENTRY(x)
#endif
#define _END(x) .size x,.-x
@@ -81,37 +96,43 @@
# define _PROF_PROLOGUE
#endif
#define ENTRY(y) _ENTRY(_C_LABEL(y)); _PROF_PROLOGUE
#define ENTRY_NP(y) _ENTRY(_C_LABEL(y))
#define END(y) _END(_C_LABEL(y))
#define ASENTRY(y) _ENTRY(_ASM_LABEL(y)); _PROF_PROLOGUE
#define ASENTRY_NP(y) _ENTRY(_ASM_LABEL(y))
#define ASEND(y) _END(_ASM_LABEL(y))
#define ENTRY(y) _ENTRY(_C_LABEL(y)); _PROF_PROLOGUE
#define ENTRY_NP(y) _ENTRY(_C_LABEL(y))
#define END(y) _END(_C_LABEL(y))
#define ARM_ENTRY(y) _ARM_ENTRY(_C_LABEL(y)); _PROF_PROLOGUE
#define ARM_ENTRY_NP(y) _ARM_ENTRY(_C_LABEL(y))
#define THUMB_ENTRY(y) _THUMB_ENTRY(_C_LABEL(y)); _PROF_PROLOGUE
#define THUMB_ENTRY_NP(y) _THUMB_ENTRY(_C_LABEL(y))
#define END(y) _END(_C_LABEL(y))
#define ASENTRY(y) _ENTRY(_ASM_LABEL(y)); _PROF_PROLOGUE
#define ASENTRY_NP(y) _ENTRY(_ASM_LABEL(y))
#define ASEND(y) _END(_ASM_LABEL(y))
#define ARM_ASENTRY(y) _ARM_ENTRY(_ASM_LABEL(y)); _PROF_PROLOGUE
#define ARM_ASENTRY_NP(y) _ARM_ENTRY(_ASM_LABEL(y))
#define THUMB_ASENTRY(y) _THUMB_ENTRY(_ASM_LABEL(y)); _PROF_PROLOGUE
#define THUMB_ASENTRY_NP(y) _THUMB_ENTRY(_ASM_LABEL(y))
#define ASMSTR .asciz
#if defined(PIC)
#ifdef __thumb__
#ifdef __PIC__
#define REL_SYM(a, b) ((a) - (b))
#define PLT_SYM(x) x
#define GOT_SYM(x) PIC_SYM(x, GOTOFF)
#define GOT_GET(x,got,sym) \
ldr x, sym; \
add x, got; \
ldr x, [x]
#else
#define PLT_SYM(x) PIC_SYM(x, PLT)
#define GOT_SYM(x) PIC_SYM(x, GOT)
#define GOT_GET(x,got,sym) \
ldr x, sym; \
ldr x, [x, got]
#endif /* __thumb__ */
#define GOT_INIT(got,gotsym,pclabel) \
ldr got, gotsym; \
add got, got, pc; \
pclabel:
pclabel: add got, got, pc
#ifdef __thumb__
#define GOT_INITSYM(gotsym,pclabel) \
gotsym: .word _C_LABEL(_GLOBAL_OFFSET_TABLE_) + (. - (pclabel+4))
.align 0; \
gotsym: .word _C_LABEL(_GLOBAL_OFFSET_TABLE_) - (pclabel+4)
#else
#define GOT_INITSYM(gotsym,pclabel) \
.align 0; \
gotsym: .word _C_LABEL(_GLOBAL_OFFSET_TABLE_) - (pclabel+8)
#endif
#ifdef __STDC__
#define PIC_SYM(x,y) x ## ( ## y ## )
@@ -120,6 +141,7 @@
#endif
#else
#define REL_SYM(a, b) (a)
#define PLT_SYM(x) x
#define GOT_SYM(x) x
#define GOT_GET(x,got,sym) \
@@ -127,7 +149,7 @@
#define GOT_INIT(got,gotsym,pclabel)
#define GOT_INITSYM(gotsym,pclabel)
#define PIC_SYM(x,y) x
#endif /* PIC */
#endif /* __PIC__ */
#define RCSID(x) .pushsection ".ident"; .asciz x; .popsection
@@ -170,19 +192,46 @@
#if defined (_ARM_ARCH_4T)
# define RET bx lr
# define RETc(c) __CONCAT(bx,c) lr
# define RETr(r) bx r
# if defined(__thumb__)
# if defined(_ARM_ARCH_7)
# define RETc(c) it c; __CONCAT(bx,c) lr
# endif
# else
# define RETc(c) __CONCAT(bx,c) lr
# endif
#else
# define RET mov pc, lr
# define RETr(r) mov pc, r
# define RETc(c) __CONCAT(mov,c) pc, lr
#endif
#ifdef _ARM_ARCH_7
#define KMODTRAMPOLINE(n) \
_ENTRY(__wrap_ ## n) \
movw ip, #:lower16:n; \
movt ip, #:upper16:n; \
bx ip
#elif defined(_ARM_ARCH_4T)
#define KMODTRAMPOLINE(n) \
_ENTRY(__wrap_ ## n) \
ldr ip, [pc]; \
bx ip; \
.word n
#else
#define KMODTRAMPOLINE(n) \
_ENTRY(__wrap_ ## n) \
ldr pc, [pc, #-4]; \
.word n
#endif
#if defined(__minix)
#define IMPORT(sym) \
.extern _C_LABEL(sym)
#define _LABEL(x) \
.globl x; x:
#define LABEL(y) _LABEL(_C_LABEL(y))
#define IMPORT(sym) \
.extern _C_LABEL(sym)
#endif /* defined(__minix) */
#endif /* !_ARM_ASM_H_ */

124
sys/arch/arm/include/bus_defs.h
View File

@@ -1,4 +1,4 @@
/* $NetBSD: bus_defs.h,v 1.2 2012/09/18 05:47:27 matt Exp $ */
/* $NetBSD: bus_defs.h,v 1.9 2013/02/16 06:49:59 matt Exp $ */
/*-
* Copyright (c) 1996, 1997, 1998, 2001 The NetBSD Foundation, Inc.
@@ -74,12 +74,18 @@
typedef u_long bus_addr_t;
typedef u_long bus_size_t;
#define PRIxBUSADDR "lx"
#define PRIxBUSSIZE "lx"
#define PRIuBUSSIZE "lu"
/*
* Access methods for bus space.
*/
typedef struct bus_space *bus_space_tag_t;
typedef u_long bus_space_handle_t;
#define PRIxBSH "lx"
/*
* int bus_space_map(bus_space_tag_t t, bus_addr_t addr,
* bus_size_t size, int flags, bus_space_handle_t *bshp);
@@ -121,84 +127,84 @@ struct bus_space {
bus_size_t, bus_size_t, int);
/* read (single) */
u_int8_t (*bs_r_1)(void *, bus_space_handle_t,
uint8_t (*bs_r_1)(void *, bus_space_handle_t,
bus_size_t);
u_int16_t (*bs_r_2)(void *, bus_space_handle_t,
uint16_t (*bs_r_2)(void *, bus_space_handle_t,
bus_size_t);
u_int32_t (*bs_r_4)(void *, bus_space_handle_t,
uint32_t (*bs_r_4)(void *, bus_space_handle_t,
bus_size_t);
u_int64_t (*bs_r_8)(void *, bus_space_handle_t,
uint64_t (*bs_r_8)(void *, bus_space_handle_t,
bus_size_t);
/* read multiple */
void (*bs_rm_1)(void *, bus_space_handle_t,
bus_size_t, u_int8_t *, bus_size_t);
bus_size_t, uint8_t *, bus_size_t);
void (*bs_rm_2)(void *, bus_space_handle_t,
bus_size_t, u_int16_t *, bus_size_t);
bus_size_t, uint16_t *, bus_size_t);
void (*bs_rm_4)(void *, bus_space_handle_t,
bus_size_t, u_int32_t *, bus_size_t);
bus_size_t, uint32_t *, bus_size_t);
void (*bs_rm_8)(void *, bus_space_handle_t,
bus_size_t, u_int64_t *, bus_size_t);
bus_size_t, uint64_t *, bus_size_t);
/* read region */
void (*bs_rr_1)(void *, bus_space_handle_t,
bus_size_t, u_int8_t *, bus_size_t);
bus_size_t, uint8_t *, bus_size_t);
void (*bs_rr_2)(void *, bus_space_handle_t,
bus_size_t, u_int16_t *, bus_size_t);
bus_size_t, uint16_t *, bus_size_t);
void (*bs_rr_4)(void *, bus_space_handle_t,
bus_size_t, u_int32_t *, bus_size_t);
bus_size_t, uint32_t *, bus_size_t);
void (*bs_rr_8)(void *, bus_space_handle_t,
bus_size_t, u_int64_t *, bus_size_t);
bus_size_t, uint64_t *, bus_size_t);
/* write (single) */
void (*bs_w_1)(void *, bus_space_handle_t,
bus_size_t, u_int8_t);
bus_size_t, uint8_t);
void (*bs_w_2)(void *, bus_space_handle_t,
bus_size_t, u_int16_t);
bus_size_t, uint16_t);
void (*bs_w_4)(void *, bus_space_handle_t,
bus_size_t, u_int32_t);
bus_size_t, uint32_t);
void (*bs_w_8)(void *, bus_space_handle_t,
bus_size_t, u_int64_t);
bus_size_t, uint64_t);
/* write multiple */
void (*bs_wm_1)(void *, bus_space_handle_t,
bus_size_t, const u_int8_t *, bus_size_t);
bus_size_t, const uint8_t *, bus_size_t);
void (*bs_wm_2)(void *, bus_space_handle_t,
bus_size_t, const u_int16_t *, bus_size_t);
bus_size_t, const uint16_t *, bus_size_t);
void (*bs_wm_4)(void *, bus_space_handle_t,
bus_size_t, const u_int32_t *, bus_size_t);
bus_size_t, const uint32_t *, bus_size_t);
void (*bs_wm_8)(void *, bus_space_handle_t,
bus_size_t, const u_int64_t *, bus_size_t);
bus_size_t, const uint64_t *, bus_size_t);
/* write region */
void (*bs_wr_1)(void *, bus_space_handle_t,
bus_size_t, const u_int8_t *, bus_size_t);
bus_size_t, const uint8_t *, bus_size_t);
void (*bs_wr_2)(void *, bus_space_handle_t,
bus_size_t, const u_int16_t *, bus_size_t);
bus_size_t, const uint16_t *, bus_size_t);
void (*bs_wr_4)(void *, bus_space_handle_t,
bus_size_t, const u_int32_t *, bus_size_t);
bus_size_t, const uint32_t *, bus_size_t);
void (*bs_wr_8)(void *, bus_space_handle_t,
bus_size_t, const u_int64_t *, bus_size_t);
bus_size_t, const uint64_t *, bus_size_t);
/* set multiple */
void (*bs_sm_1)(void *, bus_space_handle_t,
bus_size_t, u_int8_t, bus_size_t);
bus_size_t, uint8_t, bus_size_t);
void (*bs_sm_2)(void *, bus_space_handle_t,
bus_size_t, u_int16_t, bus_size_t);
bus_size_t, uint16_t, bus_size_t);
void (*bs_sm_4)(void *, bus_space_handle_t,
bus_size_t, u_int32_t, bus_size_t);
bus_size_t, uint32_t, bus_size_t);
void (*bs_sm_8)(void *, bus_space_handle_t,
bus_size_t, u_int64_t, bus_size_t);
bus_size_t, uint64_t, bus_size_t);
/* set region */
void (*bs_sr_1)(void *, bus_space_handle_t,
bus_size_t, u_int8_t, bus_size_t);
bus_size_t, uint8_t, bus_size_t);
void (*bs_sr_2)(void *, bus_space_handle_t,
bus_size_t, u_int16_t, bus_size_t);
bus_size_t, uint16_t, bus_size_t);
void (*bs_sr_4)(void *, bus_space_handle_t,
bus_size_t, u_int32_t, bus_size_t);
bus_size_t, uint32_t, bus_size_t);
void (*bs_sr_8)(void *, bus_space_handle_t,
bus_size_t, u_int64_t, bus_size_t);
bus_size_t, uint64_t, bus_size_t);
/* copy */
void (*bs_c_1)(void *, bus_space_handle_t, bus_size_t,
@@ -212,64 +218,64 @@ struct bus_space {
#ifdef __BUS_SPACE_HAS_STREAM_METHODS
/* read stream (single) */
u_int8_t (*bs_r_1_s)(void *, bus_space_handle_t,
uint8_t (*bs_r_1_s)(void *, bus_space_handle_t,
bus_size_t);
u_int16_t (*bs_r_2_s)(void *, bus_space_handle_t,
uint16_t (*bs_r_2_s)(void *, bus_space_handle_t,
bus_size_t);
u_int32_t (*bs_r_4_s)(void *, bus_space_handle_t,
uint32_t (*bs_r_4_s)(void *, bus_space_handle_t,
bus_size_t);
u_int64_t (*bs_r_8_s)(void *, bus_space_handle_t,
uint64_t (*bs_r_8_s)(void *, bus_space_handle_t,
bus_size_t);
/* read multiple stream */
void (*bs_rm_1_s)(void *, bus_space_handle_t,
bus_size_t, u_int8_t *, bus_size_t);
bus_size_t, uint8_t *, bus_size_t);
void (*bs_rm_2_s)(void *, bus_space_handle_t,
bus_size_t, u_int16_t *, bus_size_t);
bus_size_t, uint16_t *, bus_size_t);
void (*bs_rm_4_s)(void *, bus_space_handle_t,
bus_size_t, u_int32_t *, bus_size_t);
bus_size_t, uint32_t *, bus_size_t);
void (*bs_rm_8_s)(void *, bus_space_handle_t,
bus_size_t, u_int64_t *, bus_size_t);
bus_size_t, uint64_t *, bus_size_t);
/* read region stream */
void (*bs_rr_1_s)(void *, bus_space_handle_t,
bus_size_t, u_int8_t *, bus_size_t);
bus_size_t, uint8_t *, bus_size_t);
void (*bs_rr_2_s)(void *, bus_space_handle_t,
bus_size_t, u_int16_t *, bus_size_t);
bus_size_t, uint16_t *, bus_size_t);
void (*bs_rr_4_s)(void *, bus_space_handle_t,
bus_size_t, u_int32_t *, bus_size_t);
bus_size_t, uint32_t *, bus_size_t);
void (*bs_rr_8_s)(void *, bus_space_handle_t,
bus_size_t, u_int64_t *, bus_size_t);
bus_size_t, uint64_t *, bus_size_t);
/* write stream (single) */
void (*bs_w_1_s)(void *, bus_space_handle_t,
bus_size_t, u_int8_t);
bus_size_t, uint8_t);
void (*bs_w_2_s)(void *, bus_space_handle_t,
bus_size_t, u_int16_t);
bus_size_t, uint16_t);
void (*bs_w_4_s)(void *, bus_space_handle_t,
bus_size_t, u_int32_t);
bus_size_t, uint32_t);
void (*bs_w_8_s)(void *, bus_space_handle_t,
bus_size_t, u_int64_t);
bus_size_t, uint64_t);
/* write multiple stream */
void (*bs_wm_1_s)(void *, bus_space_handle_t,
bus_size_t, const u_int8_t *, bus_size_t);
bus_size_t, const uint8_t *, bus_size_t);
void (*bs_wm_2_s)(void *, bus_space_handle_t,
bus_size_t, const u_int16_t *, bus_size_t);
bus_size_t, const uint16_t *, bus_size_t);
void (*bs_wm_4_s)(void *, bus_space_handle_t,
bus_size_t, const u_int32_t *, bus_size_t);
bus_size_t, const uint32_t *, bus_size_t);
void (*bs_wm_8_s)(void *, bus_space_handle_t,
bus_size_t, const u_int64_t *, bus_size_t);
bus_size_t, const uint64_t *, bus_size_t);
/* write region stream */
void (*bs_wr_1_s)(void *, bus_space_handle_t,
bus_size_t, const u_int8_t *, bus_size_t);
bus_size_t, const uint8_t *, bus_size_t);
void (*bs_wr_2_s)(void *, bus_space_handle_t,
bus_size_t, const u_int16_t *, bus_size_t);
bus_size_t, const uint16_t *, bus_size_t);
void (*bs_wr_4_s)(void *, bus_space_handle_t,
bus_size_t, const u_int32_t *, bus_size_t);
bus_size_t, const uint32_t *, bus_size_t);
void (*bs_wr_8_s)(void *, bus_space_handle_t,
bus_size_t, const u_int64_t *, bus_size_t);
bus_size_t, const uint64_t *, bus_size_t);
#endif /* __BUS_SPACE_HAS_STREAM_METHODS */
};
@@ -300,6 +306,8 @@ struct bus_space {
* Private flags stored in the DMA map.
*/
#define _BUS_DMAMAP_COHERENT 0x10000 /* no cache flush necessary on sync */
#define _BUS_DMAMAP_IS_BOUNCING 0x20000 /* is bouncing current xfer */
#define _BUS_DMAMAP_NOALLOC 0x40000 /* don't alloc memory from this range */
/* Forwards needed by prototypes below. */
struct mbuf;
@@ -330,6 +338,7 @@ struct arm32_bus_dma_segment {
*/
bus_addr_t ds_addr; /* DMA address */
bus_size_t ds_len; /* length of transfer */
uint32_t _ds_flags; /* _BUS_DMAMAP_COHERENT */
};
typedef struct arm32_bus_dma_segment bus_dma_segment_t;
@@ -342,6 +351,7 @@ struct arm32_dma_range {
bus_addr_t dr_sysbase; /* system base address */
bus_addr_t dr_busbase; /* appears here on bus */
bus_size_t dr_len; /* length of range */
uint32_t dr_flags; /* flags for range */
};
/*

10
sys/arch/arm/include/bus_funcs.h
View File

@@ -1,4 +1,4 @@
/* $NetBSD: bus_funcs.h,v 1.3 2012/09/18 05:47:27 matt Exp $ */
/* $NetBSD: bus_funcs.h,v 1.5 2013/01/17 01:32:02 matt Exp $ */
/*-
* Copyright (c) 1996, 1997, 1998, 2001 The NetBSD Foundation, Inc.
@@ -64,6 +64,10 @@
#ifndef _ARM32_BUS_FUNCS_H_
#define _ARM32_BUS_FUNCS_H_
#ifdef _KERNEL_OPT
#include "opt_cputypes.h"
#endif
/*
* Utility macros; INTERNAL USE ONLY.
*/
@@ -587,6 +591,8 @@ struct uio;
(*(t)->_dmamap_unload)((t), (p))
#define bus_dmamap_sync(t, p, o, l, ops) \
do { \
if (((p)->_dm_flags & (_BUS_DMAMAP_COHERENT|_BUS_DMAMAP_IS_BOUNCING)) == _BUS_DMAMAP_COHERENT) \
break; \
if (((ops) & (BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE)) != 0 \
&& (t)->_dmamap_sync_pre != NULL) \
(*(t)->_dmamap_sync_pre)((t), (p), (o), (l), (ops)); \
@@ -633,7 +639,7 @@ void _bus_dmamap_unload(bus_dma_tag_t, bus_dmamap_t);
void _bus_dmamap_sync(bus_dma_tag_t, bus_dmamap_t, bus_addr_t,
bus_size_t, int);
#ifdef _ARM32_NEED_BUS_DMA_BOUNCE
#if defined(_ARM32_NEED_BUS_DMA_BOUNCE) || defined(CPU_CORTEX)
#define _BUS_DMAMAP_SYNC_FUNCS \
._dmamap_sync_pre = _bus_dmamap_sync, \
._dmamap_sync_post = _bus_dmamap_sync

7
sys/arch/arm/include/byte_swap.h
View File

@@ -1,4 +1,4 @@
/* $NetBSD: byte_swap.h,v 1.12 2012/09/05 01:03:53 matt Exp $ */
/* $NetBSD: byte_swap.h,v 1.13 2013/01/28 06:16:05 matt Exp $ */
/*-
* Copyright (c) 1997, 1999, 2002 The NetBSD Foundation, Inc.
@@ -91,8 +91,9 @@ __byte_swap_u16_variable(uint16_t v)
#ifdef _ARM_ARCH_6
if (!__builtin_constant_p(v)) {
__asm("rev16\t%0, %1" : "=r" (v) : "0" (v));
return v;
uint32_t v32 = v;
__asm("rev16\t%0, %1" : "=r" (v32) : "0" (v32));
return v32;
}
#elif !defined(__thumb__) && 0 /* gcc produces decent code for this */
if (!__builtin_constant_p(v)) {

31
sys/arch/arm/include/cdefs.h
View File

@@ -1,7 +1,7 @@
/* $NetBSD: cdefs.h,v 1.7 2012/08/05 04:13:19 matt Exp $ */
/* $NetBSD: cdefs.h,v 1.9 2013/08/17 00:21:47 matt Exp $ */
#ifndef _MACHINE_CDEFS_H_
#define _MACHINE_CDEFS_H_
#ifndef _ARM_CDEFS_H_
#define _ARM_CDEFS_H_
#if defined (__ARM_ARCH_7__) || defined (__ARM_ARCH_7A__) || \
defined (__ARM_ARCH_7R__) || defined (__ARM_ARCH_7M__) || \
@@ -9,16 +9,23 @@
#define _ARM_ARCH_7
#endif
#if defined (_ARM_ARCH_7) || defined (__ARM_ARCH_6__) || \
#if defined (_ARM_ARCH_7) || defined (__ARM_ARCH_6T2__)
#define _ARM_ARCH_T2 /* Thumb2 */
#endif
#if defined (_ARM_ARCH_T2) || defined (__ARM_ARCH_6__) || \
defined (__ARM_ARCH_6J__) || defined (__ARM_ARCH_6K__) || \
defined (__ARM_ARCH_6Z__) || defined (__ARM_ARCH_6ZK__) || \
defined (__ARM_ARCH_6T2__) || defined (__ARM_ARCH_6ZM__)
defined (__ARM_ARCH_6ZM__)
#define _ARM_ARCH_6
#endif
#if defined (_ARM_ARCH_6) || defined (__ARM_ARCH_5__) || \
defined (__ARM_ARCH_5T__) || defined (__ARM_ARCH_5TE__) || \
defined (__ARM_ARCH_5TEJ__)
#if defined (_ARM_ARCH_6) || defined (__ARM_ARCH_5T__) || \
defined (__ARM_ARCH_5TE__) || defined (__ARM_ARCH_5TEJ__)
#define _ARM_ARCH_5T
#endif
#if defined (_ARM_ARCH_6) || defined (_ARM_ARCH_5T) || defined (__ARM_ARCH_5__)
#define _ARM_ARCH_5
#endif
@@ -26,8 +33,10 @@
#define _ARM_ARCH_4T
#endif
#if defined(_ARM_ARCH_6) || defined (__ARM_ARCH_5TE__) || \
defined (__ARM_ARCH_5TEJ__)
#if defined (_ARM_ARCH_T2) || \
(!defined (__thumb__) && \
(defined (_ARM_ARCH_6) || defined (__ARM_ARCH_5TE__) || \
defined (__ARM_ARCH_5TEJ__)))
#define _ARM_ARCH_DWORD_OK
#endif
@@ -37,4 +46,4 @@
#define __ALIGNBYTES (sizeof(int) - 1)
#endif
#endif /* !_MACHINE_CDEFS_H_ */
#endif /* !_ARM_CDEFS_H_ */

3
sys/arch/arm/include/common/fenv.h Normal file
View File

@@ -0,0 +1,3 @@
/* $NetBSD: fenv.h,v 1.1 2013/05/01 12:01:55 matt Exp $ */
#include <arm/fenv.h>

164
sys/arch/arm/include/cpu.h
View File

@@ -66,75 +66,21 @@
* Kernel-only definitions
*/
#if !defined(_LKM) && defined(_KERNEL_OPT)
#if !defined(_MODULE) && defined(_KERNEL_OPT)
#include "opt_multiprocessor.h"
#include "opt_cpuoptions.h"
#include "opt_lockdebug.h"
#include "opt_cputypes.h"
#endif /* !_LKM && _KERNEL_OPT */
#include <arm/cpuconf.h>
#endif /* !_MODULE && _KERNEL_OPT */
#ifndef _LOCORE
#include <machine/frame.h>
#endif /* !_LOCORE */
#if defined(TPIDRPRW_IS_CURLWP) || defined(TPIDRPRW_IS_CURCPU)
#include <arm/armreg.h>
#endif
#ifndef _LOCORE
/* 1 == use cpu_sleep(), 0 == don't */
extern int cpu_do_powersave;
#endif
#ifdef _LOCORE
#if defined(_ARM_ARCH_6)
#define IRQdisable cpsid i
#define IRQenable cpsie i
#elif defined(__PROG32)
#define IRQdisable \
stmfd sp!, {r0} ; \
mrs r0, cpsr ; \
orr r0, r0, #(I32_bit) ; \
msr cpsr_c, r0 ; \
ldmfd sp!, {r0}
#define IRQenable \
stmfd sp!, {r0} ; \
mrs r0, cpsr ; \
bic r0, r0, #(I32_bit) ; \
msr cpsr_c, r0 ; \
ldmfd sp!, {r0}
#else
/* Not yet used in 26-bit code */
#endif
#if defined (TPIDRPRW_IS_CURCPU)
#define GET_CURCPU(rX) mrc p15, 0, rX, c13, c0, 4
#define GET_CURLWP(rX) GET_CURCPU(rX); ldr rX, [rX, #CI_CURLWP]
#elif defined (TPIDRPRW_IS_CURLWP)
#define GET_CURLWP(rX) mrc p15, 0, rX, c13, c0, 4
#define GET_CURCPU(rX) GET_CURLWP(rX); ldr rX, [rX, #L_CPU]
#elif !defined(MULTIPROCESSOR)
#define GET_CURCPU(rX) ldr rX, =_C_LABEL(cpu_info_store)
#define GET_CURLWP(rX) GET_CURCPU(rX); ldr rX, [rX, #CI_CURLWP]
#endif
#define GET_CURPCB(rX) GET_CURLWP(rX); ldr rX, [rX, #L_PCB]
#else /* !_LOCORE */
#ifdef __PROG32
#define IRQdisable __set_cpsr_c(I32_bit, I32_bit);
#define IRQenable __set_cpsr_c(I32_bit, 0);
#else
#define IRQdisable set_r15(R15_IRQ_DISABLE, R15_IRQ_DISABLE);
#define IRQenable set_r15(R15_IRQ_DISABLE, 0);
#endif
#endif /* !_LOCORE */
#ifndef _LOCORE
extern int cpu_fpu_present;
/* All the CLKF_* macros take a struct clockframe * as an argument. */
@@ -143,22 +89,22 @@ extern int cpu_do_powersave;
* frame came from USR mode or not.
*/
#ifdef __PROG32
#define CLKF_USERMODE(frame) ((frame->cf_tf.tf_spsr & PSR_MODE) == PSR_USR32_MODE)
#define CLKF_USERMODE(cf) (((cf)->cf_tf.tf_spsr & PSR_MODE) == PSR_USR32_MODE)
#else
#define CLKF_USERMODE(frame) ((frame->cf_if.if_r15 & R15_MODE) == R15_MODE_USR)
#define CLKF_USERMODE(cf) (((cf)->cf_if.if_r15 & R15_MODE) == R15_MODE_USR)
#endif
/*
* CLKF_INTR: True if we took the interrupt from inside another
* interrupt handler.
*/
#ifdef __PROG32
#if defined(__PROG32) && !defined(__ARM_EABI__)
/* Hack to treat FPE time as interrupt time so we can measure it */
#define CLKF_INTR(frame) \
((curcpu()->ci_intr_depth > 1) || \
(frame->cf_tf.tf_spsr & PSR_MODE) == PSR_UND32_MODE)
#define CLKF_INTR(cf) \
((curcpu()->ci_intr_depth > 1) || \
((cf)->cf_tf.tf_spsr & PSR_MODE) == PSR_UND32_MODE)
#else
#define CLKF_INTR(frame) (curcpu()->ci_intr_depth > 1)
#define CLKF_INTR(cf) ((void)(cf), curcpu()->ci_intr_depth > 1)
#endif
/*
@@ -179,41 +125,6 @@ extern int cpu_do_powersave;
#define LWP_PC(l) (lwp_trapframe(l)->tf_r15 & R15_PC)
#endif
/*
* Validate a PC or PSR for a user process. Used by various system calls
* that take a context passed by the user and restore it.
*/
#ifdef __PROG32
#define VALID_R15_PSR(r15,psr) \
(((psr) & PSR_MODE) == PSR_USR32_MODE && \
((psr) & (I32_bit | F32_bit)) == 0)
#else
#define VALID_R15_PSR(r15,psr) \
(((r15) & R15_MODE) == R15_MODE_USR && \
((r15) & (R15_IRQ_DISABLE | R15_FIQ_DISABLE)) == 0)
#endif
/* The address of the vector page. */
extern vaddr_t vector_page;
#ifdef __PROG32
void arm32_vector_init(vaddr_t, int);
#define ARM_VEC_RESET (1 << 0)
#define ARM_VEC_UNDEFINED (1 << 1)
#define ARM_VEC_SWI (1 << 2)
#define ARM_VEC_PREFETCH_ABORT (1 << 3)
#define ARM_VEC_DATA_ABORT (1 << 4)
#define ARM_VEC_ADDRESS_EXCEPTION (1 << 5)
#define ARM_VEC_IRQ (1 << 6)
#define ARM_VEC_FIQ (1 << 7)
#define ARM_NVEC 8
#define ARM_VEC_ALL 0xffffffff
#endif
/*
* Per-CPU information. For now we assume one CPU.
*/
@@ -221,9 +132,12 @@ static inline int curcpl(void);
static inline void set_curcpl(int);
static inline void cpu_dosoftints(void);
#ifdef _KMEMUSER
#include <sys/intr.h>
#endif
#include <sys/cpu_data.h>
#include <sys/device_if.h>
#include <sys/evcnt.h>
#include <sys/cpu_data.h>
struct cpu_info {
struct cpu_data ci_data; /* MI per-cpu data */
@@ -238,26 +152,23 @@ struct cpu_info {
int ci_want_resched; /* resched() was called */
int ci_intr_depth; /* */
struct cpu_softc *ci_softc; /* platform softc */
#ifdef __HAVE_FAST_SOFTINTS
lwp_t *ci_softlwps[SOFTINT_COUNT];
volatile uint32_t ci_softints;
#endif
lwp_t *ci_curlwp; /* current lwp */
struct evcnt ci_arm700bugcount;
int32_t ci_mtx_count;
int ci_mtx_oldspl;
register_t ci_undefsave[3];
uint32_t ci_vfp_id;
#if defined(_ARM_ARCH_7)
uint64_t ci_lastintr;
#endif
struct evcnt ci_abt_evs[FAULT_TYPE_MASK+1];
struct evcnt ci_abt_evs[16];
#if defined(MP_CPU_INFO_MEMBERS)
MP_CPU_INFO_MEMBERS
#endif
};
extern struct cpu_info cpu_info_store;
#if defined(TPIDRPRW_IS_CURLWP)
static inline struct lwp *
_curlwp(void)
@@ -306,7 +217,7 @@ void cpu_boot_secondary_processors(void);
#define CPU_IS_PRIMARY(ci) true
#define CPU_INFO_FOREACH(cii, ci) \
cii = 0, ci = curcpu(); ci != NULL; ci = NULL
cii = 0, __USE(cii), ci = curcpu(); ci != NULL; ci = NULL
#endif
#define LWP0_CPU_INFO (&cpu_info_store)
@@ -375,42 +286,7 @@ vaddr_t cpu_uarea_alloc_idlelwp(struct cpu_info *);
void cpu_attach(device_t, cpuid_t);
#endif
/*
* Random cruft
*/
struct lwp;
/* locore.S */
void atomic_set_bit(u_int *, u_int);
void atomic_clear_bit(u_int *, u_int);
/* cpuswitch.S */
struct pcb;
void savectx(struct pcb *);
/* ast.c */
void userret(register struct lwp *);
/* *_machdep.c */
void bootsync(void);
/* fault.c */
int badaddr_read(void *, size_t, void *);
/* syscall.c */
void swi_handler(trapframe_t *);
/* arm_machdep.c */
void ucas_ras_check(trapframe_t *);
/* vfp_init.c */
void vfp_attach(void);
void vfp_discardcontext(void);
void vfp_savecontext(void);
extern const pcu_ops_t arm_vfp_ops;
#endif /* !_LOCORE */
#endif /* !_LOCORE */
#endif /* _KERNEL */

9
sys/arch/arm/include/cpuconf.h
View File

@@ -1,4 +1,4 @@
/* $NetBSD: cpuconf.h,v 1.20 2011/03/10 07:47:14 bsh Exp $ */
/* $NetBSD: cpuconf.h,v 1.21 2013/05/19 15:51:10 rkujawa Exp $ */
/*
* Copyright (c) 2002 Wasabi Systems, Inc.
@@ -132,7 +132,7 @@
#define ARM_ARCH_6 0
#endif
#if defined(CPU_CORTEX)
#if defined(CPU_CORTEX) || defined(CPU_PJ4B)
#define ARM_ARCH_7 1
#else
#define ARM_ARCH_7 0
@@ -217,7 +217,8 @@
defined(CPU_ARM1136) || \
defined(CPU_ARM1176) || \
defined(CPU_ARM11) && \
!defined(CPU_CORTEX) && !defined(CPU_ARM11MPCORE)
!defined(CPU_CORTEX) && \
!defined(CPU_ARM11MPCORE) && !defined(CPU_PJ4B)
#define ARM_MMU_V6C 1
#else
#define ARM_MMU_V6C 0
@@ -234,7 +235,7 @@
#if !defined(_KERNEL_OPT) || \
defined(CPU_CORTEX)
defined(CPU_CORTEX) || defined(CPU_PJ4B)
#define ARM_MMU_V7 1
#else
#define ARM_MMU_V7 0

38
sys/arch/arm/include/cpufunc.h
View File

@@ -468,15 +468,41 @@ void armv7_dcache_wbinv_range(vaddr_t, vsize_t);
void armv7_dcache_inv_range(vaddr_t, vsize_t);
void armv7_idcache_wbinv_range(vaddr_t, vsize_t);
void armv7_dcache_wbinv_all (void);
void armv7_idcache_wbinv_all(void);
void armv7_icache_sync_all(void);
void armv7_cpu_sleep(int);
void armv7_context_switch(u_int);
void armv7_tlb_flushID_SE(u_int);
void armv7_setup (char *string);
void armv7_drain_writebuf(void);
void armv7_setup(char *string);
#endif
#if defined(CPU_CORTEX) || defined(CPU_PJ4B)
void armv7_dcache_wbinv_all (void);
void armv7_idcache_wbinv_all(void);
#endif
#if defined(CPU_PJ4B)
void pj4b_setttb(u_int, bool);
void pj4b_tlb_flushID(void);
void pj4b_tlb_flushID_SE(u_int);
void pj4b_icache_sync_range(vm_offset_t, vm_size_t);
void pj4b_idcache_wbinv_range(vm_offset_t, vm_size_t);
void pj4b_dcache_wbinv_range(vm_offset_t, vm_size_t);
void pj4b_dcache_inv_range(vm_offset_t, vm_size_t);
void pj4b_dcache_wb_range(vm_offset_t, vm_size_t);
void pj4b_drain_writebuf(void);
void pj4b_drain_readbuf(void);
void pj4b_flush_brnchtgt_all(void);
void pj4b_flush_brnchtgt_va(u_int);
void pj4b_context_switch(u_int);
void pj4b_sleep(int);
void pj4bv7_setup(char *string);
void pj4b_config(void);
#endif /* CPU_PJ4B */
#if defined(CPU_ARM1136) || defined(CPU_ARM1176)
void arm11x6_setttb (u_int, bool);
@@ -580,9 +606,9 @@ void sheeva_cpu_sleep(int);
* Macros for manipulating CPU interrupts
*/
#ifdef __PROG32
static __inline u_int32_t __set_cpsr_c(uint32_t bic, uint32_t eor) __attribute__((__unused__));
static __inline u_int32_t disable_interrupts(uint32_t mask) __attribute__((__unused__));
static __inline u_int32_t enable_interrupts(uint32_t mask) __attribute__((__unused__));
static __inline uint32_t __set_cpsr_c(uint32_t bic, uint32_t eor) __attribute__((__unused__));
static __inline uint32_t disable_interrupts(uint32_t mask) __attribute__((__unused__));
static __inline uint32_t enable_interrupts(uint32_t mask) __attribute__((__unused__));
static __inline uint32_t
__set_cpsr_c(uint32_t bic, uint32_t eor)

28
sys/arch/arm/include/disklabel.h
View File

@@ -1,4 +1,4 @@
/* $NetBSD: disklabel.h,v 1.10 2011/08/30 12:39:53 bouyer Exp $ */
/* $NetBSD: disklabel.h,v 1.12 2013/05/27 07:37:20 msaitoh Exp $ */
/*
* Copyright (c) 1994 Mark Brinicombe.
@@ -47,12 +47,28 @@
#define _ARM_DISKLABEL_H_
#ifndef LABELUSESMBR
#define LABELUSESMBR 0 /* no MBR partitionning */
#define LABELUSESMBR 1 /* use MBR partitionning */
#endif
#define LABELSECTOR 1 /* sector containing label */
#define LABELOFFSET 0 /* offset of label in sector */
#define MAXPARTITIONS 8 /* number of partitions */
#define RAW_PART 2 /* raw partition: XX?c */
#define LABELSECTOR 1 /* sector containing label */
#define LABELOFFSET 0 /* offset of label in sector */
#define MAXPARTITIONS 16 /* number of partitions */
#define OLDMAXPARTITIONS 8 /* old number of partitions */
#ifndef RAW_PART
#define RAW_PART 2 /* raw partition: XX?c */
#endif
/*
* We use the highest bit of the minor number for the partition number.
* This maintains backward compatibility with device nodes created before
* MAXPARTITIONS was increased.
*/
#define __ARM_MAXDISKS ((1 << 20) / MAXPARTITIONS)
#define DISKUNIT(dev) ((minor(dev) / OLDMAXPARTITIONS) % __ARM_MAXDISKS)
#define DISKPART(dev) ((minor(dev) % OLDMAXPARTITIONS) + \
((minor(dev) / (__ARM_MAXDISKS * OLDMAXPARTITIONS)) * OLDMAXPARTITIONS))
#define DISKMINOR(unit, part) \
(((unit) * OLDMAXPARTITIONS) + ((part) % OLDMAXPARTITIONS) + \
((part) / OLDMAXPARTITIONS) * (__ARM_MAXDISKS * OLDMAXPARTITIONS))
#if HAVE_NBTOOL_CONFIG_H
#include <nbinclude/sys/dkbad.h>

133
sys/arch/arm/include/ehabi.h Normal file
View File

@@ -0,0 +1,133 @@
/*-
* Copyright (c) 2013 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Matt Thomas of 3am Software Foundry.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/* $NetBSD: ehabi.h,v 1.1 2013/08/12 23:22:12 matt Exp $ */
#ifndef _ARM_EHABI_H_
#define _ARM_EHABI_H_
#if defined(_KERNEL) || defined(_STANDALONE)
#include <sys/types.h>
#else
#include <inttypes.h>
#endif
typedef enum {
_URC_OK = 0, /* operation complete */
_URC_FOREIGN_EXCEPTION_CAUGHT = 1,
_URC_HANDLER_FOUND = 6,
_URC_INSTALL_CONTEXT = 7,
_URC_CONTINUE_UNWIND = 8,
_URC_FAILURE = 9, /* unspecified failure */
} _Unwind_Reason_Code;
typedef enum {
_UVRSC_CORE = 0, /* integer register */
_UVRSC_VFP = 1, /* vfp */
_UVRSC_WMMXD = 3, /* Intel WMMX data register */
_UVRSC_WMMXC = 4 /* Intel WMMX control register */
} _Unwind_VRS_RegClass;
typedef enum {
_UVRSD_UINT32 = 0,
_UVRSD_VFPX = 1,
_UVRSD_UINT64 = 3,
_UVRSD_FLOAT = 4,
_UVRSD_DOUBLE = 5
} _Unwind_VRS_DataRepresentation;
typedef enum {
_UVRSR_OK = 0,
_UVRSR_NOT_IMPLEMENTED = 1,
_UVRSR_FAILED = 2
} _Unwind_VRS_Result;
typedef uint32_t _Unwind_State;
static const _Unwind_State _US_VIRTUAL_UNWIND_FRAME = 0;
static const _Unwind_State _US_UNWIND_FRAME_STARTING = 1;
static const _Unwind_State _US_UNWIND_FRAME_RESUME = 2;
typedef struct _Unwind_Control_Block _Unwind_Control_Block;
typedef struct _Unwind_Context _Unwind_Context;
typedef uint32_t _Unwind_EHT_Header;
struct _Unwind_Control_Block {
char exception_class[8];
void (*exception_cleanup)(_Unwind_Reason_Code, _Unwind_Control_Block *);
/* Unwinder cache, private fields for the unwinder's use */
struct {
uint32_t reserved1;
uint32_t reserved2;
uint32_t reserved3;
uint32_t reserved4;
uint32_t reserved5;
/* init reserved1 to 0, then don't touch */
} unwinder_cache;
/* Propagation barrier cache (valid after phase 1): */
struct {
uint32_t sp;
uint32_t bitpattern[5];
} barrier_cache;
/* Cleanup cache (preserved over cleanup): */
struct {
uint32_t bitpattern[4];
} cleanup_cache;
/* Pr cache (for pr's benefit): */
struct {
uint32_t fnstart; /* function start address */
_Unwind_EHT_Header *ehtp; /* ptr to EHT entry header word */
uint32_t additional; /* additional data */
uint32_t reserved1;
} pr_cache;
uint64_t : 0; /* Force alignment of next item to 8-byte boundary */
};
__BEGIN_DECLS
/* Unwinding functions */
void _Unwind_Resume(_Unwind_Control_Block *);
void _Unwind_Complete(_Unwind_Control_Block *);
void _Unwind_DeleteException(_Unwind_Control_Block *);
_Unwind_Reason_Code _Unwind_RaiseException(_Unwind_Control_Block *);
_Unwind_VRS_Result _Unwind_VRS_Set(_Unwind_Context *, _Unwind_VRS_RegClass,
uint32_t, _Unwind_VRS_DataRepresentation, void *);
_Unwind_VRS_Result _Unwind_VRS_Get(_Unwind_Context *, _Unwind_VRS_RegClass,
uint32_t, _Unwind_VRS_DataRepresentation, void *);
_Unwind_VRS_Result _Unwind_VRS_Pop(_Unwind_Context *, _Unwind_VRS_RegClass,
uint32_t, _Unwind_VRS_DataRepresentation);
_Unwind_Reason_Code __aeabi_unwind_cpp_pr0(_Unwind_State,
_Unwind_Control_Block *, _Unwind_Context *);
_Unwind_Reason_Code __aeabi_unwind_cpp_pr1(_Unwind_State ,
_Unwind_Control_Block *, _Unwind_Context *);
_Unwind_Reason_Code __aeabi_unwind_cpp_pr2(_Unwind_State ,
_Unwind_Control_Block *, _Unwind_Context *);
__END_DECLS
#endif /* _ARM_EHABI_H_ */

157
sys/arch/arm/include/elf_machdep.h
View File

@@ -1,4 +1,4 @@
/* $NetBSD: elf_machdep.h,v 1.10 2012/08/05 04:12:46 matt Exp $ */
/* $NetBSD: elf_machdep.h,v 1.14 2013/10/29 00:45:00 matt Exp $ */
#ifndef _ARM_ELF_MACHDEP_H_
#define _ARM_ELF_MACHDEP_H_
@@ -27,6 +27,7 @@
#define EF_ARM_NEW_ABI 0x00000080
#define EF_ARM_OLD_ABI 0x00000100
#define EF_ARM_SOFT_FLOAT 0x00000200
#define EF_ARM_BE8 0x00800000
#define EF_ARM_EABIMASK 0xff000000
#define EF_ARM_EABI_VER1 0x01000000
#define EF_ARM_EABI_VER2 0x02000000
@@ -76,13 +77,29 @@
#define R_ARM_GOTPC 25
#define R_ARM_GOT32 26
#define R_ARM_PLT32 27
#define R_ARM_CALL 28
#define R_ARM_JUMP24 29
#define R_ARM_THM_JUMP24 30
#define R_ARM_BASE_ABS 31
#define R_ARM_ALU_PCREL_7_0 32
#define R_ARM_ALU_PCREL_15_8 33
#define R_ARM_ALU_PCREL_23_15 34
#define R_ARM_ALU_SBREL_11_0 35
#define R_ARM_ALU_SBREL_19_12 36
#define R_ARM_ALU_SBREL_27_20 37
#define R_ARM_ALU_SBREL_27_20 37 // depcreated
#define R_ARM_TARGET1 38
#define R_ARM_SBREL31 39 // deprecated
#define R_ARM_V4BX 40
#define R_ARM_TARGET2 41
#define R_ARM_PREL31 42
#define R_ARM_MOVW_ABS_NC 43
#define R_ARM_MOVT_ABS 44
#define R_ARM_MOVW_PREL_NC 45
#define R_ARM_MOVT_PREL 46
#define R_ARM_THM_MOVW_ABS_NC 47
#define R_ARM_THM_MOVT_ABS 48
#define R_ARM_THM_MOVW_PREL_NC 49
#define R_ARM_THM_MOVT_PREL 50
/* 96-111 are reserved to G++. */
#define R_ARM_GNU_VTENTRY 100
@@ -110,6 +127,133 @@
#define R_ARM_RPC24 254
#define R_ARM_RBASE 255
#define R_AARCH64_ABS64 257 /* S + A */
#define R_AARCH64_ABS32 258 /* S + A */
#define R_AARCH64_ABS16 259 /* S + A */
#define R_AARCH64_PREL64 260 /* S + A - P */
#define R_AARCH64_PREL32 261 /* S + A - P */
#define R_AARCH64_PREL16 262 /* S + A - P */
#define R_AARCH64_MOVW_UABS_G0 263 /* S + A [bits 0..15] */
#define R_AARCH64_MOVW_UABS_G0_NC 264 /* S + A [bits 0..15] */
#define R_AARCH64_MOVW_UABS_G1 265 /* S + A [bits 16..31] */
#define R_AARCH64_MOVW_UABS_G1_NC 266 /* S + A [bits 16..31] */
#define R_AARCH64_MOVW_UABS_G2 267 /* S + A [bits 32..47] */
#define R_AARCH64_MOVW_UABS_G2_NC 268 /* S + A [bits 32..47] */
#define R_AARCH64_MOVW_UABS_G3 269 /* S + A [bits 48..63] */
#define R_AARCH64_MOVW_SABS_G0 270 /* S + A [bits 0..15] */
#define R_AARCH64_MOVW_SABS_G1 271 /* S + A [bits 16..31] */
#define R_AARCH64_MOVW_SABS_G2 272 /* S + A [bits 32..47] */
#define R_AARCH64_LD_PREL_LO19 273 /* S + A - P */
#define R_AARCH64_ADR_PREL_LO21 274 /* S + A - P */
#define R_AARCH64_ADR_PREL_PG_HI21 275 /* Page(S + A) - Page(P) */
#define R_AARCH64_ADR_PREL_PG_HI21_NC 276 /* Page(S + A) - Page(P) */
#define R_AARCH64_ADR_ABS_LO21_NC 277 /* S + A */
#define R_AARCH64_LDST8_ABS_LO12_NC 278 /* S + A */
#define R_AARCH_TSTBR14 279 /* S + A - P */
#define R_AARCH_CONDBR19 281 /* S + A - P */
#define R_AARCH_JUMP26 282 /* S + A - P */
#define R_AARCH_CALL26 283 /* S + A - P */
#define R_AARCH_LDST16_ABS_LO12_NC 284 /* S + A */
#define R_AARCH_LDST32_ABS_LO12_NC 285 /* S + A */
#define R_AARCH_LDST64_ABS_LO12_NC 286 /* S + A */
#define R_AARCH64_MOVW_PREL_G0 287 /* S + A - P */
#define R_AARCH64_MOVW_PREL_G0_NC 288 /* S + A - P */
#define R_AARCH64_MOVW_PREL_G1 289 /* S + A - P */
#define R_AARCH64_MOVW_PREL_G1_NC 290 /* S + A - P */
#define R_AARCH64_MOVW_PREL_G2 291 /* S + A - P */
#define R_AARCH64_MOVW_PREL_G2_NC 292 /* S + A - P */
#define R_AARCH64_MOVW_PREL_G3 293 /* S + A - P */
#define R_AARCH64_LDST128_ABS_LO12_NC 299 /* S + A */
#define R_AARCH64_MOVW_GOTOFF_G0 300 /* G(GDAT(S + A)) - GOT */
#define R_AARCH64_MOVW_GOTOFF_G0_NC 301 /* G(GDAT(S + A)) - GOT */
#define R_AARCH64_MOVW_GOTOFF_G1 302 /* G(GDAT(S + A)) - GOT */
#define R_AARCH64_MOVW_GOTOFF_G1_NC 303 /* G(GDAT(S + A)) - GOT */
#define R_AARCH64_MOVW_GOTOFF_G2 304 /* G(GDAT(S + A)) - GOT */
#define R_AARCH64_MOVW_GOTOFF_G2_NC 305 /* G(GDAT(S + A)) - GOT */
#define R_AARCH64_MOVW_GOTOFF_G3 306 /* G(GDAT(S + A)) - GOT */
#define R_AARCH64_GOTREL64 307 /* S + A - GOT */
#define R_AARCH64_GOTREL32 308 /* S + A - GOT */
#define R_AARCH64_GOT_LD_PREL19 309 /* G(GDAT(S + A)) - P */
#define R_AARCH64_LD64_GOTOFF_LO15 310 /* G(GDAT(S + A)) - GOT */
#define R_AARCH64_ADR_GOT_PAGE 311 /* Page(G(GDAT(S + A))) - Page(GOT) */
#define R_AARCH64_LD64_GOT_LO12_NC 312 /* G(GDAT(S + A)) */
#define R_AARCH64_LD64_GOTPAGE_LO15 313 /* G(GDAT(S + A)) - Page(GOT) */
#define R_AARCH64_TLSGD_ADR_PREL21 512 /* G(GTLSIDX(S,A)) - P */
#define R_AARCH64_TLSGD_ADR_PAGE21 513 /* Page(G(GTLSIDX(S,A))) - Page(P) */
#define R_AARCH64_TLSGD_ADD_LO12_NC 514 /* G(GTLSIDX(S,A)) */
#define R_AARCH64_TLSGD_MOVW_G1 515 /* G(GTLSIDX(S,A)) - GOT */
#define R_AARCH64_TLSGD_MOVW_G0_NV 516 /* G(GTLSIDX(S,A)) - GOT */
#define R_AARCH64_TLSLD_ADR_PREL21 517 /* G(GLDM(S,A)) - P */
#define R_AARCH64_TLSLD_ADR_PAGE21 518 /* Page(G(GLDM(S))) - Page(P) */
#define R_AARCH64_TLSLD_ADD_LO12_NC 519 /* G(GLDM(S)) */
#define R_AARCH64_TLSLD_MOVW_G1 520 /* G(GLDM(S)) - GOT */
#define R_AARCH64_TLSLD_MOVW_G0_NC 521 /* G(GLDM(S)) - GOT */
#define R_AARCH64_TLSLD_LD_PREL21 522 /* G(GLDM(S)) - P */
#define R_AARCH64_TLSLD_MOVW_DTPREL_G2 523 /* DTPREL(S+A) */
#define R_AARCH64_TLSLD_MOVW_DTPREL_G1 524 /* DTPREL(S+A) */
#define R_AARCH64_TLSLD_MOVW_DTPREL_G1_NC 525 /* DTPREL(S+A) */
#define R_AARCH64_TLSLD_MOVW_DTPREL_G0 526 /* DTPREL(S+A) */
#define R_AARCH64_TLSLD_MOVW_DTPREL_G0_NC 528 /* DTPREL(S+A) */
#define R_AARCH64_TLSLD_ADD_DTPREL_HI12 528 /* DTPREL(S+A) */
#define R_AARCH64_TLSLD_ADD_DTPREL_HI12 528 /* DTPREL(S+A) */
#define R_AARCH64_TLSLD_ADD_DTPREL_LO12 529 /* DTPREL(S+A) */
#define R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC 530 /* DTPREL(S+A) */
#define R_AARCH64_TLSLD_LDST8_DTPREL_LO12 531 /* DTPREL(S+A) */
#define R_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC 532 /* DTPREL(S+A) */
#define R_AARCH64_TLSLD_LDST16_DTPREL_LO12 533 /* DTPREL(S+A) */
#define R_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC 534 /* DTPREL(S+A) */
#define R_AARCH64_TLSLD_LDST32_DTPREL_LO12 535 /* DTPREL(S+A) */
#define R_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC 536 /* DTPREL(S+A) */
#define R_AARCH64_TLSLD_LDST64_DTPREL_LO12 537 /* DTPREL(S+A) */
#define R_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC 538 /* DTPREL(S+A) */
#define R_AARCH64_TLSIE_MOVW_GOTTPREL_G1 539 /* G(GTPREL(S+A)) - GOT */
#define R_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC 540 /* G(GTPREL(S+A)) - GOT */
#define R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21 541 /* Page(G(GTPREL(S+A))) - Page(P) */
#define R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC 542 /* G(GTPREL(S+A)) */
#define R_AARCH64_TLSIE_LD_GOTTPREL_PREL19 543 /* G(GTPREL(S+A)) - P */
#define R_AARCH64_TLSLE_MOVW_TPREL_G2 544 /* TPREL(S+A) */
#define R_AARCH64_MOVW_TPREL_G1 545 /* TPREL(S+A) */
#define R_AARCH64_MOVW_TPREL_G1_NC 546 /* TPREL(S+A) */
#define R_AARCH64_MOVW_TPREL_G0 547 /* TPREL(S+A) */
#define R_AARCH64_MOVW_TPREL_G0_NC 548 /* TPREL(S+A) */
#define R_AARCH64_ADD_TPREL_HI12 549 /* TPREL(S+A) */
#define R_AARCH64_ADD_TPREL_LO12 550 /* TPREL(S+A) */
#define R_AARCH64_ADD_TPREL_LO12_NC 551 /* TPREL(S+A) */
#define R_AARCH64_LDST8_TPREL_LO12 552 /* TPREL(S+A) */
#define R_AARCH64_LDST8_TPREL_LO12_NC 553 /* TPREL(S+A) */
#define R_AARCH64_LDST16_TPREL_LO12 554 /* TPREL(S+A) */
#define R_AARCH64_LDST16_TPREL_LO12_NC 555 /* TPREL(S+A) */
#define R_AARCH64_LDST32_TPREL_LO12 556 /* TPREL(S+A) */
#define R_AARCH64_LDST32_TPREL_LO12_NC 557 /* TPREL(S+A) */
#define R_AARCH64_LDST64_TPREL_LO12 558 /* TPREL(S+A) */
#define R_AARCH64_LDST64_TPREL_LO12_NC 559 /* TPREL(S+A) */
#define R_AARCH64_TLSDESC_LD_PREL19 560 /* G(GTLSDESC(S+A)) - P */
#define R_AARCH64_TLSDESC_LD_PREL21 561 /* G(GTLSDESC(S+A)) - P */
#define R_AARCH64_TLSDESC_LD_PAGE21 562 /* Page(G(GTLSDESC(S+A))) - Page(P) */
#define R_AARCH64_TLSDESC_LD64_LO12 563 /* G(GTLSDESC(S+A)) */
#define R_AARCH64_TLSDESC_ADD_LO12 564 /* G(GTLSDESC(S+A)) */
#define R_AARCH64_TLSDESC_OFF_G1 565 /* G(GTLSDESC(S+A)) - GOT */
#define R_AARCH64_TLSDESC_OFF_G0_NC 566 /* G(GTLSDESC(S+A)) - GOT */
#define R_AARCH64_TLSDESC_LDR 567 /* */
#define R_AARCH64_TLSDESC_ADD 568 /* */
#define R_AARCH64_TLSDESC_CALL 569 /* */
#define R_AARCH64_TLSLE_LDST128_TPREL_LO12 570 /* TPREL(S+A) */
#define R_AARCH64_TLSLE_LDST128_TPREL_LO12_NC 571 /* TPREL(S+A) */
#define R_AARCH64_TLSLD_LDST128_DTPREL_LO12 572 /* DTPREL(S+A) */
#define R_AARCH64_TLSLD_LDST128_DTPREL_LO12_NC 572 /* DTPREL(S+A) */
#define R_AARCH64_COPY 1024
#define R_AARCH64_GLOB_DAT 1025 /* S + A */
#define R_AARCH64_JUMP_SLOT 1026 /* S + A */
#define R_AARCH64_RELATIVE 1027 /* Delta(S) + A */
#define R_AARCH64_TLS_DTPREL64 1028 /* DTPREL(S+A) */
#define R_AARCH64_TLS_DTPMOD64 1029 /* LBM(S) */
#define R_AARCH64_TLS_TPREL64 1030 /* TPREL(S+A) */
#define R_AARCH64_TLSDESC 1031 /* TLSDESC(S+A) */
#define R_AARCH64_IRELATIVE 1032 /* Indirect(Delta(S) + A) */
#define R_TYPE(name) __CONCAT(R_ARM_,name)
/* Processor specific program header flags */
@@ -117,10 +261,17 @@
#define PF_ARM_PI 0x20000000
#define PF_ARM_ENTRY 0x80000000
/* Processor specific program header types */
#define PT_ARM_EXIDX (PT_LOPROC + 1)
#define PT_AARCH64_ARCHEXT (PT_LOPROC + 0)
#define PT_AARCH64_UNWIND (PT_LOPROC + 1)
/* Processor specific section header flags */
#define SHF_ENTRYSECT 0x10000000
#define SHF_COMDEF 0x80000000
#define SHT_AARCH64_ATTRIBUTES (SHT_LOPROC + 3)
/* Processor specific symbol types */
#define STT_ARM_TFUNC STT_LOPROC

35
sys/arch/arm/include/fenv.h Normal file
View File

@@ -0,0 +1,35 @@
/* $NetBSD: fenv.h,v 1.1 2013/04/23 05:41:12 matt Exp $ */
/*
* Based on ieeefp.h written by J.T. Conklin, Apr 28, 1995
* Public domain.
*/
#ifndef _ARM_FENV_H_
#define _ARM_FENV_H_
typedef int fenv_t;
typedef int fexcept_t;
#define FE_INVALID 0x01 /* invalid operation exception */
#define FE_DIVBYZERO 0x02 /* divide-by-zero exception */
#define FE_OVERFLOW 0x04 /* overflow exception */
#define FE_UNDERFLOW 0x08 /* underflow exception */
#define FE_INEXACT 0x10 /* imprecise (loss of precision; "inexact") */
#define FE_ALL_EXCEPT 0x1f
#define FE_TONEAREST 0 /* round to nearest representable number */
#define FE_UPWARD 1 /* round toward positive infinity */
#define FE_DOWNWARD 2 /* round toward negative infinity */
#define FE_TOWARDZERO 3 /* round to zero (truncate) */
__BEGIN_DECLS
/* Default floating-point environment */
extern const fenv_t __fe_dfl_env;
#define FE_DFL_ENV (&__fe_dfl_env)
__END_DECLS
#endif /* _ARM_FENV_H_ */

25
sys/arch/arm/include/float.h
View File

@@ -1,31 +1,8 @@
/* $NetBSD: float.h,v 1.6 2005/12/11 12:16:47 christos Exp $ */
/* $NetBSD: float.h,v 1.7 2013/01/24 10:13:35 matt Exp $ */
#ifndef _ARM_FLOAT_H_
#define _ARM_FLOAT_H_
#ifndef __VFP_FP__
#define LDBL_MANT_DIG 64
#define LDBL_EPSILON 1.0842021724855044340E-19L
#define LDBL_DIG 18
#define LDBL_MIN_EXP (-16381)
#define LDBL_MIN 1.6810515715560467531E-4932L
#define LDBL_MIN_10_EXP (-4931)
#define LDBL_MAX_EXP 16384
#define LDBL_MAX 1.1897314953572317650E+4932L
#define LDBL_MAX_10_EXP 4932
#endif
#include <sys/float_ieee754.h>
#ifndef __VFP_FP__
#if !defined(_ANSI_SOURCE) && !defined(_POSIX_C_SOURCE) && \
!defined(_XOPEN_SOURCE) || \
((__STDC_VERSION__ - 0) >= 199901L) || \
((_POSIX_C_SOURCE - 0) >= 200112L) || \
((_XOPEN_SOURCE - 0) >= 600) || \
defined(_ISOC99_SOURCE) || defined(_NETBSD_SOURCE)
#define DECIMAL_DIG 21
#endif /* !defined(_ANSI_SOURCE) && ... */
#endif /* !__VFP_FP__ */
#endif /* !_ARM_FLOAT_H_ */

86
sys/arch/arm/include/fp.h
View File

@@ -1,86 +0,0 @@
/* $NetBSD: fp.h,v 1.1 2001/01/10 19:02:06 bjh21 Exp $ */
/*
* Copyright (c) 1995 Mark Brinicombe.
* Copyright (c) 1995 Brini.
* All rights reserved.
*
* This code is derived from software written for Brini by Mark Brinicombe
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Brini.
* 4. The name of the company nor the name of the author may be used to
* endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* RiscBSD kernel project
*
* fp.h
*
* FP info
*
* Created : 10/10/95
*/
#ifndef __ARM32_FP_H
#define __ARM32_FP_H
/*
* An extended precision floating point number
*/
typedef struct fp_extended_precision {
u_int32_t fp_exponent;
u_int32_t fp_mantissa_hi;
u_int32_t fp_mantissa_lo;
} fp_extended_precision_t;
typedef struct fp_extended_precision fp_reg_t;
/*
* Information about the FPE-SP state that is stored in the pcb
*
* This needs to move and be hidden from userland.
*/
struct fpe_sp_state {
unsigned int fp_flags;
unsigned int fp_sr;
unsigned int fp_cr;
fp_reg_t fp_registers[16];
};
/*
* Type for a saved FP context, if we want to translate the context to a
* user-readable form
*/
typedef struct {
u_int32_t fpsr;
fp_extended_precision_t regs[8];
} fp_state_t;
#endif
/* End of fp.h */

9
sys/arch/arm/include/frame.h
View File

@@ -1,4 +1,4 @@
/* $NetBSD: frame.h,v 1.17 2012/08/16 17:35:01 matt Exp $ */
/* $NetBSD: frame.h,v 1.18 2013/08/18 05:07:19 matt Exp $ */
/*
* Copyright (c) 1994-1997 Mark Brinicombe.
@@ -52,7 +52,7 @@
typedef struct trapframe {
register_t tf_spsr; /* Zero on arm26 */
register_t tf_fill; /* fill here so r0 will dword aligned */
register_t tf_fill; /* fill here so r0 will be dword aligned */
register_t tf_r0;
register_t tf_r1;
register_t tf_r2;
@@ -90,14 +90,13 @@ typedef struct trapframe {
*/
#if defined(COMPAT_16) || defined(__minix)
struct sigframe_sigcontext {
#ifdef __minix
#if defined(__minix)
struct sigcontext *sf_scp; /* Let sigreturn find sigcontext */
#endif
#endif /* defined(__minix) */
struct sigcontext sf_sc;
};
#endif
/* the pointers are use in the trampoline code to locate the ucontext */
struct sigframe_siginfo {
siginfo_t sf_si; /* actual saved siginfo */

24
sys/arch/arm/include/ieeefp.h
View File

@@ -1,32 +1,18 @@
/* $NetBSD: ieeefp.h,v 1.2 2008/08/05 16:47:41 matt Exp $ */
/* $NetBSD: ieeefp.h,v 1.3 2013/04/23 05:42:23 matt Exp $ */
/*
* Based on ieeefp.h written by J.T. Conklin, Apr 28, 1995
* Public domain.
*/
#ifndef _ARM32_IEEEFP_H_
#define _ARM32_IEEEFP_H_
#ifndef _ARM_IEEEFP_H_
#define _ARM_IEEEFP_H_
#include <sys/featuretest.h>
#if defined(_NETBSD_SOURCE) || defined(_ISOC99_SOURCE)
typedef int fenv_t;
typedef int fexcept_t;
#define FE_INVALID 0x01 /* invalid operation exception */
#define FE_DIVBYZERO 0x02 /* divide-by-zero exception */
#define FE_OVERFLOW 0x04 /* overflow exception */
#define FE_UNDERFLOW 0x08 /* underflow exception */
#define FE_INEXACT 0x10 /* imprecise (loss of precision; "inexact") */
#define FE_ALL_EXCEPT 0x1f
#define FE_TONEAREST 0 /* round to nearest representable number */
#define FE_UPWARD 1 /* round toward positive infinity */
#define FE_DOWNWARD 2 /* round toward negative infinity */
#define FE_TOWARDZERO 3 /* round to zero (truncate) */
#include <arm/fenv.h>
#if !defined(_ISOC99_SOURCE)
@@ -55,4 +41,4 @@ typedef enum {
#endif /* _NETBSD_SOURCE || _ISOC99_SOURCE */
#endif /* _ARM32_IEEEFP_H_ */
#endif /* _ARM_IEEEFP_H_ */

5
sys/arch/arm/include/isa_machdep.h
View File

@@ -1,4 +1,4 @@
/* $NetBSD: isa_machdep.h,v 1.9 2012/09/21 14:21:57 matt Exp $ */
/* $NetBSD: isa_machdep.h,v 1.10 2012/10/27 17:17:39 chs Exp $ */
/*-
* Copyright (c) 1996, 1997, 1998 The NetBSD Foundation, Inc.
@@ -45,13 +45,12 @@ struct arm32_isa_chipset {
typedef struct arm32_isa_chipset *isa_chipset_tag_t;
struct device; /* XXX */
struct isabus_attach_args; /* XXX */
/*
* Functions provided to machine-independent ISA code.
*/
void isa_attach_hook(struct device *, struct device *,
void isa_attach_hook(device_t, device_t,
struct isabus_attach_args *);
void isa_detach_hook(isa_chipset_tag_t, device_t);
const struct evcnt *isa_intr_evcnt(isa_chipset_tag_t ic, int irq);

3
sys/arch/arm/include/joystick.h Normal file
View File

@@ -0,0 +1,3 @@
/* $NetBSD: joystick.h,v 1.1 2013/05/02 03:56:40 matt Exp $ */
#include <sys/joystick.h>

3
sys/arch/arm/include/limits.h
View File

@@ -1,4 +1,4 @@
/* $NetBSD: limits.h,v 1.12 2012/03/28 17:03:28 christos Exp $ */
/* $NetBSD: limits.h,v 1.13 2013/04/11 00:57:34 christos Exp $ */
/*
* Copyright (c) 1988 The Regents of the University of California.
@@ -66,6 +66,7 @@
#endif
#if defined(_NETBSD_SOURCE)
#define SSIZE_MIN LONG_MIN /* min value for a ssize_t */
#define SIZE_T_MAX LONG_MAX /* max value for a size_t */
#define UQUAD_MAX 0xffffffffffffffffULL /* max unsigned quad */

38
sys/arch/arm/include/lock.h
View File

@@ -1,4 +1,4 @@
/* $NetBSD: lock.h,v 1.21 2012/08/31 17:29:08 matt Exp $ */
/* $NetBSD: lock.h,v 1.25 2013/08/18 04:31:08 matt Exp $ */
/*-
* Copyright (c) 2000, 2001 The NetBSD Foundation, Inc.
@@ -74,16 +74,19 @@ __cpu_simple_lock_set(__cpu_simple_lock_t *__ptr)
#endif
#if defined(_KERNEL)
static __inline __cpu_simple_lock_t
static __inline unsigned char
__swp(__cpu_simple_lock_t __val, volatile __cpu_simple_lock_t *__ptr)
{
#ifdef _ARM_ARCH_6
__cpu_simple_lock_t __rv, __tmp;
uint32_t __rv, __tmp;
if (sizeof(*__ptr) == 1) {
__asm volatile(
"1:\t"
"ldrexb\t%[__rv], [%[__ptr]]" "\n\t"
"cmp\t%[__rv],%[__val]" "\n\t"
#ifdef __thumb__
"itt\tne" "\n\t"
#endif
"strexbne\t%[__tmp], %[__val], [%[__ptr]]" "\n\t"
"cmpne\t%[__tmp], #0" "\n\t"
"bne\t1b" "\n\t"
@@ -99,6 +102,9 @@ __swp(__cpu_simple_lock_t __val, volatile __cpu_simple_lock_t *__ptr)
"1:\t"
"ldrex\t%[__rv], [%[__ptr]]" "\n\t"
"cmp\t%[__rv],%[__val]" "\n\t"
#ifdef __thumb__
"itt\tne" "\n\t"
#endif
"strexne\t%[__tmp], %[__val], [%[__ptr]]" "\n\t"
"cmpne\t%[__tmp], #0" "\n\t"
"bne\t1b" "\n\t"
@@ -112,9 +118,10 @@ __swp(__cpu_simple_lock_t __val, volatile __cpu_simple_lock_t *__ptr)
}
return __rv;
#else
uint32_t __val32;
__asm volatile("swpb %0, %1, [%2]"
: "=&r" (__val) : "r" (__val), "r" (__ptr) : "memory");
return __val;
: "=&r" (__val32) : "r" (__val), "r" (__ptr) : "memory");
return __val32;
#endif
}
#else
@@ -135,11 +142,14 @@ __swp(int __val, volatile int *__ptr)
#ifdef _ARM_ARCH_6
"ldrex\t%[__rv], [%[__ptr]]" "\n\t"
"cmp\t%[__rv],%[__val]" "\n\t"
#ifdef __thumb__
"it\tne" "\n\t"
#endif
"strexne\t%[__tmp], %[__val], [%[__ptr]]" "\n\t"
#else
"swp\t%[__rv], %[__val], [%[__ptr]]" "\n\t"
"mov\t%[__tmp], #0" "\n\t"
"cmp\t%[__rv],%[__val]" "\n\t"
"movs\t%[__tmp], #0" "\n\t"
#endif
"cmpne\t%[__tmp], #0" "\n\t"
"bne\t1b" "\n\t"
@@ -156,7 +166,7 @@ __swp(int __val, volatile int *__ptr)
}
#endif /* _KERNEL */
static __inline void __attribute__((__unused__))
static __inline void __unused
__cpu_simple_lock_init(__cpu_simple_lock_t *alp)
{
@@ -166,22 +176,30 @@ __cpu_simple_lock_init(__cpu_simple_lock_t *alp)
#endif
}
static __inline void __attribute__((__unused__))
#if !defined(__thumb__) || defined(_ARM_ARCH_T2)
static __inline void __unused
__cpu_simple_lock(__cpu_simple_lock_t *alp)
{
while (__swp(__SIMPLELOCK_LOCKED, alp) != __SIMPLELOCK_UNLOCKED)
continue;
}
#else
void __cpu_simple_lock(__cpu_simple_lock_t *);
#endif
static __inline int __attribute__((__unused__))
#if !defined(__thumb__) || defined(_ARM_ARCH_T2)
static __inline int __unused
__cpu_simple_lock_try(__cpu_simple_lock_t *alp)
{
return (__swp(__SIMPLELOCK_LOCKED, alp) == __SIMPLELOCK_UNLOCKED);
}
#else
int __cpu_simple_lock_try(__cpu_simple_lock_t *);
#endif
static __inline void __attribute__((__unused__))
static __inline void __unused
__cpu_simple_unlock(__cpu_simple_lock_t *alp)
{

204
sys/arch/arm/include/locore.h Normal file
View File

@@ -0,0 +1,204 @@
/* cpu.h,v 1.45.4.7 2008/01/28 18:20:39 matt Exp */
/*
* Copyright (c) 1994-1996 Mark Brinicombe.
* Copyright (c) 1994 Brini.
* All rights reserved.
*
* This code is derived from software written for Brini by Mark Brinicombe
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Brini.
* 4. The name of the company nor the name of the author may be used to
* endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* RiscBSD kernel project
*
* cpu.h
*
* CPU specific symbols
*
* Created : 18/09/94
*
* Based on kate/katelib/arm6.h
*/
#ifndef _ARM_LOCORE_H_
#define _ARM_LOCORE_H_
#ifdef _KERNEL_OPT
#include "opt_cpuoptions.h"
#include "opt_cputypes.h"
#endif
#include <arm/cpuconf.h>
#include <arm/armreg.h>
#include <machine/frame.h>
#ifdef _LOCORE
#if defined(_ARM_ARCH_6)
#define IRQdisable cpsid i
#define IRQenable cpsie i
#elif defined(__PROG32)
#define IRQdisable \
stmfd sp!, {r0} ; \
mrs r0, cpsr ; \
orr r0, r0, #(I32_bit) ; \
msr cpsr_c, r0 ; \
ldmfd sp!, {r0}
#define IRQenable \
stmfd sp!, {r0} ; \
mrs r0, cpsr ; \
bic r0, r0, #(I32_bit) ; \
msr cpsr_c, r0 ; \
ldmfd sp!, {r0}
#else
/* Not yet used in 26-bit code */
#endif
#if defined (TPIDRPRW_IS_CURCPU)
#define GET_CURCPU(rX) mrc p15, 0, rX, c13, c0, 4
#define GET_CURLWP(rX) GET_CURCPU(rX); ldr rX, [rX, #CI_CURLWP]
#elif defined (TPIDRPRW_IS_CURLWP)
#define GET_CURLWP(rX) mrc p15, 0, rX, c13, c0, 4
#define GET_CURCPU(rX) GET_CURLWP(rX); ldr rX, [rX, #L_CPU]
#elif !defined(MULTIPROCESSOR)
#define GET_CURCPU(rX) ldr rX, =_C_LABEL(cpu_info_store)
#define GET_CURLWP(rX) GET_CURCPU(rX); ldr rX, [rX, #CI_CURLWP]
#endif
#define GET_CURPCB(rX) GET_CURLWP(rX); ldr rX, [rX, #L_PCB]
#else /* !_LOCORE */
#include <arm/cpufunc.h>
#ifdef __PROG32
#define IRQdisable __set_cpsr_c(I32_bit, I32_bit);
#define IRQenable __set_cpsr_c(I32_bit, 0);
#else
#define IRQdisable set_r15(R15_IRQ_DISABLE, R15_IRQ_DISABLE);
#define IRQenable set_r15(R15_IRQ_DISABLE, 0);
#endif
/*
* Validate a PC or PSR for a user process. Used by various system calls
* that take a context passed by the user and restore it.
*/
#ifdef __PROG32
#define VALID_R15_PSR(r15,psr) \
(((psr) & PSR_MODE) == PSR_USR32_MODE && \
((psr) & (I32_bit | F32_bit)) == 0)
#else
#define VALID_R15_PSR(r15,psr) \
(((r15) & R15_MODE) == R15_MODE_USR && \
((r15) & (R15_IRQ_DISABLE | R15_FIQ_DISABLE)) == 0)
#endif
/* The address of the vector page. */
extern vaddr_t vector_page;
#ifdef __PROG32
void arm32_vector_init(vaddr_t, int);
#define ARM_VEC_RESET (1 << 0)
#define ARM_VEC_UNDEFINED (1 << 1)
#define ARM_VEC_SWI (1 << 2)
#define ARM_VEC_PREFETCH_ABORT (1 << 3)
#define ARM_VEC_DATA_ABORT (1 << 4)
#define ARM_VEC_ADDRESS_EXCEPTION (1 << 5)
#define ARM_VEC_IRQ (1 << 6)
#define ARM_VEC_FIQ (1 << 7)
#define ARM_NVEC 8
#define ARM_VEC_ALL 0xffffffff
#endif /* __PROG32 */
#ifndef acorn26
/*
* cpu device glue (belongs in cpuvar.h)
*/
void cpu_attach(device_t, cpuid_t);
#endif
/* 1 == use cpu_sleep(), 0 == don't */
extern int cpu_do_powersave;
extern int cpu_fpu_present;
extern int cpu_hwdiv_present;
#if !defined(CPU_ARMV7)
#define CPU_IS_ARMV7_P() false
#elif defined(CPU_ARMV6) || defined(CPU_PRE_ARMV6)
extern bool cpu_armv7_p;
#define CPU_IS_ARMV7_P() (cpu_armv7_p)
#else
#define CPU_IS_ARMV7_P() true
#endif
/*
* Random cruft
*/
struct lwp;
/* locore.S */
void atomic_set_bit(u_int *, u_int);
void atomic_clear_bit(u_int *, u_int);
/* cpuswitch.S */
struct pcb;
void savectx(struct pcb *);
/* ast.c */
void userret(struct lwp *);
/* *_machdep.c */
void bootsync(void);
/* fault.c */
int badaddr_read(void *, size_t, void *);
/* syscall.c */
void swi_handler(trapframe_t *);
/* arm_machdep.c */
void ucas_ras_check(trapframe_t *);
/* vfp_init.c */
void vfp_attach(void);
void vfp_discardcontext(bool);
void vfp_savecontext(void);
void vfp_kernel_acquire(void);
void vfp_kernel_release(void);
bool vfp_used_p(void);
extern const pcu_ops_t arm_vfp_ops;
#endif /* !_LOCORE */
#endif /* !_ARM_LOCORE_H_ */

35
sys/arch/arm/include/mcontext.h
View File

@@ -1,4 +1,4 @@
/* $NetBSD: mcontext.h,v 1.11 2012/08/03 07:59:23 matt Exp $ */
/* $NetBSD: mcontext.h,v 1.16 2013/08/15 22:34:59 matt Exp $ */
/*-
* Copyright (c) 2001, 2002 The NetBSD Foundation, Inc.
@@ -32,6 +32,7 @@
#ifndef _ARM_MCONTEXT_H_
#define _ARM_MCONTEXT_H_
#include <sys/stdint.h>
/*
* General register state
*/
@@ -76,9 +77,15 @@ typedef struct {
} __fpregset_t;
typedef struct {
#ifdef __ARM_EABI__
unsigned int __vfp_fpscr;
uint64_t __vfp_fstmx[32];
unsigned int __vfp_fpsid;
#else
unsigned int __vfp_fpscr;
unsigned int __vfp_fstmx[33];
unsigned int __vfp_fpsid;
#endif
} __vfpregset_t;
typedef struct {
@@ -88,10 +95,10 @@ typedef struct {
__vfpregset_t __vfpregs;
} __fpu;
__greg_t _mc_tlsbase;
#ifdef __minix
#if defined(__minix)
int mc_flags;
int mc_magic;
#endif
#endif /* defined(__minix) */
} mcontext_t, mcontext32_t;
/* Machine-dependent uc_flags */
@@ -111,7 +118,7 @@ typedef struct {
#define _UC_MACHINE_SET_PC(uc, pc) _UC_MACHINE_PC(uc) = (pc)
#ifdef __minix
#if defined(__minix)
#define _UC_MACHINE_STACK(uc) ((uc)->uc_mcontext.__gregs[_REG_SP])
#define _UC_MACHINE_SET_STACK(uc, sp) _UC_MACHINE_STACK(uc) = (sp)
@@ -135,13 +142,18 @@ typedef struct {
#define _UC_MACHINE_R4(uc) ((uc)->uc_mcontext.__gregs[_REG_R4])
#define _UC_MACHINE_SET_R4(uc, setreg) _UC_MACHINE_R4(uc) = (setreg)
#endif
#endif /* defined(__minix) */
#ifdef __ARM_EABI__
#define __UCONTEXT_SIZE (256 + 144)
#else
#define __UCONTEXT_SIZE 256
#endif
static __inline void *
__lwp_getprivate_fast(void)
{
#if !defined(__thumb__) || defined(_ARM_ARCH_T2)
extern void *_lwp_getprivate(void);
void *rv;
__asm("mrc p15, 0, %0, c13, c0, 3" : "=r"(rv));
@@ -154,12 +166,21 @@ __lwp_getprivate_fast(void)
* syscall.
*/
return _lwp_getprivate();
#else
extern void *__aeabi_read_tp(void);
return __aeabi_read_tp();
#endif /* !__thumb__ || _ARM_ARCH_T2 */
}
#ifdef __minix
#if defined(_KERNEL)
void vfp_getcontext(struct lwp *, mcontext_t *, int *);
void vfp_setcontext(struct lwp *, const mcontext_t *);
#endif
#if defined(__minix)
int setmcontext(const mcontext_t *mcp);
int getmcontext(mcontext_t *mcp);
#define MCF_MAGIC 0xc0ffee
#endif
#endif /* defined(__minix) */
#endif /* !_ARM_MCONTEXT_H_ */

29
sys/arch/arm/include/ofisa_machdep.h
View File

@@ -1,4 +1,4 @@
/* $NetBSD: ofisa_machdep.h,v 1.2 2001/05/30 12:28:40 mrg Exp $ */
/* $NetBSD: ofisa_machdep.h,v 1.3 2012/10/27 17:17:39 chs Exp $ */
/*
* Copyright 1998
@@ -43,12 +43,12 @@ int ofisa_ignore_child(int pphandle, int cphandle);
#ifdef COMPAT_OLD_OFW
#define _OFISA_MD_MATCH
int ofisa_md_match(struct device *, struct cfdata *, void *);
int ofisa_md_match(device_t, cfdata_t, void *);
#define _COM_OFISA_MD_MATCH
#define _COM_OFISA_MD_INTR_FIXUP
int com_ofisa_md_match(struct device *, struct cfdata *, void *);
int com_ofisa_md_intr_fixup(struct device *, struct device*, void *,
int com_ofisa_md_match(device_t, cfdata_t, void *);
int com_ofisa_md_intr_fixup(device_t, device_t, void *,
struct ofisa_intr_desc *, int, int);
#define _CS_OFISA_MD_MATCH
@@ -56,31 +56,30 @@ int com_ofisa_md_intr_fixup(struct device *, struct device*, void *,
#define _CS_OFISA_MD_INTR_FIXUP
#define _CS_OFISA_MD_DMA_FIXUP
#define _CS_OFISA_MD_MEDIA_FIXUP
int cs_ofisa_md_match(struct device *, struct cfdata *, void *);
int cs_ofisa_md_reg_fixup(struct device *, struct device *, void *,
int cs_ofisa_md_match(device_t, cfdata_t, void *);
int cs_ofisa_md_reg_fixup(device_t, device_t, void *,
struct ofisa_reg_desc *, int, int);
int cs_ofisa_md_intr_fixup(struct device *, struct device *, void *,
int cs_ofisa_md_intr_fixup(device_t, device_t, void *,
struct ofisa_intr_desc *, int, int);
int cs_ofisa_md_dma_fixup(struct device *, struct device *, void *,
int cs_ofisa_md_dma_fixup(device_t, device_t, void *,
struct ofisa_dma_desc *, int, int);
int *cs_ofisa_md_media_fixup(struct device *, struct device *, void *,
int *cs_ofisa_md_media_fixup(device_t, device_t, void *,
int *, int *, int *);
#define _LPT_OFISA_MD_MATCH
#define _LPT_OFISA_MD_INTR_FIXUP
int lpt_ofisa_md_match(struct device *, struct cfdata *, void *);
int lpt_ofisa_md_intr_fixup(struct device *, struct device*, void *,
int lpt_ofisa_md_match(device_t, cfdata_t, void *);
int lpt_ofisa_md_intr_fixup(device_t, device_t, void *,
struct ofisa_intr_desc *, int, int);
#define _WDC_OFISA_MD_MATCH
#define _WDC_OFISA_MD_INTR_FIXUP
int wdc_ofisa_md_match(struct device *, struct cfdata *, void *);
int wdc_ofisa_md_intr_fixup(struct device *, struct device*, void *,
int wdc_ofisa_md_match(device_t, cfdata_t, void *);
int wdc_ofisa_md_intr_fixup(device_t, device_t, void *,
struct ofisa_intr_desc *, int, int);
#endif /* COMPAT_OLD_OFW */
/* The following aren't dependent on old OpenFirmware. */
#define _CS_OFISA_MD_CFGFLAGS_FIXUP
int cs_ofisa_md_cfgflags_fixup(struct device *, struct device *,
void *);
int cs_ofisa_md_cfgflags_fixup(device_t, device_t, void *);

134
sys/arch/arm/include/param.h
View File

@@ -1,4 +1,4 @@
/* $NetBSD: param.h,v 1.17 2012/08/03 08:11:40 matt Exp $ */
/* $NetBSD: param.h,v 1.19 2013/10/26 18:07:52 matt Exp $ */
/*
* Copyright (c) 1994,1995 Mark Brinicombe.
@@ -52,29 +52,97 @@
*/
#if defined(_KERNEL)
#ifndef MACHINE_ARCH /* XXX For now */
#ifndef __ARMEB__
#define _MACHINE_ARCH arm
#define MACHINE_ARCH "arm"
# ifndef MACHINE_ARCH /* XXX For now */
# ifndef __ARMEB__
# ifdef __ARM_EABI__
# define _MACHINE_ARCH earm
# define MACHINE_ARCH "earm"
# else
# define _MACHINE_ARCH arm
# define MACHINE_ARCH "arm"
# endif
# else
# ifdef __ARM_EABI__
# define _MACHINE_ARCH earmeb
# define MACHINE_ARCH "earmeb"
# else
# define _MACHINE_ARCH armeb
# define MACHINE_ARCH "armeb"
# endif
# endif /* __ARMEB__ */
# endif /* MACHINE_ARCH */
#else
#define _MACHINE_ARCH armeb
#define MACHINE_ARCH "armeb"
#endif /* __ARMEB__ */
#endif /* MACHINE_ARCH */
#else
#undef _MACHINE
#undef MACHINE
#undef _MACHINE_ARCH
#undef MACHINE_ARCH
#define _MACHINE arm
#define MACHINE "arm"
#ifndef __ARMEB__
#define _MACHINE_ARCH arm
#define MACHINE_ARCH "arm"
#else
#define _MACHINE_ARCH armeb
#define MACHINE_ARCH "armeb"
#endif /* __ARMEB__ */
# undef _MACHINE
# undef MACHINE
# undef _MACHINE_ARCH
# undef MACHINE_ARCH
# define _MACHINE arm
# define MACHINE "arm"
# ifndef __ARMEB__
# ifdef __ARM_EABI__
# ifdef __ARM_PCS_VFP
# ifdef _ARM_ARCH_7
# define _MACHINE_ARCH earmv7hf
# define MACHINE_ARCH "earmv7hf"
# elif defined(_ARM_ARCH_6)
# define _MACHINE_ARCH earmv6hf
# define MACHINE_ARCH "earmv6hf"
# else
# define _MACHINE_ARCH earmhf
# define MACHINE_ARCH "earmhf"
# endif
# else
# ifdef _ARM_ARCH_7
# define _MACHINE_ARCH earmv7
# define MACHINE_ARCH "earmv7"
# elif defined(_ARM_ARCH_6)
# define _MACHINE_ARCH earmv6
# define MACHINE_ARCH "earmv6"
# elif !defined(_ARM_ARCH_5T)
# define _MACHINE_ARCH earmv4
# define MACHINE_ARCH "earmv4"
# else
# define _MACHINE_ARCH earm
# define MACHINE_ARCH "earm"
# endif
# endif
# else
# define _MACHINE_ARCH arm
# define MACHINE_ARCH "arm"
# endif
# else
# ifdef __ARM_EABI__
# ifdef __ARM_PCS_VFP
# ifdef _ARM_ARCH_7
# define _MACHINE_ARCH earmv7hfeb
# define MACHINE_ARCH "earmv7hfeb"
# elif defined(_ARM_ARCH_6)
# define _MACHINE_ARCH earmv6hfeb
# define MACHINE_ARCH "earmv6hfeb"
# else
# define _MACHINE_ARCH earmhfeb
# define MACHINE_ARCH "earmhfeb"
# endif
# else
# ifdef _ARM_ARCH_7
# define _MACHINE_ARCH earmv7eb
# define MACHINE_ARCH "earmv7eb"
# elif defined(_ARM_ARCH_6)
# define _MACHINE_ARCH earmv6eb
# define MACHINE_ARCH "earmv6eb"
# elif !defined(_ARM_ARCH_5T)
# define _MACHINE_ARCH earmv4eb
# define MACHINE_ARCH "earmv4eb"
# else
# define _MACHINE_ARCH earmeb
# define MACHINE_ARCH "earmeb"
# endif
# endif
# else
# define _MACHINE_ARCH armeb
# define MACHINE_ARCH "armeb"
# endif
# endif /* __ARMEB__ */
#endif /* !_KERNEL */
#define MID_MACHINE MID_ARM6
@@ -124,20 +192,8 @@
#endif
#endif /* _KERNEL */
#ifdef __minix
/* Minix expect to find in this file PAGE_* defines. */
#include <machine/vmparam.h>
#define PGSHIFT 12 /* LOG2(NBPG) */
#define NBPG (1 << PGSHIFT) /* bytes/page */
#define PGOFSET (NBPG-1) /* byte offset into page */
#define arm_round_page(x) ((((paddr_t)(x)) + PGOFSET) & ~PGOFSET)
#define arm_trunc_page(x) ((paddr_t)(x) & ~PGOFSET)
#define trunc_page(x) arm_trunc_page(x)
#define round_page(x) arm_round_page(x)
#endif
#if defined(__minix)
/* LSC: FIXME This is a hack. Good enough for now, as we only have ARMv7 targets. */
#include <arm/arm32/param.h>
#endif /* defined(__minix) */
#endif /* _ARM_PARAM_H_ */

8
sys/arch/arm/include/pcb.h
View File

@@ -37,7 +37,6 @@
#define _ARM_PCB_H_
#include <machine/frame.h>
#include <machine/fp.h>
#include <arm/arm32/pte.h>
#include <arm/reg.h>
@@ -71,7 +70,7 @@ struct pcb_arm32 {
#define pcb_cstate pcb_un.un_32.pcb32_cstate
#define pcb_user_pid_rw pcb_un.un_32.pcb32_user_pid_rw
#ifdef __PROG32
#define pcb_sp pcb_un.un_32.pcb32_sp
#define pcb_ksp pcb_un.un_32.pcb32_sp
#endif
struct pcb_arm26 {
@@ -79,7 +78,7 @@ struct pcb_arm26 {
};
#define pcb_sf pcb_un.un_26.pcb26_sf
#ifdef __PROG26
#define pcb_sp pcb_sf.sf_r13
#define pcb_ksp pcb_sf.sf_r13
#endif
/*
@@ -92,10 +91,9 @@ struct pcb {
struct pcb_arm26 un_26;
} pcb_un;
void * pcb_onfault; /* On fault handler */
struct fpe_sp_state pcb_fpstate; /* FPA Floating Point state */
struct vfpreg pcb_vfp; /* VFP registers */
struct vfpreg pcb_kernel_vfp; /* kernel VFP state */
};
#define pcb_ff pcb_fpstate /* for arm26 */
/*
* No additional data for core dumps.

7
sys/arch/arm/include/proc.h
View File

@@ -1,4 +1,4 @@
/* $NetBSD: proc.h,v 1.12 2012/08/16 17:35:01 matt Exp $ */
/* $NetBSD: proc.h,v 1.15 2013/09/11 04:24:48 matt Exp $ */
/*
* Copyright (c) 1994 Mark Brinicombe.
@@ -48,14 +48,17 @@ struct mdlwp {
};
/* Flags setttings for md_flags */
#define MDLWP_VFPUSED 0x00000001 /* Process used the VFP */
#define MDLWP_NOALIGNFLT 0x00000002 /* For EXEC_AOUT */
#define MDLWP_VFPINTR 0x00000004 /* VFP used in intr */
struct mdproc {
void (*md_syscall)(struct trapframe *, struct lwp *, uint32_t);
int pmc_enabled; /* bitfield of enabled counters */
void *pmc_state; /* port-specific pmc state */
char md_march[12]; /* machine arch of executable */
};
#define PROC0_MD_INITIALIZERS .p_md = { .md_march = MACHINE_ARCH },
#endif /* _ARM32_PROC_H_ */

64
sys/arch/arm/include/profile.h
View File

@@ -1,4 +1,4 @@
/* $NetBSD: profile.h,v 1.8 2008/08/29 19:08:29 matt Exp $ */
/* $NetBSD: profile.h,v 1.13 2013/11/30 21:07:59 joerg Exp $ */
/*
* Copyright (c) 2001 Ben Harris
@@ -39,24 +39,20 @@
*/
#define MCOUNT_ASM_NAME "__mcount"
#ifdef PIC
#define PLTSYM "(PLT)"
#endif
#ifndef PLTSYM
#define PLTSYM
#endif
#if !defined(__ARM_EABI__)
#define MCOUNT \
__asm(".text"); \
__asm(".text"); \
__asm(".align 0"); \
__asm(".arm"); \
__asm(".type " MCOUNT_ASM_NAME ",%function"); \
__asm(".global " MCOUNT_ASM_NAME); \
__asm(".global " MCOUNT_ASM_NAME); \
__asm(MCOUNT_ASM_NAME ":"); \
/* \
* Preserve registers that are trashed during mcount \
*/ \
__asm("stmfd sp!, {r0-r3, ip, lr}"); \
__asm("push {r0-r3, ip, lr}"); \
/* Check what mode we're in. EQ => 32, NE => 26 */ \
__asm("teq r0, r0"); \
__asm("teq pc, r15"); \
@@ -80,7 +76,53 @@
/* \
* Restore registers that were trashed during mcount \
*/ \
__asm("ldmfd sp!, {r0-r3, lr, pc}");
__asm("pop {r0-r3, pc}"); \
__asm(".size " MCOUNT_ASM_NAME ", .-" MCOUNT_ASM_NAME);
#else
#define MCOUNT \
__asm(".text"); \
__asm(".align 0"); \
__asm(".arm"); \
__asm(".type " MCOUNT_ASM_NAME ",%function"); \
__asm(".global " MCOUNT_ASM_NAME); \
__asm(MCOUNT_ASM_NAME ":"); \
__asm(".fnstart"); \
__asm(".cfi_startproc"); \
/* \
* Preserve registers that are trashed during mcount \
*/ \
__asm("push {r0-r4, ip, lr}"); \
__asm(".save {r0-r4, lr}"); \
__asm(".cfi_def_cfa_offset 24"); \
__asm(".cfi_offset 14, -4"); \
__asm(".cfi_offset 4, -8"); \
__asm(".cfi_offset 3, -12"); \
__asm(".cfi_offset 2, -16"); \
__asm(".cfi_offset 1, -20"); \
__asm(".cfi_offset 0, -24"); \
/* \
* find the return address for mcount, \
* and the return address for mcount's caller. \
* \
* frompcindex = pc pushed by call into self. \
*/ \
__asm("mov r0, ip"); \
/* \
* selfpc = pc pushed by mcount call \
*/ \
__asm("mov r1, lr"); \
/* \
* Call the real mcount code \
*/ \
__asm("bl " ___STRING(_C_LABEL(_mcount)) PLTSYM); \
/* \
* Restore registers that were trashed during mcount \
*/ \
__asm("pop {r0-r4, lr, pc}"); \
__asm(".cfi_endproc"); \
__asm(".fnend"); \
__asm(".size " MCOUNT_ASM_NAME ", .-" MCOUNT_ASM_NAME);
#endif
#ifdef _KERNEL
#ifdef __PROG26

9
sys/arch/arm/include/ptrace.h
View File

@@ -1,4 +1,4 @@
/* $NetBSD: ptrace.h,v 1.5 2008/01/25 11:59:20 skrll Exp $ */
/* $NetBSD: ptrace.h,v 1.6 2012/12/05 19:05:46 matt Exp $ */
/*
* Copyright (c) 1995 Frank Lancaster
@@ -39,12 +39,15 @@
#endif
#define PT_GETREGS (PT_FIRSTMACH + 1)
#define PT_SETREGS (PT_FIRSTMACH + 2)
#define PT_GETFPREGS (PT_FIRSTMACH + 3)
#define PT_SETFPREGS (PT_FIRSTMACH + 4)
/* 3 and 4 are for FPE registers */
#define PT_GETFPREGS (PT_FIRSTMACH + 5)
#define PT_SETFPREGS (PT_FIRSTMACH + 6)
#define PT_MACHDEP_STRINGS \
"(unused)", \
"PT_GETREGS", \
"PT_SETREGS", \
"old PT_GETFPREGS", \
"old PT_SETFPREGS", \
"PT_GETFPREGS", \
"PT_SETFPREGS",

16
sys/arch/arm/include/reg.h
View File

@@ -1,4 +1,4 @@
/* $NetBSD: reg.h,v 1.2 2008/03/15 10:16:43 rearnsha Exp $ */
/* $NetBSD: reg.h,v 1.5 2013/01/11 14:04:55 matt Exp $ */
/*
* Copyright (C) 1994, 1995 Frank Lancaster
@@ -36,8 +36,6 @@
#ifndef _ARM32_REG_H_
#define _ARM32_REG_H_
#include <machine/fp.h>
struct reg {
unsigned int r[13];
unsigned int r_sp;
@@ -46,17 +44,17 @@ struct reg {
unsigned int r_cpsr;
};
struct fpreg {
unsigned int fpr_fpsr;
fp_reg_t fpr[8];
};
struct vfpreg {
uint32_t vfp_fpexc;
uint32_t vfp_fpscr;
uint32_t vfp_fpinst;
uint32_t vfp_fpinst2;
uint32_t vfp_regs[33]; /* In case we need fstmx format. */
uint64_t vfp_regs[33]; /* In case we need fstmx format. */
};
struct fpreg {
struct vfpreg fpr_vfp;
};
#endif /* !_ARM32_REG_H_ */

33
sys/arch/arm/include/setjmp.h
View File

@@ -1,4 +1,4 @@
/* $NetBSD: setjmp.h,v 1.4 2011/06/30 20:09:20 wiz Exp $ */
/* $NetBSD: setjmp.h,v 1.5 2013/01/11 13:56:32 matt Exp $ */
/*
* machine/setjmp.h: machine dependent setjmp-related information.
@@ -15,11 +15,7 @@
* Description of the setjmp buffer
*
* word 0 magic number (dependent on creator)
* 1 - 3 f4 fp register 4
* 4 - 6 f5 fp register 5
* 7 - 9 f6 fp register 6
* 10 - 12 f7 fp register 7
* 13 fpsr fp status register
* 13 fpscr vfp status control register
* 14 r4 register 4
* 15 r5 register 5
* 16 r6 register 6
@@ -35,6 +31,14 @@
* 26 (con't)
* 27 (con't)
* 28 (con't)
* 32-33 d8 (vfp register d8)
* 34-35 d9 (vfp register d9)
* 36-37 d10 (vfp register d10)
* 38-39 d11 (vfp register d11)
* 40-41 d12 (vfp register d12)
* 42-43 d13 (vfp register d13)
* 44-45 d14 (vfp register d14)
* 46-47 d15 (vfp register d15)
*
* The magic number number identifies the jmp_buf and
* how the buffer was created as well as providing
@@ -56,15 +60,13 @@
#define _JB_MAGIC__SETJMP 0x4278f500
#define _JB_MAGIC_SETJMP 0x4278f501
#define _JB_MAGIC__SETJMP_VFP 0x4278f502
#define _JB_MAGIC_SETJMP_VFP 0x4278f503
/* Valid for all jmp_buf's */
#define _JB_MAGIC 0
#define _JB_REG_F4 1
#define _JB_REG_F5 4
#define _JB_REG_F6 7
#define _JB_REG_F7 10
#define _JB_REG_FPSR 13
#define _JB_REG_FPSCR 13
#define _JB_REG_R4 14
#define _JB_REG_R5 15
#define _JB_REG_R6 16
@@ -80,3 +82,12 @@
/* Only valid with the _JB_MAGIC_SETJMP magic */
#define _JB_SIGMASK 25
#define _JB_REG_D8 32
#define _JB_REG_D9 34
#define _JB_REG_D10 36
#define _JB_REG_D11 38
#define _JB_REG_D12 40
#define _JB_REG_D13 42
#define _JB_REG_D14 44
#define _JB_REG_D15 46

10
sys/arch/arm/include/sysarch.h
View File

@@ -1,4 +1,4 @@
/* $NetBSD: sysarch.h,v 1.8 2012/08/12 05:05:47 matt Exp $ */
/* $NetBSD: sysarch.h,v 1.10 2013/02/01 15:23:11 matt Exp $ */
/*
* Copyright (c) 1996-1997 Mark Brinicombe.
@@ -41,6 +41,9 @@
* Pickup definition of uintptr_t
*/
#include <sys/stdint.h>
#ifndef _KERNEL
#include <stdbool.h>
#endif
/*
* Architecture specific syscalls (arm)
@@ -49,6 +52,7 @@
#define ARM_SYNC_ICACHE 0
#define ARM_DRAIN_WRITEBUF 1
#define ARM_VFP_FPSCR 2
#define ARM_FPU_USED 3
struct arm_sync_icache_args {
uintptr_t addr; /* Virtual start address */
@@ -60,6 +64,10 @@ struct arm_vfp_fpscr_args {
uint32_t fpscr_set; /* bits to set */
};
struct arm_unaligned_faults_args {
bool enabled; /* unaligned faults are enabled */
};
#ifndef _KERNEL
__BEGIN_DECLS
int arm_sync_icache(u_int addr, int len);

4
sys/arch/arm/include/types.h
View File

@@ -1,4 +1,4 @@
/* $NetBSD: types.h,v 1.23 2012/08/12 05:05:47 matt Exp $ */
/* $NetBSD: types.h,v 1.25 2013/07/02 05:57:00 matt Exp $ */
/*
* Copyright (c) 1990 The Regents of the University of California.
@@ -67,6 +67,7 @@ typedef int register_t, register32_t;
typedef unsigned long pmc_evid_t;
#define PMC_INVALID_EVID (-1)
typedef unsigned long pmc_ctr_t;
typedef unsigned short tlb_asid_t;
/*
* This should have always been an 8-bit type, but since it's been exposed
@@ -90,6 +91,7 @@ typedef volatile int __cpu_simple_lock_t;
#if !defined(__minix)
#define __HAVE_TLS_VARIANT_I
#endif /* !defined(__minix) */
#define __HAVE_OLD_DISKLABEL
#if defined(_KERNEL) || defined(_KMEMUSER)
#define PCU_FPU 0

27
sys/arch/arm/include/vfpreg.h
View File

@@ -1,4 +1,4 @@
/* $NetBSD: vfpreg.h,v 1.6 2012/09/22 19:45:53 matt Exp $ */
/* $NetBSD: vfpreg.h,v 1.10 2013/08/02 01:59:00 matt Exp $ */
/*
* Copyright (c) 2008 ARM Ltd
@@ -63,20 +63,29 @@
#define FPU_VFP_CORTEXA7 0x41023070
#define FPU_VFP_CORTEXA8 0x410330c0
#define FPU_VFP_CORTEXA9 0x41033090
#define FPU_VFP_CORTEXA15 0x410330f0
#define VFP_FPEXC_EX 0x80000000 /* Exception status bit */
#define VFP_FPEXC_EX 0x80000000 /* EXception status bit */
#define VFP_FPEXC_EN 0x40000000 /* VFP Enable bit */
#define VFP_FPEXC_FP2V 0x10000000 /* FPINST2 instruction valid */
#define VFP_FPEXC_VECITR 0x00000700 /* Vector iteration count */
#define VFP_FPEXC_INV 0x00000080 /* Input exception flag */
#define VFP_FPEXC_UFC 0x00000080 /* Potential underflow flag */
#define VFP_FPEXC_OFC 0x00000080 /* Potential overflow flag */
#define VFP_FPEXC_IOC 0x00000080 /* Potential inv. op. flag */
#define VFP_FPEXC_DEX 0x20000000 /* Defined sync EXception bit */
#define VFP_FPEXC_FP2V 0x10000000 /* FPinst2 instruction Valid */
#define VFP_FPEXC_VV 0x08000000 /* Vecitr Valid */
#define VFP_FPEXC_TFV 0x04000000 /* Trapped Fault Valid */
#define VFP_FPEXC_VECITR 0x00000700 /* VECtor ITeRation count */
#define VFP_FPEXC_IDF 0x00000080 /* Input Denormal flag */
#define VFP_FPEXC_IXF 0x00000010 /* Potential inexact flag */
#define VFP_FPEXC_UFF 0x00000008 /* Potential underflow flag */
#define VFP_FPEXC_OFF 0x00000004 /* Potential overflow flag */
#define VFP_FPEXC_DZF 0x00000002 /* Potential DivByZero flag */
#define VFP_FPEXC_IOF 0x00000001 /* Potential inv. op. flag */
#define VFP_FPEXE_FSUM 0x000000ff /* all flag bits */
#define VFP_FPSCR_N 0x80000000 /* set if compare <= result */
#define VFP_FPSCR_Z 0x40000000 /* set if compare = result */
#define VFP_FPSCR_C 0x20000000 /* set if compare (=,>=,UNORD) result */
#define VFP_FPSCR_V 0x10000000 /* set if compare UNORD result */
#define VFP_FPSCR_QC 0x08000000 /* Cumulative saturation (SIMD) */
#define VFP_FPSCR_AHP 0x04000000 /* Alternative Half-Precision */
#define VFP_FPSCR_DN 0x02000000 /* Default NaN mode */
#define VFP_FPSCR_FZ 0x01000000 /* Flush-to-zero mode */
#define VFP_FPSCR_RMODE 0x00c00000 /* Rounding Mode */
@@ -91,7 +100,7 @@
#define VFP_FPSCR_IXE 0x00001000 /* Inexact Exception Enable */
#define VFP_FPSCR_UFE 0x00000800 /* Underflow Exception Enable */
#define VFP_FPSCR_OFE 0x00000400 /* Overflow Exception Enable */
#define VFP_FPSCR_DZE 0x00000200 /* Inexact Exception Enable */
#define VFP_FPSCR_DZE 0x00000200 /* DivByZero Exception Enable */
#define VFP_FPSCR_IOE 0x00000100 /* Invalid Operation Cumulative Flag */
#define VFP_FPSCR_IDC 0x00000080 /* Input Subnormal Cumlative Flag */
#define VFP_FPSCR_CSUM 0x0000001f /* IXC|UFC|OFC|DZC|IOC */

3
sys/arch/arm/include/vmparam.h Normal file
View File

@@ -0,0 +1,3 @@
/* $NetBSD: vmparam.h,v 1.3 2013/05/01 12:00:51 matt Exp $ */
#include <arm/arm32/vmparam.h>

30
sys/arch/arm/include/wchar_limits.h
View File

@@ -1,4 +1,4 @@
/* $NetBSD: wchar_limits.h,v 1.3 2008/04/28 20:23:14 martin Exp $ */
/* $NetBSD: wchar_limits.h,v 1.4 2013/01/24 10:17:00 matt Exp $ */
/*-
* Copyright (c) 2004 The NetBSD Foundation, Inc.
@@ -37,11 +37,39 @@
*/
/* limits of wchar_t */
#ifdef __WCHAR_MIN__
#define WCHAR_MIN __WCHAR_MIN__ /* wchar_t */
#elif __WCHAR_UNSIGNED__
#define WCHAR_MIN 0U /* wchar_t */
#else
#define WCHAR_MIN (-0x7fffffff-1) /* wchar_t */
#endif
#ifdef __WCHAR_MAX__
#define WCHAR_MAX __WCHAR_MAX__ /* wchar_t */
#elif __WCHAR_UNSIGNED__
#define WCHAR_MAX 0xffffffffU /* wchar_t */
#else
#define WCHAR_MAX 0x7fffffff /* wchar_t */
#endif
/* limits of wint_t */
#ifdef __WINT_MIN__
#define WINT_MIN __WINT_MIN__ /* wint_t */
#elif __WINT_UNSIGNED__
#define WINT_MIN 0U /* wint_t */
#else
#define WINT_MIN (-0x7fffffff-1) /* wint_t */
#endif
#ifdef __WINT_MAX__
#define WINT_MAX __WINT_MAX__ /* wint_t */
#elif __WINT_UNSIGNED__
#define WINT_MAX 0xffffffffU /* wint_t */
#else
#define WINT_MAX 0x7fffffff /* wint_t */
#endif
#endif /* !_ARM_WCHAR_LIMITS_H_ */