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FPU context switching support by Evgeniy Ivanov.

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This commit is contained in:
Ben Gras
2009-12-02 13:01:48 +00:00
parent fce9fd4b4e
commit bd42705433
25 changed files with 434 additions and 147 deletions
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114
include/sys/sigcontext.h
View File

@@ -23,30 +23,10 @@
* be added in a different struct.
*/
#if (_MINIX_CHIP == _CHIP_INTEL)
struct sigregs {
#if _WORD_SIZE == 4
short sr_gs;
short sr_fs;
#endif /* _WORD_SIZE == 4 */
short sr_es;
short sr_ds;
int sr_di;
int sr_si;
int sr_bp;
int sr_st; /* stack top -- used in kernel */
int sr_bx;
int sr_dx;
int sr_cx;
int sr_retreg;
int sr_retadr; /* return address to caller of save -- used
* in kernel */
int sr_pc;
int sr_cs;
int sr_psw;
int sr_sp;
int sr_ss;
};
#include <sys/stackframe.h>
#include <sys/fpu.h>
typedef struct stackframe_s sigregs;
struct sigframe { /* stack frame created for signalled process */
_PROTOTYPE( void (*sf_retadr), (void) );
int sf_signo;
@@ -57,85 +37,43 @@ struct sigframe { /* stack frame created for signalled process */
struct sigcontext *sf_scpcopy;
};
#else
#if (_MINIX_CHIP == _CHIP_M68000)
struct sigregs {
long sr_retreg; /* d0 */
long sr_d1;
long sr_d2;
long sr_d3;
long sr_d4;
long sr_d5;
long sr_d6;
long sr_d7;
long sr_a0;
long sr_a1;
long sr_a2;
long sr_a3;
long sr_a4;
long sr_a5;
long sr_a6;
long sr_sp; /* also known as a7 */
long sr_pc;
short sr_psw;
short sr_dummy; /* make size multiple of 4 for system.c */
};
#else
#include "error, _MINIX_CHIP is not supported"
#endif
#endif /* _MINIX_CHIP == _CHIP_INTEL */
struct sigcontext {
int sc_flags; /* sigstack state to restore */
int sc_flags; /* sigstack state to restore (including MF_FPU_INITIALIZED) */
long sc_mask; /* signal mask to restore */
struct sigregs sc_regs; /* register set to restore */
sigregs sc_regs; /* register set to restore */
#if (_MINIX_CHIP == _CHIP_INTEL)
union fpu_state_u fpu_state;
#endif
};
#if (_MINIX_CHIP == _CHIP_INTEL)
#if _WORD_SIZE == 4
#define sc_gs sc_regs.sr_gs
#define sc_fs sc_regs.sr_fs
#define sc_gs sc_regs.gs
#define sc_fs sc_regs.fs
#endif /* _WORD_SIZE == 4 */
#define sc_es sc_regs.sr_es
#define sc_ds sc_regs.sr_ds
#define sc_di sc_regs.sr_di
#define sc_si sc_regs.sr_si
#define sc_fp sc_regs.sr_bp
#define sc_st sc_regs.sr_st /* stack top -- used in kernel */
#define sc_bx sc_regs.sr_bx
#define sc_dx sc_regs.sr_dx
#define sc_cx sc_regs.sr_cx
#define sc_retreg sc_regs.sr_retreg
#define sc_retadr sc_regs.sr_retadr /* return address to caller of
#define sc_es sc_regs.es
#define sc_ds sc_regs.ds
#define sc_di sc_regs.di
#define sc_si sc_regs.si
#define sc_fp sc_regs.bp
#define sc_st sc_regs.st /* stack top -- used in kernel */
#define sc_bx sc_regs.bx
#define sc_dx sc_regs.dx
#define sc_cx sc_regs.cx
#define sc_retreg sc_regs.retreg
#define sc_retadr sc_regs.retadr /* return address to caller of
save -- used in kernel */
#define sc_pc sc_regs.sr_pc
#define sc_cs sc_regs.sr_cs
#define sc_psw sc_regs.sr_psw
#define sc_sp sc_regs.sr_sp
#define sc_ss sc_regs.sr_ss
#define sc_pc sc_regs.pc
#define sc_cs sc_regs.cs
#define sc_psw sc_regs.psw
#define sc_sp sc_regs.sp
#define sc_ss sc_regs.ss
#endif /* _MINIX_CHIP == _CHIP_INTEL */
#if (_MINIX_CHIP == M68000)
#define sc_retreg sc_regs.sr_retreg
#define sc_d1 sc_regs.sr_d1
#define sc_d2 sc_regs.sr_d2
#define sc_d3 sc_regs.sr_d3
#define sc_d4 sc_regs.sr_d4
#define sc_d5 sc_regs.sr_d5
#define sc_d6 sc_regs.sr_d6
#define sc_d7 sc_regs.sr_d7
#define sc_a0 sc_regs.sr_a0
#define sc_a1 sc_regs.sr_a1
#define sc_a2 sc_regs.sr_a2
#define sc_a3 sc_regs.sr_a3
#define sc_a4 sc_regs.sr_a4
#define sc_a5 sc_regs.sr_a5
#define sc_fp sc_regs.sr_a6
#define sc_sp sc_regs.sr_sp
#define sc_pc sc_regs.sr_pc
#define sc_psw sc_regs.sr_psw
#endif /* _MINIX_CHIP == M68000 */
_PROTOTYPE( int sigreturn, (struct sigcontext *_scp) );
#endif /* _SIGCONTEXT_H */

8
include/sys/vm_i386.h
View File

@@ -70,9 +70,17 @@ sys/vm_i386.h
#define I386_VM_PFE_U 0x04 /* CPU in user mode (otherwise supervisor) */
/* CPUID flags */
#define CPUID1_EDX_FPU (1L) /* FPU presence */
#define CPUID1_EDX_PSE (1L << 3) /* Page Size Extension */
#define CPUID1_EDX_PGE (1L << 13) /* Page Global (bit) Enable */
#define CPUID1_EDX_APIC_ON_CHIP (1L << 9) /* APIC is present on the chip */
#define CPUID1_EDX_TSC (1L << 4) /* Timestamp counter present */
#define CPUID1_EDX_FXSR (1L << 24)
#define CPUID1_EDX_SSE (1L << 25)
#define CPUID1_EDX_SSE2 (1L << 26)
#define CPUID1_ECX_SSE3 (1L)
#define CPUID1_ECX_SSSE3 (1L << 9)
#define CPUID1_ECX_SSE4_1 (1L << 19)
#define CPUID1_ECX_SSE4_2 (1L << 20)
#endif /* __SYS_VM_386_H__ */