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align ARM cpu.h importing & using armreg.h

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Change-Id: I4793517d936f71b0bb7088fbfe67e73a65fafb11
This commit is contained in:
Ben Gras
2013-12-10 19:51:07 +01:00
committed by Lionel Sambuc
parent 81473dbba0
commit f4f382d8c0
7 changed files with 1082 additions and 61 deletions
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1
kernel/arch/earm/arch_system.c
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@@ -9,6 +9,7 @@
#include <assert.h>
#include <signal.h>
#include <machine/vm.h>
#include <arm/armreg.h>
#include <minix/u64.h>

5
kernel/arch/earm/include/archconst.h
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@@ -5,10 +5,11 @@
#include <machine/interrupt.h>
#include <machine/memory.h>
#include <machine/cpu.h>
#include <arm/armreg.h>
/* Program stack words and masks. */
#define INIT_PSR (MODE_USR | PSR_F) /* initial psr */
#define INIT_TASK_PSR (MODE_SVC | PSR_F) /* initial psr for tasks */
#define INIT_PSR (PSR_USR32_MODE | PSR_F) /* initial psr */
#define INIT_TASK_PSR (PSR_SVC32_MODE | PSR_F) /* initial psr for tasks */
/* Exception vector numbers */
#define RESET_VECTOR 0

11
kernel/arch/earm/mpx.S
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@@ -27,6 +27,7 @@
#include <machine/multiboot.h>
#include <machine/ipcconst.h>
#include <machine/cpu.h>
#include <arm/armreg.h>
#include "bsp_intr.h"
#include "arch_proto.h" /* K_STACK_SIZE */
@@ -46,11 +47,11 @@ IMPORT(svc_stack)
*/
.macro switch_to_svc lr_offset
sub lr, lr, #\lr_offset /* do the adjustment */
srsdb sp!, #MODE_SVC /* store the saved the return */
srsdb sp!, #PSR_SVC32_MODE /* store the saved the return */
/* address and program status */
/* register onto the kernel stack */
/* Also modify the stack pointer. */
cps #MODE_SVC /* do the switch to SVC. */
cps #PSR_SVC32_MODE /* do the switch to SVC. */
.endm
/*
@@ -63,8 +64,8 @@ IMPORT(svc_stack)
ldr r3, [sp, #8] /* get spsr. */
orr r3, r3, #(PSR_F | PSR_I) /* mask interrupts on return. */
str r3, [sp, #8] /* store spsr. */
and r3, r3, #PSR_MODE_MASK /* mask the ARM mode. */
cmp r3, #MODE_USR /* compare it to user mode. */
and r3, r3, #PSR_MODE /* mask the ARM mode. */
cmp r3, #PSR_USR32_MODE /* compare it to user mode. */
pop {r3}
bne \label /* In-kernel handling. */
.endm
@@ -171,7 +172,7 @@ irq_entry_from_kernel:
*/
ENTRY(svc_entry)
/* Store the LR and the SPSR of the current mode onto the SVC stack */
srsdb sp!, #MODE_SVC
srsdb sp!, #PSR_SVC32_MODE
save_process_ctx
/* save the pointer to the current process */

15
kernel/arch/earm/pg_utils.c
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@@ -5,6 +5,7 @@
#include "kernel/kernel.h"
#include "arch_proto.h"
#include <machine/cpu.h>
#include <arm/armreg.h>
#include <string.h>
#include <minix/type.h>
@@ -214,21 +215,21 @@ void vm_enable_paging(void)
sctlr = read_sctlr();
/* Enable MMU */
sctlr |= SCTLR_M;
sctlr |= CPU_CONTROL_MMU_ENABLE;
/* TRE set to zero (default reset value): TEX[2:0] are used, plus C and B bits.*/
sctlr &= ~SCTLR_TRE;
sctlr &= ~CPU_CONTROL_TR_ENABLE;
/* AFE set to zero (default reset value): not using simplified model. */
sctlr &= ~SCTLR_AFE;
sctlr &= ~CPU_CONTROL_AF_ENABLE;
/* Enable instruction ,data cache and branch prediction */
sctlr |= SCTLR_C;
sctlr |= SCTLR_I;
sctlr |= SCTLR_Z;
sctlr |= CPU_CONTROL_DC_ENABLE;
sctlr |= CPU_CONTROL_IC_ENABLE;
sctlr |= CPU_CONTROL_BPRD_ENABLE;
/* Enable barriers */
sctlr |= SCTLR_CP15BEN;
sctlr |= CPU_CONTROL_32BD_ENABLE;
/* Enable L2 cache (cortex-a8) */
#define CORTEX_A8_L2EN (0x02)