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align ARM cpu.h importing & using armreg.h

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Change-Id: I4793517d936f71b0bb7088fbfe67e73a65fafb11
This commit is contained in:
Ben Gras
2014-03-03 20:47:04 +01:00
committed by sambuc
parent 81473dbba0
commit f4f382d8c0
7 changed files with 1082 additions and 61 deletions
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kernel/arch/earm/pg_utils.c
+8 -7
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@@ -5,6 +5,7 @@
#include "kernel/kernel.h"
#include "arch_proto.h"
#include <machine/cpu.h>
#include <arm/armreg.h>
#include <string.h>
#include <minix/type.h>
@@ -214,21 +215,21 @@ void vm_enable_paging(void)
sctlr = read_sctlr();
/* Enable MMU */
sctlr |= SCTLR_M;
sctlr |= CPU_CONTROL_MMU_ENABLE;
/* TRE set to zero (default reset value): TEX[2:0] are used, plus C and B bits.*/
sctlr &= ~SCTLR_TRE;
sctlr &= ~CPU_CONTROL_TR_ENABLE;
/* AFE set to zero (default reset value): not using simplified model. */
sctlr &= ~SCTLR_AFE;
sctlr &= ~CPU_CONTROL_AF_ENABLE;
/* Enable instruction ,data cache and branch prediction */
sctlr |= SCTLR_C;
sctlr |= SCTLR_I;
sctlr |= SCTLR_Z;
sctlr |= CPU_CONTROL_DC_ENABLE;
sctlr |= CPU_CONTROL_IC_ENABLE;
sctlr |= CPU_CONTROL_BPRD_ENABLE;
/* Enable barriers */
sctlr |= SCTLR_CP15BEN;
sctlr |= CPU_CONTROL_32BD_ENABLE;
/* Enable L2 cache (cortex-a8) */
#define CORTEX_A8_L2EN (0x02)