User-space networking!
- RTL8139 driver moved to user-space; - PCI code moved to user-space; Fixed IRQ hook dump at IS server.
This commit is contained in:
Jorrit Herder
@@ -22,8 +22,7 @@ HEAD = mpx.o
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OBJS = start.o protect.o klibc.o klib.o table.o main.o proc.o \
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i8259.o exception.o system.o clock.o misc.o \
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dummy.o \
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rtl8139.o pci.o pci_table.o
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dummy.o
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SYS = system/system.a
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@@ -136,28 +135,6 @@ table.o: proc.h
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table.o: sendmask.h
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table.o: $b/int86.h
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rtl8139.o: $a
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rtl8139.o: $h/com.h
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rtl8139.o: $n/hton.h
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rtl8139.o: $g/ether.h
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rtl8139.o: $g/eth_io.h
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rtl8139.o: $i/stddef.h
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rtl8139.o: assert.h
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rtl8139.o: pci.h
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rtl8139.o: proc.h
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rtl8139.o: rtl8139.h
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pci.o: $a
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pci.o: assert.h
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pci.o: pci.h
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pci.o: pci_amd.h
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pci.o: pci_intel.h
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pci.o: pci_via.h
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pci.o: pci_sis.h
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pci_table.o: $a
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pci_table.o: pci.h
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dummy.o: $a
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system/system.a: $a $h/devio.h $h/com.h
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1227
kernel/pci.c
1227
kernel/pci.c
File diff suppressed because it is too large
Load Diff
97
kernel/pci.h
97
kernel/pci.h
@@ -1,97 +0,0 @@
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/*
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pci.h
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Created: Jan 2000 by Philip Homburg <philip@cs.vu.nl>
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*/
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#define PCI_VID 0x00 /* Vendor ID, 16-bit */
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#define PCI_DID 0x02 /* Device ID, 16-bit */
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#define PCI_CR 0x04 /* Command Register, 16-bit */
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#define PCI_PCISTS 0x06 /* PCI status, 16-bit */
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#define PSR_SSE 0x4000 /* Signaled System Error */
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#define PSR_RMAS 0x2000 /* Received Master Abort Status */
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#define PSR_RTAS 0x1000 /* Received Target Abort Status */
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#define PCI_PIFR 0x09 /* Prog. Interface Register */
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#define PCI_SCR 0x0A /* Sub-Class Register */
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#define PCI_BCR 0x0B /* Base-Class Register */
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#define PCI_HEADT 0x0E /* Header type, 8-bit */
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#define PHT_MULTIFUNC 0x80 /* Multiple functions */
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#define PCI_BAR 0x10 /* Base Address Register */
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#define PCI_ILR 0x3C /* Interrupt Line Register */
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#define PCI_IPR 0x3D /* Interrupt Pin Register */
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/* PCI bridge devices (AGP) */
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#define PPB_SBUSN 0x19 /* Secondary Bus Number */
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/* Intel compatible PCI bridge devices (AGP) */
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#define PPB_SSTS 0x1E /* Secondary PCI-to-PCI Status Register */
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#define NO_VID 0xffff /* No PCI card present */
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struct pci_vendor
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{
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u16_t vid;
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char *name;
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};
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struct pci_device
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{
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u16_t vid;
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u16_t did;
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char *name;
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};
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struct pci_baseclass
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{
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u8_t baseclass;
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char *name;
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};
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struct pci_subclass
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{
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u8_t baseclass;
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u8_t subclass;
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u16_t infclass;
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char *name;
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};
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struct pci_intel_ctrl
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{
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u16_t vid;
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u16_t did;
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};
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struct pci_isabridge
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{
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u16_t vid;
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u16_t did;
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int checkclass;
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int type;
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};
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struct pci_pcibridge
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{
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u16_t vid;
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u16_t did;
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int type;
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};
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#define PCI_IB_PIIX 1 /* Intel PIIX compatible ISA bridge */
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#define PCI_IB_VIA 2 /* VIA compatible ISA bridge */
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#define PCI_IB_AMD 3 /* AMD compatible ISA bridge */
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#define PCI_IB_SIS 4 /* SIS compatible ISA bridge */
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#define PCI_AGPB_INTEL 1 /* Intel compatible AGP bridge */
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#define PCI_AGPB_VIA 2 /* VIA compatible AGP bridge */
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extern struct pci_vendor pci_vendor_table[];
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extern struct pci_device pci_device_table[];
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extern struct pci_baseclass pci_baseclass_table[];
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extern struct pci_subclass pci_subclass_table[];
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extern struct pci_intel_ctrl pci_intel_ctrl[];
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extern struct pci_isabridge pci_isabridge[];
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extern struct pci_pcibridge pci_pcibridge[];
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/*
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* $PchId: pci.h,v 1.4 2001/12/06 20:21:22 philip Exp $
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*/
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@@ -1,21 +0,0 @@
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/*
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pci_amd.h
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Created: Nov 2001 by Philip Homburg <philip@cs.vu.nl>
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*/
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#define AMD_ISABR_FUNC 3 /* Registers are in function 3 */
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#define AMD_ISABR_PCIIRQ_LEV 0x54
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#define AMD_PCILEV_INTA 0x1
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#define AMD_PCILEV_INTB 0x2
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#define AMD_PCILEV_INTC 4x2
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#define AMD_PCILEV_INTD 4x8
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#define AMD_ISABR_PCIIRQ_ROUTE 0x56
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#define AMD_PCIIRQ_INTA_MASK 0x000F
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#define AMD_PCIIRQ_INTB_MASK 0x00F0
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#define AMD_PCIIRQ_INTC_MASK 0x0F00
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#define AMD_PCIIRQ_INTD_MASK 0xF000
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/*
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* $PchId: pci_amd.h,v 1.1 2001/11/09 19:57:37 philip Exp $
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*/
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@@ -1,58 +0,0 @@
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/*
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pci_intel.h
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Created: Jan 2000 by Philip Homburg <philip@cs.vu.nl>
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*/
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#define PCII_CONFADD 0xCF8
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#define PCIIC_CODE 0x80000000
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#define PCIIC_BUSNUM_MASK 0xff0000
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#define PCIIC_BUSNUM_SHIFT 16
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#define PCIIC_DEVNUM_MASK 0xf800
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#define PCIIC_DEVNUM_SHIFT 11
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#define PCIIC_FUNCNUM_MASK 0x700
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#define PCIIC_FUNCNUM_SHIFT 8
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#define PCIIC_REGNUM_MASK 0xfc
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#define PCIIC_REGNUM_SHIFT 2
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#define PCII_CONFDATA 0xCFC
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#define PCII_SELREG_(bus, dev, func, reg) \
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(PCIIC_CODE | \
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(((bus) << PCIIC_BUSNUM_SHIFT) & PCIIC_BUSNUM_MASK) | \
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(((dev) << PCIIC_DEVNUM_SHIFT) & PCIIC_DEVNUM_MASK) | \
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(((func) << PCIIC_FUNCNUM_SHIFT) & PCIIC_FUNCNUM_MASK) | \
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((((reg)/4) << PCIIC_REGNUM_SHIFT) & PCIIC_REGNUM_MASK))
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#define PCII_UNSEL (0)
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#define PCII_RREG8_(bus, dev, func, reg) \
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(outl(PCII_CONFADD, PCII_SELREG_(bus, dev, func, reg)), \
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inb(PCII_CONFDATA+((reg)&3)))
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#define PCII_RREG16_(bus, dev, func, reg) \
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(PCII_RREG8_(bus, dev, func, reg) | \
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(PCII_RREG8_(bus, dev, func, reg+1) << 8))
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#define PCII_RREG32_(bus, dev, func, reg) \
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(PCII_RREG16_(bus, dev, func, reg) | \
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(PCII_RREG16_(bus, dev, func, reg+2) << 16))
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#define PCII_WREG8_(bus, dev, func, reg, val) \
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(outl(PCII_CONFADD, PCII_SELREG_(bus, dev, func, reg)), \
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outb(PCII_CONFDATA+((reg)&3), (val)))
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#define PCII_WREG16_(bus, dev, func, reg, val) \
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(PCII_WREG8_(bus, dev, func, reg, (val)), \
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(PCII_WREG8_(bus, dev, func, reg+1, (val) >> 8)))
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#define PCII_WREG32_(bus, dev, func, reg, val) \
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(PCII_WREG16_(bus, dev, func, reg, (val)), \
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(PCII_WREG16_(bus, dev, func, reg+2, (val) >> 16)))
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/* PIIX configuration registers */
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#define PIIX_PIRQRCA 0x60
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#define PIIX_IRQ_DI 0x80
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#define PIIX_IRQ_MASK 0x0F
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/* PIIX extensions to the PIC */
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#define PIIX_ELCR1 0x4D0
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#define PIIX_ELCR2 0x4D1
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/*
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* $PchId: pci_intel.h,v 1.1 2000/08/12 11:20:17 philip Exp $
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*/
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@@ -1,17 +0,0 @@
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/*
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pci_sis.h
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Created: Nov 2001 by Philip Homburg <philip@cs.vu.nl>
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*/
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/* Constants are taken from pci-irq.c in the Linux kernel source */
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#define SIS_ISABR_IRQ_A 0x41 /* IRQA routing */
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#define SIS_ISABR_IRQ_B 0x42 /* IRQB routing */
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#define SIS_ISABR_IRQ_C 0x43 /* IRQC routing */
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#define SIS_ISABR_IRQ_D 0x44 /* IRQD routing */
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#define SIS_IRQ_DISABLED 0x80
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#define SIS_IRQ_MASK 0x0F
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/*
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* $PchId: pci_sis.h,v 1.1 2001/12/06 20:22:52 philip Exp $
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*/
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@@ -1,251 +0,0 @@
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/*
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pci_table.c
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Tables with PCI vendor and device identifiers
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Created: Jan 2000 by Philip Homburg <philip@cs.vu.nl>
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See the Linux PCI ID Repository <http://pciids.sourceforge.net/>.
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*/
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/* Changes from original Minix 2.0.4 version (2003-09-05):
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* 2003-11-30 (kjb) Minix 2.0.4 FIX.TAZ add D-Link RTL8139 (0x1186, 0x1300)
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* 2004-08-08 (asw) add Intel 82371AB (0x8086, 0x7100)
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*/
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#include "kernel.h"
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#include "pci.h"
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#if __minix_vmd
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#include "config.h"
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#endif
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#if ENABLE_PCI
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struct pci_vendor pci_vendor_table[]=
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{
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{ 0x1000, "NCR" },
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{ 0x1002, "ATI Technologies" },
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{ 0x100B, "National Semiconductor Corporation" },
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{ 0x1013, "Cirrus Logic" },
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{ 0x1022, "Advanced Micro Devices" },
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{ 0x102B, "Matrox Graphics, Inc." },
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{ 0x1039, "Silicon Integrated Systems (SiS)" },
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{ 0x104C, "Texas Instruments" },
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{ 0x105A, "Promise Technology" },
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{ 0x10B7, "3Com Corporation" },
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{ 0x10B9, "AcerLabs (ALI)" },
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{ 0x10DE, "nVidia Corporation" },
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{ 0x10EC, "Realtek" },
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{ 0x1106, "VIA" },
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{ 0x110A, "Siemens Nixdorf AG" },
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{ 0x125D, "ESS Technology" },
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{ 0x1274, "Ensoniq" },
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{ 0x5333, "S3" },
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{ 0x8086, "Intel" },
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{ 0x9004, "Adaptec" },
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{ 0x9005, "Adaptec" },
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{ 0x0000, NULL }
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};
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struct pci_device pci_device_table[]=
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{
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{ 0x1000, 0x0001, "NCR 53C810" },
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{ 0x1000, 0x000F, "NCR 53C875" },
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{ 0x1002, 0x4752, "ATI Rage XL PCI" },
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{ 0x100B, 0xD001, "Nat. Semi. 87410" },
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{ 0x1013, 0x00B8, "Cirrus Logic GD 5446" },
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{ 0x1013, 0x6003, "Cirrus Logic CS4614/22/24 CrystalClear" },
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{ 0x1022, 0x700C, "AMD-762 CPU to PCI Bridge (SMP chipset)" },
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{ 0x1022, 0x700D, "AMD-762 CPU to PCI Bridge (AGP 4x)" },
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{ 0x1022, 0x7410, "AMD-766 PCI to ISA/LPC Bridge" },
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{ 0x1022, 0x7411, "AMD-766 EIDE Controller" },
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{ 0x102B, 0x051B, "Matrox MGA 2164W [Millennium II]" },
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{ 0x102B, 0x0525, "Matrox MGA G400 AGP" },
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{ 0x1039, 0x0008, "SiS 85C503/5513" },
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{ 0x1039, 0x0200, "SiS 5597/5598 VGA" },
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{ 0x1039, 0x0406, "SiS 85C501/2" },
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{ 0x1039, 0x5597, "SiS 5582" },
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{ 0x104C, 0xAC1C, "TI PCI1225" },
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{ 0x105A, 0x0D30, "Promise Technology 20265" },
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{ 0x10B7, 0x9058, "3Com 3c905B-Combo" },
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{ 0x10B7, 0x9805, "3Com 3c980-TX Python-T" },
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{ 0x10B9, 0x1533, "ALI M1533 ISA-bridge [Aladdin IV]" },
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{ 0x10B9, 0x1541, "ALI M1541" },
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{ 0x10B9, 0x5229, "ALI M5229 (IDE)" },
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{ 0x10B9, 0x5243, "ALI M5243" },
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{ 0x10B9, 0x7101, "ALI M7101 PMU" },
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{ 0x10DE, 0x0020, "nVidia Riva TnT [NV04]" },
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{ 0x10DE, 0x0110, "nVidia GeForce2 MX [NV11]" },
|
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{ 0x10EC, 0x8029, "Realtek RTL8029" },
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{ 0x10EC, 0x8139, "Realtek RTL8139" },
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{ 0x1106, 0x0305, "VIA VT8363/8365 [KT133/KM133]" },
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{ 0x1106, 0x0571, "VIA IDE controller" },
|
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{ 0x1106, 0x0686, "VIA VT82C686 (Apollo South Bridge)" },
|
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{ 0x1106, 0x3038, "VT83C572 PCI USB Controller" },
|
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{ 0x1106, 0x3057, "VT82C686A ACPI Power Management Controller" },
|
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{ 0x1106, 0x3058, "VIA AC97 Audio Controller" },
|
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{ 0x1106, 0x3059, "VIA AC97 Audio Controller" },
|
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{ 0x1106, 0x3074, "VIA VT8233" },
|
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{ 0x1106, 0x3099, "VIA VT8367 [KT266]" },
|
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{ 0x1106, 0x8305, "VIA VT8365 [KM133 AGP]" },
|
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{ 0x1106, 0xB099, "VIA VT8367 [KT266 AGP]" },
|
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{ 0x110A, 0x0005, "Siemens Nixdorf Tulip Cntlr., Power Management" },
|
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{ 0x1186, 0x1300, "D-Link RTL8139" },
|
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{ 0x125D, 0x1969, "ESS ES1969 Solo-1 Audiodrive" },
|
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{ 0x1274, 0x1371, "Ensoniq ES1371 [AudioPCI-97]" },
|
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{ 0x1274, 0x5000, "Ensoniq ES1370" },
|
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{ 0x1274, 0x5880, "Ensoniq CT5880 [AudioPCI]" },
|
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{ 0x5333, 0x8811, "S3 86c764/765 [Trio32/64/64V+]" },
|
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{ 0x5333, 0x883d, "S3 Virge/VX" },
|
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{ 0x5333, 0x88d0, "S3 Vision 964 vers 0" },
|
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{ 0x5333, 0x8a01, "S3 Virge/DX or /GX" },
|
||||
{ 0x8086, 0x1004, "Intel 82543GC Gigabit Ethernet Controller" },
|
||||
{ 0x8086, 0x1229, "Intel 82557" },
|
||||
{ 0x8086, 0x122D, "Intel 82437FX" },
|
||||
{ 0x8086, 0x122E, "Intel 82371FB (PIIX)" },
|
||||
{ 0x8086, 0x1230, "Intel 82371FB (IDE)" },
|
||||
{ 0x8086, 0x1237, "Intel 82441FX (440FX)" },
|
||||
{ 0x8086, 0x1250, "Intel 82439HX" },
|
||||
{ 0x8086, 0x7000, "Intel 82371SB" },
|
||||
{ 0x8086, 0x7010, "Intel 82371SB (IDE)" },
|
||||
{ 0x8086, 0x7020, "Intel 82371SB (USB)" },
|
||||
{ 0x8086, 0x7100, "Intel 82371AB" },
|
||||
{ 0x8086, 0x7110, "Intel 82371AB (PIIX4)" },
|
||||
{ 0x8086, 0x7111, "Intel 82371AB (IDE)" },
|
||||
{ 0x8086, 0x7112, "Intel 82371AB (USB)" },
|
||||
{ 0x8086, 0x7113, "Intel 82371AB (Power)" },
|
||||
{ 0x8086, 0x7190, "Intel 82443BX" },
|
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{ 0x8086, 0x7191, "Intel 82443BX (AGP bridge)" },
|
||||
{ 0x9004, 0x8178, "Adaptec AHA-2940U/2940UW Ultra/Ultra-Wide SCSI Ctrlr" },
|
||||
{ 0x9005, 0x0080, "Adaptec AIC-7892A Ultra160/m PCI SCSI Controller" },
|
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{ 0x0000, 0x0000, NULL }
|
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};
|
||||
|
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struct pci_baseclass pci_baseclass_table[]=
|
||||
{
|
||||
{ 0x00, "No device class" },
|
||||
{ 0x01, "Mass storage controller" },
|
||||
{ 0x02, "Network controller" },
|
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{ 0x03, "Display controller" },
|
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{ 0x04, "Multimedia device" },
|
||||
{ 0x05, "Memory controller" },
|
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{ 0x06, "Bridge device" },
|
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{ 0x07, "Simple comm. controller" },
|
||||
{ 0x08, "Base system peripheral" },
|
||||
{ 0x09, "Input device" },
|
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{ 0x0A, "Docking station" },
|
||||
{ 0x0B, "Processor" },
|
||||
{ 0x0C, "Serial bus controller" },
|
||||
{ 0x0d, "Wireless controller" },
|
||||
{ 0x0e, "Intelligent I/O controller" },
|
||||
{ 0x0f, "Satellite comm. controller" },
|
||||
{ 0x10, "Encryption/decryption controller" },
|
||||
{ 0x11, "Data acquisition controller" },
|
||||
{ 0xff, "Misc. device" },
|
||||
|
||||
{ 0x00, NULL }
|
||||
};
|
||||
|
||||
/* -1 in the infclass field is a wildcard for infclass */
|
||||
struct pci_subclass pci_subclass_table[]=
|
||||
{
|
||||
{ 0x00, 0x01, 0x00, "VGA-compatible device" },
|
||||
|
||||
{ 0x01, 0x00, 0x00, "SCSI bus controller" },
|
||||
{ 0x01, 0x01, -1, "IDE controller" },
|
||||
{ 0x01, 0x02, 0x00, "Floppy disk controller" },
|
||||
{ 0x01, 0x03, 0x00, "IPI controller" },
|
||||
{ 0x01, 0x04, 0x00, "RAID controller" },
|
||||
{ 0x01, 0x80, 0x00, "Other mass storage controller" },
|
||||
|
||||
{ 0x02, 0x00, 0x00, "Ethernet controller" },
|
||||
{ 0x02, 0x01, 0x00, "Token Ring controller" },
|
||||
{ 0x02, 0x02, 0x00, "FDDI controller" },
|
||||
{ 0x02, 0x03, 0x00, "ATM controller" },
|
||||
{ 0x02, 0x04, 0x00, "ISDN controller" },
|
||||
{ 0x02, 0x80, 0x00, "Other network controller" },
|
||||
|
||||
{ 0x03, 0x00, 0x00, "VGA-compatible controller" },
|
||||
{ 0x03, 0x00, 0x01, "8514-compatible controller" },
|
||||
{ 0x03, 0x01, 0x00, "XGA controller" },
|
||||
{ 0x03, 0x02, 0x00, "3D controller" },
|
||||
{ 0x03, 0x80, 0x00, "Other display controller" },
|
||||
|
||||
{ 0x04, 0x00, 0x00, "Video device" },
|
||||
{ 0x04, 0x01, 0x00, "Audio device" },
|
||||
{ 0x04, 0x02, 0x00, "Computer telephony device" },
|
||||
{ 0x04, 0x80, 0x00, "Other multimedia device" },
|
||||
|
||||
{ 0x06, 0x00, 0x00, "Host bridge" },
|
||||
{ 0x06, 0x01, 0x00, "ISA bridge" },
|
||||
{ 0x06, 0x02, 0x00, "EISA bridge" },
|
||||
{ 0x06, 0x03, 0x00, "MCA bridge" },
|
||||
{ 0x06, 0x04, 0x00, "PCI-to-PCI bridge" },
|
||||
{ 0x06, 0x04, 0x01, "Subtractive decode PCI-to-PCI bridge" },
|
||||
{ 0x06, 0x05, 0x00, "PCMCIA bridge" },
|
||||
{ 0x06, 0x06, 0x00, "NuBus bridge" },
|
||||
{ 0x06, 0x07, 0x00, "CardBus bridge" },
|
||||
{ 0x06, 0x08, -1, "RACEway bridge" },
|
||||
{ 0x06, 0x09, -1, "Semi-transparent PCI-to-PCI bridge" },
|
||||
{ 0x06, 0x80, 0x00, "Other bridge device" },
|
||||
|
||||
{ 0x0C, 0x00, 0x00, "IEEE 1394 (FireWire)" },
|
||||
{ 0x0C, 0x00, 0x10, "IEEE 1394 (OpenHCI)" },
|
||||
{ 0x0C, 0x01, 0x00, "ACCESS bus" },
|
||||
{ 0x0C, 0x02, 0x00, "SSA" },
|
||||
{ 0x0C, 0x03, 0x00, "USB (with UHC)" },
|
||||
{ 0x0C, 0x03, 0x10, "USB (with OHC)" },
|
||||
{ 0x0C, 0x03, 0x80, "USB (other host inf.)" },
|
||||
{ 0x0C, 0x03, 0xFE, "USB device" },
|
||||
{ 0x0C, 0x04, 0x00, "Fibre Channel" },
|
||||
{ 0x0C, 0x05, 0x00, "SMBus" },
|
||||
|
||||
{ 0x00, 0x00, 0x00, NULL }
|
||||
};
|
||||
|
||||
struct pci_intel_ctrl pci_intel_ctrl[]=
|
||||
{
|
||||
{ 0x1022, 0x700C, }, /* AMD-762 */
|
||||
{ 0x1039, 0x0406, }, /* SiS 85C501/2 */
|
||||
{ 0x1039, 0x5597, }, /* SiS 5582 */
|
||||
{ 0x10B9, 0x1541, }, /* ALI M1541 */
|
||||
{ 0x1106, 0x0305, }, /* VIA VT8363/8365 */
|
||||
{ 0x1106, 0x3099, }, /* VIA VT8367 [KT266] */
|
||||
{ 0x1106, 0x3188, }, /* VIA */
|
||||
{ 0x1106, 0x0204, }, /* VIA VT8367 [KT266] */
|
||||
{ 0x8086, 0x122D, }, /* Intel 82437FX */
|
||||
{ 0x8086, 0x1237, }, /* Intel 82441FX */
|
||||
{ 0x8086, 0x1250, }, /* Intel 82439HX */
|
||||
{ 0x8086, 0x7100, }, /* Intel 82371AB */
|
||||
{ 0x8086, 0x7190, }, /* Intel 82443BX */
|
||||
{ 0x0000, 0x0000, },
|
||||
};
|
||||
|
||||
struct pci_isabridge pci_isabridge[]=
|
||||
{
|
||||
{ 0x1022, 0x7410, 1, PCI_IB_AMD, }, /* AMD-766 */
|
||||
{ 0x1039, 0x0008, 1, PCI_IB_SIS, }, /* SiS 85C503/5513 */
|
||||
{ 0x10B9, 0x1533, 1, PCI_IB_PIIX, }, /* ALI M1533 */
|
||||
{ 0x1106, 0x0686, 1, PCI_IB_VIA, }, /* VIA VT82C686 */
|
||||
{ 0x1106, 0x3074, 1, PCI_IB_VIA, }, /* VIA VT8233 */
|
||||
{ 0x1106, 0x3227, 1, PCI_IB_VIA, }, /* VIA */
|
||||
{ 0x8086, 0x122E, 1, PCI_IB_PIIX, }, /* Intel 82371FB */
|
||||
{ 0x8086, 0x7000, 1, PCI_IB_PIIX, }, /* Intel 82371SB */
|
||||
{ 0x8086, 0x7100, 1, PCI_IB_PIIX, }, /* Intel 82371AB */
|
||||
{ 0x8086, 0x7110, 1, PCI_IB_PIIX, }, /* Intel PIIX4 */
|
||||
{ 0x0000, 0x0000, 0, 0, },
|
||||
};
|
||||
|
||||
struct pci_pcibridge pci_pcibridge[]=
|
||||
{
|
||||
{ 0x8086, 0x7191, PCI_AGPB_INTEL, }, /* Intel 82443BX (AGP bridge) */
|
||||
{ 0x1022, 0x700D, PCI_AGPB_INTEL, }, /* AMD-762 (AGP 4x) */
|
||||
{ 0x10B9, 0x5243, PCI_AGPB_INTEL, }, /* ALI M5243 */
|
||||
{ 0x1106, 0x8305, PCI_AGPB_VIA, }, /* VIA VT8365 [KM133 AGP] */
|
||||
{ 0x0000, 0x0000, 0, },
|
||||
};
|
||||
#endif /* ENABLE_PCI */
|
||||
|
||||
/*
|
||||
* $PchId: pci_table.c,v 1.7 2003/09/05 10:53:22 philip Exp $
|
||||
*/
|
||||
@@ -1,27 +0,0 @@
|
||||
/*
|
||||
pci_via.h
|
||||
|
||||
Created: Jun 2001 by Philip Homburg <philip@cs.vu.nl>
|
||||
*/
|
||||
|
||||
#define VIA_ISABR_EL 0x54 /* Edge or level triggered */
|
||||
#define VIA_ISABR_EL_INTA 0x08 /* Edge (1) or level (0) */
|
||||
#define VIA_ISABR_EL_INTB 0x04
|
||||
#define VIA_ISABR_EL_INTC 0x02
|
||||
#define VIA_ISABR_EL_INTD 0x01
|
||||
|
||||
#define VIA_ISABR_IRQ_R1 0x55 /* IRQ routing 1 */
|
||||
#define VIA_ISABR_IRQ_INTD 0xf0 /* routing for INTD */
|
||||
#define VIA_ISABR_IRQ_INT0 0x0f /* routing for INT0 */
|
||||
#define VIA_ISABR_IRQ_R2 0x56 /* IRQ routing 2 */
|
||||
#define VIA_ISABR_IRQ_INTA 0xf0 /* routing for INTA */
|
||||
#define VIA_ISABR_IRQ_INTB 0x0f /* routing for INTB */
|
||||
#define VIA_ISABR_IRQ_R3 0x57 /* IRQ routing 3 */
|
||||
#define VIA_ISABR_IRQ_INTC 0xf0 /* routing for INTC */
|
||||
#define VIA_ISABR_IRQ_INT1 0x0f /* routing for INT1 */
|
||||
#define VIA_ISABR_IRQ_R4 0x58 /* IRQ routing 4 */
|
||||
#define VIA_ISABR_IRQ_INT2 0x0f /* routing for INT2 */
|
||||
|
||||
/*
|
||||
* $PchId: pci_via.h,v 1.1 2001/06/20 15:50:25 philip Exp $
|
||||
*/
|
||||
@@ -4,9 +4,6 @@
|
||||
#define PROTO_H
|
||||
|
||||
/* Struct declarations. */
|
||||
#if TEMP_CODE
|
||||
struct dpeth;
|
||||
#endif
|
||||
struct proc;
|
||||
struct time_info;
|
||||
struct timer;
|
||||
@@ -46,32 +43,6 @@ _PROTOTYPE( void stop_sequence, (struct timer *tp) );
|
||||
/* misc.c */
|
||||
_PROTOTYPE( void panic, (_CONST char *s, int n) );
|
||||
|
||||
#if TEMP_CODE
|
||||
#if ENABLE_PCI
|
||||
/* pci.c */
|
||||
_PROTOTYPE( void pci_init, (void) );
|
||||
_PROTOTYPE( int pci_find_dev, (U8_t bus, U8_t dev, U8_t func,
|
||||
int *devindp) );
|
||||
_PROTOTYPE( int pci_first_dev, (int *devindp, u16_t *vidp, u16_t *didp) );
|
||||
_PROTOTYPE( int pci_next_dev, (int *devindp, u16_t *vidp, u16_t *didp) );
|
||||
_PROTOTYPE( void pci_reserve, (int devind) );
|
||||
_PROTOTYPE( void pci_ids, (int devind, u16_t *vidp, u16_t *didp) );
|
||||
_PROTOTYPE( char *pci_slot_name, (int devind) );
|
||||
_PROTOTYPE( char *pci_dev_name, (U16_t vid, U16_t did) );
|
||||
_PROTOTYPE( u8_t pci_attr_r8, (int devind, int port) );
|
||||
_PROTOTYPE( u16_t pci_attr_r16, (int devind, int port) );
|
||||
_PROTOTYPE( u32_t pci_attr_r32, (int devind, int port) );
|
||||
_PROTOTYPE( void pci_attr_w16, (int devind, int port, U16_t value) );
|
||||
_PROTOTYPE( void pci_attr_w32, (int devind, int port, u32_t value) );
|
||||
|
||||
/* rtl8029.c */
|
||||
_PROTOTYPE( int rtl_probe, (struct dpeth *dep) );
|
||||
#endif /* ENABLE_PCI */
|
||||
/* rtl8139.c */
|
||||
_PROTOTYPE( void rtl8139_task, (void) );
|
||||
#endif /* TEMP_CODE */
|
||||
|
||||
|
||||
/* proc.c */
|
||||
_PROTOTYPE( int sys_call, (int function, int src_dest, message *m_ptr) );
|
||||
_PROTOTYPE( void notify, (int proc_nr, int notify_type) );
|
||||
@@ -102,9 +73,6 @@ _PROTOTYPE( phys_bytes umap_bios, (struct proc *rp, vir_bytes vir_addr,
|
||||
vir_bytes bytes) );
|
||||
_PROTOTYPE( int generic_handler, (irq_hook_t *hook) );
|
||||
|
||||
/* table.c */
|
||||
_PROTOTYPE( void mapdrivers, (void) );
|
||||
|
||||
#if (CHIP == INTEL)
|
||||
|
||||
/* exception.c */
|
||||
@@ -124,10 +92,10 @@ _PROTOTYPE( int disable_irq, (irq_hook_t *hook) );
|
||||
_PROTOTYPE( u16_t mem_rdw, (U16_t segm, vir_bytes offset) );
|
||||
_PROTOTYPE( void phys_copy, (phys_bytes source, phys_bytes dest,
|
||||
phys_bytes count) );
|
||||
_PROTOTYPE( void phys_insb, (Port_t port, phys_bytes buf, size_t count) );
|
||||
_PROTOTYPE( void phys_insw, (Port_t port, phys_bytes buf, size_t count) );
|
||||
_PROTOTYPE( void phys_outsb, (Port_t port, phys_bytes buf, size_t count));
|
||||
_PROTOTYPE( void phys_outsw, (Port_t port, phys_bytes buf, size_t count));
|
||||
_PROTOTYPE( void phys_insb, (U16_t port, phys_bytes buf, size_t count) );
|
||||
_PROTOTYPE( void phys_insw, (U16_t port, phys_bytes buf, size_t count) );
|
||||
_PROTOTYPE( void phys_outsb, (U16_t port, phys_bytes buf, size_t count));
|
||||
_PROTOTYPE( void phys_outsw, (U16_t port, phys_bytes buf, size_t count));
|
||||
_PROTOTYPE( void reset, (void) );
|
||||
_PROTOTYPE( void level0, (void (*func)(void)) );
|
||||
_PROTOTYPE( void monitor, (void) );
|
||||
|
||||
2548
kernel/rtl8139.c
2548
kernel/rtl8139.c
File diff suppressed because it is too large
Load Diff
430
kernel/rtl8139.h
430
kernel/rtl8139.h
@@ -1,430 +0,0 @@
|
||||
/*
|
||||
ibm/rtl8139.h
|
||||
|
||||
Created: Aug 2003 by Philip Homburg <philip@cs.vu.nl>
|
||||
*/
|
||||
|
||||
#define RL_IDR 0x00 /* Ethernet address
|
||||
* Note: RL_9346CR_EEM_CONFIG mode is
|
||||
* required the change the ethernet
|
||||
* address.
|
||||
* Note: 4-byte write access only.
|
||||
*/
|
||||
#define RL_N_TX 4 /* Number of transmit buffers */
|
||||
#define RL_TSD0 0x010 /* Transmit Status of Descriptor 0 */
|
||||
#define RL_TSD_CRS 0x80000000 /* Carrier Sense Lost */
|
||||
#define RL_TSD_TABT 0x40000000 /* Transmit Abort */
|
||||
#define RL_TSD_OWC 0x20000000 /* Out of Window Collision */
|
||||
#define RL_TSD_CDH 0x10000000 /* CD Heart Beat */
|
||||
#define RL_TSD_NCC_M 0x0F000000 /* Number of Collision Count */
|
||||
#define RL_TSD_RES 0x00C00000 /* Reserved */
|
||||
#define RL_TSD_ERTXTH_M 0x003F0000 /* Early Tx Threshold */
|
||||
#define RL_TSD_ERTXTH_S 16 /* shift */
|
||||
#define RL_TSD_ERTXTH_8 0x00000000 /* 8 bytes */
|
||||
#define RL_TSD_TOK 0x00008000 /* Transmit OK */
|
||||
#define RL_TSD_TUN 0x00004000 /* Transmit FIFO Underrun */
|
||||
#define RL_TSD_OWN 0x00002000 /* Controller (does not) Own Buf. */
|
||||
#define RL_TSD_SIZE 0x00001FFF /* Descriptor Size */
|
||||
#define RL_TSAD0 0x20 /* Transmit Start Address of Descriptor 0 */
|
||||
#define RL_RBSTART 0x30 /* Receive Buffer Start Address */
|
||||
#define RL_CR 0x37 /* Command Register */
|
||||
#define RL_CR_RES0 0xE0 /* Reserved */
|
||||
#define RL_CR_RST 0x10 /* Reset */
|
||||
#define RL_CR_RE 0x08 /* Receiver Enable */
|
||||
#define RL_CR_TE 0x04 /* Transmitter Enable *
|
||||
* Note: start with transmit buffer
|
||||
* 0 after RL_CR_TE has been reset.
|
||||
*/
|
||||
#define RL_CR_RES1 0x02 /* Reserved */
|
||||
#define RL_CR_BUFE 0x01 /* Receive Buffer Empty */
|
||||
#define RL_CAPR 0x38 /* Current Address of Packet Read */
|
||||
#define RL_CAPR_DATA_OFF 0x10 /* Packet Starts at Offset */
|
||||
#define RL_CBR 0x3A /* Current Buffer Address */
|
||||
#define RL_IMR 0x3C /* Interrupt Mask Register */
|
||||
#define RL_IMR_SERR 0x8000 /* System Error */
|
||||
#define RL_IMR_TIMEOUT 0x4000 /* Time Out */
|
||||
#define RL_IMR_LENCHG 0x2000 /* Cable Length Change */
|
||||
#define RL_IMR_RES 0x1F80 /* Reserved */
|
||||
#define RL_IMR_FOVW 0x0040 /* Rx FIFO Overflow */
|
||||
#define RL_IMR_PUN 0x0020 /* Packet Underrun / Link Change */
|
||||
#define RL_IMR_RXOVW 0x0010 /* Rx Buffer Overflow */
|
||||
#define RL_IMR_TER 0x0008 /* Transmit Error */
|
||||
#define RL_IMR_TOK 0x0004 /* Transmit OK */
|
||||
#define RL_IMR_RER 0x0002 /* Receive Error */
|
||||
#define RL_IMR_ROK 0x0001 /* Receive OK */
|
||||
#define RL_ISR 0x3E /* Interrupt Status Register */
|
||||
#define RL_ISR_SERR 0x8000 /* System Error */
|
||||
#define RL_ISR_TIMEOUT 0x4000 /* Time Out */
|
||||
#define RL_ISR_LENCHG 0x2000 /* Cable Length Change */
|
||||
#define RL_ISR_RES 0x1F80 /* Reserved */
|
||||
#define RL_ISR_FOVW 0x0040 /* Rx FIFO Overflow */
|
||||
#define RL_ISR_PUN 0x0020 /* Packet Underrun / Link Change */
|
||||
#define RL_ISR_RXOVW 0x0010 /* Rx Buffer Overflow */
|
||||
#define RL_ISR_TER 0x0008 /* Transmit Error */
|
||||
#define RL_ISR_TOK 0x0004 /* Transmit OK */
|
||||
#define RL_ISR_RER 0x0002 /* Receive Error */
|
||||
#define RL_ISR_ROK 0x0001 /* Receive OK */
|
||||
#define RL_TCR 0x40 /* Transmit Configuration Register
|
||||
* Note: RL_CR_TE has to be set to
|
||||
* set/change RL_TCR.
|
||||
*/
|
||||
#define RL_TCR_RES0 0x80000000 /* Reserved */
|
||||
#define RL_TCR_HWVER_AM 0x7C000000 /* Hardware Version ID A */
|
||||
#define RL_TCR_IFG_M 0x03000000 /* Interframe Gap Time */
|
||||
#define RL_TCR_IFG_STD 0x03000000 /* IEEE 802.3 std */
|
||||
#if 0
|
||||
#undef RL_TCR_IFG_STD
|
||||
#define RL_TCR_IFG_STD 0x00000000
|
||||
#endif
|
||||
#define RL_TCR_HWVER_BM 0x00C00000 /* Hardware Version ID B */
|
||||
#define RL_TCR_HWVER_RTL8139 0x60000000 /* RTL8139 */
|
||||
#define RL_TCR_HWVER_RTL8139A 0x70000000 /* RTL8139A */
|
||||
#define RL_TCR_HWVER_RTL8139AG 0x74000000 /* RTL8139A-G */
|
||||
#define RL_TCR_HWVER_RTL8139B 0x78000000 /* RTL8139B */
|
||||
#define RL_TCR_HWVER_RTL8130 0x78000000 /* RTL8130 (dup) */
|
||||
#define RL_TCR_HWVER_RTL8139C 0x74000000 /* RTL8139C (dup) */
|
||||
#define RL_TCR_HWVER_RTL8100 0x78800000 /* RTL8100 */
|
||||
#define RL_TCR_HWVER_RTL8100B 0x74400000 /* RTL8100B /
|
||||
RTL8139D */
|
||||
#define RL_TCR_HWVER_RTL8139CP 0x74800000 /* RTL8139C+ */
|
||||
#define RL_TCR_HWVER_RTL8101 0x74C00000 /* RTL8101 */
|
||||
#define RL_TCR_RES1 0x00380000 /* Reserved */
|
||||
#define RL_TCR_LBK_M 0x00060000 /* Loopback Test */
|
||||
#define RL_TCR_LBK_NORMAL 0x00000000 /* Normal */
|
||||
#define RL_TCR_LBK_LOOKBOCK 0x00060000 /* Loopback Mode */
|
||||
#define RL_TCR_CRC 0x00010000 /* (Do not) Append CRC */
|
||||
#define RL_TCR_RES2 0x0000F800 /* Reserved */
|
||||
#define RL_TCR_MXDMA_M 0x00000700 /* Max DMA Burst Size Tx */
|
||||
#define RL_TCR_MXDMA_16 0x00000000 /* 16 bytes */
|
||||
#define RL_TCR_MXDMA_32 0x00000100 /* 32 bytes */
|
||||
#define RL_TCR_MXDMA_64 0x00000200 /* 64 bytes */
|
||||
#define RL_TCR_MXDMA_128 0x00000300 /* 128 bytes */
|
||||
#define RL_TCR_MXDMA_128 0x00000300 /* 128 bytes */
|
||||
#define RL_TCR_MXDMA_256 0x00000400 /* 256 bytes */
|
||||
#define RL_TCR_MXDMA_512 0x00000500 /* 512 bytes */
|
||||
#define RL_TCR_MXDMA_1024 0x00000600 /* 1024 bytes */
|
||||
#define RL_TCR_MXDMA_2048 0x00000700 /* 2048 bytes */
|
||||
#define RL_TCR_TXRR_M 0x000000F0 /* Tx Retry Count */
|
||||
#define RL_TCR_RES3 0x0000000E /* Reserved */
|
||||
#define RL_TCR_CLRABT 0x00000001 /* Clear Abort */
|
||||
#define RL_RCR 0x44 /* Receive Configuration Register
|
||||
* Note: RL_CR_RE has to be set to
|
||||
* set/change RL_RCR.
|
||||
*/
|
||||
#define RL_RCR_RES0 0xF0000000 /& Reserved */
|
||||
#define RL_RCR_ERTH_M 0x0F000000 /* Early Rx Threshold */
|
||||
#define RL_RCR_ERTH_0 0x00000000 /* No threshold */
|
||||
#define RL_RCR_ERTH_1 0x01000000 /* 1/16 */
|
||||
#define RL_RCR_ERTH_2 0x02000000 /* 2/16 */
|
||||
#define RL_RCR_ERTH_3 0x03000000 /* 3/16 */
|
||||
#define RL_RCR_ERTH_4 0x04000000 /* 4/16 */
|
||||
#define RL_RCR_ERTH_5 0x05000000 /* 5/16 */
|
||||
#define RL_RCR_ERTH_6 0x06000000 /* 6/16 */
|
||||
#define RL_RCR_ERTH_7 0x07000000 /* 7/16 */
|
||||
#define RL_RCR_ERTH_8 0x08000000 /* 8/16 */
|
||||
#define RL_RCR_ERTH_9 0x09000000 /* 9/16 */
|
||||
#define RL_RCR_ERTH_10 0x0A000000 /* 10/16 */
|
||||
#define RL_RCR_ERTH_11 0x0B000000 /* 11/16 */
|
||||
#define RL_RCR_ERTH_12 0x0C000000 /* 12/16 */
|
||||
#define RL_RCR_ERTH_13 0x0D000000 /* 13/16 */
|
||||
#define RL_RCR_ERTH_14 0x0E000000 /* 14/16 */
|
||||
#define RL_RCR_ERTH_15 0x0F000000 /* 15/16 */
|
||||
#define RL_RCR_RES1 0x00FC0000 /* Reserved */
|
||||
#define RL_RCR_MULERINT 0x00020000 /* Multiple Early Int Select */
|
||||
#define RL_RCR_RER8 0x00010000 /* Receive small error packet */
|
||||
#define RL_RCR_RXFTH_M 0x0000E000 /* Rx FIFO Threshold */
|
||||
#define RL_RCR_RXFTH_16 0x00000000 /* 16 bytes */
|
||||
#define RL_RCR_RXFTH_32 0x00002000 /* 32 bytes */
|
||||
#define RL_RCR_RXFTH_64 0x00004000 /* 64 bytes */
|
||||
#define RL_RCR_RXFTH_128 0x00006000 /* 128 bytes */
|
||||
#define RL_RCR_RXFTH_256 0x00008000 /* 256 bytes */
|
||||
#define RL_RCR_RXFTH_512 0x0000A000 /* 512 bytes */
|
||||
#define RL_RCR_RXFTH_1024 0x0000C000 /* 1024 bytes */
|
||||
#define RL_RCR_RXFTH_UNLIM 0x0000E000 /* unlimited */
|
||||
#define RL_RCR_RBLEM_M 0x00001800 /* Rx Buffer Length */
|
||||
#define RL_RCR_RBLEN_8K 0x00000000 /* 8KB + 16 bytes */
|
||||
#define RL_RCR_RBLEN_8K_SIZE (8*1024)
|
||||
#define RL_RCR_RBLEN_16K 0x00000800 /* 16KB + 16 bytes */
|
||||
#define RL_RCR_RBLEN_16K_SIZE (16*1024)
|
||||
#define RL_RCR_RBLEN_32K 0x00001000 /* 32KB + 16 bytes */
|
||||
#define RL_RCR_RBLEN_32K_SIZE (32*1024)
|
||||
#define RL_RCR_RBLEN_64K 0x00001800 /* 64KB + 16 bytes */
|
||||
#define RL_RCR_RBLEN_64K_SIZE (64*1024)
|
||||
/* Note: the documentation for the RTL8139C(L) or
|
||||
* for the RTL8139D(L) claims that the buffer should
|
||||
* be 16 bytes larger. Multiples of 8KB are the
|
||||
* correct values.
|
||||
*/
|
||||
#define RL_RCR_MXDMA_M 0x00000700 /* Rx DMA burst size */
|
||||
#define RL_RCR_MXDMA_16 0x00000000 /* 16 bytes */
|
||||
#define RL_RCR_MXDMA_32 0x00000100 /* 32 bytes */
|
||||
#define RL_RCR_MXDMA_64 0x00000200 /* 64 bytes */
|
||||
#define RL_RCR_MXDMA_128 0x00000300 /* 128 bytes */
|
||||
#define RL_RCR_MXDMA_256 0x00000400 /* 256 bytes */
|
||||
#define RL_RCR_MXDMA_512 0x00000500 /* 512 bytes */
|
||||
#define RL_RCR_MXDMA_1024 0x00000600 /* 1024 bytes */
|
||||
#define RL_RCR_MXDMA_UNLIM 0x00000700 /* unlimited */
|
||||
#define RL_RCR_WRAP 0x00000080 /* (Do not) Wrap on receive */
|
||||
#define RL_RCR_RES2 0x00000040 /* EEPROM type? */
|
||||
#define RL_RCR_AER 0x00000020 /* Accept Error Packets */
|
||||
#define RL_RCR_AR 0x00000010 /* Accept Runt Packets */
|
||||
#define RL_RCR_AB 0x00000008 /* Accept Broadcast Packets */
|
||||
#define RL_RCR_AM 0x00000004 /* Accept Multicast Packets */
|
||||
#define RL_RCR_APM 0x00000002 /* Accept Physical Match Packets */
|
||||
#define RL_RCR_AAP 0x00000001 /* Accept All Packets */
|
||||
#define RL_MPC 0x4c /* Missed Packet Counter */
|
||||
#define RL_9346CR 0x50 /* 93C46 Command Register */
|
||||
#define RL_9346CR_EEM_M 0xC0 /* Operating Mode */
|
||||
#define RL_9346CR_EEM_NORMAL 0x00 /* Normal Mode */
|
||||
#define RL_9346CR_EEM_AUTOLOAD 0x40 /* Load from 93C46 */
|
||||
#define RL_9346CR_EEM_PROG 0x80 /* 93C46 Programming */
|
||||
#define RL_9346CR_EEM_CONFIG 0xC0 /* Config Write Enable */
|
||||
#define RL_9346CR_RES 0x30 /* Reserved */
|
||||
#define RL_9346CR_EECS 0x08 /* EECS Pin */
|
||||
#define RL_9346CR_EESK 0x04 /* EESK Pin */
|
||||
#define RL_9346CR_EEDI 0x02 /* EEDI Pin */
|
||||
#define RL_9346CR_EEDO 0x01 /* EEDO Pin */
|
||||
#define RL_CONFIG0 0x51 /* Configuration Register 0 */
|
||||
#define RL_CONFIG1 0x52 /* Configuration Register 1 */
|
||||
#define RL_MSR 0x58 /* Media Status Register */
|
||||
#define RL_MSR_TXFCE 0x80 /* Tx Flow Control Enable */
|
||||
#define RL_MSR_RXFCE 0x40 /* Rx Flow Control Enable */
|
||||
#define RL_MSR_RES 0x20 /* Reserved */
|
||||
#define RL_MSR_AUXSTAT 0x10 /* Aux. Power Present */
|
||||
#define RL_MSR_SPEED_10 0x08 /* In 10 Mbps mode */
|
||||
#define RL_MSR_LINKB 0x04 /* link Failed */
|
||||
#define RL_MSR_TXPF 0x02 /* Sent Pause Packet */
|
||||
#define RL_MSR_RXPF 0x01 /* Received Pause Packet */
|
||||
#define RL_CONFIG3 0x59 /* Configuration Register 3 */
|
||||
#define RL_CONFIG4 0x5A /* Configuration Register 4 */
|
||||
/* 0x5B */ /* Reserved */
|
||||
#define RL_REVID 0x5E /* PCI Revision ID */
|
||||
/* 0x5F */ /* Reserved */
|
||||
#define RL_TSAD 0x60 /* Transmit Status of All Descriptors */
|
||||
#define RL_TSAD_TOK3 0x8000 /* TOK bit of Descriptor 3 */
|
||||
#define RL_TSAD_TOK2 0x4000 /* TOK bit of Descriptor 2 */
|
||||
#define RL_TSAD_TOK1 0x2000 /* TOK bit of Descriptor 1 */
|
||||
#define RL_TSAD_TOK0 0x1000 /* TOK bit of Descriptor 0 */
|
||||
#define RL_TSAD_TUN3 0x0800 /* TUN bit of Descriptor 3 */
|
||||
#define RL_TSAD_TUN2 0x0400 /* TUN bit of Descriptor 2 */
|
||||
#define RL_TSAD_TUN1 0x0200 /* TUN bit of Descriptor 1 */
|
||||
#define RL_TSAD_TUN0 0x0100 /* TUN bit of Descriptor 0 */
|
||||
#define RL_TSAD_TABT3 0x0080 /* TABT bit of Descriptor 3 */
|
||||
#define RL_TSAD_TABT2 0x0040 /* TABT bit of Descriptor 2 */
|
||||
#define RL_TSAD_TABT1 0x0020 /* TABT bit of Descriptor 1 */
|
||||
#define RL_TSAD_TABT0 0x0010 /* TABT bit of Descriptor 0 */
|
||||
#define RL_TSAD_OWN3 0x0008 /* OWN bit of Descriptor 3 */
|
||||
#define RL_TSAD_OWN2 0x0004 /* OWN bit of Descriptor 2 */
|
||||
#define RL_TSAD_OWN1 0x0002 /* OWN bit of Descriptor 1 */
|
||||
#define RL_TSAD_OWN0 0x0001 /* OWN bit of Descriptor 0 */
|
||||
#define RL_BMCR 0x62 /* Basic Mode Control Register (MII_CTRL) */
|
||||
#define RL_BMSR 0x64 /* Basic Mode Status Register (MII_STATUS) */
|
||||
#define RL_ANAR 0x66 /* Auto-Neg Advertisement Register (MII_ANA) */
|
||||
#define RL_ANLPAR 0x68 /* Auto-Neg Link Partner Register (MII_ANLPA) */
|
||||
#define RL_ANER 0x6a /* Auto-Neg Expansion Register (MII_ANE) */
|
||||
#define RL_NWAYTR 0x70 /* N-way Test Register */
|
||||
#define RL_CSCR 0x74 /* CS Configuration Register */
|
||||
#define RL_CONFIG5 0xD8 /* Configuration Register 5 */
|
||||
|
||||
/* Status word in receive buffer */
|
||||
#define RL_RXS_LEN_M 0xFFFF0000 /* Length Field, Excl. Status word */
|
||||
#define RL_RXS_LEN_S 16 /* Shift For Length */
|
||||
#define RL_RXS_MAR 0x00008000 /* Multicast Address Received */
|
||||
#define RL_RXS_PAR 0x00004000 /* Physical Address Matched */
|
||||
#define RL_RXS_BAR 0x00002000 /* Broadcast Address Received */
|
||||
#define RL_RXS_RES_M 0x00001FC0 /* Reserved */
|
||||
#define RL_RXS_ISE 0x00000020 /* Invalid Symbol Error */
|
||||
#define RL_RXS_RUNT 0x00000010 /* Runt Packet Received */
|
||||
#define RL_RXS_LONG 0x00000008 /* Long (>4KB) Packet */
|
||||
#define RL_RXS_CRC 0x00000004 /* CRC Error */
|
||||
#define RL_RXS_FAE 0x00000002 /* Frame Alignment Error */
|
||||
#define RL_RXS_ROK 0x00000001 /* Receive OK */
|
||||
|
||||
|
||||
/* Registers in the Machine Independent Interface (MII) to the PHY.
|
||||
* IEEE 802.3 (2000 Edition) Clause 22.
|
||||
*/
|
||||
#define MII_CTRL 0x0 /* Control Register (basic) */
|
||||
#define MII_CTRL_RST 0x8000 /* Reset PHY */
|
||||
#define MII_CTRL_LB 0x4000 /* Enable Loopback Mode */
|
||||
#define MII_CTRL_SP_LSB 0x2000 /* Speed Selection (LSB) */
|
||||
#define MII_CTRL_ANE 0x1000 /* Auto Negotiation Enable */
|
||||
#define MII_CTRL_PD 0x0800 /* Power Down */
|
||||
#define MII_CTRL_ISO 0x0400 /* Isolate */
|
||||
#define MII_CTRL_RAN 0x0200 /* Restart Auto-Negotiation Process */
|
||||
#define MII_CTRL_DM 0x0100 /* Full Duplex */
|
||||
#define MII_CTRL_CT 0x0080 /* Enable COL Signal Test */
|
||||
#define MII_CTRL_SP_MSB 0x0040 /* Speed Selection (MSB) */
|
||||
#define MII_CTRL_SP_10 0x0000 /* 10 Mb/s */
|
||||
#define MII_CTRL_SP_100 0x2000 /* 100 Mb/s */
|
||||
#define MII_CTRL_SP_1000 0x0040 /* 1000 Mb/s */
|
||||
#define MII_CTRL_SP_RES 0x2040 /* Reserved */
|
||||
#define MII_CTRL_RES 0x003F /* Reserved */
|
||||
#define MII_STATUS 0x1 /* Status Register (basic) */
|
||||
#define MII_STATUS_100T4 0x8000 /* 100Base-T4 support */
|
||||
#define MII_STATUS_100XFD 0x4000 /* 100Base-X FD support */
|
||||
#define MII_STATUS_100XHD 0x2000 /* 100Base-X HD support */
|
||||
#define MII_STATUS_10FD 0x1000 /* 10 Mb/s FD support */
|
||||
#define MII_STATUS_10HD 0x0800 /* 10 Mb/s HD support */
|
||||
#define MII_STATUS_100T2FD 0x0400 /* 100Base-T2 FD support */
|
||||
#define MII_STATUS_100T2HD 0x0200 /* 100Base-T2 HD support */
|
||||
#define MII_STATUS_EXT_STAT 0x0100 /* Supports MII_EXT_STATUS */
|
||||
#define MII_STATUS_RES 0x0080 /* Reserved */
|
||||
#define MII_STATUS_MFPS 0x0040 /* MF Preamble Suppression */
|
||||
#define MII_STATUS_ANC 0x0020 /* Auto-Negotiation Completed */
|
||||
#define MII_STATUS_RF 0x0010 /* Remote Fault Detected */
|
||||
#define MII_STATUS_ANA 0x0008 /* Auto-Negotiation Ability */
|
||||
#define MII_STATUS_LS 0x0004 /* Link Up */
|
||||
#define MII_STATUS_JD 0x0002 /* Jabber Condition Detected */
|
||||
#define MII_STATUS_EC 0x0001 /* Ext Register Capabilities */
|
||||
#define MII_PHYID_H 0x2 /* PHY ID (high) */
|
||||
#define MII_PHYID_L 0x3 /* PHY ID (low) */
|
||||
#define MII_ANA 0x4 /* Auto-Negotiation Advertisement */
|
||||
#define MII_ANA_NP 0x8000 /* Next PAge */
|
||||
#define MII_ANA_RES 0x4000 /* Reserved */
|
||||
#define MII_ANA_RF 0x2000 /* Remote Fault */
|
||||
#define MII_ANA_TAF_M 0x1FE0 /* Technology Ability Field */
|
||||
#define MII_ANA_TAF_S 5 /* Shift */
|
||||
#define MII_ANA_TAF_RES 0x1000 /* Reserved */
|
||||
#define MII_ANA_PAUSE_ASYM 0x0800 /* Asym. Pause */
|
||||
#define MII_ANA_PAUSE_SYM 0x0400 /* Sym. Pause */
|
||||
#define MII_ANA_100T4 0x0200 /* 100Base-T4 */
|
||||
#define MII_ANA_100TXFD 0x0100 /* 100Base-TX FD */
|
||||
#define MII_ANA_100TXHD 0x0080 /* 100Base-TX HD */
|
||||
#define MII_ANA_10TFD 0x0040 /* 10Base-T FD */
|
||||
#define MII_ANA_10THD 0x0020 /* 10Base-T HD */
|
||||
#define MII_ANA_SEL_M 0x001F /* Selector Field */
|
||||
#define MII_ANA_SEL_802_3 0x0001 /* 802.3 */
|
||||
#define MII_ANLPA 0x5 /* Auto-Neg Link Partner Ability Register */
|
||||
#define MII_ANLPA_NP 0x8000 /* Next Page */
|
||||
#define MII_ANLPA_ACK 0x4000 /* Acknowledge */
|
||||
#define MII_ANLPA_RF 0x2000 /* Remote Fault */
|
||||
#define MII_ANLPA_TAF_M 0x1FC0 /* Technology Ability Field */
|
||||
#define MII_ANLPA_SEL_M 0x001F /* Selector Field */
|
||||
#define MII_ANE 0x6 /* Auto-Negotiation Expansion */
|
||||
#define MII_ANE_RES 0xFFE0 /* Reserved */
|
||||
#define MII_ANE_PDF 0x0010 /* Parallel Detection Fault */
|
||||
#define MII_ANE_LPNPA 0x0008 /* Link Partner is Next Page Able */
|
||||
#define MII_ANE_NPA 0x0002 /* Local Device is Next Page Able */
|
||||
#define MII_ANE_PR 0x0002 /* New Page has been received */
|
||||
#define MII_ANE_LPANA 0x0001 /* Link Partner is Auto-Neg.able */
|
||||
#define MII_ANNPT 0x7 /* Auto-Negotiation Next Page Transmit */
|
||||
#define MII_ANLPRNP 0x8 /* Auto-Neg Link Partner Received Next Page */
|
||||
#define MII_MS_CTRL 0x9 /* MASTER-SLAVE Control Register */
|
||||
#define MII_MS_STATUS 0xA /* MASTER-SLAVE Status Register */
|
||||
/* 0xB ... 0xE */ /* Reserved */
|
||||
#define MII_EXT_STATUS 0xF /* Extended Status */
|
||||
#define MII_ESTAT_1000XFD 0x8000 /* 1000Base-X Full Duplex */
|
||||
#define MII_ESTAT_1000XHD 0x4000 /* 1000Base-X Half Duplex */
|
||||
#define MII_ESTAT_1000TFD 0x2000 /* 1000Base-T Full Duplex */
|
||||
#define MII_ESTAT_1000THD 0x1000 /* 1000Base-T Half Duplex */
|
||||
#define MII_ESTAT_RES 0x0FFF /* Reserved */
|
||||
/* 0x10 ... 0x1F */ /* Vendor Specific */
|
||||
|
||||
#if 0
|
||||
34-35 R ERBCR Early Receive (Rx) Byte Count Register
|
||||
36 R ERSR Early Rx Status Register
|
||||
7-4 reserved
|
||||
3 R ERGood Early Rx Good packet
|
||||
2 R ERBad Early Rx Bad packet
|
||||
1 R EROVW Early Rx OverWrite
|
||||
0 R EROK Early Rx OK
|
||||
51 R/W CONFIG0 Configuration Register 0
|
||||
7 R SCR Scrambler Mode
|
||||
6 R PCS PCS Mode
|
||||
5 R T10 10 Mbps Mode
|
||||
4-3 R PL[1-0] Select 10 Mbps medium type
|
||||
2-0 R BS[2-0] Select Boot ROM size
|
||||
52 R/W CONFIG1 Configuration Register 1
|
||||
7-6 R/W LEDS[1-0] LED PIN
|
||||
5 R/W DVRLOAD Driver Load
|
||||
4 R/W LWACT LWAKE active mode
|
||||
3 R MEMMAP Memory Mapping
|
||||
2 R IOMAP I/O Mapping
|
||||
1 R/W VPD Set to enable Vital Product Data
|
||||
0 R/W PMEn Power Management Enable
|
||||
59 R/W CONFIG3 Configuration Register 3
|
||||
7 R GNTSel Gnt Select
|
||||
6 R/W PARM_En Parameter Enable
|
||||
5 R/W Magic Magic Packet
|
||||
4 R/W LinkUp Link Up
|
||||
3 reserved
|
||||
2 R CLKRUN_En CLKRUN Enable
|
||||
1 reserved
|
||||
0 R FBtBEn Fast Back to Back Enable
|
||||
5a R/W CONFIG4 Configuration Register 4
|
||||
7 R/W RxFIFOAutoClr Auto Clear the Rx FIFO on overflow
|
||||
6 R/W AnaOff Analog Power Off
|
||||
5 R/W LongWF Long Wake-up Frame
|
||||
4 R/W LWPME LANWAKE vs PMEB
|
||||
3 reserved
|
||||
2 R/W LWPTN LWAKE pattern
|
||||
1 reserved
|
||||
0 R/W PBWakeup Pre-Boot Wakeup
|
||||
5c-5d R/W MULINT Multiple Interrupt Select
|
||||
15-12 reserved
|
||||
11-0 R/W MISR[11-0] Multiple Interrupt Select
|
||||
68-69 R ANLPAR Auto-Negotiation Link Partnet Register
|
||||
15 R NP Next Page bit
|
||||
14 R ACK acknowledge received from link partner
|
||||
13 R/W RF received remote fault detection capability
|
||||
12-11 reserved
|
||||
10 R Pause Flow control is supported
|
||||
9 R T4 100Base-T4 is supported
|
||||
8 R/W TXFD 100Base-TX full duplex is supported
|
||||
7 R/W TX 100Base-TX is supported
|
||||
6 R/W 10FD 10Base-T full duplex is supported
|
||||
5 R/W 10 10Base-T is supported
|
||||
4-0 R/W Selector Binary encoded selector
|
||||
6a-6b R ANER Auto-Negotiation Expansion Register
|
||||
15-5 reserved
|
||||
4 R MLF Multiple link fault occured
|
||||
3 R LP_NP_ABLE Link partner supports Next Page
|
||||
2 R NP_ABLE Local node is able to send add. Next Pages
|
||||
1 R PAGE_RX Link Code Word Page received
|
||||
0 R LP_NW_ABLE Link partner supports NWay auto-negotiation
|
||||
70-71 R/W NWAYTR N-way Test Register
|
||||
15-8 reserved
|
||||
7 R/W NWLPBK NWay loopback mode
|
||||
6-4 reserved
|
||||
3 R ENNWLE LED0 pin indicates linkpulse
|
||||
2 R FLAGABD Auto-neg experienced ability detect state
|
||||
1 R FLAGPDF Auto-neg exp. par. detection fault state
|
||||
0 R FLAGLSC Auto-neg experienced link status check state
|
||||
74-75 R/W CSCR CS Configuration Register
|
||||
15 W Testfun Auto-neg speeds up internal timer
|
||||
14-10 reserved
|
||||
9 R/W LD Active low TPI link disable signal
|
||||
8 R/W HEARTBEAT HEART BEAT enable
|
||||
7 R/W JBEN Enable jabber function
|
||||
6 R/W F_LINK_100 Force 100 Mbps
|
||||
5 R/W F_Conect Bypass disconnect function
|
||||
4 reserved
|
||||
3 R Con_status Connected link detected
|
||||
2 R/W Con_status_En Configures LED1 to indicate conn. stat.
|
||||
1 reserved
|
||||
0 R/W PASS_SCR Bypass scramble
|
||||
76-77 reserved
|
||||
78-7b R/W PHY1_PARM PHY parameter 1
|
||||
7c-7f R/W TW_PARM Twister parameter
|
||||
80 R/W PHY2_PARM PHY parameter 2
|
||||
81-83 reserved
|
||||
84-8b R/W CRC[0-7] Power Management CRC reg.[0-7] for frame[0-7]
|
||||
8c-cb R/W Wakeup[0-7] Power Management wakeup frame[0-7] (64 bit)
|
||||
cc-d3 R/W LSBCRC[0-7] LSB of the mask byte of makeup frame[0-7]
|
||||
d4-d7 reserved
|
||||
d8 R/W Config5 Configuration register 5
|
||||
7 reserved
|
||||
6 R/W BWF Broadcast Wakeup Frame
|
||||
5 R/W MWF Multicast Wakeup Frame
|
||||
4 R/W UWF Unicast Wakeup Frame
|
||||
3 R/W FifoAddrPtr FIFO Address Pointer
|
||||
2 R/W LDPS Link Down Power Saving mode
|
||||
1 R/W LANWake LANWake Signal
|
||||
0 R/W PME_STS PME_Status bit
|
||||
d9-ff reserved
|
||||
#endif
|
||||
|
||||
/*
|
||||
* $PchId: rtl8139.h,v 1.1 2003/09/05 10:58:50 philip Exp $
|
||||
*/
|
||||
@@ -54,11 +54,7 @@
|
||||
allow_all_mask
|
||||
|
||||
#define RTL8139_SENDMASK \
|
||||
deny_all_mask \
|
||||
allow(1, USER_PROC_NR) /* inet server starts as user process */ \
|
||||
allow(1, TTY) /* need to register function key */ \
|
||||
allow(1, SYSTASK) /* need system functionality */ \
|
||||
allow(1, CLOCK) /* need clock functionality */
|
||||
allow_all_mask
|
||||
|
||||
#define IDLE_SENDMASK \
|
||||
deny_all_mask
|
||||
|
||||
@@ -99,7 +99,7 @@ message *m_ptr; /* pointer to request message */
|
||||
case SYSSENDMASK: {
|
||||
rp->p_type = P_SERVER;
|
||||
rp->p_sendmask = ALLOW_ALL_MASK;
|
||||
send_mask_allow(proc_addr(RTL8139)->p_sendmask, proc_nr);
|
||||
send_mask_allow(proc_addr(USR8139)->p_sendmask, proc_nr);
|
||||
send_mask_allow(proc_addr(PM_PROC_NR)->p_sendmask, proc_nr);
|
||||
send_mask_allow(proc_addr(FS_PROC_NR)->p_sendmask, proc_nr);
|
||||
send_mask_allow(proc_addr(IS_PROC_NR)->p_sendmask, proc_nr);
|
||||
|
||||
@@ -47,11 +47,9 @@
|
||||
#define HARDWARE_STACK NO_STACK /* dummy task, uses kernel stack */
|
||||
#define SYS_STACK SMALL_STACK
|
||||
#define CLOCK_STACK SMALL_STACK
|
||||
#define RTL8139_STACK (2 * SMALL_STACK * ENABLE_RTL8139)
|
||||
|
||||
/* Stack space for all the task stacks. Declared as (char *) to align it. */
|
||||
#define TOT_STACK_SPACE (IDLE_STACK + HARDWARE_STACK + CLOCK_STACK + SYS_STACK \
|
||||
+ RTL8139_STACK )
|
||||
#define TOT_STACK_SPACE (IDLE_STACK+HARDWARE_STACK+CLOCK_STACK+SYS_STACK )
|
||||
PUBLIC char *t_stack[TOT_STACK_SPACE / sizeof(char *)];
|
||||
|
||||
|
||||
@@ -63,9 +61,6 @@ PUBLIC char *t_stack[TOT_STACK_SPACE / sizeof(char *)];
|
||||
* routine and stack size is also provided.
|
||||
*/
|
||||
PUBLIC struct system_image image[] = {
|
||||
#if ENABLE_RTL8139
|
||||
{ RTL8139, rtl8139_task, P_TASK, PPRI_TASK, RTL8139_STACK, RTL8139_SENDMASK, "RTL8139" },
|
||||
#endif
|
||||
{ IDLE, idle_task, P_IDLE, PPRI_IDLE, IDLE_STACK, IDLE_SENDMASK, "IDLE" },
|
||||
{ CLOCK, clock_task, P_TASK, PPRI_TASK, CLOCK_STACK, CLOCK_SENDMASK, "CLOCK" },
|
||||
{ SYSTASK, sys_task, P_TASK, PPRI_TASK, SYS_STACK, SYSTEM_SENDMASK, "SYS" },
|
||||
@@ -83,6 +78,9 @@ PUBLIC struct system_image image[] = {
|
||||
#endif
|
||||
#if ENABLE_PRINTER
|
||||
{ PRINTER, 0, P_DRIVER, PPRI_NORMAL, 0, PRN_SENDMASK, "PRINTER" },
|
||||
#endif
|
||||
#if ENABLE_RTL8139
|
||||
{ USR8139, 0, P_DRIVER, PPRI_HIGH, 0, RTL8139_SENDMASK, "RTL8139" },
|
||||
#endif
|
||||
{ INIT_PROC_NR, 0, P_USER, PPRI_USER, 0, INIT_SENDMASK, "INIT" },
|
||||
};
|
||||
|
||||
@@ -28,8 +28,6 @@ struct memory {
|
||||
|
||||
|
||||
#if (CHIP == INTEL)
|
||||
typedef u16_t port_t;
|
||||
typedef U16_t Port_t;
|
||||
typedef unsigned reg_t; /* machine register */
|
||||
|
||||
/* The stack frame layout is determined by the software, but for efficiency
|
||||
|
||||
Reference in New Issue
Block a user