1247 lines
38 KiB
C
1247 lines
38 KiB
C
#include <minix/drivers.h>
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#include <minix/netdriver.h>
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#include <net/gen/ether.h>
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#include <net/gen/eth_io.h>
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#include <minix/sysutil.h>
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#include <minix/board.h>
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#include "assert.h"
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#include "lan8710a.h"
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#include "lan8710a_reg.h"
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/* Local functions */
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static void lan8710a_readv_s(message *m, int from_int);
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static void lan8710a_writev_s(message *m, int from_int);
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static void lan8710a_conf(message *m);
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static void lan8710a_getstat(message *m);
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static void lan8710a_init(void);
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static void lan8710a_enable_interrupt(int interrupt);
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static void lan8710a_interrupt(message *m);
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static void lan8710a_map_regs(void);
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static void lan8710a_stop(void);
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static void lan8710a_dma_config_tx(u8_t desc_idx);
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static void lan8710a_dma_reset_init(void);
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static void lan8710a_init_addr(void);
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static void lan8710a_init_desc(void);
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static void lan8710a_init_mdio(void);
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static int lan8710a_init_hw(void);
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static void lan8710a_reset_hw();
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static void lan8710a_phy_write(u32_t reg, u32_t value);
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static u32_t lan8710a_phy_read(u32_t reg);
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static u32_t lan8710a_reg_read(volatile u32_t *reg);
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static void lan8710a_reg_write(volatile u32_t *reg, u32_t value);
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static void lan8710a_reg_set(volatile u32_t *reg, u32_t value);
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static void lan8710a_reg_unset(volatile u32_t *reg, u32_t value);
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static void mess_reply(message *req, message *reply);
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static void reply(lan8710a_t *e);
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/* Local variables */
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static lan8710a_t lan8710a_state;
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/* SEF functions and variables. */
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static void sef_local_startup(void);
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static int sef_cb_init_fresh(int type, sef_init_info_t *info);
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static void sef_cb_signal_handler(int signal);
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/*============================================================================*
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* main *
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*============================================================================*/
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int
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main(int argc, char *argv[])
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{
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/* Local variables */
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message m;
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int r;
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int ipc_status;
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struct machine machine ;
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sys_getmachine(&machine);
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if ( BOARD_IS_BB(machine.board_id)) {
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/* SEF local startup */
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env_setargs(argc, argv);
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sef_local_startup();
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/* Main driver loop */
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for (;;) {
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r = netdriver_receive(ANY, &m, &ipc_status);
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if (r != OK) {
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panic("netdriver_receive failed: %d", r);
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}
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if (is_ipc_notify(ipc_status)) {
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switch (_ENDPOINT_P(m.m_source)) {
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case HARDWARE:
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lan8710a_interrupt(&m);
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break;
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}
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} else {
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switch (m.m_type) {
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case DL_WRITEV_S:
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lan8710a_writev_s(&m, FALSE);
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break;
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case DL_READV_S:
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lan8710a_readv_s(&m, FALSE);
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break;
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case DL_CONF:
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lan8710a_conf(&m);
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break;
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case DL_GETSTAT_S:
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lan8710a_getstat(&m);
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break;
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default:
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panic("Illegal message: %d", m.m_type);
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}
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}
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}
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}
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return EXIT_SUCCESS;
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}
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/*============================================================================*
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* sef_local_startup *
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*============================================================================*/
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static void
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sef_local_startup()
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{
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/* Register init callbacks. */
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sef_setcb_init_fresh(sef_cb_init_fresh);
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sef_setcb_init_lu(sef_cb_init_fresh);
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sef_setcb_init_restart(sef_cb_init_fresh);
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/* Register live update callbacks. */
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sef_setcb_lu_prepare(sef_cb_lu_prepare_always_ready);
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sef_setcb_lu_state_isvalid(sef_cb_lu_state_isvalid_workfree);
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/* Register signal callbacks. */
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sef_setcb_signal_handler(sef_cb_signal_handler);
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/* Let SEF perform startup. */
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sef_startup();
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}
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/*============================================================================*
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* sef_cb_init_fresh *
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*============================================================================*/
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static int
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sef_cb_init_fresh(int UNUSED( type), sef_init_info_t *UNUSED( info))
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{
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/* Initialize the ethernet driver. */
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long v = 0;
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/* Clear state. */
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memset(&lan8710a_state, 0, sizeof(lan8710a_state));
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/* Initialize driver. */
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lan8710a_init();
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/* Get instance of ethernet device */
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env_parse("instance", "d", 0, &v, 0, 255);
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lan8710a_state.instance = (int) v;
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/* Announce we are up! */
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netdriver_announce();
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return OK;
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}
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/*============================================================================*
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* sef_cb_signal_handler *
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*============================================================================*/
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static void
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sef_cb_signal_handler(int signal)
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{
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/* Only check for termination signal, ignore anything else. */
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if (signal != SIGTERM)
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return;
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lan8710a_stop();
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}
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/*============================================================================*
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* lan8710a_enable_interrupt *
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*============================================================================*/
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static void
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lan8710a_enable_interrupt(interrupt)
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u8_t interrupt;
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{
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int r;
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if (interrupt & RX_INT) {
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if ((r = sys_irqenable(&lan8710a_state.irq_rx_hook)) != OK) {
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panic("sys_irqenable failed: %d", r);
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}
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}
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if (interrupt & TX_INT) {
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if ((r = sys_irqenable(&lan8710a_state.irq_tx_hook)) != OK) {
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panic("sys_irqenable failed: %d", r);
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}
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}
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}
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/*============================================================================*
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* lan8710a_interrupt *
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*============================================================================*/
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static void
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lan8710a_interrupt(m)
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message *m;
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{
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lan8710a_t *e = &lan8710a_state;
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u32_t dma_status;
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/* Check the card for interrupt reason(s). */
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u32_t rx_stat = lan8710a_reg_read(CPSW_WR_C0_RX_STAT);
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u32_t tx_stat = lan8710a_reg_read(CPSW_WR_C0_TX_STAT);
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u32_t cp;
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/* Handle interrupts. */
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if (rx_stat) {
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cp = lan8710a_reg_read(CPDMA_STRAM_RX_CP(0));
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lan8710a_readv_s(&(e->rx_message), TRUE);
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lan8710a_reg_write(CPDMA_STRAM_RX_CP(0), cp);
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lan8710a_reg_write(CPDMA_EOI_VECTOR, RX_INT);
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}
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if (tx_stat) {
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cp = lan8710a_reg_read(CPDMA_STRAM_TX_CP(0));
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/* Disabling channels, where Tx interrupt occurred */
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lan8710a_reg_set(CPDMA_TX_INTMASK_CLEAR, tx_stat);
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lan8710a_writev_s(&(e->tx_message), TRUE);
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lan8710a_reg_write(CPDMA_STRAM_TX_CP(0), cp);
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lan8710a_reg_write(CPDMA_EOI_VECTOR, TX_INT);
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}
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dma_status = lan8710a_reg_read(CPDMA_STATUS);
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if (dma_status & CPDMA_ERROR) {
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LAN8710A_DEBUG_PRINT(("CPDMA error: 0x%X, reset", dma_status));
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lan8710a_dma_reset_init();
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}
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/* Re-enable Rx interrupt. */
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if(m->m_notify.interrupts & (1 << RX_INT))
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lan8710a_enable_interrupt(RX_INT);
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/* Re-enable Tx interrupt. */
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if(m->m_notify.interrupts & (1 << TX_INT))
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lan8710a_enable_interrupt(TX_INT);
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}
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/*============================================================================*
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* lan8710a_conf *
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*============================================================================*/
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static void
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lan8710a_conf(m)
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message *m;
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{
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message reply;
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if (!(lan8710a_state.status & LAN8710A_ENABLED) &&
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!(lan8710a_init_hw())) {
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reply.m_type = DL_CONF_REPLY;
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reply.m_netdrv_net_dl_conf.stat = ENXIO;
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mess_reply(m, &reply);
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return;
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}
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/* Reply back to INET. */
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reply.m_type = DL_CONF_REPLY;
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reply.m_netdrv_net_dl_conf.stat = OK;
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memcpy(reply.m_netdrv_net_dl_conf.hw_addr,
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lan8710a_state.address.ea_addr,
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sizeof(reply.m_netdrv_net_dl_conf.hw_addr));
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mess_reply(m, &reply);
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}
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/*============================================================================*
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* lan8710a_init *
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*============================================================================*/
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static void
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lan8710a_init(void)
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{
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lan8710a_map_regs();
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strlcpy(lan8710a_state.name, "lan8710a#0", LAN8710A_NAME_LEN);
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lan8710a_state.name[9] += lan8710a_state.instance;
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lan8710a_state.status |= LAN8710A_DETECTED;
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if (!(lan8710a_state.status & LAN8710A_ENABLED) &&
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!(lan8710a_init_hw())) {
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return;
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}
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}
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/*============================================================================*
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* lan8710a_init_addr *
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*============================================================================*/
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static void
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lan8710a_init_addr(void)
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{
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static char eakey[]= LAN8710A_ENVVAR "#_EA";
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static char eafmt[]= "x:x:x:x:x:x";
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int i;
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long v;
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/*
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* Do we have a user defined ethernet address?
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*/
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eakey[sizeof(LAN8710A_ENVVAR)-1] = '0' + lan8710a_state.instance;
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for (i= 0; i < 6; i++) {
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if (env_parse(eakey, eafmt, i, &v, 0x00L, 0xFFL) != EP_SET)
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break;
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else
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lan8710a_state.address.ea_addr[i] = v;
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}
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if (i != 6) {
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lan8710a_state.address.ea_addr[0] =
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(lan8710a_reg_read(CTRL_MAC_ID0_HI) & 0xFF);
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lan8710a_state.address.ea_addr[1] =
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((lan8710a_reg_read(CTRL_MAC_ID0_HI) & 0xFF00) >> 8);
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lan8710a_state.address.ea_addr[2] =
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((lan8710a_reg_read(CTRL_MAC_ID0_HI) & 0xFF0000) >> 16);
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lan8710a_state.address.ea_addr[3] =
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((lan8710a_reg_read(CTRL_MAC_ID0_HI) & 0xFF000000) >> 24);
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lan8710a_state.address.ea_addr[4] =
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(lan8710a_reg_read(CTRL_MAC_ID0_LO) & 0xFF);
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lan8710a_state.address.ea_addr[5] =
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((lan8710a_reg_read(CTRL_MAC_ID0_LO) & 0xFF00) >> 8);
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}
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}
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/*============================================================================*
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* lan8710a_map_regs *
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*============================================================================*/
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static void
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lan8710a_map_regs(void)
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{
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struct minix_mem_range mr;
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mr.mr_base = CM_PER_BASE_ADR;
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mr.mr_limit = CM_PER_BASE_ADR + MEMORY_LIMIT;
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if (sys_privctl(SELF, SYS_PRIV_ADD_MEM, &mr) != 0) {
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panic("Unable to request permission to map memory");
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}
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lan8710a_state.regs_cp_per =
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(vir_bytes)vm_map_phys(SELF, (void *)CM_PER_BASE_ADR, 512);
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if ((void *)lan8710a_state.regs_cp_per == MAP_FAILED) {
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panic("lan8710a_state.regs_cp_per: vm_map_phys failed");
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}
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lan8710a_state.regs_cpdma_stram =
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(vir_bytes)vm_map_phys(SELF, (void *)CPDMA_STRAM_BASE_ADR, 512);
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if ((void *)lan8710a_state.regs_cpdma_stram == MAP_FAILED) {
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panic("lan8710a_state.regs_cpdma_stram: vm_map_phys failed");
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}
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lan8710a_state.regs_cpsw_cpdma =
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(vir_bytes)vm_map_phys(SELF, (void *)CPSW_CPDMA_BASE_ADR, 512);
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if ((void *)lan8710a_state.regs_cpsw_cpdma == MAP_FAILED) {
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panic("lan8710a_state.regs_cpsw_cpdma: vm_map_phys failed");
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}
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lan8710a_state.regs_cpsw_ale =
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(vir_bytes)vm_map_phys(SELF, (void *)CPSW_ALE_BASE_ADR, 256);
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if ((void *)lan8710a_state.regs_cpsw_ale == MAP_FAILED) {
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panic("lan8710a_state.regs_cpsw_ale: vm_map_phys failed");
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}
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lan8710a_state.regs_cpsw_sl =
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(vir_bytes)vm_map_phys(SELF, (void *)CPSW_SL_BASE_ADR, 512);
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if ((void *)lan8710a_state.regs_cpsw_sl == MAP_FAILED) {
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panic("lan8710a_state.regs_cpsw_sl: vm_map_phys failed");
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}
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lan8710a_state.regs_cpsw_ss =
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(vir_bytes)vm_map_phys(SELF, (void *)CPSW_SS_BASE_ADR, 512);
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if ((void *)lan8710a_state.regs_cpsw_ss == MAP_FAILED) {
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panic("lan8710a_state.regs_cpsw_ss: vm_map_phys failed");
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}
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lan8710a_state.regs_cpsw_wr =
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(vir_bytes)vm_map_phys(SELF, (void *)CPSW_WR_BASE_ADR, 512);
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if ((void *)lan8710a_state.regs_cpsw_wr == MAP_FAILED) {
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panic("lan8710a_state.regs_cpsw_wr: vm_map_phys failed");
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}
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lan8710a_state.regs_ctrl_mod =
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(vir_bytes)vm_map_phys(SELF, (void *)CTRL_MOD_BASE_ADR, 2560);
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if ((void *)lan8710a_state.regs_ctrl_mod == MAP_FAILED) {
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panic("lan8710a_state.regs_ctrl_mod: vm_map_phys failed");
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}
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lan8710a_state.regs_intc =
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(vir_bytes)vm_map_phys(SELF, (void *)INTC_BASE_ADR, 512);
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if ((void *)lan8710a_state.regs_intc == MAP_FAILED) {
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panic("lan8710a_state.regs_intc: vm_map_phys failed");
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}
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lan8710a_state.regs_mdio =
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(vir_bytes)vm_map_phys(SELF, (void *)MDIO_BASE_ADDR, 512);
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if ((void *)lan8710a_state.regs_mdio == MAP_FAILED) {
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panic("lan8710a_state.regs_mdio: vm_map_phys failed");
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}
|
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mr.mr_base = BEGINNING_DESC_MEM;
|
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mr.mr_limit = BEGINNING_DESC_MEM + DESC_MEMORY_LIMIT;
|
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|
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if (sys_privctl(SELF, SYS_PRIV_ADD_MEM, &mr) != 0) {
|
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panic("Unable to request permission to map memory");
|
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}
|
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lan8710a_state.rx_desc_phy = BEGINNING_RX_DESC_MEM;
|
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lan8710a_state.tx_desc_phy = BEGINNING_TX_DESC_MEM;
|
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lan8710a_state.rx_desc = (lan8710a_desc_t *)vm_map_phys(SELF,
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(void *)lan8710a_state.rx_desc_phy, 1024);
|
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if ((void *)lan8710a_state.rx_desc == MAP_FAILED) {
|
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panic("lan8710a_state.rx_desc: vm_map_phys failed");
|
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}
|
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lan8710a_state.tx_desc = (lan8710a_desc_t *)vm_map_phys(SELF,
|
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(void *)lan8710a_state.tx_desc_phy, 1024);
|
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if ((void *)lan8710a_state.tx_desc == MAP_FAILED) {
|
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panic("lan8710a_state.tx_desc: vm_map_phys failed");
|
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}
|
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|
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mr.mr_base = CPSW_STATS_BASE_ADR;
|
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mr.mr_limit = CPSW_STATS_BASE_ADR + CPSW_STATS_MEM_LIMIT;
|
||
|
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if (sys_privctl(SELF, SYS_PRIV_ADD_MEM, &mr) != 0) {
|
||
panic("Unable to request permission to map memory");
|
||
}
|
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lan8710a_state.regs_cpsw_stats =
|
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(vir_bytes)vm_map_phys(SELF, (void *)CPSW_STATS_BASE_ADR, 256);
|
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if ((void *)lan8710a_state.regs_cpsw_stats == MAP_FAILED) {
|
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panic("lan8710a_state.regs_cpsw_stats: vm_map_phys failed");
|
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}
|
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}
|
||
|
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/*============================================================================*
|
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* lan8710a_getstat *
|
||
*============================================================================*/
|
||
static void
|
||
lan8710a_getstat(mp)
|
||
message *mp;
|
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{
|
||
int r;
|
||
eth_stat_t stats;
|
||
|
||
stats.ets_recvErr = lan8710a_reg_read(CPSW_STAT_RX_CRC_ERR)
|
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+ lan8710a_reg_read(CPSW_STAT_RX_AGNCD_ERR)
|
||
+ lan8710a_reg_read(CPSW_STAT_RX_OVERSIZE);
|
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stats.ets_sendErr = 0;
|
||
stats.ets_OVW = 0;
|
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stats.ets_CRCerr = lan8710a_reg_read(CPSW_STAT_RX_CRC_ERR);
|
||
stats.ets_frameAll = lan8710a_reg_read(CPSW_STAT_RX_AGNCD_ERR);
|
||
stats.ets_missedP = 0;
|
||
stats.ets_packetR = lan8710a_reg_read(CPSW_STAT_RX_GOOD);
|
||
stats.ets_packetT = lan8710a_reg_read(CPSW_STAT_TX_GOOD);
|
||
stats.ets_collision = lan8710a_reg_read(CPSW_STAT_COLLISIONS);
|
||
stats.ets_transAb = 0;
|
||
stats.ets_carrSense = lan8710a_reg_read(CPSW_STAT_CARR_SENS_ERR);
|
||
stats.ets_fifoUnder = lan8710a_reg_read(CPSW_STAT_TX_UNDERRUN);
|
||
stats.ets_fifoOver = lan8710a_reg_read(CPSW_STAT_RX_OVERRUN);
|
||
stats.ets_CDheartbeat = 0;
|
||
stats.ets_OWC = 0;
|
||
|
||
sys_safecopyto(mp->m_source, mp->m_net_netdrv_dl_getstat_s.grant, 0,
|
||
(vir_bytes)&stats, sizeof(stats));
|
||
mp->m_type = DL_STAT_REPLY;
|
||
|
||
if ((r=ipc_send(mp->m_source, mp)) != OK) {
|
||
panic("lan8710a_getstat: ipc_send() failed: %d", r);
|
||
}
|
||
}
|
||
|
||
/*============================================================================*
|
||
* lan8710a_stop *
|
||
*============================================================================*/
|
||
static void
|
||
lan8710a_stop(void)
|
||
{
|
||
/* Reset hardware. */
|
||
lan8710a_reset_hw();
|
||
|
||
/* Exit driver. */
|
||
exit(EXIT_SUCCESS);
|
||
}
|
||
|
||
/*============================================================================*
|
||
* lan8710a_dma_config_tx *
|
||
*============================================================================*/
|
||
static void
|
||
lan8710a_dma_config_tx(desc_idx)
|
||
u8_t desc_idx;
|
||
{
|
||
phys_bytes phys_addr;
|
||
int i;
|
||
for (i = 0; i < TX_DMA_CHANNELS; ++i) {
|
||
if (!lan8710a_reg_read(CPDMA_STRAM_TX_HDP(i))) break;
|
||
}
|
||
if (i == TX_DMA_CHANNELS) {
|
||
panic("There are no free TX DMA channels.");
|
||
}
|
||
|
||
/* Enabling only one channel Tx interrupt */
|
||
lan8710a_reg_write(CPDMA_TX_INTMASK_SET, 1 << i);
|
||
/* Routing only one channel Tx int to TX_PULSE signal */
|
||
lan8710a_reg_write(CPSW_WR_C0_TX_EN, 1 << i);
|
||
|
||
/* Setting HDP */
|
||
phys_addr = lan8710a_state.tx_desc_phy +
|
||
(desc_idx * sizeof(lan8710a_desc_t));
|
||
lan8710a_reg_write(CPDMA_STRAM_TX_HDP(i), (u32_t)phys_addr);
|
||
}
|
||
|
||
/*============================================================================*
|
||
* lan8710a_dma_reset_init *
|
||
*============================================================================*/
|
||
static void
|
||
lan8710a_dma_reset_init(void)
|
||
{
|
||
int i;
|
||
lan8710a_reg_write(CPDMA_SOFT_RESET, SOFT_RESET);
|
||
while ((lan8710a_reg_read(CPDMA_SOFT_RESET) & SOFT_RESET));
|
||
|
||
/*
|
||
* Initialize the HDPs (Header Description Pointers) and
|
||
* CPs (Completion Pointers) to NULL.
|
||
*/
|
||
for (i = 0; i < DMA_MAX_CHANNELS; ++i) {
|
||
lan8710a_reg_write(CPDMA_STRAM_TX_HDP(i), 0);
|
||
lan8710a_reg_write(CPDMA_STRAM_RX_HDP(i), 0);
|
||
lan8710a_reg_write(CPDMA_STRAM_TX_CP(i), 0);
|
||
lan8710a_reg_write(CPDMA_STRAM_RX_CP(i), 0);
|
||
}
|
||
|
||
lan8710a_reg_write(CPDMA_RX_INTMASK_CLEAR, 0xFFFFFFFF);
|
||
lan8710a_reg_write(CPDMA_TX_INTMASK_CLEAR, 0xFFFFFFFF);
|
||
|
||
/* Configure the CPDMA controller. */
|
||
lan8710a_reg_set(CPDMA_RX_CONTROL, CPDMA_RX_EN); /* RX Enabled */
|
||
lan8710a_reg_set(CPDMA_TX_CONTROL, CPDMA_TX_EN); /* TX Enabled */
|
||
|
||
/* Enabling first channel Rx interrupt */
|
||
lan8710a_reg_set(CPDMA_RX_INTMASK_SET, CPDMA_FIRST_CHAN_INT);
|
||
|
||
/*
|
||
* Writing the address of the first buffer descriptor in the queue
|
||
* (nonzero value)to the channel’s head descriptor pointer in the
|
||
* channel’s Rx DMA state.
|
||
*/
|
||
lan8710a_reg_write(CPDMA_STRAM_RX_HDP(0),
|
||
(u32_t)lan8710a_state.rx_desc_phy);
|
||
|
||
lan8710a_state.rx_desc_idx = 0;
|
||
lan8710a_state.tx_desc_idx = 0;
|
||
}
|
||
|
||
/*============================================================================*
|
||
* lan8710a_init_desc *
|
||
*============================================================================*/
|
||
static void
|
||
lan8710a_init_desc(void)
|
||
{
|
||
lan8710a_desc_t *p_rx_desc;
|
||
lan8710a_desc_t *p_tx_desc;
|
||
phys_bytes buf_phys_addr;
|
||
u8_t *p_buf;
|
||
u8_t i;
|
||
|
||
/* Attempt to allocate. */
|
||
if ((lan8710a_state.p_rx_buf = alloc_contig((LAN8710A_NUM_RX_DESC
|
||
* LAN8710A_IOBUF_SIZE), AC_ALIGN4K,
|
||
&buf_phys_addr)) == NULL) {
|
||
panic("failed to allocate RX buffers.");
|
||
}
|
||
p_buf = lan8710a_state.p_rx_buf;
|
||
for (i = 0; i < LAN8710A_NUM_RX_DESC; i++) {
|
||
p_rx_desc = &(lan8710a_state.rx_desc[i]);
|
||
memset(p_rx_desc, 0x0, sizeof(lan8710a_desc_t));
|
||
p_rx_desc->pkt_len_flags = LAN8710A_DESC_FLAG_OWN;
|
||
p_rx_desc->buffer_length_off = LAN8710A_IOBUF_SIZE;
|
||
p_rx_desc->buffer_pointer = (u32_t)(buf_phys_addr +
|
||
(i * LAN8710A_IOBUF_SIZE));
|
||
|
||
p_rx_desc->next_pointer =
|
||
(u32_t)((i == (LAN8710A_NUM_RX_DESC - 1)) ?
|
||
(lan8710a_state.rx_desc_phy) :
|
||
(lan8710a_state.rx_desc_phy +
|
||
((i + 1) * sizeof(lan8710a_desc_t))));
|
||
}
|
||
|
||
/* Attempt to allocate. */
|
||
if ((lan8710a_state.p_tx_buf = alloc_contig((LAN8710A_NUM_TX_DESC
|
||
* LAN8710A_IOBUF_SIZE), AC_ALIGN4K,
|
||
&buf_phys_addr)) == NULL) {
|
||
panic("failed to allocate TX buffers");
|
||
}
|
||
p_buf = lan8710a_state.p_tx_buf;
|
||
for (i = 0; i < LAN8710A_NUM_TX_DESC; i++) {
|
||
p_tx_desc = &(lan8710a_state.tx_desc[i]);
|
||
memset(p_tx_desc, 0x0, sizeof(lan8710a_desc_t));
|
||
p_tx_desc->buffer_pointer = (u32_t)(buf_phys_addr +
|
||
(i * LAN8710A_IOBUF_SIZE));
|
||
}
|
||
lan8710a_state.rx_desc_idx = 0;
|
||
lan8710a_state.tx_desc_idx = 0;
|
||
}
|
||
|
||
/*============================================================================*
|
||
* lan8710a_init_hw *
|
||
*============================================================================*/
|
||
static int
|
||
lan8710a_init_hw(void)
|
||
{
|
||
int r, i;
|
||
|
||
lan8710a_state.status |= LAN8710A_ENABLED;
|
||
|
||
/*
|
||
* Set the interrupt handler and policy. Do not automatically
|
||
* re-enable interrupts. Return the IRQ line number on interrupts.
|
||
*/
|
||
lan8710a_state.irq_rx_hook = RX_INT;
|
||
if ((r = sys_irqsetpolicy(LAN8710A_RX_INTR, 0,
|
||
&lan8710a_state.irq_rx_hook)) != OK) {
|
||
panic("sys_irqsetpolicy failed: %d", r);
|
||
}
|
||
lan8710a_state.irq_tx_hook = TX_INT;
|
||
if ((r = sys_irqsetpolicy(LAN8710A_TX_INTR, 0,
|
||
&lan8710a_state.irq_tx_hook)) != OK) {
|
||
panic("sys_irqsetpolicy failed: %d", r);
|
||
}
|
||
|
||
/* Reset hardware. */
|
||
lan8710a_reset_hw();
|
||
|
||
/*
|
||
* Select the Interface (GMII/RGMII/MII) Mode in the Control Module.
|
||
* Port1 GMII/MII Mode, Port2 not used.
|
||
*/
|
||
lan8710a_reg_write(GMII_SEL, (GMII2_SEL_BIT1 | GMII2_SEL_BIT0));
|
||
|
||
/*
|
||
* Configure pads (PIN muxing) as per the Interface Selected using the
|
||
* appropriate pin muxing conf_xxx registers in the Control Module.
|
||
*
|
||
* CONF_MOD_SLEW_CTRL when 0 - Fast Mode, when 1 - Slow Mode
|
||
* CONF_MOD_RX_ACTIVE when 0 - Only output, when 1 - Also input
|
||
* CONF_MOD_PU_TYPESEL when 0 - Pull-down, when 1 - Pull-up
|
||
* CONF_MOD_PUDEN when 0 Pull* enabled, when 1 Pull* disabled
|
||
* CONF_MOD_MMODE_MII selects pin to work for MII interface
|
||
*/
|
||
lan8710a_reg_unset(CONF_MII1_COL, CONF_MOD_SLEW_CTRL);
|
||
lan8710a_reg_set(CONF_MII1_COL, CONF_MOD_RX_ACTIVE);
|
||
lan8710a_reg_set(CONF_MII1_COL, CONF_MOD_PU_TYPESEL);
|
||
lan8710a_reg_unset(CONF_MII1_COL, CONF_MOD_PUDEN);
|
||
lan8710a_reg_unset(CONF_MII1_COL, CONF_MOD_MMODE_MII);
|
||
|
||
lan8710a_reg_unset(CONF_MII1_CRS, CONF_MOD_SLEW_CTRL);
|
||
lan8710a_reg_set(CONF_MII1_CRS, CONF_MOD_RX_ACTIVE);
|
||
lan8710a_reg_set(CONF_MII1_CRS, CONF_MOD_PU_TYPESEL);
|
||
lan8710a_reg_unset(CONF_MII1_CRS, CONF_MOD_PUDEN);
|
||
lan8710a_reg_unset(CONF_MII1_CRS, CONF_MOD_MMODE_MII);
|
||
|
||
lan8710a_reg_unset(CONF_MII1_RX_ER, CONF_MOD_SLEW_CTRL);
|
||
lan8710a_reg_set(CONF_MII1_RX_ER, CONF_MOD_RX_ACTIVE);
|
||
lan8710a_reg_set(CONF_MII1_RX_ER, CONF_MOD_PU_TYPESEL);
|
||
lan8710a_reg_unset(CONF_MII1_RX_ER, CONF_MOD_PUDEN);
|
||
lan8710a_reg_unset(CONF_MII1_RX_ER, CONF_MOD_MMODE_MII);
|
||
|
||
lan8710a_reg_unset(CONF_MII1_TX_EN, CONF_MOD_SLEW_CTRL);
|
||
lan8710a_reg_unset(CONF_MII1_TX_EN, CONF_MOD_RX_ACTIVE);
|
||
lan8710a_reg_set(CONF_MII1_TX_EN, CONF_MOD_PUDEN);
|
||
lan8710a_reg_unset(CONF_MII1_TX_EN, CONF_MOD_MMODE_MII);
|
||
|
||
lan8710a_reg_unset(CONF_MII1_RX_DV, CONF_MOD_SLEW_CTRL);
|
||
lan8710a_reg_set(CONF_MII1_RX_DV, CONF_MOD_RX_ACTIVE);
|
||
lan8710a_reg_set(CONF_MII1_RX_DV, CONF_MOD_PU_TYPESEL);
|
||
lan8710a_reg_unset(CONF_MII1_RX_DV, CONF_MOD_PUDEN);
|
||
lan8710a_reg_unset(CONF_MII1_RX_DV, CONF_MOD_MMODE_MII);
|
||
|
||
lan8710a_reg_unset(CONF_MII1_TXD3, CONF_MOD_SLEW_CTRL);
|
||
lan8710a_reg_unset(CONF_MII1_TXD3, CONF_MOD_RX_ACTIVE);
|
||
lan8710a_reg_set(CONF_MII1_TXD3, CONF_MOD_PUDEN);
|
||
lan8710a_reg_unset(CONF_MII1_TXD3, CONF_MOD_MMODE_MII);
|
||
|
||
lan8710a_reg_unset(CONF_MII1_TXD2, CONF_MOD_SLEW_CTRL);
|
||
lan8710a_reg_unset(CONF_MII1_TXD2, CONF_MOD_RX_ACTIVE);
|
||
lan8710a_reg_set(CONF_MII1_TXD2, CONF_MOD_PUDEN);
|
||
lan8710a_reg_unset(CONF_MII1_TXD2, CONF_MOD_MMODE_MII);
|
||
|
||
lan8710a_reg_unset(CONF_MII1_TXD1, CONF_MOD_SLEW_CTRL);
|
||
lan8710a_reg_unset(CONF_MII1_TXD1, CONF_MOD_RX_ACTIVE);
|
||
lan8710a_reg_set(CONF_MII1_TXD1, CONF_MOD_PUDEN);
|
||
lan8710a_reg_unset(CONF_MII1_TXD1, CONF_MOD_MMODE_MII);
|
||
|
||
lan8710a_reg_unset(CONF_MII1_TXD0, CONF_MOD_SLEW_CTRL);
|
||
lan8710a_reg_unset(CONF_MII1_TXD0, CONF_MOD_RX_ACTIVE);
|
||
lan8710a_reg_set(CONF_MII1_TXD0, CONF_MOD_PUDEN);
|
||
lan8710a_reg_unset(CONF_MII1_TXD0, CONF_MOD_MMODE_MII);
|
||
|
||
lan8710a_reg_unset(CONF_MII1_TX_CLK, CONF_MOD_SLEW_CTRL);
|
||
lan8710a_reg_set(CONF_MII1_TX_CLK, CONF_MOD_RX_ACTIVE);
|
||
lan8710a_reg_set(CONF_MII1_TX_CLK, CONF_MOD_PUDEN);
|
||
lan8710a_reg_unset(CONF_MII1_TX_CLK, CONF_MOD_MMODE_MII);
|
||
|
||
lan8710a_reg_unset(CONF_MII1_RX_CLK, CONF_MOD_SLEW_CTRL);
|
||
lan8710a_reg_set(CONF_MII1_RX_CLK, CONF_MOD_RX_ACTIVE);
|
||
lan8710a_reg_set(CONF_MII1_RX_CLK, CONF_MOD_PUDEN);
|
||
lan8710a_reg_unset(CONF_MII1_RX_CLK, CONF_MOD_MMODE_MII);
|
||
|
||
lan8710a_reg_unset(CONF_MII1_RXD3, CONF_MOD_SLEW_CTRL);
|
||
lan8710a_reg_set(CONF_MII1_RXD3, CONF_MOD_RX_ACTIVE);
|
||
lan8710a_reg_set(CONF_MII1_RXD3, CONF_MOD_PU_TYPESEL);
|
||
lan8710a_reg_unset(CONF_MII1_RXD3, CONF_MOD_PUDEN);
|
||
lan8710a_reg_unset(CONF_MII1_RXD3, CONF_MOD_MMODE_MII);
|
||
|
||
lan8710a_reg_unset(CONF_MII1_RXD2, CONF_MOD_SLEW_CTRL);
|
||
lan8710a_reg_set(CONF_MII1_RXD2, CONF_MOD_RX_ACTIVE);
|
||
lan8710a_reg_set(CONF_MII1_RXD2, CONF_MOD_PU_TYPESEL);
|
||
lan8710a_reg_unset(CONF_MII1_RXD2, CONF_MOD_PUDEN);
|
||
lan8710a_reg_unset(CONF_MII1_RXD2, CONF_MOD_MMODE_MII);
|
||
|
||
lan8710a_reg_unset(CONF_MII1_RXD1, CONF_MOD_SLEW_CTRL);
|
||
lan8710a_reg_set(CONF_MII1_RXD1, CONF_MOD_RX_ACTIVE);
|
||
lan8710a_reg_set(CONF_MII1_RXD1, CONF_MOD_PU_TYPESEL);
|
||
lan8710a_reg_unset(CONF_MII1_RXD1, CONF_MOD_PUDEN);
|
||
lan8710a_reg_unset(CONF_MII1_RXD1, CONF_MOD_MMODE_MII);
|
||
|
||
lan8710a_reg_unset(CONF_MII1_RXD0, CONF_MOD_SLEW_CTRL);
|
||
lan8710a_reg_set(CONF_MII1_RXD0, CONF_MOD_RX_ACTIVE);
|
||
lan8710a_reg_set(CONF_MII1_RXD0, CONF_MOD_PU_TYPESEL);
|
||
lan8710a_reg_unset(CONF_MII1_RXD0, CONF_MOD_PUDEN);
|
||
lan8710a_reg_unset(CONF_MII1_RXD0, CONF_MOD_MMODE_MII);
|
||
|
||
lan8710a_reg_unset(CONF_MDIO, CONF_MOD_SLEW_CTRL);
|
||
lan8710a_reg_set(CONF_MDIO, CONF_MOD_RX_ACTIVE);
|
||
lan8710a_reg_set(CONF_MDIO, CONF_MOD_PU_TYPESEL);
|
||
lan8710a_reg_unset(CONF_MDIO, CONF_MOD_PUDEN);
|
||
lan8710a_reg_unset(CONF_MDIO, CONF_MOD_MMODE_MII);
|
||
|
||
lan8710a_reg_unset(CONF_MDC, CONF_MOD_SLEW_CTRL);
|
||
lan8710a_reg_unset(CONF_MDC, CONF_MOD_RX_ACTIVE);
|
||
lan8710a_reg_set(CONF_MDC, CONF_MOD_PUDEN);
|
||
lan8710a_reg_unset(CONF_MDC, CONF_MOD_MMODE_MII);
|
||
|
||
/* Apply soft reset to 3PSW Subsytem, CPSW_3G, CPGMAC_SL, and CPDMA. */
|
||
lan8710a_reg_write(CPSW_SS_SOFT_RESET, SOFT_RESET);
|
||
lan8710a_reg_write(CPSW_SL_SOFT_RESET(1), SOFT_RESET);
|
||
lan8710a_reg_write(CPSW_SL_SOFT_RESET(2), SOFT_RESET);
|
||
|
||
/* Wait for software resets completion */
|
||
while ((lan8710a_reg_read(CPSW_SS_SOFT_RESET) & SOFT_RESET) ||
|
||
(lan8710a_reg_read(CPSW_SL_SOFT_RESET(1)) & SOFT_RESET) ||
|
||
(lan8710a_reg_read(CPSW_SL_SOFT_RESET(2)) & SOFT_RESET));
|
||
|
||
/* Configure the Statistics Port Enable register. */
|
||
/* Enable port 0 and 1 statistics. */
|
||
lan8710a_reg_write(CPSW_SS_STAT_PORT_EN, (CPSW_P1_STAT_EN |
|
||
CPSW_P0_STAT_EN));
|
||
|
||
/*
|
||
* Configure the ALE.
|
||
* Enabling Ale.
|
||
* All packets received on ports 1 are
|
||
* sent to the host (only to the host).
|
||
*/
|
||
lan8710a_reg_write(CPSW_ALE_CONTROL, (CPSW_ALE_ENABLE |
|
||
CPSW_ALE_BYPASS));
|
||
/* Port 0 (host) in forwarding mode. */
|
||
lan8710a_reg_write(CPSW_ALE_PORTCTL0, CPSW_ALE_PORT_FWD);
|
||
/* Port 1 in forwarding mode. */
|
||
lan8710a_reg_write(CPSW_ALE_PORTCTL1, CPSW_ALE_PORT_FWD);
|
||
|
||
/*
|
||
* Configure CPSW_SL Register
|
||
* Full duplex mode.
|
||
*/
|
||
lan8710a_reg_write(CPSW_SL_MACCONTROL(1), CPSW_SL_FULLDUPLEX);
|
||
|
||
/* Initialize MDIO Protocol */
|
||
lan8710a_init_mdio();
|
||
|
||
/* Getting MAC Address */
|
||
lan8710a_init_addr();
|
||
|
||
/* Initialize descriptors */
|
||
lan8710a_init_desc();
|
||
|
||
/* Reset and initialize CPDMA */
|
||
lan8710a_dma_reset_init();
|
||
|
||
/*
|
||
* Configure the Interrupts.
|
||
* Routing all channel Rx int to RX_PULSE signal.
|
||
*/
|
||
lan8710a_reg_set(CPSW_WR_C0_RX_EN, CPSW_FIRST_CHAN_INT);
|
||
|
||
/*
|
||
* Enabling LAN8710A Auto-negotiation
|
||
*/
|
||
lan8710a_phy_write(LAN8710A_CTRL_REG, LAN8710A_AUTO_NEG);
|
||
|
||
/* Waiting for auto-negotiaion completion. */
|
||
for (i = 0; !(lan8710a_phy_read(LAN8710A_STATUS_REG) &
|
||
LAN8710A_AUTO_NEG_COMPL); ++i) {
|
||
if (i == 100) {
|
||
LAN8710A_DEBUG_PRINT(("Autonegotiation failed"));
|
||
break;
|
||
}
|
||
tickdelay(100);
|
||
}
|
||
|
||
/* GMII RX and TX release from reset. */
|
||
lan8710a_reg_set(CPSW_SL_MACCONTROL(1), CPSW_SL_GMII_EN);
|
||
|
||
/* Enable interrupts. */
|
||
lan8710a_enable_interrupt(RX_INT | TX_INT);
|
||
|
||
return TRUE;
|
||
}
|
||
|
||
/*============================================================================*
|
||
* lan8710a_init_mdio *
|
||
*============================================================================*/
|
||
static void
|
||
lan8710a_init_mdio(void)
|
||
{
|
||
u16_t address = 0;
|
||
u32_t r;
|
||
|
||
/* Clearing MDIOCONTROL register */
|
||
lan8710a_reg_write(MDIOCONTROL, 0);
|
||
/* Configure the PREAMBLE and CLKDIV in the MDIO control register */
|
||
lan8710a_reg_unset(MDIOCONTROL, MDIO_PREAMBLE); /* CLKDIV default */
|
||
/* Enable sending MDIO frame preambles */
|
||
lan8710a_reg_set(MDIOCONTROL, (MDCLK_DIVIDER | MDIO_ENABLE));
|
||
/* Enable the MDIO module by setting the ENABLE bit in MDIOCONTROL */
|
||
|
||
while (!(r = lan8710a_reg_read(MDIOALIVE)));
|
||
|
||
/* Get PHY address */
|
||
while (r >>= 1) {
|
||
++address;
|
||
}
|
||
lan8710a_state.phy_address = address;
|
||
|
||
/* Setup appropiate address in MDIOUSERPHYSEL0 */
|
||
lan8710a_reg_set(MDIOUSERPHYSEL0, address);
|
||
}
|
||
|
||
/*============================================================================*
|
||
* lan8710a_writev_s *
|
||
*============================================================================*/
|
||
static void
|
||
lan8710a_writev_s(mp, from_int)
|
||
message *mp;
|
||
int from_int;
|
||
{
|
||
iovec_s_t iovec[LAN8710A_IOVEC_NR];
|
||
lan8710a_t *e = &lan8710a_state;
|
||
lan8710a_desc_t *p_tx_desc;
|
||
u8_t *p_buf;
|
||
int r, size, buf_data_len, i;
|
||
|
||
/* Are we called from the interrupt handler? */
|
||
if (!from_int) {
|
||
/* We cannot write twice simultaneously. */
|
||
assert(!(e->status & LAN8710A_WRITING));
|
||
|
||
/* Copy write message. */
|
||
e->tx_message = *mp;
|
||
e->client = mp->m_source;
|
||
e->status |= LAN8710A_WRITING;
|
||
|
||
/* verify vector count */
|
||
assert(mp->m_net_netdrv_dl_writev_s.count > 0);
|
||
assert(mp->m_net_netdrv_dl_writev_s.count < LAN8710A_IOVEC_NR);
|
||
|
||
/*
|
||
* Copy the I/O vector table.
|
||
*/
|
||
if ((r = sys_safecopyfrom(mp->m_source,
|
||
mp->m_net_netdrv_dl_writev_s.grant, 0,
|
||
(vir_bytes) iovec,
|
||
mp->m_net_netdrv_dl_writev_s.count *
|
||
sizeof(iovec_s_t))) != OK) {
|
||
panic("sys_safecopyfrom() failed: %d", r);
|
||
}
|
||
/* setup descriptors */
|
||
p_tx_desc = &(e->tx_desc[e->tx_desc_idx]);
|
||
|
||
/*
|
||
* Check if descriptor is available for host
|
||
* and drop the packet if not.
|
||
*/
|
||
if (LAN8710A_DESC_FLAG_OWN & p_tx_desc->pkt_len_flags) {
|
||
panic("No available transmit descriptor.");
|
||
}
|
||
|
||
/* virtual address of buffer */
|
||
p_buf = e->p_tx_buf + e->tx_desc_idx * LAN8710A_IOBUF_SIZE;
|
||
buf_data_len = 0;
|
||
for (i = 0; i < mp->m_net_netdrv_dl_writev_s.count; i++) {
|
||
if ((buf_data_len + iovec[i].iov_size)
|
||
> LAN8710A_IOBUF_SIZE) {
|
||
panic("packet too long");
|
||
}
|
||
|
||
/* copy data to buffer */
|
||
size = iovec[i].iov_size
|
||
< (LAN8710A_IOBUF_SIZE - buf_data_len) ?
|
||
iovec[i].iov_size
|
||
: (LAN8710A_IOBUF_SIZE - buf_data_len);
|
||
|
||
/* Copy bytes to TX queue buffers. */
|
||
if ((r = sys_safecopyfrom(mp->m_source,
|
||
iovec[i].iov_grant, 0,
|
||
(vir_bytes) p_buf, size)) != OK) {
|
||
panic("sys_safecopyfrom() failed: %d", r);
|
||
}
|
||
p_buf += size;
|
||
buf_data_len += size;
|
||
}
|
||
|
||
/* set descriptor length */
|
||
p_tx_desc->buffer_length_off = buf_data_len;
|
||
/* set flags */
|
||
p_tx_desc->pkt_len_flags = (LAN8710A_DESC_FLAG_OWN |
|
||
LAN8710A_DESC_FLAG_SOP |
|
||
LAN8710A_DESC_FLAG_EOP |
|
||
TX_DESC_TO_PORT1 |
|
||
TX_DESC_TO_PORT_EN);
|
||
p_tx_desc->pkt_len_flags |= buf_data_len;
|
||
|
||
/* setup DMA transfer */
|
||
lan8710a_dma_config_tx(e->tx_desc_idx);
|
||
|
||
e->tx_desc_idx++;
|
||
if (LAN8710A_NUM_TX_DESC == e->tx_desc_idx) {
|
||
e->tx_desc_idx = 0;
|
||
}
|
||
} else {
|
||
e->status |= LAN8710A_TRANSMIT;
|
||
}
|
||
reply(e);
|
||
}
|
||
|
||
/*============================================================================*
|
||
* lan8710a_readv_s *
|
||
*============================================================================*/
|
||
static void
|
||
lan8710a_readv_s(mp, from_int)
|
||
message *mp;
|
||
int from_int;
|
||
{
|
||
iovec_s_t iovec[LAN8710A_IOVEC_NR];
|
||
lan8710a_t *e = &lan8710a_state;
|
||
lan8710a_desc_t *p_rx_desc;
|
||
u32_t flags;
|
||
u8_t *p_buf;
|
||
u16_t pkt_data_len;
|
||
u16_t buf_bytes, buf_len;
|
||
int i, r, size;
|
||
|
||
/* Are we called from the interrupt handler? */
|
||
if (!from_int) {
|
||
e->rx_message = *mp;
|
||
e->client = mp->m_source;
|
||
e->status |= LAN8710A_READING;
|
||
e->rx_size = 0;
|
||
|
||
assert(e->rx_message.m_net_netdrv_dl_readv_s.count > 0);
|
||
assert(e->rx_message.m_net_netdrv_dl_readv_s.count < LAN8710A_IOVEC_NR);
|
||
}
|
||
if (e->status & LAN8710A_READING) {
|
||
/*
|
||
* Copy the I/O vector table first.
|
||
*/
|
||
if ((r = sys_safecopyfrom(e->rx_message.m_source,
|
||
e->rx_message.m_net_netdrv_dl_readv_s.grant, 0,
|
||
(vir_bytes) iovec,
|
||
e->rx_message.m_net_netdrv_dl_readv_s.count *
|
||
sizeof(iovec_s_t))) != OK) {
|
||
panic("sys_safecopyfrom() failed: %d", r);
|
||
}
|
||
|
||
/*
|
||
* Only handle one packet at a time.
|
||
*/
|
||
p_rx_desc = &(e->rx_desc[e->rx_desc_idx]);
|
||
/* find next OWN descriptor with SOP flag */
|
||
while ((0 == (LAN8710A_DESC_FLAG_SOP &
|
||
p_rx_desc->pkt_len_flags)) &&
|
||
(0 == (LAN8710A_DESC_FLAG_OWN &
|
||
p_rx_desc->pkt_len_flags))) {
|
||
p_rx_desc->buffer_length_off = LAN8710A_IOBUF_SIZE;
|
||
/* set ownership of current descriptor to EMAC */
|
||
p_rx_desc->pkt_len_flags = LAN8710A_DESC_FLAG_OWN;
|
||
|
||
e->rx_desc_idx++;
|
||
if (LAN8710A_NUM_RX_DESC == e->rx_desc_idx)
|
||
e->rx_desc_idx = 0;
|
||
p_rx_desc = &(e->rx_desc[e->rx_desc_idx]);
|
||
}
|
||
if (0 == (LAN8710A_DESC_FLAG_SOP & p_rx_desc->pkt_len_flags)) {
|
||
/* SOP was not found */
|
||
reply(e);
|
||
return;
|
||
}
|
||
|
||
/*
|
||
* Copy to vector elements.
|
||
*/
|
||
pkt_data_len = 0;
|
||
buf_bytes = 0;
|
||
p_buf = e->p_rx_buf + e->rx_desc_idx * LAN8710A_IOBUF_SIZE;
|
||
for (i = 0; i < e->rx_message.m_net_netdrv_dl_readv_s.count; i++) {
|
||
buf_len = p_rx_desc->buffer_length_off & 0xFFFF;
|
||
if (buf_bytes == buf_len) {
|
||
/* Whole buffer move to the next descriptor */
|
||
p_rx_desc->buffer_length_off =
|
||
LAN8710A_IOBUF_SIZE;
|
||
/* set ownership of current desc to EMAC */
|
||
p_rx_desc->pkt_len_flags =
|
||
LAN8710A_DESC_FLAG_OWN;
|
||
buf_bytes = 0;
|
||
|
||
e->rx_desc_idx++;
|
||
if (LAN8710A_NUM_RX_DESC == e->rx_desc_idx)
|
||
e->rx_desc_idx = 0;
|
||
p_rx_desc = &(e->rx_desc[e->rx_desc_idx]);
|
||
p_buf = e->p_rx_buf + (e->rx_desc_idx *
|
||
LAN8710A_IOBUF_SIZE) +
|
||
(p_rx_desc->buffer_length_off >> 16);
|
||
buf_len = p_rx_desc->buffer_length_off & 0xFFFF;
|
||
}
|
||
size = iovec[i].iov_size < (buf_len - buf_bytes) ?
|
||
iovec[i].iov_size :
|
||
(buf_len - buf_bytes);
|
||
|
||
if ((r = sys_safecopyto(e->rx_message.m_source,
|
||
iovec[i].iov_grant, 0,
|
||
(vir_bytes) p_buf,
|
||
size)) != OK) {
|
||
panic("sys_safecopyto() failed: %d", r);
|
||
}
|
||
p_buf += size;
|
||
buf_bytes += size;
|
||
pkt_data_len += size;
|
||
|
||
/* if EOP flag is set -> stop processing */
|
||
if ((LAN8710A_DESC_FLAG_EOP & p_rx_desc->pkt_len_flags) &&
|
||
(buf_bytes == buf_len)) {
|
||
/* end of packet */
|
||
break;
|
||
}
|
||
}
|
||
do {
|
||
/* reset owned descriptors up to EOP flag */
|
||
flags = p_rx_desc->pkt_len_flags;
|
||
p_rx_desc->buffer_length_off = LAN8710A_IOBUF_SIZE;
|
||
/* set ownership of current descriptor to EMAC */
|
||
p_rx_desc->pkt_len_flags = LAN8710A_DESC_FLAG_OWN;
|
||
|
||
e->rx_desc_idx++;
|
||
if (LAN8710A_NUM_RX_DESC == e->rx_desc_idx)
|
||
e->rx_desc_idx = 0;
|
||
|
||
p_rx_desc = &(e->rx_desc[e->rx_desc_idx]);
|
||
}
|
||
while (0 == (flags & LAN8710A_DESC_FLAG_EOP));
|
||
|
||
/*
|
||
* Update state.
|
||
*/
|
||
e->status |= LAN8710A_RECEIVED;
|
||
e->rx_size = pkt_data_len;
|
||
|
||
}
|
||
reply(e);
|
||
}
|
||
|
||
/*============================================================================*
|
||
* lan8710a_phy_write *
|
||
*============================================================================*/
|
||
static void
|
||
lan8710a_phy_write(reg, value)
|
||
u32_t reg;
|
||
u32_t value;
|
||
{
|
||
if (!(lan8710a_reg_read(MDIOUSERACCESS0) & MDIO_GO)) {
|
||
/* Clearing MDIOUSERACCESS0 register */
|
||
lan8710a_reg_write(MDIOUSERACCESS0, 0);
|
||
/* Setting proper values in MDIOUSERACCESS0 */
|
||
lan8710a_reg_set(MDIOUSERACCESS0, MDIO_WRITE);
|
||
lan8710a_reg_set(MDIOUSERACCESS0, reg << MDIO_REGADR);
|
||
lan8710a_reg_set(MDIOUSERACCESS0,
|
||
lan8710a_state.phy_address << MDIO_PHYADR);
|
||
/* Data written only 16 bits. */
|
||
lan8710a_reg_set(MDIOUSERACCESS0, (value & 0xFFFF) << MDIO_DATA);
|
||
lan8710a_reg_set(MDIOUSERACCESS0, MDIO_GO);
|
||
|
||
/* Waiting for writing completion */
|
||
while (lan8710a_reg_read(MDIOUSERACCESS0) & MDIO_GO);
|
||
}
|
||
}
|
||
|
||
/*============================================================================*
|
||
* lan8710a_phy_read *
|
||
*============================================================================*/
|
||
static u32_t
|
||
lan8710a_phy_read(reg)
|
||
u32_t reg;
|
||
{
|
||
u32_t value = 0xFFFFFFFF;
|
||
|
||
if (!(lan8710a_reg_read(MDIOUSERACCESS0) & MDIO_GO)) {
|
||
/* Clearing MDIOUSERACCESS0 register */
|
||
lan8710a_reg_write(MDIOUSERACCESS0, 0);
|
||
/* Setting proper values in MDIOUSERACCESS0 */
|
||
lan8710a_reg_unset(MDIOUSERACCESS0, MDIO_WRITE);
|
||
/* Reg number must be 5 bit long */
|
||
lan8710a_reg_set(MDIOUSERACCESS0, (reg & 0x1F) << MDIO_REGADR);
|
||
/* Addr must be 5 bit long */
|
||
lan8710a_reg_set(MDIOUSERACCESS0,
|
||
(lan8710a_state.phy_address & 0x1F) << MDIO_PHYADR);
|
||
lan8710a_reg_set(MDIOUSERACCESS0, MDIO_GO);
|
||
|
||
/* Waiting for reading completion */
|
||
while ((lan8710a_reg_read(MDIOUSERACCESS0) & MDIO_GO)
|
||
&& !(lan8710a_reg_read(MDIOUSERACCESS0) & MDIO_ACK));
|
||
|
||
/* Reading data */
|
||
value = lan8710a_reg_read(MDIOUSERACCESS0) & 0xFFFF;
|
||
}
|
||
return value;
|
||
}
|
||
|
||
/*============================================================================*
|
||
* lan8710a_reset_hw *
|
||
*============================================================================*/
|
||
static void
|
||
lan8710a_reset_hw()
|
||
{
|
||
/* Assert a Device Reset signal. */
|
||
lan8710a_phy_write(LAN8710A_CTRL_REG, LAN8710A_SOFT_RESET);
|
||
|
||
/* Waiting for reset completion. */
|
||
while (lan8710a_phy_read(LAN8710A_CTRL_REG) & LAN8710A_SOFT_RESET);
|
||
}
|
||
|
||
/*============================================================================*
|
||
* lan8710a_reg_read *
|
||
*============================================================================*/
|
||
static u32_t
|
||
lan8710a_reg_read(reg)
|
||
volatile u32_t *reg;
|
||
{
|
||
u32_t value;
|
||
|
||
/* Read from memory mapped register. */
|
||
value = *reg;
|
||
|
||
/* Return the result. */
|
||
return value;
|
||
}
|
||
|
||
/*============================================================================*
|
||
* lan8710a_reg_write *
|
||
*============================================================================*/
|
||
static void
|
||
lan8710a_reg_write(reg, value)
|
||
volatile u32_t *reg;
|
||
u32_t value;
|
||
{
|
||
/* Write to memory mapped register. */
|
||
*reg = value;
|
||
}
|
||
|
||
/*============================================================================*
|
||
* lan8710a_reg_set *
|
||
*============================================================================*/
|
||
static void
|
||
lan8710a_reg_set(reg, value)
|
||
volatile u32_t *reg;
|
||
u32_t value;
|
||
{
|
||
u32_t data;
|
||
|
||
/* First read the current value. */
|
||
data = lan8710a_reg_read(reg);
|
||
|
||
/* Set value, and write back. */
|
||
lan8710a_reg_write(reg, data | value);
|
||
}
|
||
|
||
/*============================================================================*
|
||
* lan8710a_reg_unset *
|
||
*============================================================================*/
|
||
static void
|
||
lan8710a_reg_unset(reg, value)
|
||
volatile u32_t *reg;
|
||
u32_t value;
|
||
{
|
||
u32_t data;
|
||
|
||
/* First read the current value. */
|
||
data = lan8710a_reg_read(reg);
|
||
|
||
/* Unset value, and write back. */
|
||
lan8710a_reg_write(reg, data & ~value);
|
||
}
|
||
|
||
/*============================================================================*
|
||
* mess_reply *
|
||
*============================================================================*/
|
||
static void
|
||
mess_reply(req, reply)
|
||
message *req;message *reply;
|
||
{
|
||
if (ipc_send(req->m_source, reply) != OK) {
|
||
panic("unable to send reply message");
|
||
}
|
||
}
|
||
|
||
/*============================================================================*
|
||
* reply *
|
||
*============================================================================*/
|
||
static void
|
||
reply(e)
|
||
lan8710a_t *e;
|
||
{
|
||
message msg;
|
||
int r;
|
||
|
||
/* Only reply to client for read/write request. */
|
||
if (!(e->status & LAN8710A_READING ||
|
||
e->status & LAN8710A_WRITING)) {
|
||
return;
|
||
}
|
||
/* Construct reply message. */
|
||
msg.m_type = DL_TASK_REPLY;
|
||
msg.m_netdrv_net_dl_task.flags = DL_NOFLAGS;
|
||
msg.m_netdrv_net_dl_task.count = 0;
|
||
|
||
/* Did we successfully receive packet(s)? */
|
||
if (e->status & LAN8710A_READING &&
|
||
e->status & LAN8710A_RECEIVED) {
|
||
msg.m_netdrv_net_dl_task.flags |= DL_PACK_RECV;
|
||
msg.m_netdrv_net_dl_task.count =
|
||
e->rx_size >= ETH_MIN_PACK_SIZE ?
|
||
e->rx_size : ETH_MIN_PACK_SIZE;
|
||
|
||
/* Clear flags. */
|
||
e->status &= ~(LAN8710A_READING | LAN8710A_RECEIVED);
|
||
}
|
||
/* Did we successfully transmit packet(s)? */
|
||
if (e->status & LAN8710A_TRANSMIT &&
|
||
e->status & LAN8710A_WRITING) {
|
||
msg.m_netdrv_net_dl_task.flags |= DL_PACK_SEND;
|
||
|
||
/* Clear flags. */
|
||
e->status &= ~(LAN8710A_WRITING | LAN8710A_TRANSMIT);
|
||
}
|
||
|
||
/* Acknowledge to INET. */
|
||
if ((r = ipc_send(e->client, &msg) != OK)) {
|
||
panic("ipc_send() failed: %d", r);
|
||
}
|
||
}
|