457 lines
17 KiB
C
457 lines
17 KiB
C
/* $NetBSD: armreg.h,v 1.2 2015/04/27 06:54:12 skrll Exp $ */
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/*-
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* Copyright (c) 2014 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Matt Thomas of 3am Software Foundry.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _AARCH64_ARMREG_H_
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#define _AARCH64_ARMREG_H_
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#ifdef __aarch64__
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#include <sys/types.h>
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#define AARCH64REG_READ_INLINE2(regname, regdesc) \
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static uint64_t inline \
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reg_##regname##_read(void) \
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{ \
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uint64_t __rv; \
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__asm("mrs %0, " #regdesc : "=r"(__rv)); \
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return __rv; \
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}
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#define AARCH64REG_WRITE_INLINE2(regname, regdesc) \
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static void inline \
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reg_##regname##_write(uint64_t __val) \
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{ \
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__asm("msr " #regdesc ", %0" :: "r"(__val)); \
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}
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#define AARCH64REG_WRITEIMM_INLINE2(regname, regdesc) \
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static void inline \
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reg_##regname##_write(uint64_t __val) \
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{ \
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__asm("msr " #regdesc ", %0" :: "n"(__val)); \
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}
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#define AARCH64REG_READ_INLINE(regname) \
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AARCH64REG_READ_INLINE2(regname, regname)
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#define AARCH64REG_WRITE_INLINE(regname) \
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AARCH64REG_WRITE_INLINE2(regname, regname)
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#define AARCH64REG_WRITEIMM_INLINE(regname) \
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AARCH64REG_WRITEIMM_INLINE2(regname, regname)
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/*
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* System registers available at EL0 (user)
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*/
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AARCH64REG_READ_INLINE(ctr_el0) // Cache Type Register
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static const uintmax_t
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CTR_EL0_CWG_LINE = __BITS(27,24), // Cacheback Writeback Granule
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CTR_EL0_ERG_LINE = __BITS(23,20), // Exclusives Reservation Granule
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CTR_EL0_DMIN_LINE = __BITS(19,16), // Dcache MIN LINE size (log2 - 2)
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CTR_EL0_L1IP_MASK = __BITS(15,14),
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CTR_EL0_L1IP_AIVIVT = 1, // ASID-tagged Virtual Index, Virtual Tag
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CTR_EL0_L1IP_VIPT = 2, // Virtual Index, Physical Tag
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CTR_EL0_L1IP_PIPT = 3, // Physical Index, Physical Tag
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CTR_EL0_IMIN_LINE = __BITS(3,0); // Icache MIN LINE size (log2 - 2)
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AARCH64REG_READ_INLINE(dczid_el0) // Data Cache Zero ID Register
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static const uintmax_t
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DCZID_DZP = __BIT(4), // Data Zero Prohibited
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DCZID_BS = __BITS(3,0); // Block Size (log2 - 2)
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AARCH64REG_READ_INLINE(tpidrro_el0) // Thread Pointer ID Register (RO)
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AARCH64REG_READ_INLINE(fpcr) // Floating Point Control Register
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AARCH64REG_WRITE_INLINE(fpcr)
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static const uintmax_t
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FPCR_AHP = __BIT(26), // Alternative Half Precision
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FPCR_DN = __BIT(25), // Default Nan Control
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FPCR_FZ = __BIT(24), // Flush-To-Zero
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FPCR_RMODE = __BITS(23,22),// Rounding Mode
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FPCR_RN = 0, // Round Nearest
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FPCR_RP = 1, // Round towards Plus infinity
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FPCR_RM = 2, // Round towards Minus infinity
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FPCR_RZ = 3, // Round towards Zero
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FPCR_STRIDE = __BITS(21,20),
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FPCR_LEN = __BITS(18,16),
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FPCR_IDE = __BIT(15), // Input Denormal Exception enable
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FPCR_IXE = __BIT(12), // IneXact Exception enable
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FPCR_UFE = __BIT(11), // UnderFlow Exception enable
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FPCR_OFE = __BIT(10), // OverFlow Exception enable
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FPCR_DZE = __BIT(9), // Divide by Zero Exception enable
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FPCR_IOE = __BIT(8), // Invalid Operation Exception enable
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FPCR_ESUM = 0x1F00;
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AARCH64REG_READ_INLINE(fpsr) // Floating Point Status Register
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AARCH64REG_WRITE_INLINE(fpsr)
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static const uintmax_t
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FPSR_N32 = __BIT(31), // AARCH32 Negative
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FPSR_Z32 = __BIT(30), // AARCH32 Zero
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FPSR_C32 = __BIT(29), // AARCH32 Carry
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FPSR_V32 = __BIT(28), // AARCH32 Overflow
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FPSR_QC = __BIT(27), // SIMD Saturation
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FPSR_IDC = __BIT(7), // Input Denormal Cumulative status
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FPSR_IXC = __BIT(4), // IneXact Cumulative status
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FPSR_UFC = __BIT(3), // UnderFlow Cumulative status
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FPSR_OFC = __BIT(2), // OverFlow Cumulative status
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FPSR_DZC = __BIT(1), // Divide by Zero Cumulative status
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FPSR_IOC = __BIT(0), // Invalid Operation Cumulative status
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FPSR_CSUM = 0x1F;
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AARCH64REG_READ_INLINE(nzcv) // condition codes
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AARCH64REG_WRITE_INLINE(nzcv)
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static const uintmax_t
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NZCV_N = __BIT(31), // Negative
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NZCV_Z = __BIT(30), // Zero
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NZCV_C = __BIT(29), // Carry
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NZCV_V = __BIT(28); // Overflow
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AARCH64REG_READ_INLINE(tpidr_el0) // Thread Pointer ID Register (RW)
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AARCH64REG_WRITE_INLINE(tpidr_el0)
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/*
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* From here on, these can only be accessed at EL1 (kernel)
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*/
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/*
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* These are readonly registers
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*/
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AARCH64REG_READ_INLINE2(cbar_el1, s3_1_c15_c3_0) // Cortex-A57
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static const uintmax_t CBAR_PA = __BITS(47,18);
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AARCH64REG_READ_INLINE(clidr_el1)
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AARCH64REG_READ_INLINE(ccsidr_el1)
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AARCH64REG_READ_INLINE(id_afr0_el1)
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AARCH64REG_READ_INLINE(id_adr0_el1)
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AARCH64REG_READ_INLINE(id_isar0_el1)
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AARCH64REG_READ_INLINE(id_isar1_el1)
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AARCH64REG_READ_INLINE(id_isar2_el1)
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AARCH64REG_READ_INLINE(id_isar3_el1)
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AARCH64REG_READ_INLINE(id_isar4_el1)
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AARCH64REG_READ_INLINE(id_isar5_el1)
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AARCH64REG_READ_INLINE(id_mmfr0_el1)
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AARCH64REG_READ_INLINE(id_mmfr1_el1)
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AARCH64REG_READ_INLINE(id_mmfr2_el1)
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AARCH64REG_READ_INLINE(id_mmfr3_el1)
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AARCH64REG_READ_INLINE(id_prf0_el1)
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AARCH64REG_READ_INLINE(id_prf1_el1)
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AARCH64REG_READ_INLINE(isr_el1)
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AARCH64REG_READ_INLINE(midr_el1)
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AARCH64REG_READ_INLINE(mpidr_el1)
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AARCH64REG_READ_INLINE(mvfr0_el1)
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AARCH64REG_READ_INLINE(mvfr1_el1)
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AARCH64REG_READ_INLINE(mvfr2_el1)
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AARCH64REG_READ_INLINE(revidr_el1)
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/*
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* These are read/write registers
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*/
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AARCH64REG_READ_INLINE(ccselr_el1) // Cache Size Selection Register
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AARCH64REG_WRITE_INLINE(ccselr_el1)
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AARCH64REG_READ_INLINE(cpacr_el1) // Coprocessor Access Control Regiser
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AARCH64REG_WRITE_INLINE(cpacr_el1)
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static const uintmax_t
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CPACR_TTA = __BIT(28), // System Register Access Traps
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CPACR_FPEN = __BITS(21,20),
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CPACR_FPEN_NONE = __SHIFTIN(0, CPACR_FPEN),
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CPACR_FPEN_EL1 = __SHIFTIN(1, CPACR_FPEN),
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CPACR_FPEN_NONE_2 = __SHIFTIN(2, CPACR_FPEN),
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CPACR_FPEN_ALL = __SHIFTIN(3, CPACR_FPEN);
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AARCH64REG_READ_INLINE(elr_el1) // Exception Link Register
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AARCH64REG_WRITE_INLINE(elr_el1)
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AARCH64REG_READ_INLINE(esr_el1) // Exception Symdrone Register
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AARCH64REG_WRITE_INLINE(esr_el1)
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static const uintmax_t
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ESR_EC = __BITS(31,26), // Exception Cause
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ESR_EC_UNKOWN = 0, // AXX: Unknown Reason
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ESR_EC_WFX = 1, // AXX: WFI or WFE instruction execution
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ESR_EC_CP15_RT = 3, // A32: MCR/MRC access to CP15 !EC=0
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ESR_EC_CP15_RRT = 4, // A32: MCRR/MRRC access to CP15 !EC=0
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ESR_EC_CP14_RT = 5, // A32: MCR/MRC access to CP14
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ESR_EC_CP14_DT = 6, // A32: LDC/STC access to CP14
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ESR_EC_FP_ACCCES = 7, // AXX: Access to SIMD/FP Registers
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ESR_EC_FPID = 8, // A32: MCR/MRC access to CP10 !EC=7
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ESR_EC_CP14_RRT = 12, // A32: MRRC access to CP14
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ESR_EC_ILL_STATE = 14, // AXX: Illegal Execution State
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ESR_EC_SVC_A32 = 17, // A32: SVC Instruction Execution
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ESR_EC_HVC_A32 = 18, // A32: HVC Instruction Execution
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ESR_EC_SMC_A32 = 19, // A32: SMC Instruction Execution
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ESR_EC_SVC_A64 = 21, // A64: SVC Instruction Execution
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ESR_EC_HVC_A64 = 22, // A64: HVC Instruction Execution
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ESR_EC_SMC_A64 = 23, // A64: SMC Instruction Execution
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ESR_EC_SYS_REG = 24, // A64: MSR/MRS/SYS instruction (!EC0/1/7)
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ESR_EC_INSN_ABT_EL0 = 32, // AXX: Instruction Abort (EL0)
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ESR_EC_INSN_ABT_EL1 = 33, // AXX: Instruction Abort (EL1)
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ESR_EC_PC_ALIGNMENT = 34, // AXX: Misaligned PC
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ESR_EC_DATA_ABT_EL0 = 36, // AXX: Data Abort (EL0)
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ESR_EC_DATA_ABT_EL1 = 37, // AXX: Data Abort (EL1)
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ESR_EC_SP_ALIGNMENT = 38, // AXX: Misaligned SP
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ESR_EC_FP_TRAP_A32 = 40, // A32: FP Exception
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ESR_EC_FP_TRAP_A64 = 44, // A64: FP Exception
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ESR_EC_SERROR = 47, // AXX: SError Interrupt
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ESR_EC_BRKPNT_EL0 = 48, // AXX: Breakpoint Exception (EL0)
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ESR_EC_BRKPNT_EL1 = 49, // AXX: Breakpoint Exception (EL1)
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ESR_EC_SW_STEP_EL0 = 50, // AXX: Software Step (EL0)
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ESR_EC_SW_STEP_EL1 = 51, // AXX: Software Step (EL1)
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ESR_EC_WTCHPNT_EL0 = 52, // AXX: Watchpoint (EL0)
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ESR_EC_WTCHPNT_EL1 = 53, // AXX: Watchpoint (EL1)
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ESR_EC_BKPT_INSN_A32 = 56, // A32: BKPT Instruction Execution
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ESR_EC_VECTOR_CATCH = 58, // A32: Vector Catch Exception
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ESR_EC_BKPT_INSN_A64 = 60, // A64: BKPT Instruction Execution
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ESR_IL = __BIT(25), // Instruction Length (1=32-bit)
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ESR_ISS = __BITS(24,0); // Instruction Specific Syndrome
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AARCH64REG_READ_INLINE(far_el1) // Fault Address Register
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AARCH64REG_WRITE_INLINE(far_el1)
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AARCH64REG_READ_INLINE(mair_el1) // Main Id Register
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AARCH64REG_WRITE_INLINE(mair_el1)
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AARCH64REG_READ_INLINE(par_el1) // Physical Address Register
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AARCH64REG_WRITE_INLINE(par_el1)
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static const uintmax_t
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PAR_ATTR = __BITS(63,56),// F=0 memory attributes
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PAR_PA = __BITS(47,12),// F=0 physical address
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PAR_NS = __BIT(9), // F=0 non-secure
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PAR_S = __BIT(9), // F=1 failure stage
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PAR_SHA = __BITS(8,7), // F=0 shareability attribute
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PAR_SHA_NONE = 0,
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PAR_SHA_OUTER = 2,
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PAR_SHA_INNER = 3,
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PAR_PTW = __BIT(8), // F=1 partial table walk
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PAR_FST = __BITS(6,1), // F=1 fault status code
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PAR_F = __BIT(0); // translation failed
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AARCH64REG_READ_INLINE(rmr_el1) // Reset Management Register
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AARCH64REG_WRITE_INLINE(rmr_el1)
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AARCH64REG_READ_INLINE(rvbar_el1) // Reset Vector Base Address Register
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AARCH64REG_WRITE_INLINE(rvbar_el1)
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AARCH64REG_READ_INLINE(sctlr_el1) // System Control Register
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AARCH64REG_WRITE_INLINE(sctlr_el1)
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AARCH64REG_READ_INLINE(sp_el0) // Stack Pointer
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AARCH64REG_WRITE_INLINE(sp_el0)
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AARCH64REG_READ_INLINE(daif) // Debug Async Irq Fiq mask register
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AARCH64REG_WRITE_INLINE(daif)
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AARCH64REG_WRITEIMM_INLINE(daifclr)
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AARCH64REG_WRITEIMM_INLINE(daifset)
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static const uintmax_t
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DAIF_D = __BIT(3), // Debug Exception Mask
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DAIF_A = __BIT(2), // SError Abort Mask
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DAIF_I = __BIT(1), // IRQ Mask
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DAIF_F = __BIT(0); // FIQ Mask
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AARCH64REG_READ_INLINE(spsr_el1) // Saved Program Status Register
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AARCH64REG_WRITE_INLINE(spsr_el1)
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static const uintmax_t
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SPSR_NZCV = __BITS(31,28), // mask of N Z C V
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SPSR_N = __BIT(31), // Negative
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SPSR_Z = __BIT(30), // Zero
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SPSR_C = __BIT(29), // Carry
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SPSR_V = __BIT(28), // oVerflow
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SPSR_A32_Q = __BIT(27), // A32: Overflow
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SPSR_A32_J = __BIT(24), // A32: Jazelle Mode
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SPSR_A32_IT1 = __BIT(23), // A32: IT[1]
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SPSR_A32_IT0 = __BIT(22), // A32: IT[0]
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SPSR_SS = __BIT(21), // Software Step
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SPSR_IL = __BIT(20), // Instruction Length
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SPSR_GE = __BITS(19,16), // A32: SIMD GE
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SPSR_IT7 = __BIT(15), // A32: IT[7]
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SPSR_IT6 = __BIT(14), // A32: IT[6]
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SPSR_IT5 = __BIT(13), // A32: IT[5]
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SPSR_IT4 = __BIT(12), // A32: IT[4]
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SPSR_IT3 = __BIT(11), // A32: IT[3]
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SPSR_IT2 = __BIT(10), // A32: IT[2]
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SPSR_A64_D = __BIT(9), // A64: Debug Exception Mask
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SPSR_A32_E = __BIT(9), // A32: BE Endian Mode
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SPSR_A = __BIT(8), // Async abort (SError) Mask
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SPSR_I = __BIT(7), // IRQ Mask
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SPSR_F = __BIT(6), // FIQ Mask
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SPSR_A32_T = __BIT(5), // A32 Thumb Mode
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SPSR_M = __BITS(4,0), // Execution State
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SPSR_M_EL3H = 0x0d,
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SPSR_M_EL3T = 0x0c,
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SPSR_M_EL2H = 0x09,
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SPSR_M_EL2T = 0x08,
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SPSR_M_EL1H = 0x05,
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SPSR_M_EL1T = 0x04,
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SPSR_M_EL0T = 0x00,
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SPSR_M_SYS32 = 0x1f,
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SPSR_M_UND32 = 0x1b,
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SPSR_M_ABT32 = 0x17,
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SPSR_M_SVC32 = 0x13,
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SPSR_M_IRQ32 = 0x12,
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SPSR_M_FIQ32 = 0x11,
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SPSR_M_USR32 = 0x10;
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AARCH64REG_READ_INLINE(tcr_el1) // Translation Control Register
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AARCH64REG_WRITE_INLINE(tcr_el1)
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static const uintmax_t
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TCR_TBI1 = __BIT(38), // ignore Top Byte for TTBR1_EL1
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TCR_TBI0 = __BIT(37), // ignore Top Byte for TTBR0_EL1
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TCR_AS64K = __BIT(36), // Use 64K ASIDs
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TCR_IPS = __BITS(34,32), // Intermediate Phys Addr Size
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TCR_IPS_256TB = 5, // 48 bits (256 TB)
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TCR_IPS_64TB = 4, // 44 bits (16 TB)
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TCR_IPS_4TB = 3, // 42 bits ( 4 TB)
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TCR_IPS_1TB = 2, // 40 bits ( 1 TB)
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TCR_IPS_64GB = 1, // 36 bits (64 GB)
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TCR_IPS_4GB = 0, // 32 bits (4 GB)
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TCR_TG1 = __BITS(31,30), // Page Granule Size
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TCR_TG_4KB = 1, // 4KB page size
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TCR_TG_16KB = 2, // 16KB page size
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TCR_TG_64KB = 3, // 64KB page size
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TCR_SH1 = __BITS(29,28),
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TCR_SH_NONE = 0,
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TCR_SH_OUTER = 1,
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TCR_SH_INNER = 2,
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TCR_ORGN1 = __BITS(27,26),
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TCR_XRGN_NC = 0, // Non Cacheable
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TCR_XRGN_WB_WA = 1, // WriteBack WriteAllocate
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TCR_XRGN_WT = 2, // WriteThrough
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TCR_XRGN_WB = 3, // WriteBack
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TCR_IRGN1 = __BITS(25,24),
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TCR_EPD1 = __BIT(23), // Walk Disable for TTBR1_EL1
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TCR_A1 = __BIT(22), // ASID is in TTBR1_EL1
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TCR_T1SZ = __BITS(21,16), // Size offset for TTBR1_EL1
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TCR_TG0 = __BITS(15,14),
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TCR_SH0 = __BITS(13,12),
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TCR_ORGN0 = __BITS(11,10),
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TCR_IRGN0 = __BITS(9,8),
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TCR_EPD0 = __BIT(7), // Walk Disable for TTBR0
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TCR_T0SZ = __BITS(5,0); // Size offset for TTBR0_EL1
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#define TCR_PAGE_SIZE1(tcr) (1L << (__SHIFTOUT(tcr, TCR_TG1) * 2 + 10))
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AARCH64REG_READ_INLINE(tpidr_el1) // Thread ID Register (EL1)
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AARCH64REG_WRITE_INLINE(tpidr_el1)
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AARCH64REG_WRITE_INLINE(tpidrro_el0) // Thread ID Register (RO for EL0)
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AARCH64REG_READ_INLINE(ttbr0_el0) // Translation Table Base Register 0 EL0
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AARCH64REG_WRITE_INLINE(ttbr0_el0)
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AARCH64REG_READ_INLINE(ttbr0_el1) // Translation Table Base Register 0 EL0
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AARCH64REG_WRITE_INLINE(ttbr0_el1)
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AARCH64REG_READ_INLINE(ttbr1_el1) // Translation Table Base Register 1 EL1
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AARCH64REG_WRITE_INLINE(ttbr1_el1)
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static const uint64_t
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TTBR_ASID = __BITS(63, 48),
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TTBR_BADDR = __BITS(47, 0);
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AARCH64REG_READ_INLINE(vbar_el1) // Vector Base Address Register
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AARCH64REG_WRITE_INLINE(vbar_el1)
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AARCH64REG_READ_INLINE(pmccfiltr_el0)
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AARCH64REG_WRITE_INLINE(pmccfiltr_el0)
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static const uintmax_t
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PMCCFILTR_P = __BIT(31), // Don't count cycles in EL1
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PMCCFILTR_U = __BIT(30), // Don't count cycles in EL0
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PMCCFILTR_NSK = __BIT(29), // Don't count cycles in NS EL1
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PMCCFILTR_NSU = __BIT(28), // Don't count cycles in NS EL0
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PMCCFILTR_NSH = __BIT(27), // Don't count cycles in NS EL2
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PMCCFILTR_M = __BIT(26); // Don't count cycles in EL3
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AARCH64REG_READ_INLINE(pmccntr_el0)
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AARCH64REG_READ_INLINE(cntfrq_el0)
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AARCH64REG_READ_INLINE(cntkctl_el1)
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AARCH64REG_WRITE_INLINE(cntkctl_el1)
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static const uintmax_t
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CNTKCTL_EL0PTEN = __BIT(9), // EL0 access for CNTP CVAL/TVAL/CTL
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CNTKCTL_EL0VTEN = __BIT(8), // EL0 access for CNTV CVAL/TVAL/CTL
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CNTKCTL_ELNTI = __BITS(7,4),
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CNTKCTL_EVNTDIR = __BIT(3),
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CNTKCTL_EVNTEN = __BIT(2),
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CNTKCTL_EL0VCTEN = __BIT(1), // EL0 access for CNTVCT and CNTFRQ
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CNTKCTL_EL0PCTEN = __BIT(0); // EL0 access for CNTPCT and CNTFRQ
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AARCH64REG_READ_INLINE(cntp_ctl_el0)
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AARCH64REG_WRITE_INLINE(cntp_ctl_el0)
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AARCH64REG_READ_INLINE(cntp_cval_el0)
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AARCH64REG_WRITE_INLINE(cntp_cval_el0)
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AARCH64REG_READ_INLINE(cntp_tval_el0)
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AARCH64REG_WRITE_INLINE(cntp_tval_el0)
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AARCH64REG_READ_INLINE(cntpct_el0)
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AARCH64REG_WRITE_INLINE(cntpct_el0)
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AARCH64REG_READ_INLINE(cntps_ctl_el1)
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AARCH64REG_WRITE_INLINE(cntps_ctl_el1)
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AARCH64REG_READ_INLINE(cntps_cval_el1)
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AARCH64REG_WRITE_INLINE(cntps_cval_el1)
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AARCH64REG_READ_INLINE(cntps_tval_el1)
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AARCH64REG_WRITE_INLINE(cntps_tval_el1)
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AARCH64REG_READ_INLINE(cntv_ctl_el0)
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AARCH64REG_WRITE_INLINE(cntv_ctl_el0)
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AARCH64REG_READ_INLINE(cntv_cval_el0)
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AARCH64REG_WRITE_INLINE(cntv_cval_el0)
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AARCH64REG_READ_INLINE(cntv_tval_el0)
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AARCH64REG_WRITE_INLINE(cntv_tval_el0)
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AARCH64REG_READ_INLINE(cntvct_el0)
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AARCH64REG_WRITE_INLINE(cntvct_el0)
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static const uintmax_t
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CNTCTL_ISTATUS = __BIT(2), // Interrupt Asserted
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CNTCTL_IMASK = __BIT(1), // Timer Interrupt is Masked
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CNTCTL_ENABLE = __BIT(0); // Timer Enabled
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#elif defined(__arm__)
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#include <arm/armreg.h>
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#endif /* __aarch64__/__arm__ */
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#endif /* _AARCH64_ARMREG_H_ */
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