169 lines
3.8 KiB
C++
169 lines
3.8 KiB
C++
/* $NetBSD: epoc32.cpp,v 1.1 2013/04/28 12:11:27 kiyohara Exp $ */
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/*
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* Copyright (c) 2013 KIYOHARA Takashi
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <e32base.h>
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#include <e32def.h>
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#include <e32std.h>
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#include "cpu.h"
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#include "e32boot.h"
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#include "ekern.h"
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#include "epoc32.h"
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#include "arm/armreg.h"
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#include "arm/arm32/pte.h"
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static inline void
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AllowAllDomains(void)
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{
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TUint domains;
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#define ALL_DOMAINS(v) \
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(((v) << 28) | \
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((v) << 24) | \
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((v) << 20) | \
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((v) << 16) | \
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((v) << 12) | \
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((v) << 8) | \
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((v) << 4) | \
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((v) << 0))
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domains = ALL_DOMAINS(0xf);
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__asm("mcr p15, 0, %0, c3, c0" : : "r"(domains));
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}
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EPOC32::EPOC32(void)
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{
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TUint procid;
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__asm("mrc p15, 0, %0, c0, c0" : "=r"(procid));
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if (procid == CPU_ID_SA1100) {
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cpu = new SA1100;
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} else if ((procid & CPU_ID_IMPLEMENTOR_MASK) == CPU_ID_ARM_LTD) {
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if (CPU_ID_IS7(procid)) {
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if ((procid & CPU_ID_7ARCH_MASK) == CPU_ID_7ARCH_V3)
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cpu = new ARM7;
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else
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cpu = new ARM7TDMI;
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}
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}
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}
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EPOC32::~EPOC32(void)
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{
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}
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TAny *
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EPOC32::GetPhysicalAddress(TAny *address)
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{
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TUint l1Index, l1, pageOffset, pa, va;
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TUint *l1Tbl;
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AllowAllDomains();
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l1Tbl = GetTTB();
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va = (TUint)address;
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pa = pageOffset = 0;
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l1Index = (va & L1_ADDR_BITS) >> L1_S_SHIFT;
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l1 = *(l1Tbl + l1Index);
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switch (l1 & L1_TYPE_MASK) {
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case L1_TYPE_INV:
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case L1_TYPE_F:
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return NULL;
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case L1_TYPE_S:
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pa = l1 & L1_S_ADDR_MASK;
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pageOffset = va & L1_S_OFFSET;
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break;
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case L1_TYPE_C:
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{
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TUint *l2Tbl, tag;
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l2Tbl = (TUint *)(l1 & L1_C_ADDR_MASK);
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tag = MapPhysicalAddress(l2Tbl, (TAny **)&l2Tbl);
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pa = *(l2Tbl + ((va & L2_ADDR_BITS) >> 12));
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UnmapPhysicalAddress(l2Tbl, tag);
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switch (pa & L2_TYPE_MASK) {
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case L2_TYPE_L:
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pa &= L2_L_FRAME;
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pageOffset = va & L2_L_OFFSET;
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break;
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case L2_TYPE_S:
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pa &= L2_S_FRAME;
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pageOffset = va & L2_S_OFFSET;
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break;
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default:
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pageOffset = 0xffffffff; /* XXXX */
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}
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}
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}
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return (TAny *)(pa | pageOffset);
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}
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TUint
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EPOC32::MapPhysicalAddress(TAny *pa, TAny **vap)
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{
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TUint *l1Tbl, l1Index, l1, tag;
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AllowAllDomains();
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l1Tbl = GetTTB();
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l1Index = ((TUint)pa & L1_ADDR_BITS) >> L1_S_SHIFT;
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l1 = ((TUint)pa & L1_S_ADDR_MASK) |
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L1_S_AP(AP_KRW) | L1_S_IMP | L1_TYPE_S;
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tag = *(l1Tbl + l1Index);
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*(l1Tbl + l1Index) = l1;
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cpu->cacheFlush();
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cpu->tlbFlush();
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*vap = pa;
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return tag;
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}
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void
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EPOC32::UnmapPhysicalAddress(TAny *address, TUint tag)
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{
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TUint *l1Tbl, l1Index, pa;
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AllowAllDomains();
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l1Tbl = GetTTB();
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pa = (TUint)address;
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l1Index = (pa & L1_ADDR_BITS) >> L1_S_SHIFT;
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*(l1Tbl + l1Index) = tag;
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cpu->cacheFlush();
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cpu->tlbFlush();
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}
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