329 lines
8.3 KiB
ArmAsm
329 lines
8.3 KiB
ArmAsm
/*-
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* Copyright (c) 2014 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Matt Thomas of 3am Software Foundry.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "opt_rockchip.h"
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#include "opt_com.h"
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#include "opt_cpuoptions.h"
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#include "opt_cputypes.h"
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#include "opt_multiprocessor.h"
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#include "opt_arm_debug.h"
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#include <arm/asm.h>
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#include <arm/armreg.h>
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#include "assym.h"
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#include <arm/rockchip/rockchip_reg.h>
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#include <evbarm/rockchip/platform.h>
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#include <arm/cortex/scu_reg.h>
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RCSID("$NetBSD: rockchip_start.S,v 1.4 2014/12/30 21:24:36 jmcneill Exp $")
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#if defined(VERBOSE_INIT_ARM)
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#define XPUTC(n) mov r0, n; bl xputc
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#if KERNEL_BASE_VOFFSET == 0
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#define XPUTC2(n) mov r0, n; bl xputc
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#else
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#define XPUTC2(n) mov r0, n; blx r11
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#endif
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#ifdef __ARMEB__
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#define COM_BSWAP
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#endif
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#define COM_MULT 4
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#define XPUTC_COM 1
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#else
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#define XPUTC(n)
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#define XPUTC2(n)
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#endif
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#define INIT_MEMSIZE 128
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#define TEMP_L1_TABLE (KERNEL_BASE - KERNEL_BASE_VOFFSET + INIT_MEMSIZE * L1_S_SIZE - L1_TABLE_SIZE)
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#define MD_CPU_HATCH _C_LABEL(a9tmr_init_cpu_clock)
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/*
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* Kernel start routine for CUBIE (Allwinner) boards.
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* At this point, this code has been loaded into SDRAM
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* and the MMU maybe on or maybe off.
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*/
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#ifdef KERNEL_BASES_EQUAL
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.text
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#else
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.section .start,"ax",%progbits
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#endif
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.global _C_LABEL(rockchip_start)
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_C_LABEL(rockchip_start):
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#ifdef __ARMEB__
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setend be /* force big endian */
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#endif
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mov r9, #0
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/* Move into supervisor mode and disable IRQs/FIQs. */
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cpsid if, #PSR_SVC32_MODE
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/*
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* Save any arguments passed to us.
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*/
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movw r4, #:lower16:uboot_args
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movt r4, #:upper16:uboot_args
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#if KERNEL_BASE_VOFFSET != 0
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/*
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* But since .start is at 0x40000000 and .text is at 0x8000000, we
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* can't directly use the address that the linker gave us directly.
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* We have to adjust the address the linker gave us to get the to
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* the physical address.
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*/
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sub r4, r4, #KERNEL_BASE_VOFFSET
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#endif
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stmia r4, {r0-r3} // Save the arguments
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/*
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* Turn on the SMP bit
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*/
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bl cortex_init
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/*
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* Set up a preliminary mapping in the MMU to allow us to run
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* at KERNEL_BASE with caches on.
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*/
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movw r0, #:lower16:TEMP_L1_TABLE
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movt r0, #:upper16:TEMP_L1_TABLE
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movw r1, #:lower16:.Lmmu_init_table
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movt r1, #:upper16:.Lmmu_init_table
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bl arm_boot_l1pt_init
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XPUTC(#68)
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/*
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* Turn on the MMU, Caches, etc. Return to new enabled address space.
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*/
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movw r0, #:lower16:TEMP_L1_TABLE
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movt r0, #:upper16:TEMP_L1_TABLE
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#if KERNEL_BASE_VOFFSET == 0
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bl arm_cpuinit
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#else
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/*
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* After the MMU is on, we can execute in the normal .text segment
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* so setup the lr to be in .text. Cache the address for xputc
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* before we go.
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*/
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#if defined(VERBOSE_INIT_ARM)
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adr r11, xputc @ for XPUTC2
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#endif
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movw lr, #:lower16:1f
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movt lr, #:upper16:1f
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b arm_cpuinit
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.pushsection .text,"ax",%progbits
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1:
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#endif
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XPUTC2(#90)
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#if defined(MULTIPROCESSOR)
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// Now spin up the second processors into the same state we are now.
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XPUTC2(#77)
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XPUTC2(#80)
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XPUTC2(#60)
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// Make sure the cache is flushed out to RAM for the other CPUs
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bl _C_LABEL(armv7_dcache_wbinv_all)
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bl rockchip_mpinit
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XPUTC2(#62)
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#endif /* MULTIPROCESSOR */
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XPUTC2(#13)
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XPUTC2(#10)
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/*
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* Jump to start in locore.S, which in turn will call initarm and main.
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*/
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b start
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/* NOTREACHED */
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#ifndef KERNEL_BASES_EQUAL
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.popsection
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#endif
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#include <arm/cortex/a9_mpsubr.S>
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#define PMU_PWRDN_REG 0x0008
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#define PMU_PWRDN_SCU __BIT(4)
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#if defined(MULTIPROCESSOR)
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#ifndef KERNEL_BASES_EQUAL
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.pushsection .text,"ax",%progbits
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#endif
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rockchip_mptramp:
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ldr pc, 1f
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.global rockchip_mpstart_vec
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rockchip_mpstart_vec:
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1: .space 4
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rockchip_mpinit:
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mov r4, lr
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/* r5: SCU, r6: PMU, r7: SRAM */
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movw r5, #:lower16:(ROCKCHIP_CORE0_BASE+ROCKCHIP_SCU_OFFSET)
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movt r5, #:upper16:(ROCKCHIP_CORE0_BASE+ROCKCHIP_SCU_OFFSET)
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movw r6, #:lower16:(ROCKCHIP_CORE1_BASE+ROCKCHIP_PMU_OFFSET)
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movt r6, #:upper16:(ROCKCHIP_CORE1_BASE+ROCKCHIP_PMU_OFFSET)
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movw r7, #:lower16:(ROCKCHIP_CORE0_BASE+ROCKCHIP_SRAM_OFFSET)
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movt r7, #:upper16:(ROCKCHIP_CORE0_BASE+ROCKCHIP_SRAM_OFFSET)
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/* Set where the other CPU(s) are going to execute */
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XPUTC2(#118)
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movw r1, #:lower16:rockchip_mpstart
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movt r1, #:upper16:rockchip_mpstart
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ldr r0, =rockchip_mpstart_vec
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str r1, [r0]
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ldr r0, =rockchip_mptramp
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mov r2, #0
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1: ldr r1, [r0, r2]
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str r1, [r7, r2]
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add r2, r2, #4
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cmp r2, #32
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blt 1b
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dsb
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/* Invalid SCU cache tags */
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XPUTC2(#45)
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movw r1, #0xffff
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movt r1, #0
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str r1, [r5, #SCU_INV_ALL_REG]
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/* Get CPU count */
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ldr r1, [r5, #SCU_CFG]
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and r2, r1, #SCU_CFG_CPUMAX
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add r2, r2, #1
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/* Convert to CPU1..N mask */
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mov r7, #0
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lsl r7, r2, #1
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sub r7, r7, #1
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and r7, r7, #~1
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/* Power down secondary CPUs */
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XPUTC2(#46)
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ldr r1, [r6, #PMU_PWRDN_REG]
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orr r1, r1, r7
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str r1, [r6, #PMU_PWRDN_REG]
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dsb
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/* Power up SCU */
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XPUTC2(#46)
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ldr r1, [r6, #PMU_PWRDN_REG]
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and r1, r1, #~PMU_PWRDN_SCU
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str r1, [r6, #PMU_PWRDN_REG]
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dsb
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/* Enable SCU */
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XPUTC2(#46)
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ldr r1, [r5, #SCU_CTL]
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orr r1, r1, #SCU_CTL_SCU_ENA
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str r1, [r5, #SCU_CTL]
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dsb
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/* Power up secondary CPUs */
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XPUTC2(#33)
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ldr r1, [r6, #PMU_PWRDN_REG]
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and r1, r1, r7
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str r1, [r6, #PMU_PWRDN_REG]
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dsb
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XPUTC2(#49)
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XPUTC2(#50)
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XPUTC2(#51)
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//
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// Wait up a second for CPU1 to hatch.
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//
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movw r2, #:lower16:arm_cpu_hatched
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movt r2, #:upper16:arm_cpu_hatched
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mov r1, #0x10000000
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1: dmb
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ldr r0, [r2]
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cmp r0, r7
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beq .hatched
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subs r1, r1, #1
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bne 1b
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.hatched:
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bx r4
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ASEND(rockchip_mpinit)
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#ifndef KERNEL_BASES_EQUAL
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.popsection
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#endif
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rockchip_mpstart:
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/* invalidate cache */
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movw ip, #:lower16:_C_LABEL(armv7_dcache_inv_all)
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movt ip, #:upper16:_C_LABEL(armv7_dcache_inv_all)
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#ifndef KERNEL_BASES_EQUAL
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sub ip, ip, #KERNEL_BASE_VOFFSET
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#endif
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blx ip
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b _C_LABEL(cortex_mpstart)
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#endif /* MULTIPROCESSOR */
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.Lmmu_init_table:
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/* Map KERNEL_BASE VA to SDRAM PA, write-back cacheable, shareable */
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MMU_INIT(KERNEL_BASE, KERNEL_BASE - KERNEL_BASE_VOFFSET, INIT_MEMSIZE,
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L1_S_PROTO_armv7 | L1_S_APv7_KRW | L1_S_CACHEABLE)
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#if KERNEL_BASE_VOFFSET != 0
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/* Map memory 1:1 VA to PA, write-back cacheable, shareable */
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MMU_INIT(KERNEL_BASE - KERNEL_BASE_VOFFSET,
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KERNEL_BASE - KERNEL_BASE_VOFFSET, INIT_MEMSIZE,
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L1_S_PROTO_armv7 | L1_S_APv7_KRW | L1_S_CACHEABLE)
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#endif
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/* Map ROCKCHIP CORE0 */
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MMU_INIT(ROCKCHIP_CORE0_VBASE, ROCKCHIP_CORE0_BASE,
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(ROCKCHIP_CORE0_SIZE + L1_S_SIZE - 1) / L1_S_SIZE,
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L1_S_PROTO_armv7 | L1_S_APv7_KRW | L1_S_V6_XN)
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/* Map ROCKCHIP CORE0 */
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MMU_INIT(ROCKCHIP_CORE0_BASE, ROCKCHIP_CORE0_BASE,
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(ROCKCHIP_CORE0_SIZE + L1_S_SIZE - 1) / L1_S_SIZE,
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L1_S_PROTO_armv7 | L1_S_APv7_KRW | L1_S_V6_XN)
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/* Map ROCKCHIP CORE1 (so console will work) */
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MMU_INIT(ROCKCHIP_CORE1_VBASE, ROCKCHIP_CORE1_BASE,
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(ROCKCHIP_CORE1_SIZE + L1_S_SIZE - 1) / L1_S_SIZE,
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L1_S_PROTO_armv7 | L1_S_APv7_KRW | L1_S_V6_XN)
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/* Map ROCKCHIP CORE1 (so console will work) */
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MMU_INIT(ROCKCHIP_CORE1_BASE, ROCKCHIP_CORE1_BASE,
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(ROCKCHIP_CORE1_SIZE + L1_S_SIZE - 1) / L1_S_SIZE,
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L1_S_PROTO_armv7 | L1_S_APv7_KRW | L1_S_V6_XN)
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/* end of table */
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MMU_INIT(0, 0, 0, 0)
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END(_C_LABEL(rockchip_start))
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