158 lines
5.4 KiB
C
158 lines
5.4 KiB
C
/* $Id: pinctrl_prep.c,v 1.4 2013/10/07 17:36:40 matt Exp $ */
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/*
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* Copyright (c) 2012 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Petri Laakso.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/param.h>
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#include <sys/cdefs.h>
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#include <sys/types.h>
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#include <arm/imx/imx23_pinctrlreg.h>
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#include <lib/libsa/stand.h>
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#include "common.h"
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#define CTRL (HW_PINCTRL_BASE + HW_PINCTRL_CTRL)
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#define CTRL_S (HW_PINCTRL_BASE + HW_PINCTRL_CTRL_SET)
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#define CTRL_C (HW_PINCTRL_BASE + HW_PINCTRL_CTRL_CLR)
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#define CTRL_MUX0 (HW_PINCTRL_BASE + HW_PINCTRL_MUXSEL0)
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#define CTRL_MUX0_S (HW_PINCTRL_BASE + HW_PINCTRL_MUXSEL0_SET)
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#define CTRL_MUX0_C (HW_PINCTRL_BASE + HW_PINCTRL_MUXSEL0_CLR)
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#define CTRL_MUX1 (CTRL_MUX0 + 0x10)
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#define CTRL_MUX1_S (CTRL_MUX0_S + 0x10)
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#define CTRL_MUX1_C (CTRL_MUX0_C + 0x10)
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#define CTRL_MUX2 (CTRL_MUX0 + 0x20)
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#define CTRL_MUX2_S (CTRL_MUX0_S + 0x20)
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#define CTRL_MUX2_C (CTRL_MUX0_C + 0x20)
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#define CTRL_MUX3 (CTRL_MUX0 + 0x30)
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#define CTRL_MUX3_S (CTRL_MUX0_S + 0x30)
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#define CTRL_MUX3_C (CTRL_MUX0_C + 0x30)
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#define CTRL_MUX4 (CTRL_MUX0 + 0x40)
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#define CTRL_MUX4_S (CTRL_MUX0_S + 0x40)
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#define CTRL_MUX4_C (CTRL_MUX0_C + 0x40)
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#define CTRL_MUX5 (CTRL_MUX0 + 0x50)
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#define CTRL_MUX5_S (CTRL_MUX0_S + 0x50)
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#define CTRL_MUX5_C (CTRL_MUX0_C + 0x50)
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#define CTRL_MUX6 (CTRL_MUX0 + 0x60)
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#define CTRL_MUX6_S (CTRL_MUX0_S + 0x60)
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#define CTRL_MUX6_C (CTRL_MUX0_C + 0x60)
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#define CTRL_MUX7 (CTRL_MUX0 + 0x70)
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#define CTRL_MUX7_S (CTRL_MUX0_S + 0x70)
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#define CTRL_MUX7_C (CTRL_MUX0_C + 0x70)
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#define CTRL_DRV0 (HW_PINCTRL_BASE + HW_PINCTRL_DRIVE0)
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#define CTRL_DRV0_S (HW_PINCTRL_BASE + HW_PINCTRL_DRIVE0_SET)
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#define CTRL_DRV0_C (HW_PINCTRL_BASE + HW_PINCTRL_DRIVE0_CLR)
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#define CTRL_DRV8 (CTRL_DRV0 + 0x80)
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#define CTRL_DRV8_S (CTRL_DRV0_S + 0x80)
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#define CTRL_DRV8_C (CTRL_DRV0_C + 0x80)
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#define CTRL_DRV9 (CTRL_DRV0 + 0x90)
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#define CTRL_DRV9_S (CTRL_DRV0_S + 0x90)
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#define CTRL_DRV9_C (CTRL_DRV0_C + 0x90)
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#define CTRL_DRV10 (CTRL_DRV0 + 0xa0)
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#define CTRL_DRV10_S (CTRL_DRV0_S + 0xa0)
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#define CTRL_DRV10_C (CTRL_DRV0_C + 0xa0)
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#define CTRL_DRV11 (CTRL_DRV0 + 0xb0)
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#define CTRL_DRV11_S (CTRL_DRV0_S + 0xb0)
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#define CTRL_DRV11_C (CTRL_DRV0_C + 0xb0)
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#define CTRL_DRV12 (CTRL_DRV0 + 0xc0)
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#define CTRL_DRV12_S (CTRL_DRV0_S + 0xc0)
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#define CTRL_DRV12_C (CTRL_DRV0_C + 0xc0)
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#define CTRL_DRV13 (CTRL_DRV0 + 0xd0)
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#define CTRL_DRV13_S (CTRL_DRV0_S + 0xd0)
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#define CTRL_DRV13_C (CTRL_DRV0_C + 0xd0)
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#define CTRL_DRV14 (CTRL_DRV0 + 0xe0)
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#define CTRL_DRV14_S (CTRL_DRV0_S + 0xe0)
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#define CTRL_DRV14_C (CTRL_DRV0_C + 0xe0)
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#define CTRL_PULL0 (HW_PINCTRL_BASE + HW_PINCTRL_PULL0)
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#define CTRL_PULL1 (CTRL_PULL0 + 0x10)
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#define CTRL_PULL2 (CTRL_PULL0 + 0x20)
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#define CTRL_PULL3 (CTRL_PULL0 + 0x30)
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/*
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* Configure initial pin settings.
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*/
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int
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pinctrl_prep(void)
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{
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REG_WR(CTRL_C, (HW_PINCTRL_CTRL_SFTRST | HW_PINCTRL_CTRL_CLKGATE));
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delay(10000);
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/*
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* EMI MUX.
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*/
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REG_WR(CTRL_MUX4_C, 0xfffc0000); /* A00:06 */
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REG_WR(CTRL_MUX5_C, 0xfc3fffff); /* A07:12, BA0:1, CASN, CE0N,
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* CE1N, CKE, RASN, WEN */
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REG_WR(CTRL_MUX6_C, 0xffffffff); /* D00:15 */
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REG_WR(CTRL_MUX7_C, 0xfff); /* DQM0:1, DQS0:1, CLK, CLKN */
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/*
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* EMI pin drive strength and voltage to 12mA @ 2.5V.
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*/
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REG_WR(CTRL_DRV9, 0x22222220); /* A00:06 */
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REG_WR(CTRL_DRV10, 0x22222222); /* A07:A12, BA0:1 */
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REG_WR(CTRL_DRV11, 0x22200222); /* CASN, CE0N, CE1N, CKE, RASN, WEN */
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REG_WR(CTRL_DRV12, 0x22222222); /* D00:07 */
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REG_WR(CTRL_DRV13, 0x22222222); /* D08:15 */
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REG_WR(CTRL_DRV14, 0x222222); /* DQM0:1, DQS0:1, CLK, CLKN */
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/*
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* Disable EMI pad keepers.
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*/
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REG_WR(CTRL_PULL3, 0x3ffff); /* D00:D15, DQM0:1 */
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/*
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* SSP MUX.
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*/
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REG_WR(CTRL_MUX4_C, 0x3ff3); /* CMD, DATA0:3, SCK */
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REG_WR(CTRL_MUX4_S, 0xc); /* SSP1_DETECT as GPIO */
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/*
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* SSP pin drive strength.
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*/
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REG_WR(CTRL_DRV8, 0x01111101); /* CMD, DATA0:3, SCK to 8mA
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* SSP1_DETECT to 4mA */
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/*
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* SSP pull ups.
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*/
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REG_WR(CTRL_PULL2, 0x3d); /* Pull-up DATA0:3, CMD and
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* no pull-up SSP1_DETECT */
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/*
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* Debug UART MUX.
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*/
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REG_WR(CTRL_MUX3_C, 0xf00000);
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REG_WR(CTRL_MUX3_S, 0xa00000);
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return 0;
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}
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