140 lines
4.3 KiB
C
140 lines
4.3 KiB
C
/* $NetBSD: autoconf.c,v 1.5 2014/04/30 01:02:40 matt Exp $ */
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/*-
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* Copyright (c) 2011 CradlePoint Technology, Inc.
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* All rights reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY CRADLEPOINT TECHNOLOGY, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: autoconf.c,v 1.5 2014/04/30 01:02:40 matt Exp $");
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <sys/conf.h>
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#include <sys/device.h>
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#include <sys/systm.h>
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#include <mips/ralink/ralink_reg.h>
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#include <mips/ralink/ralink_var.h>
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/*
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* Configure all devices on system
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*/
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void
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cpu_configure(void)
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{
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intr_init();
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/* Kick off autoconfiguration. */
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if (config_rootfound("mainbus", NULL) == NULL)
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panic("no mainbus found");
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/*
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* Hardware interrupts will be enabled in
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* sys/arch/mips/mips/mips3_clockintr.c:mips3_initclocks()
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* to avoid hardclock(9) by CPU INT5 before softclockintr is
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* initialized in initclocks().
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*/
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}
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void
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cpu_rootconf(void)
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{
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rootconf();
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}
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static const struct cfg_info {
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const char *map_name;
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uint32_t map_rst;
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uint32_t map_clkcfg1;
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} map_info[] = {
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#if defined(MT7620)
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{ "rpci", RST_PCIE0_7620, SYSCTL_CLKCFG1_PCIE_CLK_EN_7620 },
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{ "ohci", RST_UHST0_7620|RST_UHST, SYSCTL_CLKCFG1_UPHY0_CLK_EN_7620 },
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{ "ehci", RST_UHST0_7620|RST_UHST, SYSCTL_CLKCFG1_UPHY0_CLK_EN_7620 },
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{ "sdhc", RST_SDHC_7620, SYSCTL_CLKCFG1_SDHC_CLK_EN },
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{ "rsw", RST_ESW_7620, SYSCTL_CLKCFG1_ESW_CLK_EN },
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#endif
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#if defined(RT3883)
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{ "rpci", RST_PCI_3883 | RST_PCIPCIE_3883,
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SYSCTL_CLKCFG1_PCI_CLK_EN|SYSCTL_CLKCFG1_PCIE_CLK_EN_3883 },
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{ "ohci", RST_UHST, SYSCTL_CLKCFG1_UPHY0_CLK_EN_3883 },
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{ "ehci", RST_UHST, SYSCTL_CLKCFG1_UPHY0_CLK_EN_3883 },
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#endif
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};
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static void
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ra_device_fixup(bus_space_tag_t bst, const struct cfg_info *map)
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{
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const uint32_t clkcfg1 = bus_space_read_4(bst, ra_sysctl_bsh,
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RA_SYSCTL_CLKCFG1);
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if ((clkcfg1 & map->map_clkcfg1) != map->map_clkcfg1) {
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bus_space_write_4(bst, ra_sysctl_bsh, RA_SYSCTL_CLKCFG1,
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clkcfg1 | map->map_clkcfg1);
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delay(10000);
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}
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const uint32_t rst = bus_space_read_4(bst, ra_sysctl_bsh,
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RA_SYSCTL_RST);
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if ((rst & map->map_rst) != 0) {
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bus_space_write_4(bst, ra_sysctl_bsh, RA_SYSCTL_RST,
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rst & ~map->map_rst);
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delay(10000);
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}
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}
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void
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device_register(device_t self, void *aux)
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{
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device_t parent = device_parent(self);
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if (parent != NULL && device_is_a(parent, "mainbus")) {
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// If we are attaching a mainbus device, see if we know how
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// to bring it out of reset.
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struct mainbus_attach_args * const ma = aux;
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for (const struct cfg_info *map = map_info;
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map < map_info + __arraycount(map_info);
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map++) {
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if (device_is_a(self, map->map_name)) {
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ra_device_fixup(ma->ma_memt, map);
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delay(1000);
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break;
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}
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}
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#if defined(RT3883) || defined(MT7620)
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if (device_is_a(self, "ohci") || device_is_a(self, "ehci")) {
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const uint32_t cfg1 = bus_space_read_4(ma->ma_memt,
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ra_sysctl_bsh, RA_SYSCTL_CFG1);
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if ((cfg1 & SYSCTL_CFG1_USB0_HOST_MODE) == 0) {
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bus_space_write_4(ma->ma_memt, ra_sysctl_bsh,
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RA_SYSCTL_CFG1,
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cfg1 | SYSCTL_CFG1_USB0_HOST_MODE);
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delay(10);
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}
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}
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#endif
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}
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}
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