88 lines
3.3 KiB
C
88 lines
3.3 KiB
C
/* $NetBSD: dcr.h,v 1.1 2006/12/02 22:18:47 freza Exp $ */
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/*
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* Copyright (c) 2006 Jachym Holecek
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* All rights reserved.
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*
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* Written for DFC Design, s.r.o.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* DCR is an user accesible bus on Xilinx PPC405D5Xn cores and may contain
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* arbitrary devices. Because we want to be able to share drivers with
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* OPB/PLB, we make it a bus space backend. Each platform ("design", "board")
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* has to provide the leaf _read_4/_write_4 routines specific to device
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* instances. This is dictated by the fact that DCR can only by accessed
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* by m{f,t}dcr instructions for which the address is encoded as immediate
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* operand (and hence needs to be a compile-time constant).
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*
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* The flexibility is well worth the price of one indirection (and a sum
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* and a branch), critical paths can still be implemented with m{f,t}dcr().
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*/
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#ifndef _VIRTEX_DCRVAR_H_
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#define _VIRTEX_DCRVAR_H_
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/* From evbppc/virtex/machdep.c */
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int dcr_subregion(bus_space_tag_t, bus_space_handle_t, bus_size_t,
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bus_size_t, bus_space_handle_t *);
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int dcr_map(bus_space_tag_t, bus_addr_t, bus_size_t, int,
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bus_space_handle_t *);
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void dcr_unmap(bus_space_tag_t, bus_space_handle_t, bus_size_t);
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/* Bus space tag contents, one tag per DCR device. */
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#define DCR_BST_BODY(base, read, write) \
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.pbs_flags = _BUS_SPACE_BIG_ENDIAN, \
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.pbs_offset = 0, \
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.pbs_base = (base), \
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.pbs_limit = 0x03ff, \
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.pbs_scalar = { \
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.pbss_write_4 = (write), \
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.pbss_read_4 = (read), \
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}, \
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.pbs_map = dcr_map, \
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.pbs_unmap = dcr_unmap, \
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.pbs_subregion = dcr_subregion,
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/*
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* Utility macros for leaf access routines. Note they assume variables
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* in local scope, and are furthermore assumed to be used in switch()
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* dispatch over destination address.
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*/
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#define WCASE(base, addr) \
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case (addr): mtdcr((base) + (addr) / 4, val); break
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#define WDEAD(addr) \
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default: panic("%s: unexpected offset %#08x", __func__, (addr))
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#define RCASE(base, addr) \
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case (addr): val = mfdcr((base) + (addr) / 4); break
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#define RDEAD(addr) \
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default: panic("%s: unexpected offset %#08x", __func__, (addr))
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#endif /* _VIRTEX_DCRVAR_H_ */
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