123 lines
4.4 KiB
C
123 lines
4.4 KiB
C
/* $NetBSD */
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/*
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* Copyright (c) 2006 Jachym Holecek
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* All rights reserved.
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*
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* Written for DFC Design, s.r.o.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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#ifndef _VIRTEX_DEV_CDMACREG_H_
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#define _VIRTEX_DEV_CDMACREG_H_
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/*
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* CDMAC registers and data structures. Keep the names fully qualified, users
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* need at least CDMAC_STAT bits to manipulate descriptor queues. The offsets
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* are multiplied by four compared to Xilinx documentation -- so don't get
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* confused, bus space will deal.
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*
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* The number of channels and interrupt wiring differs per design.
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*/
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/* Status and control register block sizes. */
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#define CDMAC_CTRL_SIZE 0x0c
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#define CDMAC_STAT_SIZE 0x04
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/* Status and control register offsets per channel. */
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#define CDMAC_STAT_BASE(n) (0x80 + (n) * 0x04)
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#define CDMAC_CTRL_BASE(n) (0x00 + (n) * 0x10)
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/* Individual engine control registers. */
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#define CDMAC_NEXT 0x0000 /* Next descriptor pointer,
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* 32B aligned, 0x0 = stop */
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#define CDMAC_CURADDR 0x0004 /* Address being transferred */
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#define CDMAC_CURSIZE 0x0008 /* Remaining length */
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#define CDMAC_CURDESC 0x000c /* Current descriptor pointer */
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#define CDMAC_CURSIZE_MASK 0x00ffffff
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/* Engine status reg bits. */
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#define CDMAC_STAT_ERROR 0x80000000 /* EINVAL -> halt, interrupt */
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#define CDMAC_STAT_INTR 0x40000000 /* Interrupt on end of descr */
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#define CDMAC_STAT_STOP 0x20000000 /* Stop on end of descr */
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#define CDMAC_STAT_DONE 0x10000000 /* Descriptor done */
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#define CDMAC_STAT_SOP 0x08000000 /* Start of packet */
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#define CDMAC_STAT_EOP 0x04000000 /* End of packet */
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#define CDMAC_STAT_BUSY 0x02000000 /* Engine busy */
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#define CDMAC_STAT_RESET 0x01000000 /* Channel reset */
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#ifdef notdef
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/*
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* DMA engine timers, 8bit. Rather useless -- we need "interrupt
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* if transfer stalls for N cycles", not "fire after N cycles".
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* If we ever use this, move definitions to design-specific code
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* like we do with STAT.
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*/
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#define CDMAC_TIMER_TX0 0x00a0
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#define CDMAC_TIMER_RX0 0x00a4
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#define CDMAC_TIMER_TX1 0x00a8
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#define CDMAC_TIMER_RX1 0x00ac
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#endif /* notdef */
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/* Interrupt register (active-high level-sensitive intr). */
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#define CDMAC_INTR 0x00bc
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#define CDMAC_INTR_MIE 0x80000000 /* Master interrupt enable */
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#define CDMAC_INTR_TX0 0x00000001 /* Descriptor interrupts */
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#define CDMAC_INTR_RX0 0x00000002
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#define CDMAC_INTR_TX1 0x00000004
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#define CDMAC_INTR_RX1 0x00000008
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#define CDMAC_TIMO_TX0 0x01000000 /* Timer interrupts */
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#define CDMAC_TIMO_RX0 0x02000000
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#define CDMAC_TIMO_TX1 0x04000000
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#define CDMAC_TIMO_RX1 0x08000000
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#define CDMAC_CHAN_INTR(n) (1 << (n))
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/*
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* Wire data structure of transfer descriptor (shared for Rx/Tx).
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*/
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struct cdmac_descr {
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uint32_t desc_next; /* Next descriptor */
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uint32_t desc_addr; /* Payload address */
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uint32_t desc_size; /* Payload size */
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/* Application defined fields, valid in 1st desc on Tx, last on Rx. */
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uint32_t desc_user0; /* See below */
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#define desc_stat desc_user0
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uint32_t desc_user1;
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uint32_t desc_user2;
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uint32_t desc_user3;
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uint32_t desc_user4;
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} __aligned(8) __packed;
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#define DMAC_STAT_MASK 0xff000000 /* CDMAC portion of desc_user0 */
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#define DMAC_USER_MASK 0x00ffffff /* User defined part of desc_user0 */
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#endif /*_VIRTEX_DEV_CDMACREG_H_*/
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