118 lines
5.0 KiB
C
118 lines
5.0 KiB
C
/* $NetBSD: temacreg.h,v 1.1 2006/12/02 22:18:47 freza Exp $ */
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/*
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* Copyright (c) 2006 Jachym Holecek
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* All rights reserved.
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*
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* Written for DFC Design, s.r.o.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _VIRTEX_DEV_TEMACREG_H_
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#define _VIRTEX_DEV_TEMACREG_H_
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/*
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* Ethernet peripheral control (single register, see temac_control()).
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* This goes over normal DCR bus and is configured on EMAC block.
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*/
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#define TEMAC_SIZE 0x001c
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#define TEMAC_RESET 0x0000
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#define TEMAC_RESET_PERIPH 0x80000000 /* Reset ethernet peripheral */
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#define TEMAC_RESET_EMAC 0x40000000 /* Reset EMAC core */
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#define TEMAC_RESET_PHY 0x20000000 /* Reset PHY core */
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/* LocalLink GMAC registers. Only ERRCNT implemented in temac. */
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#define TEMAC_GMAC_ERRCNT 0x0018
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#define GMAC_ERR_FRAME(val) (((val) >> 16) & 0xffff)
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#define GMAC_ERR_OVERRUN(val) ((val) & 0xffff)
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/*
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* Host interface ("GMI") registers, accessed indirectly via IDCR.
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*/
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/* Pause frame address, bytes 0-3 */
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#define TEMAC_GMI_RXCF0 0x0200 /* Receiver conf word 0 */
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#define TEMAC_GMI_RXCF1 0x0240 /* Receiver conf word 1 */
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#define GMI_RX_RESET 0x80000000 /* Receiver reset */
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#define GMI_RX_JUMBO 0x40000000 /* Jumbo frame enable */
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#define GMI_RX_FCS 0x20000000 /* Pass FCS on Rx */
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#define GMI_RX_ENABLE 0x10000000 /* Enable receiver block */
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#define GMI_RX_VLAN 0x08000000 /* Receive VLAN tagged frames */
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#define GMI_RX_HDX 0x04000000 /* Half duplex Rx */
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#define GMI_RX_NOCHECK 0x02000000 /* Disable Length/Type check */
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#define GMI_RX_PAUSE_MASK 0x0000ffff /* Pause frame addr 4-5 */
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#define TEMAC_GMI_TXCF 0x0280 /* Transmitter configuration */
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#define GMI_TX_RESET 0x80000000 /* Transmitter reset */
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#define GMI_TX_JUMBO 0x40000000 /* Jumbo frame enable */
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#define GMI_TX_FCS 0x20000000 /* Take FCS field from client */
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#define GMI_TX_ENABLE 0x10000000 /* Enable transmitter block */
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#define GMI_TX_VLAN 0x08000000 /* Transmit VLAN frames */
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#define GMI_TX_HDX 0x04000000 /* Half duplex Tx */
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#define GMI_TX_IFG 0x02000000 /* IFG adjustment enable */
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#define TEMAC_GMI_FLOWCF 0x02c0 /* Flow control configuration */
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#define GMI_FLOWCF_TX 0x40000000 /* Honor CLIENTEMAC#PAUSEREQ */
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#define GMI_FLOWCF_RX 0x20000000 /* HW pause frame handling */
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#define TEMAC_GMI_MMC 0x0300 /* MAC mode configuration */
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#define GMI_MMC_SPEED_MASK 0xc0000000
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#define GMI_MMC_SPEED_NA 0xc0000000
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#define GMI_MMC_SPEED_1000 0x80000000
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#define GMI_MMC_SPEED_100 0x40000000
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#define GMI_MMC_SPEED_10 0x00000000
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#define GMI_MMC_RGMII 0x20000000 /* Enable RGMII mode */
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#define GMI_MMC_SGMII 0x10000000 /* Enable SGMII mode */
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#define GMI_MMC_1000BaseX 0x08000000 /* Enable 1000Base-X mode */
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#define GMI_MMC_HIE 0x04000000 /* Host interface enable */
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#define GMI_MMC_TX16 0x02000000 /* [1000BaseX] 16bit TX lane */
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#define GMI_MMC_RX16 0x01000000 /* [1000BaseX] 16bit RX lane */
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#define TEMAC_GMI_MGMTCF 0x0340 /* Management configuration */
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#define GMI_MGMT_CLKDIV_MASK 0x0000003f /* MDIO clock divisor */
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#define GMI_MGMT_MDIO 0x00000040 /* MDIO link enable */
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/* MII clock divisor constant for DCR running at 100MHz. */
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#define GMI_MGMT_CLKDIV_100MHz 0x00000028
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#define TEMAC_GMI_UNI0 0x0380 /* Unicast address word 0 */
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#define TEMAC_GMI_UNI1 0x0384 /* Unicast address word 1 */
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#define TEMAC_GMI_MAT0 0x0388 /* Multicast filter word 0 */
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#define TEMAC_GMI_MAT1 0x038c /* Multicast filter word 1 */
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#define TEMAC_GMI_AFM 0x0390 /* Address filter mode */
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#define GMI_AFM_PROMISC 0x80000000 /* Promiscuous mode */
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#define TEMAC_GMI_IRQSTAT 0x03a0
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#define TEMAC_GMI_IRQEN 0x03a4
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#define TEMAC_GMI_MII_WRVAL 0x03b0 /* MII write data */
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#define TEMAC_GMI_MII_ADDR 0x03b4 /* MII address */
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#define GMI_MII_ADDR_REG(val) ((val) & 0x01f)
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#define GMI_MII_ADDR_PHY(val) (((val) & 0x01f) << 5)
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#endif /*_VIRTEX_DEV_TEMACREG_H_*/
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