58 lines
2.3 KiB
C
58 lines
2.3 KiB
C
/* $NetBSD: xintcreg.h,v 1.1 2006/12/02 22:18:47 freza Exp $ */
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/*
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* Copyright (c) 2006 Jachym Holecek
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* All rights reserved.
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*
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* Written for DFC Design, s.r.o.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _VIRTEX_DEV_XINTCREG_H_
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#define _VIRTEX_DEV_XINTCREG_H_
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#ifdef _KERNEL_OPT
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#include "opt_xintc.h"
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#endif
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#ifndef DCR_XINTC_BASE
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#error "XINTC component DCR base address undefined!"
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#endif
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/* Xilinx "XintC" interrupt controller, connects to DCR. */
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#define XINTC_ISR (DCR_XINTC_BASE + 0) /* Status (not masked) */
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#define XINTC_IPR (DCR_XINTC_BASE + 1) /* opt: Pending (masked) */
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#define XINTC_IER (DCR_XINTC_BASE + 2) /* Enable */
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#define XINTC_IAR (DCR_XINTC_BASE + 3) /* Acknowledge */
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#define XINTC_SIE (DCR_XINTC_BASE + 4) /* opt: Set Enable bits */
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#define XINTC_CIE (DCR_XINTC_BASE + 5) /* opt: Clr Enable bits */
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#define XINTC_IVR (DCR_XINTC_BASE + 6) /* opt: Vector */
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#define XINTC_MER (DCR_XINTC_BASE + 7) /* Master enable */
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#define MER_ME 0x00000001 /* Master enable */
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#define MER_HIE 0x00000002 /* Hw intr enable, write once */
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#endif /*_VIRTEX_DEV_XINTCREG_H_*/
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