63 lines
2.3 KiB
C
63 lines
2.3 KiB
C
/* $NetBSD: xlcomreg.h,v 1.1 2006/12/02 22:18:47 freza Exp $ */
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/*
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* Copyright (c) 2006 Jachym Holecek
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* All rights reserved.
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*
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* Written for DFC Design, s.r.o.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _VIRTEX_DEV_XLCOMREG_H_
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#define _VIRTEX_DEV_XLCOMREG_H_
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/*
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* Xilinx UART Lite (opb_uartlite_0 in EDK) registers. Note that all
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* line parameter are hardcoded at synthesis time. There is no hardware
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* flow control, just RX and TX signals.
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*/
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#define XLCOM_SIZE 0x0c
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/* 16B FIFOs */
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#define XLCOM_RX_FIFO 0x0000
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#define XLCOM_TX_FIFO 0x0004
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#define XLCOM_STAT 0x0008 /* ro */
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#define STAT_PARITY_ERR 0x80
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#define STAT_FRAME_ERR 0x40
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#define STAT_OVERRUN_ERR 0x20
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#define STAT_INTR_EN 0x10 /* Interrupt enabled */
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#define STAT_TX_FULL 0x08
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#define STAT_TX_EMPTY 0x04
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#define STAT_RX_FULL 0x02
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#define STAT_RX_DATA 0x01 /* RX FIFO has valid data */
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#define XLCOM_CNTL 0x000c /* wo */
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#define CNTL_INTR_EN 0x10
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#define CNTL_RX_CLEAR 0x02 /* Reset/clear FIFOs */
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#define CNTL_TX_CLEAR 0x01
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#endif /*_VIRTEX_DEV_XLCOMREG_H_*/
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