205 lines
5.0 KiB
C
205 lines
5.0 KiB
C
/* $NetBSD: locore.h,v 1.2 2015/03/28 16:13:56 matt Exp $ */
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/*-
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* Copyright (c) 2014 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Matt Thomas of 3am Software Foundry.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _RISCV_LOCORE_H_
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#define _RISCV_LOCORE_H_
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#include <sys/lwp.h>
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#include <sys/userret.h>
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#include <riscv/reg.h>
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#include <riscv/sysreg.h>
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struct trapframe {
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struct reg tf_regs;
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register_t tf_badaddr;
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uint32_t tf_cause; // 32-bit register
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uint32_t tf_sr; // 32-bit register
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#define tf_reg tf_regs.r_reg
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#define tf_pc tf_regs.r_pc
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#define tf_ra tf_reg[_X_RA]
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#define tf_sp tf_reg[_X_SP]
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#define tf_gp tf_reg[_X_GP]
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#define tf_tp tf_reg[_X_TP]
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#define tf_t0 tf_reg[_X_T0]
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#define tf_t1 tf_reg[_X_T1]
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#define tf_t2 tf_reg[_X_T2]
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#define tf_s0 tf_reg[_X_S0]
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#define tf_s1 tf_reg[_X_S1]
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#define tf_a0 tf_reg[_X_A0]
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#define tf_a1 tf_reg[_X_A1]
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#define tf_a2 tf_reg[_X_A2]
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#define tf_a3 tf_reg[_X_A3]
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#define tf_a4 tf_reg[_X_A4]
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#define tf_a5 tf_reg[_X_A5]
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#define tf_a6 tf_reg[_X_A6]
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#define tf_a7 tf_reg[_X_A7]
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#define tf_s2 tf_reg[_X_S2]
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#define tf_s3 tf_reg[_X_S3]
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#define tf_s4 tf_reg[_X_S4]
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#define tf_s5 tf_reg[_X_S5]
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#define tf_s6 tf_reg[_X_S6]
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#define tf_s7 tf_reg[_X_S7]
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#define tf_s8 tf_reg[_X_S8]
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#define tf_s9 tf_reg[_X_S9]
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#define tf_s10 tf_reg[_X_S10]
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#define tf_s11 tf_reg[_X_S11]
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#define tf_t3 tf_reg[_X_T3]
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#define tf_t4 tf_reg[_X_T4]
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#define tf_t5 tf_reg[_X_T5]
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#define tf_t6 tf_reg[_X_T6]
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};
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// For COMPAT_NETBDS32 coredumps
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struct trapframe32 {
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struct reg32 tf_regs;
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register32_t tf_badaddr;
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uint32_t tf_cause; // 32-bit register
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uint32_t tf_sr; // 32-bit register
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};
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#define FB_A0 0
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#define FB_RA 1
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#define FB_SP 2
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#define FB_GP 3
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#define FB_S0 4
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#define FB_S1 5
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#define FB_S2 6
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#define FB_S3 7
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#define FB_S4 8
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#define FB_S5 9
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#define FB_S6 10
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#define FB_S7 11
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#define FB_S8 12
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#define FB_S9 13
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#define FB_S10 14
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#define FB_S11 15
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#define FB_MAX 16
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struct faultbuf {
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register_t fb_reg[FB_MAX];
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uint32_t fb_sr;
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};
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CTASSERT(sizeof(label_t) == sizeof(struct faultbuf));
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struct mainbus_attach_args {
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const char *maa_name;
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u_int maa_instance;
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};
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#ifdef _KERNEL
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extern int cpu_printfataltraps;
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extern const pcu_ops_t pcu_fpu_ops;
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static inline vaddr_t
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stack_align(vaddr_t sp)
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{
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return sp & ~STACK_ALIGNBYTES;
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}
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static inline void
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userret(struct lwp *l)
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{
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mi_userret(l);
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}
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static inline void
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fpu_load(void)
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{
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pcu_load(&pcu_fpu_ops);
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}
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static inline void
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fpu_save(void)
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{
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pcu_save(&pcu_fpu_ops);
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}
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static inline void
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fpu_discard(void)
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{
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pcu_discard(&pcu_fpu_ops, false);
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}
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static inline void
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fpu_replace(void)
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{
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pcu_discard(&pcu_fpu_ops, true);
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}
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static inline bool
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fpu_valid_p(void)
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{
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return pcu_valid_p(&pcu_fpu_ops);
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}
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void __syncicache(const void *, size_t);
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int cpu_set_onfault(struct faultbuf *, register_t) __returns_twice;
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void cpu_jump_onfault(struct trapframe *, const struct faultbuf *);
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static inline void
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cpu_unset_onfault(void)
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{
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curlwp->l_md.md_onfault = NULL;
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}
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static inline struct faultbuf *
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cpu_disable_onfault(void)
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{
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struct faultbuf * const fb = curlwp->l_md.md_onfault;
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curlwp->l_md.md_onfault = NULL;
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return fb;
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}
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static inline void
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cpu_enable_onfault(struct faultbuf *fb)
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{
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curlwp->l_md.md_onfault = fb;
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}
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void cpu_intr(struct trapframe */*tf*/, register_t /*epc*/,
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register_t /*status*/, register_t /*cause*/);
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void cpu_trap(struct trapframe */*tf*/, register_t /*epc*/,
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register_t /*status*/, register_t /*cause*/,
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register_t /*badvaddr*/);
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void cpu_ast(struct trapframe *);
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void cpu_fast_switchto(struct lwp *, int);
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void cpu_lwp_trampoline(void);
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void * cpu_sendsig_getframe(struct lwp *, int, bool *);
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void init_riscv(vaddr_t, vaddr_t);
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#endif
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#endif /* _RISCV_LOCORE_H_ */
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