125 lines
4.7 KiB
C
125 lines
4.7 KiB
C
/* $NetBSD: ubcreg.h,v 1.5 2008/06/06 03:17:28 uwe Exp $ */
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/*-
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* Copyright (C) 1999 SAITOH Masanobu. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _SH3_UBCREG_H_
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#define _SH3_UBCREG_H_
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#include <sh3/devreg.h>
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/*
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* User Break Controller
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*/
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/* Channel A */
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#define SH3_BARA 0xffffffb0 /* 32: address */
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#define SH3_BAMRA 0xffffffb4 /* 32: address mask */
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#define SH3_BASRA 0xffffffe4 /* 16: ASID */
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#define SH3_BBRA 0xffffffb8 /* 16: bus cycle */
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/* Channel B */
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#define SH3_BARB 0xffffffa0 /* 32: address */
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#define SH3_BAMRB 0xffffffa4 /* 32: address mask */
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#define SH3_BDRB 0xffffff90 /* 32: data */
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#define SH3_BDMRB 0xffffff94 /* 32: data mask */
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#define SH3_BASRB 0xffffffe8 /* 16: asid */
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#define SH3_BBRB 0xffffffa8 /* 16: bus cycle */
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/* Common */
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#define SH3_BRCR 0xffffff98 /* 32: control */
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/* Channel A */
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#define SH4_BARA 0xff200000 /* 32: address */
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#define SH4_BAMRA 0xff200004 /* 8: address/asid mask */
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#define SH4_BASRA 0xff000014 /* 8: ASID */
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#define SH4_BBRA 0xff200008 /* 16: bus cycle */
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/* Channel B */
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#define SH4_BARB 0xff20000c /* 32: address */
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#define SH4_BAMRB 0xff200010 /* 8: address/asid mask */
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#define SH4_BASRB 0xff000018 /* 8: ASID */
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#define SH4_BDRB 0xff200018 /* 32: data */
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#define SH4_BDMRB 0xff20001c /* 32: data mask */
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#define SH4_BBRB 0xff200014 /* 16: bus cycle */
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/* common */
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#define SH4_BRCR 0xff200020 /* 16: control */
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/* SH4_BAMRx bits (sh3 uses plain 32-bit address mask) */
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#define SH4_UBC_MASK_ASID 0x04 /* ignore BASRx */
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#define SH4_UBC_MASK_MASK 0x0b /* mask BARx: */
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#define SH4_UBC_MASK_NONE 0x00 /* - compare all bits */
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#define SH4_UBC_MASK_10 0x01 /* - mask lower 10 bits */
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#define SH4_UBC_MASK_12 0x02 /* - mask lower 12 bits */
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#define SH4_UBC_MASK_ALL 0x03 /* - mask all bits */
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#define SH4_UBC_MASK_16 0x08 /* - mask lower 16 bits */
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#define SH4_UBC_MASK_20 0x09 /* - mask lower 20 bits */
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/* BBRx bits */
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#define SH3_UBC_CYCLE_SZ_MASK 0x03 /* exclusive */
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#define SH4_UBC_CYCLE_SZ_MASK 0x43
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#define UBC_CYCLE_8 0x01
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#define UBC_CYCLE_16 0x02
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#define UBC_CYCLE_32 0x03
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#define SH4_UBC_CYCLE_64 0x40
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#define UBC_CYCLE_RW_MASK 0x0c /* can be combined */
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#define UBC_CYCLE_READ 0x04
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#define UBC_CYCLE_WRITE 0x08
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#define UBC_CYCLE_ID_MASK 0x30 /* can be combined */
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#define UBC_CYCLE_INSN 0x10
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#define UBC_CYCLE_DATA 0x20
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#define SH3_UBC_CYCLE_CD_MASK 0xc0 /* exclusive */
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#define SH3_UBC_CYCLE_CPU 0x40
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#define SH3_UBC_CYCLE_DMAC 0x80
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/* BRCR bits */
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#define UBC_CTL_SEQ 0x0008 /* A||B vs A&&B */
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#define UBC_CTL_B_AFTER_INSN 0x0040 /* B: before/after execution */
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#define UBC_CTL_B_DATA 0x0080 /* B: match BDRB/BDMRB */
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#define UBC_CTL_A_AFTER_INSN 0x0400 /* A: before/after execution */
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#define UBC_CTL_B_MATCH 0x4000 /* B matched (sh3: cpu) */
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#define UBC_CTL_A_MATCH 0x8000 /* A matched (sh3: cpu) */
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#define SH3_UBC_CTL_B_MASK_ASID 0x00100000 /* ignore BASRB */
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#define SH3_UBC_CTL_A_MASK_ASID 0x00200000 /* ignore BASRA */
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#ifndef _LOCORE
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#if defined(SH3) && defined(SH4)
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extern uint32_t __sh_BARA;
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extern uint32_t __sh_BAMRA;
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extern uint32_t __sh_BASRA;
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extern uint32_t __sh_BBRA;
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extern uint32_t __sh_BARB;
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extern uint32_t __sh_BAMRB;
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extern uint32_t __sh_BASRB;
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extern uint32_t __sh_BBRB;
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extern uint32_t __sh_BDRB;
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extern uint32_t __sh_BDMRB;
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extern uint32_t __sh_BRCR;
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#endif /* SH3 && SH4 */
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#endif /* !_LOCORE */
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#endif /* !_SH3_UBCREG_H_ */
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