244 lines
7.8 KiB
C
244 lines
7.8 KiB
C
$NetBSD$
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--- gcc/config/i386/i386.c.orig Thu Feb 17 21:22:02 2011
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+++ gcc/config/i386/i386.c
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@@ -46,6 +46,7 @@ along with GCC; see the file COPYING3. If not see
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#include "target.h"
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#include "target-def.h"
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#include "langhooks.h"
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+#include "reload.h"
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#include "cgraph.h"
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#include "gimple.h"
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#include "dwarf2.h"
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@@ -1540,7 +1541,7 @@ unsigned char ix86_arch_features[X86_ARCH_LAST];
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/* Feature tests against the various architecture variations, used to create
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ix86_arch_features based on the processor mask. */
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static unsigned int initial_ix86_arch_features[X86_ARCH_LAST] = {
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- /* X86_ARCH_CMOVE: Conditional move was added for pentiumpro. */
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+ /* X86_ARCH_CMOV: Conditional move was added for pentiumpro. */
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~(m_386 | m_486 | m_PENT | m_K6),
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/* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486. */
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@@ -3071,7 +3072,7 @@ override_options (bool main_args_p)
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-mtune (rather than -march) points us to a processor that has them.
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However, the VIA C3 gives a SIGILL, so we only do that for i686 and
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higher processors. */
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- if (TARGET_CMOVE
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+ if (TARGET_CMOV
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&& (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE)))
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x86_prefetch_sse = true;
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break;
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@@ -3400,11 +3401,6 @@ override_options (bool main_args_p)
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target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
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}
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- /* For sane SSE instruction set generation we need fcomi instruction.
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- It is safe to enable all CMOVE instructions. */
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- if (TARGET_SSE)
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- TARGET_CMOVE = 1;
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-
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/* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
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{
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char *p;
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@@ -9875,6 +9871,64 @@ legitimate_pic_address_disp_p (rtx disp)
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return 0;
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}
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+/* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
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+ replace the input X, or the original X if no replacement is called for.
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+ The output parameter *WIN is 1 if the calling macro should goto WIN,
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+ 0 if it should not. */
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+
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+bool
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+ix86_legitimize_reload_address (rtx x,
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+ enum machine_mode mode ATTRIBUTE_UNUSED,
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+ int opnum, int type,
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+ int ind_levels ATTRIBUTE_UNUSED)
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+{
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+ /* Reload can generate:
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+
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+ (plus:DI (plus:DI (unspec:DI [(const_int 0 [0])] UNSPEC_TP)
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+ (reg:DI 97))
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+ (reg:DI 2 cx))
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+
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+ This RTX is rejected from ix86_legitimate_address_p due to
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+ non-strictness of base register 97. Following this rejection,
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+ reload pushes all three components into separate registers,
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+ creating invalid memory address RTX.
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+
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+ Following code reloads only the invalid part of the
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+ memory address RTX. */
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+
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+ if (GET_CODE (x) == PLUS
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+ && REG_P (XEXP (x, 1))
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+ && GET_CODE (XEXP (x, 0)) == PLUS
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+ && REG_P (XEXP (XEXP (x, 0), 1)))
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+ {
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+ rtx base, index;
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+ bool something_reloaded = false;
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+
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+ base = XEXP (XEXP (x, 0), 1);
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+ if (!REG_OK_FOR_BASE_STRICT_P (base))
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+ {
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+ push_reload (base, NULL_RTX, &XEXP (XEXP (x, 0), 1), NULL,
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+ BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
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+ opnum, (enum reload_type)type);
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+ something_reloaded = true;
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+ }
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+
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+ index = XEXP (x, 1);
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+ if (!REG_OK_FOR_INDEX_STRICT_P (index))
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+ {
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+ push_reload (index, NULL_RTX, &XEXP (x, 1), NULL,
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+ INDEX_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
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+ opnum, (enum reload_type)type);
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+ something_reloaded = true;
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+ }
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+
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+ gcc_assert (something_reloaded);
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+ return true;
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+ }
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+
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+ return false;
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+}
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+
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/* Recognizes RTL expressions that are valid memory addresses for an
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instruction. The MODE argument is the machine mode for the MEM
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expression that wants to use this address.
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@@ -11872,6 +11926,13 @@ print_operand (FILE *file, rtx x, int code)
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return;
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case 'H':
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+ if (!offsettable_memref_p (x))
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+ {
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+ output_operand_lossage ("operand is not an offsettable memory "
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+ "reference, invalid operand "
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+ "code 'H'");
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+ return;
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+ }
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/* It doesn't actually matter what mode we use here, as we're
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only going to use this for printing. */
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x = adjust_address_nv (x, DImode, 8);
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@@ -14610,11 +14671,15 @@ ix86_match_ccmode (rtx insn, enum machine_mode req_mod
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if (req_mode == CCZmode)
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return 0;
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/* FALLTHRU */
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+ case CCZmode:
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+ break;
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+
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case CCAmode:
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case CCCmode:
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case CCOmode:
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case CCSmode:
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- case CCZmode:
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+ if (set_mode != req_mode)
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+ return 0;
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break;
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default:
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@@ -16196,11 +16261,15 @@ ix86_expand_sse_movcc (rtx dest, rtx cmp, rtx op_true,
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}
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else if (TARGET_XOP)
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{
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- rtx pcmov = gen_rtx_SET (mode, dest,
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- gen_rtx_IF_THEN_ELSE (mode, cmp,
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- op_true,
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- op_false));
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- emit_insn (pcmov);
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+ op_true = force_reg (mode, op_true);
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+
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+ if (!nonimmediate_operand (op_false, mode))
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+ op_false = force_reg (mode, op_false);
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+
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+ emit_insn (gen_rtx_SET (mode, dest,
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+ gen_rtx_IF_THEN_ELSE (mode, cmp,
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+ op_true,
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+ op_false)));
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}
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else
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{
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@@ -20104,7 +20173,9 @@ ix86_local_alignment (tree exp, enum machine_mode mode
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if (!TARGET_64BIT
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&& align == 64
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&& ix86_preferred_stack_boundary < 64
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- && (mode == DImode || (type && TYPE_MODE (type) == DImode))
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+ && (mode == DImode || (type && TYPE_MODE (type) == DImode)
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+ || mode == DFmode || (type && TYPE_MODE (type) == DFmode)
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+ || mode == DCmode || (type && TYPE_MODE (type) == DCmode))
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&& (!type || !TYPE_USER_ALIGN (type))
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&& (!decl || !DECL_USER_ALIGN (decl)))
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align = 32;
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@@ -20150,7 +20221,8 @@ ix86_local_alignment (tree exp, enum machine_mode mode
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|| TREE_CODE (type) == QUAL_UNION_TYPE)
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&& TYPE_FIELDS (type))
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{
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- if (DECL_MODE (TYPE_FIELDS (type)) == DFmode && align < 64)
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+ if (DECL_MODE (TYPE_FIELDS (type)) == DFmode && align < 64
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+ && ix86_preferred_stack_boundary >= 64)
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return 64;
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if (ALIGN_MODE_128 (DECL_MODE (TYPE_FIELDS (type))) && align < 128)
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return 128;
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@@ -20159,7 +20231,8 @@ ix86_local_alignment (tree exp, enum machine_mode mode
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|| TREE_CODE (type) == INTEGER_TYPE)
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{
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- if (TYPE_MODE (type) == DFmode && align < 64)
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+ if (TYPE_MODE (type) == DFmode && align < 64
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+ && ix86_preferred_stack_boundary >= 64)
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return 64;
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if (ALIGN_MODE_128 (TYPE_MODE (type)) && align < 128)
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return 128;
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@@ -23991,8 +24064,8 @@ ix86_expand_special_args_builtin (const struct builtin
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arg_adjust = 0;
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if (optimize
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|| target == 0
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- || GET_MODE (target) != tmode
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- || ! (*insn_p->operand[0].predicate) (target, tmode))
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+ || !register_operand (target, tmode)
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+ || GET_MODE (target) != tmode)
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target = gen_reg_rtx (tmode);
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}
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@@ -25067,7 +25140,7 @@ ix86_preferred_reload_class (rtx x, enum reg_class reg
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zero above. We only want to wind up preferring 80387 registers if
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we plan on doing computation with them. */
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if (TARGET_80387
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- && standard_80387_constant_p (x))
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+ && standard_80387_constant_p (x) > 0)
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{
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/* Limit class to non-sse. */
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if (regclass == FLOAT_SSE_REGS)
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@@ -27711,10 +27784,19 @@ ix86_expand_vector_set (bool mmx_ok, rtx target, rtx v
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break;
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case V2DImode:
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- use_vec_merge = TARGET_SSE4_1;
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+ use_vec_merge = TARGET_SSE4_1 && TARGET_64BIT;
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if (use_vec_merge)
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break;
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+ tmp = gen_reg_rtx (GET_MODE_INNER (mode));
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+ ix86_expand_vector_extract (false, tmp, target, 1 - elt);
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+ if (elt == 0)
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+ tmp = gen_rtx_VEC_CONCAT (mode, tmp, val);
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+ else
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+ tmp = gen_rtx_VEC_CONCAT (mode, val, tmp);
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+ emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
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+ return;
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+
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case V2DFmode:
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{
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rtx op0, op1;
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@@ -30651,6 +30733,11 @@ ix86_enum_va_list (int idx, const char **pname, tree *
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#undef TARGET_ASM_CODE_END
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#define TARGET_ASM_CODE_END ix86_code_end
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+
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+#if TARGET_MACHO
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+#undef TARGET_INIT_LIBFUNCS
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+#define TARGET_INIT_LIBFUNCS darwin_rename_builtins
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+#endif
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struct gcc_target targetm = TARGET_INITIALIZER;
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