Synchronize on NetBSD-CVS (2013/12/1 12:00:00 UTC)
- Fix for possible unset uid/gid in toproto
- Fix for default mtree style
- Update libelf
- Importing libexecinfo
- Resynchronize GCC, mpc, gmp, mpfr
- build.sh: Replace params with show-params.
This has been done as the make target has been renamed in the same
way, while a new target named params has been added. This new
target generates a file containing all the parameters, instead of
printing it on the console.
- Update test48 with new etc/services (Fix by Ben Gras <ben@minix3.org)
get getservbyport() out of the inner loop
Change-Id: Ie6ad5226fa2621ff9f0dee8782ea48f9443d2091
This commit is contained in:
@@ -1,4 +1,4 @@
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/* $NetBSD: bzero.S,v 1.11 2011/01/29 02:21:20 matt Exp $ */
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/* $NetBSD: bzero.S,v 1.14 2013/09/12 15:36:15 joerg Exp $ */
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/*-
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* Copyright (C) 2001 Martin J. Laubach <mjl@NetBSD.org>
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@@ -32,12 +32,10 @@
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#if defined(LIBC_SCCS) && !defined(lint)
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__RCSID("$NetBSD: bzero.S,v 1.11 2011/01/29 02:21:20 matt Exp $")
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__RCSID("$NetBSD: bzero.S,v 1.14 2013/09/12 15:36:15 joerg Exp $")
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#endif /* LIBC_SCCS && !lint */
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#ifdef _KERNEL
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#include <assym.h>
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#endif
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#include "assym.h"
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#define USE_STSWX 0 /* don't. slower than trivial copy loop */
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@@ -73,132 +71,20 @@ cb_memset:
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/*----------------------------------------------------------------------*/
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#ifndef _KERNEL
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/* First find out cache line size */
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#ifdef __PIC__
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/* First get cache line size */
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mflr %r9
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#ifdef PIC
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PIC_GOTSETUP(%r10)
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bcl 20,31,1f
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1: mflr %r10
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mtlr %r9
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lwz %r5,cache_info@got(%r10)
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addis %r10,%r10,_libc_powerpc_cache_info+CACHE_INFO_DCACHE_LINE_SIZE-1b@ha
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lwz %r9,_libc_powerpc_cache_info+CACHE_INFO_DCACHE_LINE_SIZE-1b@l(%r10)
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#else
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lis %r5,cache_info@h
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ori %r5,%r5,cache_info@l
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lis %r10,_libc_powerpc_cache_info+CACHE_INFO_DCACHE_LINE_SIZE@ha
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lwz %r9,_libc_powerpc_cache_info+CACHE_INFO_DCACHE_LINE_SIZE@l(%r10)
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#endif
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lwz %r6, 4(%r5)
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cmpwi %r6, -1
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bne+ cb_cacheline_known
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/*----------------------------------------------------------------------*/
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#define CTL_MACHDEP 7
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#define CPU_CACHELINE 1
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#define CPU_CACHEINFO 5
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#define STKFRAME_SZ 64
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#define MIB 8
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#define OLDPLEN 16
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#define R3_SAVE 20
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#define R4_SAVE 24
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#define R0_SAVE 28
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#define R8_SAVE 32
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#define R31_SAVE 36
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#ifdef PIC
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#define R30_SAVE 40
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#endif
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stw %r9, 4(%r1)
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stwu %r1, -STKFRAME_SZ(%r1)
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stw %r31, R31_SAVE(%r1)
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mr %r31, %r5 /* cache info */
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#ifdef PIC
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stw %r30, R30_SAVE(%r1)
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PIC_TOCSETUP(cb_memset,%r30)
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#endif
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stw %r8, R8_SAVE(%r1)
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stw %r3, R3_SAVE(%r1)
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stw %r4, R4_SAVE(%r1)
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stw %r0, R0_SAVE(%r1)
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li %r0, CTL_MACHDEP /* Construct MIB */
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stw %r0, MIB(%r1)
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li %r0, CPU_CACHEINFO
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stw %r0, MIB+4(%r1)
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li %r0, 4*4 /* Oldlenp := 4*4 */
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stw %r0, OLDPLEN(%r1)
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addi %r3, %r1, MIB
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li %r4, 2 /* namelen */
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/* %r5 already contains &cache_info */
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addi %r6, %r1, OLDPLEN
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li %r7, 0
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li %r8, 0
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bl PIC_PLT(_C_LABEL(sysctl))
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cmpwi %r3, 0 /* Check result */
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beq 1f
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/* Failure, try older sysctl */
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li %r0, CTL_MACHDEP /* Construct MIB */
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stw %r0, MIB(%r1)
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li %r0, CPU_CACHELINE
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stw %r0, MIB+4(%r1)
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li %r0, 4 /* Oldlenp := 4 */
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stw %r0, OLDPLEN(%r1)
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addi %r3, %r1, MIB
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li %r4, 2 /* namelen */
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addi %r5, %r31, 4
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addi %r6, %r1, OLDPLEN
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li %r7, 0
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li %r8, 0
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bl PIC_PLT(_C_LABEL(sysctl))
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1:
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lwz %r3, R3_SAVE(%r1)
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lwz %r4, R4_SAVE(%r1)
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lwz %r8, R8_SAVE(%r1)
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lwz %r0, R0_SAVE(%r1)
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lwz %r9, 4(%r31)
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lwz %r31, R31_SAVE(%r1)
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#ifdef PIC
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lwz %r30, R30_SAVE(%r1)
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#endif
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addi %r1, %r1, STKFRAME_SZ
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lwz %r7, 4(%r1)
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mtlr %r7
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cntlzw %r6, %r9 /* compute shift value */
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li %r5, 31
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subf %r5, %r6, %r5
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#ifdef PIC
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mflr %r9
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PIC_GOTSETUP(%r10)
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mtlr %r9
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lwz %r6, cache_sh@got(%r10)
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stw %r5, 0(%r6)
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#else
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lis %r6, cache_sh@ha
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stw %r5, cache_sh@l(%r6)
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#endif
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/*----------------------------------------------------------------------*/
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/* Okay, we know the cache line size (%r9) and shift value (%r10) */
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cb_cacheline_known:
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#ifdef PIC
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lwz %r5, cache_info@got(%r10)
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lwz %r9, 4(%r5)
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lwz %r5, cache_sh@got(%r10)
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lwz %r10, 0(%r5)
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#else
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lis %r9, cache_info+4@ha
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lwz %r9, cache_info+4@l(%r9)
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lis %r10, cache_sh@ha
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lwz %r10, cache_sh@l(%r10)
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#endif
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cmplwi %cr1, %r9, 0 /* Unknown? */
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beq- simple_fill /* a trivial fill routine */
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#else /* _KERNEL */
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#ifdef MULTIPROCESSOR
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mfsprg %r10, 0 /* Get cpu_info pointer */
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@@ -206,11 +92,11 @@ cb_cacheline_known:
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lis %r10, cpu_info_store@ha
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addi %r10, %r10, cpu_info_store@l
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#endif
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lwz %r9, CPU_CI+4(%r10) /* Load D$ line size */
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lwz %r9, CPU_CI+CACHE_INFO_DCACHE_LINE_SIZE(%r10) /* Load D$ line size */
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#endif /* _KERNEL */
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cntlzw %r10, %r9 /* Calculate shift.. */
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li %r6, 31
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subf %r10, %r10, %r6
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#endif /* _KERNEL */
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/* Back in memory filling business */
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cmplwi %cr1, r_len, 0 /* Nothing to do? */
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@@ -371,6 +257,7 @@ END(memset)
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/*----------------------------------------------------------------------*/
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#ifndef _KERNEL
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.data
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.p2align 2
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cache_info: .long -1, -1, -1, -1
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cache_sh: .long 0
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