Synchronize on NetBSD-CVS (2013/12/1 12:00:00 UTC)

- Fix for possible unset uid/gid in toproto
 - Fix for default mtree style
 - Update libelf
 - Importing libexecinfo
 - Resynchronize GCC, mpc, gmp, mpfr
 - build.sh: Replace params with show-params.
     This has been done as the make target has been renamed in the same
     way, while a new target named params has been added. This new
     target generates a file containing all the parameters, instead of
     printing it on the console.
 - Update test48 with new etc/services (Fix by Ben Gras <ben@minix3.org)
     get getservbyport() out of the inner loop

Change-Id: Ie6ad5226fa2621ff9f0dee8782ea48f9443d2091

sys/arch/arm/include/arm32/db_machdep.h

@@ -1,11 +1,10 @@
-/* $NetBSD: db_machdep.h,v 1.6 2012/09/21 22:12:36 matt Exp $ */
+/* $NetBSD: db_machdep.h,v 1.7 2013/01/05 15:06:51 christos Exp $ */
 
 #ifndef _ARM32_DB_MACHDEP_H_
 #define _ARM32_DB_MACHDEP_H_
 
 #include <arm/db_machdep.h>
 
-void db_show_panic_cmd(db_expr_t, bool, db_expr_t, const char *);
 void db_show_frame_cmd(db_expr_t, bool, db_expr_t, const char *);
 void db_show_fault_cmd(db_expr_t, bool, db_expr_t, const char *);
 

sys/arch/arm/include/arm32/frame.h

@@ -1,4 +1,4 @@
-/*	$NetBSD: frame.h,v 1.33 2012/08/29 07:09:12 matt Exp $	*/
+/*	$NetBSD: frame.h,v 1.36 2013/08/18 06:37:02 matt Exp $	*/
 
 /*
  * Copyright (c) 1994-1997 Mark Brinicombe.
@@ -50,14 +50,6 @@
 
 #ifndef _LOCORE
 
-/*
- * System stack frames.
- */
-
-struct clockframe {
-	struct trapframe cf_tf;
-};
-
 /*
  * Switch frame.
  *
@@ -73,6 +65,14 @@ struct switchframe {
 	u_int	sf_pc;
 };
  
+/*
+ * System stack frames.
+ */
+
+struct clockframe {
+	struct trapframe cf_tf;
+};
+
 /*
  * Stack frame. Used during stack traces (db_trace.c)
  */
@@ -96,16 +96,33 @@ void validate_trapframe(trapframe_t *, int);
 #include "opt_arm_debug.h"
 #include "opt_cputypes.h"
 
-#include <machine/cpu.h>
+#include <arm/locore.h>
 
 /*
  * This macro is used by DO_AST_AND_RESTORE_ALIGNMENT_FAULTS to process
  * any pending softints.
  */
+#ifdef _ARM_ARCH_4T
+#define	B_CF_CONTROL(rX)						;\
+	ldr	ip, [rX, #CF_CONTROL]	/* get function addr */		;\
+	bx	ip			/* branch to cpu_control */
+#else
+#define	B_CF_CONTROL(rX)						;\
+	ldr	pc, [rX, #CF_CONTROL]	/* branch to cpu_control */
+#endif
+#ifdef _ARM_ARCH_5T
+#define	BL_CF_CONTROL(rX)						;\
+	ldr	ip, [rX, #CF_CONTROL]	/* get function addr */		;\
+	blx	ip			/* call cpu_control */
+#else
+#define	BL_CF_CONTROL(rX)						;\
+	mov	lr, pc							;\
+	ldr	pc, [rX, #CF_CONTROL]	/* call cpu_control */
+#endif
 #if defined(__HAVE_FAST_SOFTINTS) && !defined(__HAVE_PIC_FAST_SOFTINTS)
 #define	DO_PENDING_SOFTINTS						\
 	ldr	r0, [r4, #CI_INTR_DEPTH]/* Get current intr depth */	;\
-	teq	r0, #0			/* Test for 0. */		;\
+	cmp	r0, #0			/* Test for 0. */		;\
 	bne	10f			/*   skip softints if != 0 */	;\
 	ldr	r0, [r4, #CI_CPL]	/* Get current priority level */;\
 	ldr	r1, [r4, #CI_SOFTINTS]	/* Get pending softint mask */	;\
@@ -183,8 +200,7 @@ void validate_trapframe(trapframe_t *, int);
 	ldr	r2, .Laflt_cpufuncs					;\
 	ldr	r1, [r4, #CI_CTRL]	/* Fetch control register */	;\
 	mov	r0, #-1							;\
-	mov	lr, pc							;\
-	ldr	pc, [r2, #CF_CONTROL]	/* Enable alignment faults */	;\
+	BL_CF_CONTROL(r2)		/* Enable alignment faults */	;\
 1:	KERNEL_LOCK
 
 /*
@@ -211,7 +227,7 @@ void validate_trapframe(trapframe_t *, int);
 	mov	r0, #-1							;\
 	bic	r1, r1, #CPU_CONTROL_AFLT_ENABLE  /* Disable AFLTs */	;\
 	adr	lr, 3f							;\
-	ldr	pc, [r2, #CF_CONTROL]	/* Set new CTRL reg value */	;\
+	B_CF_CONTROL(r2)		/* Set new CTRL reg value */	;\
 	/* NOTREACHED */						\
 2:	mov	r1, #0x00000000						;\
 	str	r1, [r4, #CI_ASTPENDING] /* Clear astpending */		;\
@@ -323,7 +339,7 @@ LOCK_CAS_DEBUG_LOCALS
  */
 #define	PUSHUSERREGS							   \
 	stmia	sp, {r0-r12};		/* Push the user mode registers */ \
-	add	r0, sp, #(4*13);	/* Adjust the stack pointer */	   \
+	add	r0, sp, #(TF_USR_SP-TF_R0); /* Adjust the stack pointer */ \
 	stmia	r0, {r13-r14}^		/* Push the user mode registers */
 #else
 #define	PUSHUSERREGS							   \
@@ -332,11 +348,61 @@ LOCK_CAS_DEBUG_LOCALS
 
 #define PUSHFRAME							   \
 	str	lr, [sp, #-4]!;		/* Push the return address */	   \
-	sub	sp, sp, #(4*17);	/* Adjust the stack pointer */	   \
+	sub	sp, sp, #(TF_PC-TF_R0);	/* Adjust the stack pointer */	   \
 	PUSHUSERREGS;			/* Push the user mode registers */ \
 	mov     r0, r0;                 /* NOP for previous instruction */ \
 	mrs	r0, spsr_all;		/* Get the SPSR */		   \
-	str	r0, [sp, #-8]!		/* Push the SPSR on the stack */
+	str	r0, [sp, #-TF_R0]!	/* Push the SPSR on the stack */
+
+/*
+ * Push a minimal trapframe so we can dispatch an interrupt from the
+ * idle loop.  The only reason the idle loop wakes up is to dispatch
+ * interrupts so why take the avoid of a full exception when we can do
+ * something minimal.
+ */
+#define PUSHIDLEFRAME							   \
+	str	lr, [sp, #-4]!;		/* save SVC32 lr */		   \
+	str	r6, [sp, #(TF_R6-TF_PC)]!; /* save callee-saved r6 */	   \
+	str	r4, [sp, #(TF_R4-TF_R6)]!; /* save callee-saved r4 */	   \
+	mrs	r0, cpsr_all;		/* Get the CPSR */		   \
+	str	r0, [sp, #(-TF_R4)]!	/* Push the CPSR on the stack */
+
+/*
+ * Push a trapframe to be used by cpu_switchto
+ */
+#define PUSHSWITCHFRAME(rX)						\
+	mov	ip, sp;							\
+	sub	sp, sp, #(TRAPFRAMESIZE-TF_R12); /* Adjust the stack pointer */ \
+	push	{r4-r11};		/* Push the callee saved registers */ \
+	sub	sp, sp, #TF_R4;		/* reserve rest of trapframe */	\
+	str	ip, [sp, #TF_SVC_SP];					\
+	str	lr, [sp, #TF_SVC_LR];					\
+	str	lr, [sp, #TF_PC];					\
+	mrs	rX, cpsr_all;		/* Get the CPSR */		\
+	str	rX, [sp, #TF_SPSR]	/* save in trapframe */
+
+#define PUSHSWITCHFRAME1						   \
+	mov	ip, sp;							   \
+	sub	sp, sp, #(TRAPFRAMESIZE-TF_R8); /* Adjust the stack pointer */ \
+	push	{r4-r7};		/* Push some of the callee saved registers */ \
+	sub	sp, sp, #TF_R4;		/* reserve rest of trapframe */	\
+	str	ip, [sp, #TF_SVC_SP];					\
+	str	lr, [sp, #TF_SVC_LR];					\
+	str	lr, [sp, #TF_PC]
+
+#if defined(_ARM_ARCH_DWORD_OK) && __ARM_EABI__
+#define	PUSHSWITCHFRAME2						\
+	strd	r10, [sp, #TF_R10];	/* save r10 & r11 */		\
+	strd	r8, [sp, #TF_R8];	/* save r8 & r9 */		\
+	mrs	r0, cpsr_all;		/* Get the CPSR */		\
+	str	r0, [sp, #TF_SPSR]	/* save in trapframe */
+#else
+#define	PUSHSWITCHFRAME2						\
+	add	r0, sp, #TF_R8;		/* get ptr to r8 and above */	\
+	stmia	r0, {r8-r11};		/* save rest of registers */	\
+	mrs	r0, cpsr_all;		/* Get the CPSR */		\
+	str	r0, [sp, #TF_SPSR]	/* save in trapframe */
+#endif
 
 /*
  * PULLFRAME - macro to pull a trap frame from the stack in the current mode
@@ -344,13 +410,28 @@ LOCK_CAS_DEBUG_LOCALS
  */
 
 #define PULLFRAME							   \
-	ldr     r0, [sp], #0x0008;      /* Pop the SPSR from stack */	   \
+	ldr     r0, [sp], #TF_R0;	/* Pop the SPSR from stack */	   \
 	msr     spsr_all, r0;						   \
 	ldmia   sp, {r0-r14}^;		/* Restore registers (usr mode) */ \
 	mov     r0, r0;                 /* NOP for previous instruction */ \
-	add	sp, sp, #(4*17);	/* Adjust the stack pointer */	   \
+	add	sp, sp, #(TF_PC-TF_R0);	/* Adjust the stack pointer */	   \
  	ldr	lr, [sp], #0x0004	/* Pop the return address */
 
+#define PULLIDLEFRAME							   \
+	add	sp, sp, #TF_R4;		/* Adjust the stack pointer */	   \
+	ldr	r4, [sp], #(TF_R6-TF_R4); /* restore callee-saved r4 */	   \
+	ldr	r6, [sp], #(TF_PC-TF_R6); /* restore callee-saved r6 */	   \
+ 	ldr	lr, [sp], #4		/* Pop the return address */
+
+/*
+ * Pop a trapframe to be used by cpu_switchto (don't touch r0 & r1).
+ */
+#define PULLSWITCHFRAME							\
+	add	sp, sp, #TF_R4;		/* Adjust the stack pointer */	\
+	pop	{r4-r11};		/* pop the callee saved registers */ \
+	add	sp, sp, #(TF_PC-TF_R12); /* Adjust the stack pointer */	\
+	ldr	lr, [sp], #4;		/* pop the return address */
+
 /*
  * PUSHFRAMEINSVC - macro to push a trap frame on the stack in SVC32 mode
  * This should only be used if the processor is not currently in SVC32
@@ -385,11 +466,11 @@ LOCK_CAS_DEBUG_LOCALS
 	mov	sp, r2;			/* Keep stack aligned */	   \
 	msr     spsr_all, r3;		/* Restore correct spsr */	   \
 	ldmdb	r1, {r0-r3};		/* Restore 4 regs from xxx mode */ \
-	sub	sp, sp, #(4*15);	/* Adjust the stack pointer */	   \
+	sub	sp, sp, #(TF_SVC_SP-TF_R0); /* Adjust the stack pointer */ \
 	PUSHUSERREGS;			/* Push the user mode registers */ \
 	mov     r0, r0;                 /* NOP for previous instruction */ \
 	mrs	r0, spsr_all;		/* Get the SPSR */		   \
-	str	r0, [sp, #-8]!		/* Push the SPSR onto the stack */
+	str	r0, [sp, #-TF_R0]!	/* Push the SPSR onto the stack */
 
 /*
  * PULLFRAMEFROMSVCANDEXIT - macro to pull a trap frame from the stack
@@ -403,7 +484,7 @@ LOCK_CAS_DEBUG_LOCALS
 	msr     spsr_all, r0;		/* restore SPSR */		   \
 	ldmia   sp, {r0-r14}^;		/* Restore registers (usr mode) */ \
 	mov     r0, r0;	  		/* NOP for previous instruction */ \
-	add	sp, sp, #(4*15);	/* Adjust the stack pointer */	   \
+	add	sp, sp, #(TF_SVC_SP-TF_R0); /* Adjust the stack pointer */ \
 	ldmia	sp, {sp, lr, pc}^	/* Restore lr and exit */
 
 #endif /* _LOCORE */

sys/arch/arm/include/arm32/machdep.h

@@ -1,4 +1,4 @@
-/* $NetBSD: machdep.h,v 1.16 2012/09/01 12:19:32 martin Exp $ */
+/* $NetBSD: machdep.h,v 1.17 2012/10/20 14:42:20 matt Exp $ */
 
 #ifndef _ARM32_BOOT_MACHDEP_H_
 #define _ARM32_BOOT_MACHDEP_H_
@@ -43,7 +43,7 @@ struct bootmem_info {
 	 */
 	pv_addr_t bmi_vector_l2pt;
 	pv_addr_t bmi_io_l2pt;
-	pv_addr_t bmi_l2pts[16];
+	pv_addr_t bmi_l2pts[32];	// for large memory disks.
 	u_int bmi_freepages;
 	u_int bmi_nfreeblocks;
 };

sys/arch/arm/include/arm32/param.h

@@ -1,4 +1,4 @@
-/*	$NetBSD: param.h,v 1.17 2012/02/04 17:56:16 para Exp $	*/
+/*	$NetBSD: param.h,v 1.20 2013/05/29 23:29:44 rkujawa Exp $	*/
 
 /*
  * Copyright (c) 1994,1995 Mark Brinicombe.
@@ -57,7 +57,7 @@
 #define USPACE          (UPAGES * NBPG) /* total size of u-area */
 
 #ifndef MSGBUFSIZE
-#define MSGBUFSIZE	NBPG		/* default message buffer size */
+#define MSGBUFSIZE	16384	 	/* default message buffer size */
 #endif
 
 /*
@@ -72,17 +72,13 @@
 /*
  * The USPACE area contains :
  * 1. the pcb structure for the process
- * 2. the fp context for FP emulation
- * 3. the kernel (svc) stack
+ * 2. the kernel (svc) stack
  *
  * The layout of the area looks like this
  *
- * | uarea | FP context | kernel stack |
+ * | uarea | kernel stack |
  *
  * The size of the uarea is known.
- * The size of the FP context is variable depending of the FP emulator
- * in use and whether there is hardware FP support. However we can put
- * an upper limit on it.
  * The kernel stack should be at least 4K is size.
  *
  * The stack top addresses are used to set the stack pointers. The stack bottom
@@ -90,12 +86,11 @@
  *
  */
 
-#define FPCONTEXTSIZE			(0x100)
 #define USPACE_SVC_STACK_TOP		(USPACE)
-#define USPACE_SVC_STACK_BOTTOM		(sizeof(struct pcb) + FPCONTEXTSIZE + 10)
+#define USPACE_SVC_STACK_BOTTOM		(sizeof(struct pcb))
 
-#define arm_btop(x)			((x) >> PGSHIFT)
-#define arm_ptob(x)			((x) << PGSHIFT)
+#define arm_btop(x)			((unsigned)(x) >> PGSHIFT)
+#define arm_ptob(x)			((unsigned)(x) << PGSHIFT)
 #define arm_trunc_page(x)		((unsigned)(x) & ~PGOFSET)
     
 #ifdef _KERNEL

sys/arch/arm/include/arm32/pmap.h

@@ -1,4 +1,4 @@
-/*	$NetBSD: pmap.h,v 1.112 2012/09/22 00:33:38 matt Exp $	*/
+/*	$NetBSD: pmap.h,v 1.122 2013/08/18 05:01:47 matt Exp $	*/
 
 /*
  * Copyright (c) 2002, 2003 Wasabi Systems, Inc.
@@ -143,16 +143,16 @@ struct l2_dtable;
 union pmap_cache_state {
 	struct {
 		union {
-			u_int8_t csu_cache_b[2];
-			u_int16_t csu_cache;
+			uint8_t csu_cache_b[2];
+			uint16_t csu_cache;
 		} cs_cache_u;
 
 		union {
-			u_int8_t csu_tlb_b[2];
-			u_int16_t csu_tlb;
+			uint8_t csu_tlb_b[2];
+			uint16_t csu_tlb;
 		} cs_tlb_u;
 	} cs_s;
-	u_int32_t cs_all;
+	uint32_t cs_all;
 };
 #define	cs_cache_id	cs_s.cs_cache_u.csu_cache_b[0]
 #define	cs_cache_d	cs_s.cs_cache_u.csu_cache_b[1]
@@ -182,11 +182,13 @@ struct pmap_devmap {
  * The pmap structure itself
  */
 struct pmap {
-	u_int8_t		pm_domain;
+	uint8_t			pm_domain;
 	bool			pm_remove_all;
 	bool			pm_activated;
 	struct l1_ttable	*pm_l1;
+#ifndef ARM_HAS_VBAR
 	pd_entry_t		*pm_pl1vec;
+#endif
 	pd_entry_t		pm_l1vec;
 	union pmap_cache_state	pm_cstate;
 	struct uvm_object	pm_obj;
@@ -269,6 +271,7 @@ extern pv_addr_t kernel_l1pt;
  * Commonly referenced structures
  */
 extern int		pmap_debug_level; /* Only exists if PMAP_DEBUG */
+extern int		arm_poolpage_vmfreelist;
 
 /*
  * Macros that we need to export
@@ -321,6 +324,7 @@ void	pmap_do_remove(pmap_t, vaddr_t, vaddr_t, int);
 int	pmap_fault_fixup(pmap_t, vaddr_t, vm_prot_t, int);
 bool	pmap_get_pde_pte(pmap_t, vaddr_t, pd_entry_t **, pt_entry_t **);
 bool	pmap_get_pde(pmap_t, vaddr_t, pd_entry_t **);
+struct pcb;
 void	pmap_set_pcb_pagedir(pmap_t, struct pcb *);
 
 void	pmap_debug(int);
@@ -448,6 +452,27 @@ pmap_ptesync(pt_entry_t *ptep, size_t cnt)
 				 (L2_B | L2_C | L2_XS_T_TEX(TEX_XSCALE_X)))\
 				 == (L2_C | L2_XS_T_TEX(TEX_XSCALE_X)))
 
+static inline void
+l2pte_set(pt_entry_t *ptep, pt_entry_t pte, pt_entry_t opte)
+{
+	KASSERT(*ptep == opte);
+	*ptep = pte;
+	for (vsize_t k = 1; k < PAGE_SIZE / L2_S_SIZE; k++) {
+		KASSERT(ptep[k] == opte ? opte + k * L2_S_SIZE : 0);
+		pte += L2_S_SIZE;
+		ptep[k] = pte;
+	}
+}       
+
+static inline void
+l2pte_reset(pt_entry_t *ptep)
+{
+	*ptep = 0;
+	for (vsize_t k = 1; k < PAGE_SIZE / L2_S_SIZE; k++) {
+		ptep[k] = 0;
+	}
+}       
+
 /* L1 and L2 page table macros */
 #define pmap_pde_v(pde)		l1pte_valid(*(pde))
 #define pmap_pde_section(pde)	l1pte_section_p(*(pde))
@@ -462,6 +487,14 @@ pmap_ptesync(pt_entry_t *ptep, size_t cnt)
 #define KERNEL_PD_SIZE	\
 	(L1_TABLE_SIZE - (KERNEL_BASE >> L1_S_SHIFT) * sizeof(pd_entry_t))
 
+void	bzero_page(vaddr_t);
+void	bcopy_page(vaddr_t, vaddr_t);
+
+#ifdef FPU_VFP
+void	bzero_page_vfp(vaddr_t);
+void	bcopy_page_vfp(vaddr_t, vaddr_t);
+#endif
+
 /************************* ARM MMU configuration *****************************/
 
 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0
@@ -881,12 +914,22 @@ extern void (*pmap_zero_page_func)(paddr_t);
 #define	L2_L_MAPPABLE_P(va, pa, size)					\
 	((((va) | (pa)) & L2_L_OFFSET) == 0 && (size) >= L2_L_SIZE)
 
+#ifndef _LOCORE
 /*
  * Hooks for the pool allocator.
  */
 #define	POOL_VTOPHYS(va)	vtophys((vaddr_t) (va))
-
-#ifndef _LOCORE
+extern paddr_t physical_start, physical_end;
+#ifdef PMAP_NEED_ALLOC_POOLPAGE
+struct vm_page *arm_pmap_alloc_poolpage(int);
+#define	PMAP_ALLOC_POOLPAGE	arm_pmap_alloc_poolpage
+#endif
+#if defined(PMAP_NEED_ALLOC_POOLPAGE) || defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS)
+#define	PMAP_MAP_POOLPAGE(pa) \
+        ((vaddr_t)((paddr_t)(pa) - physical_start + KERNEL_BASE))
+#define PMAP_UNMAP_POOLPAGE(va) \
+        ((paddr_t)((vaddr_t)(va) - KERNEL_BASE + physical_start))
+#endif
 
 /*
  * pmap-specific data store in the vm_page structure.

sys/arch/arm/include/arm32/types.h

@@ -1,4 +1,4 @@
-/*	$NetBSD: types.h,v 1.9 2010/07/07 01:20:50 chs Exp $	*/
+/*	$NetBSD: types.h,v 1.11 2013/05/07 23:01:55 matt Exp $	*/
 
 /*
  * Copyright (c) 2001 Wasabi Systems, Inc.

sys/arch/arm/include/arm32/vmparam.h

@@ -1,4 +1,4 @@
-/*	$NetBSD: vmparam.h,v 1.27 2012/08/16 07:25:37 matt Exp $	*/
+/*	$NetBSD: vmparam.h,v 1.29 2013/02/27 17:50:07 matt Exp $	*/
 
 /*
  * Copyright (c) 2001, 2002 Wasabi Systems, Inc.
@@ -55,25 +55,25 @@
  * Note that MAXTSIZ can't be larger than 32M, otherwise the compiler
  * would have to be changed to not generate "bl" instructions.
  */
-#define	MAXTSIZ		(16*1024*1024)		/* max text size */
+#define	MAXTSIZ		(64*1024*1024)		/* max text size */
 #ifndef	DFLDSIZ
 #define	DFLDSIZ		(128*1024*1024)		/* initial data size limit */
 #endif
 #ifndef	MAXDSIZ
-#define	MAXDSIZ		(512*1024*1024)		/* max data size */
+#define	MAXDSIZ		(1024*1024*1024)	/* max data size */
 #endif
 #ifndef	DFLSSIZ
 #define	DFLSSIZ		(2*1024*1024)		/* initial stack size limit */
 #endif
 #ifndef	MAXSSIZ
-#define	MAXSSIZ		(8*1024*1024)		/* max stack size */
+#define	MAXSSIZ		(32*1024*1024)		/* max stack size */
 #endif
 
 /*
  * While the ARM architecture defines Section mappings, large pages,
  * and small pages, the standard page size is (and will always be) 4K.
  */
-#define	PAGE_SHIFT	12
+#define	PAGE_SHIFT	PGSHIFT
 #define	PAGE_SIZE	(1 << PAGE_SHIFT)
 #define	PAGE_MASK	(PAGE_SIZE - 1)