imported code harmonisation
. common/include/arch/i386 is not actually an imported sys/arch/i386/include but leftover Minix files; remove and move to include/ . move include/ufs to sys/ufs, where it came from, now that we have a sys/ hierarchy . move mdocml/ to external/bsd/, now we have that . single sys/arch/i386/stand/ import for boot stuff
This commit is contained in:
Ben Gras
@@ -1,9 +0,0 @@
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.include <bsd.own.mk>
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.PATH: ${MINIXSRCDIR}/common/include/arch/i386
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INCS+= archtypes.h bios.h cmos.h cpu.h diskparm.h fpu.h int86.h \
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interrupt.h memory.h multiboot.h partition.h \
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pci.h pci_amd.h pci_intel.h pci_sis.h pci_via.h \
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ports.h stackframe.h vm.h elf.h elf_machdep.h mutex.h \
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disklabel.h
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@@ -1,47 +0,0 @@
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#ifndef _I386_TYPES_H
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#define _I386_TYPES_H
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#include <minix/sys_config.h>
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#include <machine/stackframe.h>
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#include <machine/fpu.h>
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#include <sys/cdefs.h>
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struct segdesc_s { /* segment descriptor for protected mode */
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u16_t limit_low;
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u16_t base_low;
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u8_t base_middle;
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u8_t access; /* |P|DL|1|X|E|R|A| */
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u8_t granularity; /* |G|X|0|A|LIMT| */
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u8_t base_high;
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};
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#define LDT_SIZE 2 /* CS and DS */
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/* Fixed local descriptors. */
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#define CS_LDT_INDEX 0 /* process CS */
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#define DS_LDT_INDEX 1 /* process DS=ES=FS=GS=SS */
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typedef struct segframe {
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reg_t p_ldt_sel; /* selector in gdt with ldt base and limit */
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reg_t p_cr3; /* page table root */
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u32_t *p_cr3_v;
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struct segdesc_s p_ldt[LDT_SIZE]; /* CS, DS and remote */
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} segframe_t;
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/* fpu_state_s is used in kernel proc table.
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* Any changes in this structure requires changes in sconst.h,
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* since this structure is used in proc structure. */
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struct fpu_state_s {
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union fpu_state_u *fpu_save_area_p; /* 16-aligned fpu_save_area */
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/* fpu_image includes 512 bytes of image itself and
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* additional 15 bytes required for manual 16-byte alignment. */
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char fpu_image[527];
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};
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#define INMEMORY(p) (!p->p_seg.p_cr3 || get_cpulocal_var(ptproc) == p)
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typedef u32_t atomic_t; /* access to an aligned 32bit value is atomic on i386 */
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#endif /* #ifndef _I386_TYPES_H */
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@@ -1,125 +0,0 @@
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/* Definitions of several known BIOS addresses. The addresses listed here
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* are found in three memory areas that have been defined in <ibm/memory.h>.
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* - the BIOS interrupt vectors
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* - the BIOS data area
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* - the motherboard BIOS memory
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*
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* Created: March 2005, Jorrit N. Herder
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*/
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#ifndef _BIOS_H
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#define _BIOS_H
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/* PART I --
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* The BIOS interrupt vector table (IVT) area (1024 B as of address 0x0000).
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* Although this area holds 256 interrupt vectors (with jump addresses), some
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* vectors actually contain important BIOS data. Some addresses are below.
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*/
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#define BIOS_EQUIP_CHECK_ADDR 0x0044
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#define BIOS_EQUIP_CHECK_SIZE 4L
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#define BIOS_VIDEO_PARAMS_ADDR 0x0074
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#define BIOS_VIDEO_PARAMS_SIZE 4L
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#define BIOS_FLOP_PARAMS_ADDR 0x0078
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#define BIOS_FLOP_PARAMS_SIZE 4L
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#define BIOS_HD0_PARAMS_ADDR 0x0104 /* disk 0 parameters */
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#define BIOS_HD0_PARAMS_SIZE 4L
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#define BIOS_HD1_PARAMS_ADDR 0x0118 /* disk 1 parameters */
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#define BIOS_HD1_PARAMS_SIZE 4L
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/* PART I --
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* Addresses in the BIOS data area (256 B as of address 0x0400). The addresses
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* listed below are the most important ones, and the ones that are currently
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* used. Other addresses may be defined below when new features are added.
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*/
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/* Serial ports (COM1-COM4). */
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#define COM1_IO_PORT_ADDR 0x400 /* COM1 port address */
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#define COM1_IO_PORT_SIZE 2L
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#define COM2_IO_PORT_ADDR 0x402 /* COM2 port address */
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#define COM2_IO_PORT_SIZE 2L
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#define COM3_IO_PORT_ADDR 0x404 /* COM3 port address */
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#define COM3_IO_PORT_SIZE 2L
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#define COM4_IO_PORT_ADDR 0x406 /* COM4 port address */
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#define COM4_IO_PORT_SIZE 2L
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/* Parallel ports (LPT1-LPT4). */
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#define LPT1_IO_PORT_ADDR 0x408 /* LPT1 port address */
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#define LPT1_IO_PORT_SIZE 2L
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#define LPT2_IO_PORT_ADDR 0x40A /* LPT2 port address */
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#define LPT2_IO_PORT_SIZE 2L
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#define LPT3_IO_PORT_ADDR 0x40C /* LPT3 port address */
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#define LPT3_IO_PORT_SIZE 2L
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#define LPT4_IO_PORT_ADDR 0x40E /* LPT4 port (except on PS/2) */
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#define LPT4_IO_PORT_SIZE 2L
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/* Video controller (VDU). */
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#define VDU_SCREEN_COLS_ADDR 0x44A /* VDU nr of screen columns */
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#define VDU_SCREEN_COLS_SIZE 2L
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/* Base I/O port address for active 6845 CRT controller. */
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#define VDU_CRT_BASE_ADDR 0x463 /* 3B4h = mono, 3D4h = color */
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#define VDU_CRT_BASE_SIZE 2L
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/* Soft reset flags to control shutdown. */
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#define SOFT_RESET_FLAG_ADDR 0x472 /* soft reset flag on Ctl-Alt-Del */
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#define SOFT_RESET_FLAG_SIZE 2L
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#define STOP_MEM_CHECK 0x1234 /* bypass memory tests & CRT init */
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#define PRESERVE_MEMORY 0x4321 /* preserve memory */
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#define SYSTEM_SUSPEND 0x5678 /* system suspend */
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#define MANUFACTURER_TEST 0x9ABC /* manufacturer test */
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#define CONVERTIBLE_POST 0xABCD /* convertible POST loop */
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/* ... many other values are used during POST */
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/* Hard disk parameters. (Also see BIOS interrupt vector table above.) */
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#define NR_HD_DRIVES_ADDR 0x475 /* number of hard disk drives */
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#define NR_HD_DRIVES_SIZE 1L
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/* Parallel ports (LPT1-LPT4) timeout values. */
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#define LPT1_TIMEOUT_ADDR 0x478 /* time-out value for LPT1 */
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#define LPT1_TIMEOUT_SIZE 1L
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#define LPT2_TIMEOUT_ADDR 0x479 /* time-out value for LPT2 */
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#define LPT2_TIMEOUT_SIZE 1L
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#define LPT3_TIMEOUT_ADDR 0x47A /* time-out value for LPT3 */
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#define LPT3_TIMEOUT_SIZE 1L
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#define LPT4_TIMEOUT_ADDR 0x47B /* time-out for LPT4 (except PS/2) */
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#define LPT4_TIMEOUT_SIZE 1L
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/* Serial ports (COM1-COM4) timeout values. */
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#define COM1_TIMEOUT_ADDR 0x47C /* time-out value for COM1 */
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#define COM1_TIMEOUT_SIZE 1L
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#define COM2_TIMEOUT_ADDR 0x47D /* time-out value for COM2 */
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#define COM2_TIMEOUT_SIZE 1L
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#define COM3_TIMEOUT_ADDR 0x47E /* time-out value for COM3 */
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#define COM3_TIMEOUT_SIZE 1L
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#define COM4_TIMEOUT_ADDR 0x47F /* time-out value for COM4 */
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#define COM4_TIMEOUT_SIZE 1L
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/* Video controller (VDU). */
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#define VDU_SCREEN_ROWS_ADDR 0x484 /* screen rows (less 1, EGA+)*/
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#define VDU_SCREEN_ROWS_SIZE 1L
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#define VDU_FONTLINES_ADDR 0x485 /* point height of char matrix */
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#define VDU_FONTLINES_SIZE 2L
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/* Video controller (VDU). */
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#define VDU_VIDEO_MODE_ADDR 0x49A /* current video mode */
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#define VDU_VIDEO_MODE_SIZE 1L
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/* PART III --
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* The motherboard BIOS memory contains some known values that are currently
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* in use. Other sections in the upper memory area (UMA) addresses vary in
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* size and locus and are not further defined here. A rough map is given in
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* <ibm/memory.h>.
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*/
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/* Machine ID (we're interested in PS/2 and AT models). */
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#define MACHINE_ID_ADDR 0xFFFFE /* BIOS machine ID byte */
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#define MACHINE_ID_SIZE 1L
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#define PS_386_MACHINE 0xF8 /* ID byte for PS/2 modela 70/80 */
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#define PC_AT_MACHINE 0xFC /* PC/AT, PC/XT286, PS/2 models 50/60 */
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#endif /* _BIOS_H */
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@@ -1,85 +0,0 @@
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/*
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ibm/cmos.h
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Created: Dec 1998 by Philip Homburg <philip@cs.vu.nl>
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Definitions for the CMOS/realtime clock. Based on the datasheet for the
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Dallas DS12887, compatible with the Motorola MC146818
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*/
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#define RTC_INDEX 0x70 /* Bit 7 = NMI enable (1) / disable (0)
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* bits 0..6 index
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*/
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#define RTC_IO 0x71 /* Data register,
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* Note: the operation following a write to
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* RTC_INDEX should an access (read or write)
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* to RTC_IO
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*/
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#define RTC_SEC 0x0 /* Seconds register */
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#define RTC_SEC_ALRM 0x1 /* Seconds register for alarm */
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#define RTC_MIN 0x2 /* Minutes register */
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#define RTC_MIN_ALRM 0x3 /* Minutes register for alarm */
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#define RTC_HOUR 0x4 /* Hours register */
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#define RTC_HOUR_ALRM 0x5 /* Hours register for alarm */
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#define RTC_WDAY 0x6 /* Day of the week, 1..7, Sunday = 1 */
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#define RTC_MDAY 0x7 /* Day of the month, 1..31 */
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#define RTC_MONTH 0x8 /* Month, 1..12 */
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#define RTC_YEAR 0x9 /* Year, 0..99 */
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#define RTC_REG_A 0xA
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#define RTC_A_UIP 0x80 /* Update in progress. When clear,
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* no update will occur for 244
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* micro seconds.
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*/
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#define RTC_A_DV 0x70 /* Divider bits, valid values are: */
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#define RTC_A_DV_OK 0x20 /* Normal */
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#define RTC_A_DV_STOP 0x70 /* Stop, a re-start starts
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* halfway through a cycle,
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* i.e. the update occurs after
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* 500ms.
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*/
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#define RTC_A_RS 0x0F /* Int. freq */
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/* 0 None
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* 1 256 Hz
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* 2 128 Hz
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* 3 8192 Hz
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* 4 4096 Hz
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* 5 2048 Hz
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* 6 1024 Hz
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* 7 512 Hz
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* 8 256 Hz
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* 9 128 Hz
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* 10 64 Hz
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* 11 32 Hz
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* 12 16 Hz
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* 13 8 Hz
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* 14 4 Hz
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* 15 2 Hz
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*/
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#define RTC_A_RS_DEF 6 /* Default freq. */
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#define RTC_REG_B 0xB
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#define RTC_B_SET 0x80 /* Inhibit updates */
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#define RTC_B_PIE 0x40 /* Enable periodic interrupts */
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#define RTC_B_AIE 0x20 /* Enable alarm interrupts */
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#define RTC_B_UIE 0x10 /* Enable update ended interrupts */
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#define RTC_B_SQWE 0x08 /* Enable square wave output */
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#define RTC_B_DM_BCD 0x04 /* Data is in BCD (otherwise binary) */
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#define RTC_B_24 0x02 /* Count hours in 24-hour mode */
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#define RTC_B_DSE 0x01 /* Automatic (wrong) daylight savings
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* updates
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*/
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#define RTC_REG_C 0xC
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/* Contents of the general purpose CMOS RAM (source IBM reference manual) */
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#define CMOS_STATUS 0xE
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#define CS_LOST_POWER 0x80 /* Chip lost power */
|
||||
#define CS_BAD_CHKSUM 0x40 /* Checksum is incorrect */
|
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#define CS_BAD_CONFIG 0x20 /* Bad configuration info */
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#define CS_BAD_MEMSIZE 0x10 /* Wrong memory size of CMOS */
|
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#define CS_BAD_HD 0x08 /* Harddisk failed */
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#define CS_BAD_TIME 0x04 /* CMOS time is invalid */
|
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/* bits 0 and 1 are reserved */
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|
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/*
|
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* $PchId: cmos.h,v 1.1 1998/12/16 09:14:21 philip Exp $
|
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*/
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@@ -1,19 +0,0 @@
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#ifndef _IBM_CPU_H
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#define _IBM_CPU_H 1
|
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#define X86_FLAG_C (1L << 0) /* S Carry */
|
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#define X86_FLAG_P (1L << 2) /* S Parity */
|
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#define X86_FLAG_A (1L << 4) /* S Aux. carry */
|
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#define X86_FLAG_Z (1L << 6) /* S Zero */
|
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#define X86_FLAG_S (1L << 7) /* S Sign */
|
||||
|
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#define X86_FLAG_T (1L << 8) /* X Trap */
|
||||
#define X86_FLAG_I (1L << 9) /* X Interrupt */
|
||||
#define X86_FLAG_D (1L << 10) /* C Direction */
|
||||
#define X86_FLAG_O (1L << 11) /* S Overflow */
|
||||
|
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/* User flags are S (Status) and C (Control) flags. */
|
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#define X86_FLAGS_USER (X86_FLAG_C | X86_FLAG_P | X86_FLAG_A | X86_FLAG_Z | \
|
||||
X86_FLAG_S | X86_FLAG_D | X86_FLAG_O)
|
||||
|
||||
#endif
|
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@@ -1,75 +0,0 @@
|
||||
/* $NetBSD: disklabel.h,v 1.16 2011/08/30 12:39:55 bouyer Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1994 Christopher G. Demetriou
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed by Christopher G. Demetriou.
|
||||
* 4. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _I386_DISKLABEL_H_
|
||||
#define _I386_DISKLABEL_H_
|
||||
|
||||
#define LABELUSESMBR 1 /* use MBR partitionning */
|
||||
#define LABELSECTOR 1 /* sector containing label */
|
||||
#define LABELOFFSET 0 /* offset of label in sector */
|
||||
#define MAXPARTITIONS 16 /* number of partitions */
|
||||
#define OLDMAXPARTITIONS 8 /* number of partitions before 1.6 */
|
||||
#define RAW_PART 3 /* raw partition: XX?d (XXX) */
|
||||
|
||||
/*
|
||||
* We use the highest bit of the minor number for the partition number.
|
||||
* This maintains backward compatibility with device nodes created before
|
||||
* MAXPARTITIONS was increased.
|
||||
*/
|
||||
#define __I386_MAXDISKS ((1 << 20) / MAXPARTITIONS)
|
||||
#define DISKUNIT(dev) ((minor(dev) / OLDMAXPARTITIONS) % __I386_MAXDISKS)
|
||||
#define DISKPART(dev) ((minor(dev) % OLDMAXPARTITIONS) + \
|
||||
((minor(dev) / (__I386_MAXDISKS * OLDMAXPARTITIONS)) * OLDMAXPARTITIONS))
|
||||
#define DISKMINOR(unit, part) \
|
||||
(((unit) * OLDMAXPARTITIONS) + ((part) % OLDMAXPARTITIONS) + \
|
||||
((part) / OLDMAXPARTITIONS) * (__I386_MAXDISKS * OLDMAXPARTITIONS))
|
||||
|
||||
/* Pull in MBR partition definitions. */
|
||||
#if HAVE_NBTOOL_CONFIG_H
|
||||
#include <nbinclude/sys/bootblock.h>
|
||||
#else
|
||||
#include <sys/bootblock.h>
|
||||
#endif /* HAVE_NBTOOL_CONFIG_H */
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
#if HAVE_NBTOOL_CONFIG_H
|
||||
#include <nbinclude/sys/dkbad.h>
|
||||
#else
|
||||
#include <sys/dkbad.h>
|
||||
#endif /* HAVE_NBTOOL_CONFIG_H */
|
||||
struct cpu_disklabel {
|
||||
#define __HAVE_DISKLABEL_DKBAD
|
||||
struct dkbad bad;
|
||||
};
|
||||
#endif
|
||||
|
||||
#endif /* _I386_DISKLABEL_H_ */
|
||||
@@ -1,20 +0,0 @@
|
||||
/* PC (and AT) BIOS structure to hold disk parameters. Under Minix, it is
|
||||
* used mainly for formatting.
|
||||
*/
|
||||
|
||||
#ifndef _DISKPARM_H
|
||||
#define _DISKPARM_H
|
||||
struct disk_parameter_s {
|
||||
char spec1;
|
||||
char spec2;
|
||||
char motor_turnoff_sec;
|
||||
char sector_size_code;
|
||||
char sectors_per_cylinder;
|
||||
char gap_length;
|
||||
char dtl;
|
||||
char gap_length_for_format;
|
||||
char fill_byte_for_format;
|
||||
char head_settle_msec;
|
||||
char motor_start_eigth_sec;
|
||||
};
|
||||
#endif /* _DISKPARM_H */
|
||||
@@ -1,116 +0,0 @@
|
||||
/*-
|
||||
* Copyright (c) 1996-1997 John D. Polstra.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* $FreeBSD$
|
||||
*/
|
||||
|
||||
#ifndef _MACHINE_ELF_H_
|
||||
#define _MACHINE_ELF_H_ 1
|
||||
|
||||
/*
|
||||
* ELF definitions for the i386 architecture.
|
||||
*/
|
||||
|
||||
#include <sys/elf32.h> /* Definitions common to all 32 bit architectures. */
|
||||
#if defined(__ELF_WORD_SIZE) && __ELF_WORD_SIZE == 64
|
||||
#include <sys/elf64.h> /* Definitions common to all 64 bit architectures. */
|
||||
#endif
|
||||
|
||||
#ifndef __ELF_WORD_SIZE
|
||||
#define __ELF_WORD_SIZE 32 /* Used by <sys/elf_generic.h> */
|
||||
#endif
|
||||
|
||||
#include <sys/elf_generic.h>
|
||||
|
||||
#define ELF_ARCH EM_386
|
||||
|
||||
#define ELF_MACHINE_OK(x) ((x) == EM_386 || (x) == EM_486)
|
||||
|
||||
/*
|
||||
* Auxiliary vector entries for passing information to the interpreter.
|
||||
*
|
||||
* The i386 supplement to the SVR4 ABI specification names this "auxv_t",
|
||||
* but POSIX lays claim to all symbols ending with "_t".
|
||||
*/
|
||||
|
||||
typedef struct { /* Auxiliary vector entry on initial stack */
|
||||
int a_type; /* Entry type. */
|
||||
union {
|
||||
long a_val; /* Integer value. */
|
||||
void *a_ptr; /* Address. */
|
||||
void (*a_fcn)(void); /* Function pointer (not used). */
|
||||
} a_un;
|
||||
} Elf32_Auxinfo;
|
||||
|
||||
#if __ELF_WORD_SIZE == 64
|
||||
/* Fake for amd64 loader support */
|
||||
typedef struct {
|
||||
int fake;
|
||||
} Elf64_Auxinfo;
|
||||
#endif
|
||||
|
||||
__ElfType(Auxinfo);
|
||||
|
||||
/* Values for a_type. */
|
||||
#define AT_NULL 0 /* Terminates the vector. */
|
||||
#define AT_IGNORE 1 /* Ignored entry. */
|
||||
#define AT_EXECFD 2 /* File descriptor of program to load. */
|
||||
#define AT_PHDR 3 /* Program header of program already loaded. */
|
||||
#define AT_PHENT 4 /* Size of each program header entry. */
|
||||
#define AT_PHNUM 5 /* Number of program header entries. */
|
||||
#define AT_PAGESZ 6 /* Page size in bytes. */
|
||||
#define AT_BASE 7 /* Interpreter's base address. */
|
||||
#define AT_FLAGS 8 /* Flags (unused for i386). */
|
||||
#define AT_ENTRY 9 /* Where interpreter should transfer control. */
|
||||
#define AT_NOTELF 10 /* Program is not ELF ?? */
|
||||
#define AT_UID 11 /* Real uid. */
|
||||
#define AT_EUID 12 /* Effective uid. */
|
||||
#define AT_GID 13 /* Real gid. */
|
||||
#define AT_EGID 14 /* Effective gid. */
|
||||
#define AT_EXECPATH 15 /* Path to the executable. */
|
||||
#define AT_CANARY 16 /* Canary for SSP. */
|
||||
#define AT_CANARYLEN 17 /* Length of the canary. */
|
||||
#define AT_OSRELDATE 18 /* OSRELDATE. */
|
||||
#define AT_NCPUS 19 /* Number of CPUs. */
|
||||
#define AT_PAGESIZES 20 /* Pagesizes. */
|
||||
#define AT_PAGESIZESLEN 21 /* Number of pagesizes. */
|
||||
|
||||
#define AT_COUNT 22 /* Count of defined aux entry types. */
|
||||
|
||||
/*
|
||||
* Relocation types.
|
||||
*/
|
||||
|
||||
#define R_386_COUNT 38 /* Count of defined relocation types. */
|
||||
|
||||
/* Define "machine" characteristics */
|
||||
#define ELF_TARG_CLASS ELFCLASS32
|
||||
#define ELF_TARG_DATA ELFDATA2LSB
|
||||
#define ELF_TARG_MACH EM_386
|
||||
#define ELF_TARG_VER 1
|
||||
|
||||
#define ET_DYN_LOAD_ADDR 0x01001000
|
||||
|
||||
#endif /* !_MACHINE_ELF_H_ */
|
||||
@@ -1,63 +0,0 @@
|
||||
/* $NetBSD: elf_machdep.h,v 1.10 2009/05/30 05:56:52 skrll Exp $ */
|
||||
|
||||
#define ELF32_MACHDEP_ENDIANNESS ELFDATA2LSB
|
||||
#define ELF32_MACHDEP_ID_CASES \
|
||||
case EM_386: \
|
||||
case EM_486: \
|
||||
break;
|
||||
|
||||
#define ELF64_MACHDEP_ENDIANNESS XXX /* break compilation */
|
||||
#define ELF64_MACHDEP_ID_CASES \
|
||||
/* no 64-bit ELF machine types supported */
|
||||
|
||||
#define ELF32_MACHDEP_ID EM_386
|
||||
|
||||
#define ARCH_ELFSIZE 32 /* MD native binary size */
|
||||
|
||||
/* i386 relocations */
|
||||
#define R_386_NONE 0
|
||||
#define R_386_32 1
|
||||
#define R_386_PC32 2
|
||||
#define R_386_GOT32 3
|
||||
#define R_386_PLT32 4
|
||||
#define R_386_COPY 5
|
||||
#define R_386_GLOB_DAT 6
|
||||
#define R_386_JMP_SLOT 7
|
||||
#define R_386_RELATIVE 8
|
||||
#define R_386_GOTOFF 9
|
||||
#define R_386_GOTPC 10
|
||||
|
||||
/* TLS relocations */
|
||||
#define R_386_TLS_TPOFF 14
|
||||
#define R_386_TLS_IE 15
|
||||
#define R_386_TLS_GOTIE 16
|
||||
#define R_386_TLS_LE 17
|
||||
#define R_386_TLS_GD 18
|
||||
#define R_386_TLS_LDM 19
|
||||
|
||||
/* The following relocations are GNU extensions. */
|
||||
#define R_386_16 20
|
||||
#define R_386_PC16 21
|
||||
#define R_386_8 22
|
||||
#define R_386_PC8 23
|
||||
|
||||
/* More TLS relocations */
|
||||
#define R_386_TLS_GD_32 24
|
||||
#define R_386_TLS_GD_PUSH 25
|
||||
#define R_386_TLS_GD_CALL 26
|
||||
#define R_386_TLS_GD_POP 27
|
||||
#define R_386_TLS_LDM_32 28
|
||||
#define R_386_TLS_LDM_PUSH 29
|
||||
#define R_386_TLS_LDM_CALL 30
|
||||
#define R_386_TLS_LDM_POP 31
|
||||
#define R_386_TLS_LDO_32 32
|
||||
#define R_386_TLS_IE_32 33
|
||||
#define R_386_TLS_LE_32 34
|
||||
#define R_386_TLS_DTPMOD32 35
|
||||
#define R_386_TLS_DTPOFF32 36
|
||||
#define R_386_TLS_TPOFF32 37
|
||||
#define R_386_TLS_GOTDESC 39
|
||||
#define R_386_TLS_DESC_CALL 40
|
||||
#define R_386_TLS_DESC 41
|
||||
|
||||
#define R_TYPE(name) __CONCAT(R_386_,name)
|
||||
@@ -1,50 +0,0 @@
|
||||
#ifndef FPU_H
|
||||
#define FPU_H
|
||||
|
||||
/* x87 FPU state, MMX Technolodgy.
|
||||
* 108 bytes.*/
|
||||
struct fpu_regs_s {
|
||||
u16_t fp_control; /* control */
|
||||
u16_t fp_unused_1;
|
||||
u16_t fp_status; /* status */
|
||||
u16_t fp_unused_2;
|
||||
u16_t fp_tag; /* register tags */
|
||||
u16_t fp_unused_3;
|
||||
u32_t fp_eip; /* eip at failed instruction */
|
||||
u16_t fp_cs; /* cs at failed instruction */
|
||||
u16_t fp_opcode; /* opcode of failed instruction */
|
||||
u32_t fp_dp; /* data address */
|
||||
u16_t fp_ds; /* data segment */
|
||||
u16_t fp_unused_4;
|
||||
u16_t fp_st_regs[8][5]; /* 8 80-bit FP registers */
|
||||
};
|
||||
|
||||
/* x87 FPU, MMX Technolodgy and SSE state.
|
||||
* 512 bytes (if you need size use FPU_XFP_SIZE). */
|
||||
struct xfp_save {
|
||||
u16_t fp_control; /* control */
|
||||
u16_t fp_status; /* status */
|
||||
u16_t fp_tag; /* register tags */
|
||||
u16_t fp_opcode; /* opcode of failed instruction */
|
||||
u32_t fp_eip; /* eip at failed instruction */
|
||||
u16_t fp_cs; /* cs at failed instruction */
|
||||
u16_t fp_unused_1;
|
||||
u32_t fp_dp; /* data address */
|
||||
u16_t fp_ds; /* data segment */
|
||||
u16_t fp_unused_2;
|
||||
u32_t fp_mxcsr; /* MXCSR */
|
||||
u32_t fp_mxcsr_mask; /* MXCSR_MASK */
|
||||
u16_t fp_st_regs[8][8]; /* 128 bytes for ST/MM regs */
|
||||
u32_t fp_xreg_word[32]; /* space for 8 128-bit XMM registers */
|
||||
u32_t fp_padding[56];
|
||||
};
|
||||
|
||||
/* Size of xfp_save structure. */
|
||||
#define FPU_XFP_SIZE 512
|
||||
|
||||
union fpu_state_u {
|
||||
struct fpu_regs_s fpu_regs;
|
||||
struct xfp_save xfp_regs;
|
||||
};
|
||||
|
||||
#endif /* #ifndef FPU_H */
|
||||
@@ -1,61 +0,0 @@
|
||||
/* int86.h - 8086 interrupt types Author: Kees J. Bot
|
||||
* 3 May 2000
|
||||
*/
|
||||
|
||||
/* Registers used in an PC real mode call for BIOS or DOS services. A
|
||||
* driver is called through the vector if the interrupt number is zero.
|
||||
*/
|
||||
union reg86 {
|
||||
struct l {
|
||||
u32_t ef; /* 32 bit flags (output only) */
|
||||
u32_t vec; /* Driver vector (input only) */
|
||||
u32_t _ds_es[1];
|
||||
u32_t eax; /* 32 bit general registers */
|
||||
u32_t ebx;
|
||||
u32_t ecx;
|
||||
u32_t edx;
|
||||
u32_t esi;
|
||||
u32_t edi;
|
||||
u32_t ebp;
|
||||
} l;
|
||||
struct w {
|
||||
u16_t f, _ef[1]; /* 16 bit flags (output only) */
|
||||
u16_t off, seg; /* Driver vector (input only) */
|
||||
u16_t ds, es; /* DS and ES real mode segment regs */
|
||||
u16_t ax, _eax[1]; /* 16 bit general registers */
|
||||
u16_t bx, _ebx[1];
|
||||
u16_t cx, _ecx[1];
|
||||
u16_t dx, _edx[1];
|
||||
u16_t si, _esi[1];
|
||||
u16_t di, _edi[1];
|
||||
u16_t bp, _ebp[1];
|
||||
} w;
|
||||
struct b {
|
||||
u8_t intno, _intno[3]; /* Interrupt number (input only) */
|
||||
u8_t _vec[4];
|
||||
u8_t _ds_es[4];
|
||||
u8_t al, ah, _eax[2]; /* 8 bit general registers */
|
||||
u8_t bl, bh, _ebx[2];
|
||||
u8_t cl, ch, _ecx[2];
|
||||
u8_t dl, dh, _edx[2];
|
||||
u8_t _esi[4];
|
||||
u8_t _edi[4];
|
||||
u8_t _ebp[4];
|
||||
} b;
|
||||
};
|
||||
|
||||
struct reg86u { union reg86 u; }; /* Better for forward declarations */
|
||||
|
||||
/* Parameters passed on ioctls to the memory task. */
|
||||
|
||||
struct mio_int86 { /* MIOCINT86 */
|
||||
union reg86 reg86; /* x86 registers as above */
|
||||
u16_t off, seg; /* Address of kernel buffer */
|
||||
void *buf; /* User data buffer */
|
||||
size_t len; /* Size of user buffer */
|
||||
};
|
||||
|
||||
struct mio_ldt86 { /* MIOCGLDT86, MIOCSLDT86 */
|
||||
size_t idx; /* Index in process' LDT */
|
||||
u16_t entry[4]; /* One LDT entry to get or set. */
|
||||
};
|
||||
@@ -1,66 +0,0 @@
|
||||
/* Interrupt numbers and hardware vectors. */
|
||||
|
||||
#ifndef _INTERRUPT_H
|
||||
#define _INTERRUPT_H
|
||||
|
||||
#if (CHIP == INTEL)
|
||||
|
||||
/* 8259A interrupt controller ports. */
|
||||
#define INT_CTL 0x20 /* I/O port for interrupt controller */
|
||||
#define INT_CTLMASK 0x21 /* setting bits in this port disables ints */
|
||||
#define INT2_CTL 0xA0 /* I/O port for second interrupt controller */
|
||||
#define INT2_CTLMASK 0xA1 /* setting bits in this port disables ints */
|
||||
|
||||
/* Magic numbers for interrupt controller. */
|
||||
#define END_OF_INT 0x20 /* code used to re-enable after an interrupt */
|
||||
|
||||
/* Interrupt vectors defined/reserved by processor. */
|
||||
#define DIVIDE_VECTOR 0 /* divide error */
|
||||
#define DEBUG_VECTOR 1 /* single step (trace) */
|
||||
#define NMI_VECTOR 2 /* non-maskable interrupt */
|
||||
#define BREAKPOINT_VECTOR 3 /* software breakpoint */
|
||||
#define OVERFLOW_VECTOR 4 /* from INTO */
|
||||
|
||||
/* Fixed system call vector. */
|
||||
#define KERN_CALL_VECTOR 32 /* system calls are made with int SYSVEC */
|
||||
#define IPC_VECTOR 33 /* interrupt vector for ipc */
|
||||
|
||||
/* Suitable irq bases for hardware interrupts. Reprogram the 8259(s) from
|
||||
* the PC BIOS defaults since the BIOS doesn't respect all the processor's
|
||||
* reserved vectors (0 to 31).
|
||||
*/
|
||||
#define BIOS_IRQ0_VEC 0x08 /* base of IRQ0-7 vectors used by BIOS */
|
||||
#define BIOS_IRQ8_VEC 0x70 /* base of IRQ8-15 vectors used by BIOS */
|
||||
#define IRQ0_VECTOR 0x50 /* nice vectors to relocate IRQ0-7 to */
|
||||
#define IRQ8_VECTOR 0x70 /* no need to move IRQ8-15 */
|
||||
|
||||
/* Hardware interrupt numbers. */
|
||||
#ifndef USE_APIC
|
||||
#define NR_IRQ_VECTORS 16
|
||||
#else
|
||||
#define NR_IRQ_VECTORS 64
|
||||
#endif
|
||||
#define CLOCK_IRQ 0
|
||||
#define KEYBOARD_IRQ 1
|
||||
#define CASCADE_IRQ 2 /* cascade enable for 2nd AT controller */
|
||||
#define ETHER_IRQ 3 /* default ethernet interrupt vector */
|
||||
#define SECONDARY_IRQ 3 /* RS232 interrupt vector for port 2 */
|
||||
#define RS232_IRQ 4 /* RS232 interrupt vector for port 1 */
|
||||
#define XT_WINI_IRQ 5 /* xt winchester */
|
||||
#define FLOPPY_IRQ 6 /* floppy disk */
|
||||
#define PRINTER_IRQ 7
|
||||
#define SPURIOUS_IRQ 7
|
||||
#define CMOS_CLOCK_IRQ 8
|
||||
#define KBD_AUX_IRQ 12 /* AUX (PS/2 mouse) port in kbd controller */
|
||||
#define AT_WINI_0_IRQ 14 /* at winchester controller 0 */
|
||||
#define AT_WINI_1_IRQ 15 /* at winchester controller 1 */
|
||||
|
||||
/* Interrupt number to hardware vector. */
|
||||
#define BIOS_VECTOR(irq) \
|
||||
(((irq) < 8 ? BIOS_IRQ0_VEC : BIOS_IRQ8_VEC) + ((irq) & 0x07))
|
||||
#define VECTOR(irq) \
|
||||
(((irq) < 8 ? IRQ0_VECTOR : IRQ8_VECTOR) + ((irq) & 0x07))
|
||||
|
||||
#endif /* (CHIP == INTEL) */
|
||||
|
||||
#endif /* _INTERRUPT_H */
|
||||
@@ -1,171 +0,0 @@
|
||||
/* Physical memory layout on IBM compatible PCs. Only the major, fixed memory
|
||||
* areas are detailed here. Known addresses of the BIOS data area are defined
|
||||
* in <ibm/bios.h>. The map upper memory area (UMA) is only roughly defined
|
||||
* since the UMA sections may vary in size and locus.
|
||||
*
|
||||
* Created: March 2005, Jorrit N. Herder
|
||||
*/
|
||||
|
||||
/* I/O-mapped peripherals. I/O addresses are different from memory addresses
|
||||
* due to the I/O signal on the ISA bus. Individual I/O ports are defined by
|
||||
* the drivers that use them or looked up with help of the BIOS.
|
||||
*/
|
||||
#define IO_MEMORY_BEGIN 0x0000
|
||||
#define IO_MEMORY_END 0xFFFF
|
||||
|
||||
|
||||
/* Physical memory layout. Design decisions made for the earliest PCs, caused
|
||||
* memory to be broken broken into the following four basic pieces:
|
||||
* - Conventional or base memory: first 640 KB (incl. BIOS data, see below);
|
||||
* The top of conventional memory is often used by the BIOS to store data.
|
||||
* - Upper Memory Area (UMA): upper 384 KB of the first megabyte of memory;
|
||||
* - High Memory Area (HMA): ~ first 64 KB of the second megabyte of memory;
|
||||
* - Extended Memory: all the memory above first megabyte of memory.
|
||||
* The high memory area overlaps with the first 64 KB of extended memory, but
|
||||
* is different from the rest of extended memory because it can be accessed
|
||||
* when the processor is in real mode.
|
||||
*/
|
||||
#define BASE_MEM_BEGIN 0x000000
|
||||
#define BASE_MEM_TOP 0x090000
|
||||
#define BASE_MEM_END 0x09FFFF
|
||||
|
||||
#define UPPER_MEM_BEGIN 0x0A0000
|
||||
#define UPPER_MEM_END 0x0FFFFF
|
||||
|
||||
#define HIGH_MEM_BEGIN 0x100000
|
||||
#define HIGH_MEM_END 0x10FFEF
|
||||
|
||||
#define EXTENDED_MEM_BEGIN 0x100000
|
||||
#define EXTENDED_MEM_END ((unsigned) -1)
|
||||
|
||||
|
||||
/* The logical memory map of the first 1.5 MB is as follows (hexadecimals):
|
||||
*
|
||||
* offset [size] (id) = memory usage
|
||||
* ------------------------------------------------------------------------
|
||||
* 000000 [00400] (I) = Real-Mode Interrupt Vector Table (1024 B)
|
||||
* 000400 [00100] (B) = BIOS Data Area (256 B)
|
||||
* 000800 [00066] (W) = 80286 Loadall workspace
|
||||
* 010000 [10000] (c) = Real-Mode Compatibility Segment (64 KB)
|
||||
* 020000 [70000] (.) = Program-accessible memory (free)
|
||||
* 090000 [10000] (E) = BIOS Extension
|
||||
* 0A0000 [10000] (G) = Graphics Mode Video RAM
|
||||
* 0B0000 [08000] (M) = Monochrome Text Mode Video RAM
|
||||
* 0B8000 [08000] (C) = Color Text Mode Video RAM
|
||||
* 0C0000 [08000] (V) = Video ROM BIOS (would be "a" in PS/2)
|
||||
* 0C8000 [18000] (a) = Adapter ROM + special-purpose RAM (free UMA space)
|
||||
* 0E0000 [10000] (r) = PS/2 Motherboard ROM BIOS (free UMA in non-PS/2)
|
||||
* 0F0000 [06000] (R) = Motherboard ROM BIOS
|
||||
* 0F6000 [08000] (b) = IBM Cassette BASIC ROM ("R" in IBM compatibles)
|
||||
* 0FD000 [02000] (R) = Motherboard ROM BIOS
|
||||
* 100000 [.....] (.) = Extended memory, program-accessible (free)
|
||||
* 100000 [0FFEF] (h) = High Memory Area (HMA)
|
||||
*
|
||||
*
|
||||
* Conventional (Base) Memory:
|
||||
*
|
||||
* : [~~~~~16 KB~~~~][~~~~~16 KB~~~~][~~~~~16 KB~~~~][~~~~~16 KB~~~~]
|
||||
* : 0---1---2---3---4---5---6---7---8---9---A---B---C---D---E---F---
|
||||
* 000000: IBW.............................................................
|
||||
* 010000: cccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccc
|
||||
* 020000: ................................................................
|
||||
* 030000: ................................................................
|
||||
* 040000: ................................................................
|
||||
* 050000: ................................................................
|
||||
* 060000: ................................................................
|
||||
* 070000: ................................................................
|
||||
* 080000: ................................................................
|
||||
* 090000: EEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEE
|
||||
*
|
||||
* Upper Memory Area (UMA):
|
||||
*
|
||||
* : 0---1---2---3---4---5---6---7---8---9---A---B---C---D---E---F---
|
||||
* 0A0000: GGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGG
|
||||
* 0B0000: MMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC
|
||||
* 0C0000: VVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
|
||||
* 0D0000: aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
|
||||
* 0E0000: rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr
|
||||
* 0F0000: RRRRRRRRRRRRRRRRRRRRRRRRbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbRRRRRRRR
|
||||
*
|
||||
* Extended Memory:
|
||||
*
|
||||
* : 0---1---2---3---4---5---6---7---8---9---A---B---C---D---E---F---
|
||||
* 100000: hhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhh.
|
||||
* 110000: ................................................................
|
||||
* 120000: ................................................................
|
||||
* 130000: ................................................................
|
||||
* 140000: ................................................................
|
||||
* 150000: ................................................................
|
||||
* 160000: ................................................................
|
||||
* 170000: ................................................................
|
||||
*
|
||||
* Source: The logical memory map was partly taken from the book "Upgrading
|
||||
* & Repairing PCs Eight Edition", Macmillan Computer Publishing.
|
||||
*/
|
||||
|
||||
|
||||
/* The bottom part of conventional or base memory is occupied by BIOS data.
|
||||
* The BIOS memory can be distinguished in two parts:
|
||||
* o The first the first 1024 bytes of addressable memory contains the BIOS
|
||||
* real-mode interrupt vector table (IVT). The table is used to access BIOS
|
||||
* hardware services in real-mode by loading a interrupt vector and issuing
|
||||
* an INT instruction. Some vectors contain BIOS data that can be retrieved
|
||||
* directly and are useful in protected-mode as well.
|
||||
* o The BIOS data area is located directly above the interrupt vectors. It
|
||||
* comprises 256 bytes of memory. These data are used by the device drivers
|
||||
* to retrieve hardware details, such as I/O ports to be used.
|
||||
*/
|
||||
#define BIOS_MEM_BEGIN 0x00000 /* all BIOS memory */
|
||||
#define BIOS_MEM_END 0x004FF
|
||||
#define BIOS_IVT_BEGIN 0x00000 /* BIOS interrupt vectors */
|
||||
#define BIOS_IVT_END 0x003FF
|
||||
#define BIOS_DATA_BEGIN 0x00400 /* BIOS data area */
|
||||
#define BIOS_DATA_END 0x004FF
|
||||
|
||||
/* The base memory is followed by 384 KB reserved memory located at the top of
|
||||
* the first MB of physical memory. This memory is known as the upper memory
|
||||
* area (UMA). It is used for memory-mapped peripherals, such as video RAM,
|
||||
* adapter BIOS (adapter ROM and special purpose RAM), and the motherboard
|
||||
* BIOS (I/O system, Power-On Self Test, bootstrap loader). The upper memory
|
||||
* can roughly be distinguished in three parts:
|
||||
*
|
||||
* o The first 128K of the upper memory area (A0000-BFFFF) is reserved for use
|
||||
* by memory-mapped video adapters. Hence, it is also called Video RAM. The
|
||||
* display driver can directly write to this memory and request the hardware
|
||||
* to show the data on the screen.
|
||||
*/
|
||||
#define UMA_VIDEO_RAM_BEGIN 0xA0000 /* video RAM */
|
||||
#define UMA_VIDEO_RAM_END 0xBFFFF
|
||||
#define UMA_GRAPHICS_RAM_BEGIN 0xA0000 /* graphics RAM */
|
||||
#define UMA_GRAPHICS_RAM_END 0xAFFFF
|
||||
#define UMA_MONO_TEXT_BEGIN 0xB0000 /* monochrome text */
|
||||
#define UMA_MONO_TEXT_END 0xB7FFF
|
||||
#define UMA_COLOR_TEXT_BEGIN 0xB8000 /* color text */
|
||||
#define UMA_COLOR_TEXT_END 0xBFFFF
|
||||
|
||||
/* o The next 128K (the memory range C0000-DFFFF) is reserved for the adapter
|
||||
* BIOS that resides in the ROM on some adapter boards. Most VGA-compatible
|
||||
* video adapters use the first 32 KB of this area for their on-board BIOS.
|
||||
* The rest can be used by any other adapters. The IDE controller often
|
||||
* occupies the second 32 KB.
|
||||
*/
|
||||
#define UMA_ADAPTER_BIOS_BEGIN 0xC0000 /* adapter BIOS */
|
||||
#define UMA_ADAPTER_BIOS_END 0xDFFFF
|
||||
#define UMA_VIDEO_BIOS_BEGIN 0xC0000 /* video adapter */
|
||||
#define UMA_VIDEO_BIOS_END 0xC7FFF
|
||||
#define UMA_IDE_HD_BIOS_BEGIN 0xC8000 /* IDE hard disk */
|
||||
#define UMA_IDE_HD_BIOS_END 0xCBFFF
|
||||
|
||||
/* o The last 128K of the upper memory area (E0000-FFFFF) is reserved for
|
||||
* motherboard BIOS (Basic I/O System). The POST (Power-On Self Test) and
|
||||
* bootstrap loader also reside in this space. The memory falls apart in
|
||||
* two areas: Plug & Play BIOS data and the system BIOS data.
|
||||
*/
|
||||
#define UMA_MB_BIOS_BEGIN 0xE0000 /* motherboard BIOS */
|
||||
#define UMA_MB_BIOS_END 0xFFFFF
|
||||
#define UMA_PNP_ESCD_BIOS_BEGIN 0xE0000 /* PnP extended data */
|
||||
#define UMA_PNP_ESCD_BIOS_END 0xEFFFF
|
||||
#define UMA_SYSTEM_BIOS_BEGIN 0xF0000 /* system BIOS */
|
||||
#define UMA_SYSTEM_BIOS_END 0xFFFFF
|
||||
|
||||
|
||||
@@ -1,128 +0,0 @@
|
||||
#ifndef __MULTIBOOT_H__
|
||||
#define __MULTIBOOT_H__
|
||||
|
||||
#define MULTIBOOT_HEADER_MAGIC 0x1BADB002
|
||||
|
||||
#define MULTIBOOT_BOOTLOADER_MAGIC 0x2BADB002
|
||||
|
||||
/* Must pass memory information to OS. */
|
||||
#define MULTIBOOT_PAGE_ALIGN 0x00000001
|
||||
|
||||
#define MULTIBOOT_MEMORY_INFO 0x00000002
|
||||
|
||||
#define MULTIBOOT_VIDEO_MODE 0x00000004
|
||||
|
||||
#define MULTIBOOT_AOUT_KLUDGE 0x00010000
|
||||
|
||||
#define MULTIBOOT_FLAGS (MULTIBOOT_MEMORY_INFO | MULTIBOOT_PAGE_ALIGN)
|
||||
|
||||
/* consts used for Multiboot pre-init */
|
||||
|
||||
#define MULTIBOOT_VIDEO_MODE_EGA 1
|
||||
|
||||
#define MULTIBOOT_VIDEO_BUFFER 0xB8000
|
||||
|
||||
/* Usable lower memory chunk has a upper bound */
|
||||
#define MULTIBOOT_LOWER_MEM_MAX 0x7f800
|
||||
|
||||
#define MULTIBOOT_CONSOLE_LINES 25
|
||||
#define MULTIBOOT_CONSOLE_COLS 80
|
||||
|
||||
|
||||
#define MULTIBOOT_STACK_SIZE 4096
|
||||
#define MULTIBOOT_PARAM_BUF_SIZE 1024
|
||||
|
||||
/* Flags to be set in the ’flags’ member of the multiboot info structure. */
|
||||
|
||||
#define MULTIBOOT_INFO_MEMORY 0x00000001
|
||||
|
||||
/* Is there a boot device set? */
|
||||
#define MULTIBOOT_INFO_BOOTDEV 0x00000002
|
||||
|
||||
/* Is the command-line defined? */
|
||||
#define MULTIBOOT_INFO_CMDLINE 0x00000004
|
||||
|
||||
/* Are there modules to do something with? */
|
||||
#define MULTIBOOT_INFO_MODS 0x00000008
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#include <minix/types.h>
|
||||
/* The symbol table for a.out. */
|
||||
struct multiboot_aout_symbol_table
|
||||
{
|
||||
u32_t tabsize;
|
||||
u32_t strsize;
|
||||
u32_t addr;
|
||||
u32_t reserved;
|
||||
};
|
||||
/* The section header table for ELF. */
|
||||
struct multiboot_elf_section_header_table
|
||||
{
|
||||
u32_t num;
|
||||
u32_t size;
|
||||
u32_t addr;
|
||||
u32_t shndx;
|
||||
};
|
||||
|
||||
typedef struct multiboot_elf_section_header_table multiboot_elf_section_header_table_t;
|
||||
typedef struct multiboot_aout_symbol_table multiboot_aout_symbol_table_t;
|
||||
|
||||
struct multiboot_info
|
||||
{
|
||||
/* Multiboot info version number */
|
||||
u32_t flags;
|
||||
/* Available memory from BIOS */
|
||||
u32_t mem_lower;
|
||||
u32_t mem_upper;
|
||||
/* "root" partition */
|
||||
u32_t boot_device;
|
||||
/* Kernel command line */
|
||||
u32_t cmdline;
|
||||
/* Boot-Module list */
|
||||
u32_t mods_count;
|
||||
u32_t mods_addr;
|
||||
union
|
||||
{
|
||||
multiboot_aout_symbol_table_t aout_sym;
|
||||
multiboot_elf_section_header_table_t elf_sec;
|
||||
} u;
|
||||
/* Memory Mapping buffer */
|
||||
u32_t mmap_length;
|
||||
u32_t mmap_addr;
|
||||
/* Drive Info buffer */
|
||||
u32_t drives_length;
|
||||
u32_t drives_addr;
|
||||
/* ROM configuration table */
|
||||
u32_t config_table;
|
||||
/* Boot Loader Name */
|
||||
u32_t boot_loader_name;
|
||||
/* APM table */
|
||||
u32_t apm_table;
|
||||
/* Video */
|
||||
u32_t vbe_control_info;
|
||||
u32_t vbe_mode_info;
|
||||
u16_t vbe_mode;
|
||||
u16_t vbe_interface_seg;
|
||||
u16_t vbe_interface_off;
|
||||
u16_t vbe_interface_len;
|
||||
};
|
||||
typedef struct multiboot_info multiboot_info_t;
|
||||
|
||||
struct multiboot_mod_list
|
||||
{
|
||||
/* Memory used goes from bytes 'mod_start' to 'mod_end-1' inclusive */
|
||||
u32_t mod_start;
|
||||
u32_t mod_end;
|
||||
/* Module command line */
|
||||
u32_t cmdline;
|
||||
/* Pad struct to 16 bytes (must be zero) */
|
||||
u32_t pad;
|
||||
};
|
||||
typedef struct multiboot_mod_list multiboot_module_t;
|
||||
|
||||
/* Buffer for multiboot parameters */
|
||||
extern char multiboot_param_buf[];
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __MULTIBOOT_H__ */
|
||||
@@ -1,3 +0,0 @@
|
||||
/* $NetBSD: mutex.h,v 1.2 2007/02/09 21:55:05 ad Exp $ */
|
||||
|
||||
#include <x86/mutex.h>
|
||||
@@ -1,26 +0,0 @@
|
||||
/* Description of entry in partition table. */
|
||||
#ifndef _PARTITION_H
|
||||
#define _PARTITION_H
|
||||
|
||||
struct part_entry {
|
||||
unsigned char bootind; /* boot indicator 0/ACTIVE_FLAG */
|
||||
unsigned char start_head; /* head value for first sector */
|
||||
unsigned char start_sec; /* sector value + cyl bits for first sector */
|
||||
unsigned char start_cyl; /* track value for first sector */
|
||||
unsigned char sysind; /* system indicator */
|
||||
unsigned char last_head; /* head value for last sector */
|
||||
unsigned char last_sec; /* sector value + cyl bits for last sector */
|
||||
unsigned char last_cyl; /* track value for last sector */
|
||||
unsigned long lowsec; /* logical first sector */
|
||||
unsigned long size; /* size of partition in sectors */
|
||||
};
|
||||
|
||||
#define ACTIVE_FLAG 0x80 /* value for active in bootind field (hd0) */
|
||||
#define NR_PARTITIONS 4 /* number of entries in partition table */
|
||||
#define PART_TABLE_OFF 0x1BE /* offset of partition table in boot sector */
|
||||
|
||||
/* Partition types. */
|
||||
#define NO_PART 0x00 /* unused entry */
|
||||
#define MINIX_PART 0x81 /* Minix partition type */
|
||||
|
||||
#endif /* _PARTITION_H */
|
||||
@@ -1,147 +0,0 @@
|
||||
/*
|
||||
pci.h
|
||||
|
||||
Created: Jan 2000 by Philip Homburg <philip@cs.vu.nl>
|
||||
*/
|
||||
|
||||
/* Header type 00, normal PCI devices */
|
||||
#define PCI_VID 0x00 /* Vendor ID, 16-bit */
|
||||
#define PCI_DID 0x02 /* Device ID, 16-bit */
|
||||
#define PCI_CR 0x04 /* Command Register, 16-bit */
|
||||
#define PCI_CR_MAST_EN 0x0004 /* Enable Busmaster Access */
|
||||
#define PCI_CR_MEM_EN 0x0002 /* Enable Mem Cycles */
|
||||
#define PCI_CR_IO_EN 0x0001 /* Enable I/O Cycles */
|
||||
#define PCI_SR 0x06 /* PCI status, 16-bit */
|
||||
#define PSR_SSE 0x4000 /* Signaled System Error */
|
||||
#define PSR_RMAS 0x2000 /* Received Master Abort Status */
|
||||
#define PSR_RTAS 0x1000 /* Received Target Abort Status */
|
||||
#define PSR_CAPPTR 0x0010 /* Capabilities list */
|
||||
#define PCI_REV 0x08 /* Revision ID */
|
||||
#define PCI_PIFR 0x09 /* Prog. Interface Register */
|
||||
#define PCI_SCR 0x0A /* Sub-Class Register */
|
||||
#define PCI_BCR 0x0B /* Base-Class Register */
|
||||
#define PCI_CLS 0x0C /* Cache Line Size */
|
||||
#define PCI_LT 0x0D /* Latency Timer */
|
||||
#define PCI_HEADT 0x0E /* Header type, 8-bit */
|
||||
#define PHT_MASK 0x7F /* Header type mask */
|
||||
#define PHT_NORMAL 0x00
|
||||
#define PHT_BRIDGE 0x01
|
||||
#define PHT_CARDBUS 0x02
|
||||
#define PHT_MULTIFUNC 0x80 /* Multiple functions */
|
||||
#define PCI_BIST 0x0F /* Built-in Self Test */
|
||||
#define PCI_BAR 0x10 /* Base Address Register */
|
||||
#define PCI_BAR_IO 0x00000001 /* Reg. refers to I/O space */
|
||||
#define PCI_BAR_TYPE 0x00000006 /* Memory BAR type */
|
||||
#define PCI_TYPE_32 0x00000000 /* 32-bit BAR */
|
||||
#define PCI_TYPE_32_1M 0x00000002 /* 32-bit below 1MB (legacy) */
|
||||
#define PCI_TYPE_64 0x00000004 /* 64-bit BAR */
|
||||
#define PCI_BAR_PREFETCH 0x00000008 /* Memory is prefetchable */
|
||||
#define PCI_BAR_IO_MASK 0xFFFFFFFC /* I/O address mask */
|
||||
#define PCI_BAR_MEM_MASK 0xFFFFFFF0 /* Memory address mask */
|
||||
#define PCI_BAR_2 0x14 /* Base Address Register */
|
||||
#define PCI_BAR_3 0x18 /* Base Address Register */
|
||||
#define PCI_BAR_4 0x1C /* Base Address Register */
|
||||
#define PCI_BAR_5 0x20 /* Base Address Register */
|
||||
#define PCI_BAR_6 0x24 /* Base Address Register */
|
||||
#define PCI_CBCISPTR 0x28 /* Cardbus CIS Pointer */
|
||||
#define PCI_SUBVID 0x2C /* Subsystem Vendor ID */
|
||||
#define PCI_SUBDID 0x2E /* Subsystem Device ID */
|
||||
#define PCI_EXPROM 0x30 /* Expansion ROM Base Address */
|
||||
#define PCI_CAPPTR 0x34 /* Capabilities Pointer */
|
||||
#define PCI_CP_MASK 0xfc /* Lower 2 bits should be ignored */
|
||||
#define PCI_ILR 0x3C /* Interrupt Line Register */
|
||||
#define PCI_ILR_UNKNOWN 0xFF /* IRQ is unassigned or unknown */
|
||||
#define PCI_IPR 0x3D /* Interrupt Pin Register */
|
||||
#define PCI_MINGNT 0x3E /* Min Grant */
|
||||
#define PCI_MAXLAT 0x3F /* Max Latency */
|
||||
|
||||
/* Header type 01, PCI-to-PCI bridge devices */
|
||||
/* The following registers are in common with type 00:
|
||||
* PCI_VID, PCI_DID, PCI_CR, PCI_SR, PCI_REV, PCI_PIFR, PCI_SCR, PCI_BCR,
|
||||
* PCI_CLS, PCI_LT, PCI_HEADT, PCI_BIST, PCI_BAR, PCI_BAR2, PCI_CAPPTR,
|
||||
* PCI_ILR, PCI_IPR.
|
||||
*/
|
||||
#define PPB_PRIMBN 0x18 /* Primary Bus Number */
|
||||
#define PPB_SECBN 0x19 /* Secondary Bus Number */
|
||||
#define PPB_SUBORDBN 0x1A /* Subordinate Bus Number */
|
||||
#define PPB_SECBLT 0x1B /* Secondary Bus Latency Timer */
|
||||
#define PPB_IOBASE 0x1C /* I/O Base */
|
||||
#define PPB_IOB_MASK 0xf0
|
||||
#define PPB_IOLIMIT 0x1D /* I/O Limit */
|
||||
#define PPB_IOL_MASK 0xf0
|
||||
#define PPB_SSTS 0x1E /* Secondary Status Register */
|
||||
#define PPB_MEMBASE 0x20 /* Memory Base */
|
||||
#define PPB_MEMB_MASK 0xfff0
|
||||
#define PPB_MEMLIMIT 0x22 /* Memory Limit */
|
||||
#define PPB_MEML_MASK 0xfff0
|
||||
#define PPB_PFMEMBASE 0x24 /* Prefetchable Memory Base */
|
||||
#define PPB_PFMEMB_MASK 0xfff0
|
||||
#define PPB_PFMEMLIMIT 0x26 /* Prefetchable Memory Limit */
|
||||
#define PPB_PFMEML_MASK 0xfff0
|
||||
#define PPB_PFMBU32 0x28 /* Prefetchable Memory Base Upper 32 */
|
||||
#define PPB_PFMLU32 0x2C /* Prefetchable Memory Limit Upper 32 */
|
||||
#define PPB_IOBASEU16 0x30 /* I/O Base Upper 16 */
|
||||
#define PPB_IOLIMITU16 0x32 /* I/O Limit Upper 16 */
|
||||
#define PPB_EXPROM 0x38 /* Expansion ROM Base Address */
|
||||
#define PPB_BRIDGECTRL 0x3E /* Bridge Control */
|
||||
#define PPB_BC_CRST 0x40 /* Assert reset line */
|
||||
|
||||
/* Header type 02, Cardbus bridge devices */
|
||||
/* The following registers are in common with type 00:
|
||||
* PCI_VID, PCI_DID, PCI_CR, PCI_SR, PCI_REV, PCI_PIFR, PCI_SCR, PCI_BCR,
|
||||
* PCI_CLS, PCI_LT, PCI_HEADT, PCI_BIST, PCI_BAR, PCI_ILR, PCI_IPR.
|
||||
*/
|
||||
/* The following registers are in common with type 01:
|
||||
* PPB_PRIMBN, PPB_SECBN, PPB_SUBORDBN, PPB_SECBLT.
|
||||
*/
|
||||
#define CBB_CAPPTR 0x14 /* Capability Pointer */
|
||||
#define CBB_SSTS 0x16 /* Secondary Status Register */
|
||||
#define CBB_MEMBASE_0 0x1C /* Memory Base 0 */
|
||||
#define CBB_MEMLIMIT_0 0x20 /* Memory Limit 0 */
|
||||
#define CBB_MEML_MASK 0xfffff000
|
||||
#define CBB_MEMBASE_1 0x24 /* Memory Base 1 */
|
||||
#define CBB_MEMLIMIT_1 0x28 /* Memory Limit 1 */
|
||||
#define CBB_IOBASE_0 0x2C /* I/O Base 0 */
|
||||
#define CBB_IOLIMIT_0 0x30 /* I/O Limit 0 */
|
||||
#define CBB_IOL_MASK 0xfffffffc
|
||||
#define CBB_IOBASE_1 0x34 /* I/O Base 1 */
|
||||
#define CBB_IOLIMIT_1 0x38 /* I/O Limit 1 */
|
||||
#define CBB_BRIDGECTRL 0x3E /* Bridge Control */
|
||||
#define CBB_BC_INTEXCA 0x80 /* Interrupt are routed to ExCAs */
|
||||
#define CBB_BC_CRST 0x40 /* Assert reset line */
|
||||
|
||||
#define CAP_TYPE 0x00 /* Type field in capability */
|
||||
#define CAP_NEXT 0x01 /* Next field in capability */
|
||||
|
||||
#define PCI_BCR_MASS_STORAGE 0x01 /* Mass Storage class */
|
||||
#define PCI_MS_IDE 0x01 /* IDE storage class */
|
||||
#define PCI_IDE_PRI_NATIVE 0x01 /* Primary channel is
|
||||
* in native mode.
|
||||
*/
|
||||
#define PCI_IDE_SEC_NATIVE 0x04 /* Secondary channel is
|
||||
* in native mode.
|
||||
*/
|
||||
|
||||
/* Device type values as ([PCI_BCR] << 16) | ([PCI_SCR] << 8) | [PCI_PIFR] */
|
||||
#define PCI_T3_VGA_OLD 0x000100 /* OLD VGA class code */
|
||||
#define PCI_T3_RAID 0x010400 /* RAID controller */
|
||||
#define PCI_T3_AHCI 0x010601 /* AHCI controller */
|
||||
#define PCI_T3_VGA 0x030000 /* VGA-compatible video card */
|
||||
#define PCI_T3_ISA 0x060100 /* ISA bridge */
|
||||
#define PCI_T3_PCI2PCI 0x060400 /* PCI-to-PCI Bridge device */
|
||||
#define PCI_T3_PCI2PCI_SUBTR 0x060401 /* Subtr. PCI-to-PCI Bridge */
|
||||
#define PCI_T3_CARDBUS 0x060700 /* Bardbus Bridge */
|
||||
|
||||
#define NO_VID 0xffff /* No PCI card present */
|
||||
|
||||
/* Capabilities */
|
||||
#define CAP_T_SECURE_DEV 0x0f /* (AMD) Secure device
|
||||
* capability
|
||||
*/
|
||||
#define CAP_SD_INFO 2 /* Offset from CAP ptr */
|
||||
#define CAP_SD_SUBTYPE_MASK 0x0f /* Mask for subtype */
|
||||
#define CAP_T_SD_DEV 0 /* AMD DEV */
|
||||
|
||||
/*
|
||||
* $PchId: pci.h,v 1.4 2001/12/06 20:21:22 philip Exp $
|
||||
*/
|
||||
@@ -1,21 +0,0 @@
|
||||
/*
|
||||
pci_amd.h
|
||||
|
||||
Created: Nov 2001 by Philip Homburg <philip@cs.vu.nl>
|
||||
*/
|
||||
|
||||
#define AMD_ISABR_FUNC 3 /* Registers are in function 3 */
|
||||
#define AMD_ISABR_PCIIRQ_LEV 0x54
|
||||
#define AMD_PCILEV_INTA 0x1
|
||||
#define AMD_PCILEV_INTB 0x2
|
||||
#define AMD_PCILEV_INTC 4x2
|
||||
#define AMD_PCILEV_INTD 4x8
|
||||
#define AMD_ISABR_PCIIRQ_ROUTE 0x56
|
||||
#define AMD_PCIIRQ_INTA_MASK 0x000F
|
||||
#define AMD_PCIIRQ_INTB_MASK 0x00F0
|
||||
#define AMD_PCIIRQ_INTC_MASK 0x0F00
|
||||
#define AMD_PCIIRQ_INTD_MASK 0xF000
|
||||
|
||||
/*
|
||||
* $PchId: pci_amd.h,v 1.1 2001/11/09 19:57:37 philip Exp $
|
||||
*/
|
||||
@@ -1,58 +0,0 @@
|
||||
/*
|
||||
pci_intel.h
|
||||
|
||||
Created: Jan 2000 by Philip Homburg <philip@cs.vu.nl>
|
||||
*/
|
||||
|
||||
#define PCII_CONFADD 0xCF8
|
||||
#define PCIIC_CODE 0x80000000
|
||||
#define PCIIC_BUSNUM_MASK 0xff0000
|
||||
#define PCIIC_BUSNUM_SHIFT 16
|
||||
#define PCIIC_DEVNUM_MASK 0xf800
|
||||
#define PCIIC_DEVNUM_SHIFT 11
|
||||
#define PCIIC_FUNCNUM_MASK 0x700
|
||||
#define PCIIC_FUNCNUM_SHIFT 8
|
||||
#define PCIIC_REGNUM_MASK 0xfc
|
||||
#define PCIIC_REGNUM_SHIFT 2
|
||||
#define PCII_CONFDATA 0xCFC
|
||||
|
||||
#define PCII_SELREG_(bus, dev, func, reg) \
|
||||
(PCIIC_CODE | \
|
||||
(((bus) << PCIIC_BUSNUM_SHIFT) & PCIIC_BUSNUM_MASK) | \
|
||||
(((dev) << PCIIC_DEVNUM_SHIFT) & PCIIC_DEVNUM_MASK) | \
|
||||
(((func) << PCIIC_FUNCNUM_SHIFT) & PCIIC_FUNCNUM_MASK) | \
|
||||
((((reg)/4) << PCIIC_REGNUM_SHIFT) & PCIIC_REGNUM_MASK))
|
||||
#define PCII_UNSEL (0)
|
||||
|
||||
#define PCII_RREG8_(bus, dev, func, reg) \
|
||||
(pci_outl(PCII_CONFADD, PCII_SELREG_(bus, dev, func, reg)), \
|
||||
pci_inb(PCII_CONFDATA+((reg)&3)))
|
||||
#define PCII_RREG16_(bus, dev, func, reg) \
|
||||
(pci_outl(PCII_CONFADD, PCII_SELREG_(bus, dev, func, reg)), \
|
||||
pci_inw(PCII_CONFDATA+((reg)&2)))
|
||||
#define PCII_RREG32_(bus, dev, func, reg) \
|
||||
(pci_outl(PCII_CONFADD, PCII_SELREG_(bus, dev, func, reg)), \
|
||||
pci_inl(PCII_CONFDATA))
|
||||
|
||||
#define PCII_WREG8_(bus, dev, func, reg, val) \
|
||||
(pci_outl(PCII_CONFADD, PCII_SELREG_(bus, dev, func, reg)), \
|
||||
pci_outb(PCII_CONFDATA+((reg)&3), (val)))
|
||||
#define PCII_WREG16_(bus, dev, func, reg, val) \
|
||||
(pci_outl(PCII_CONFADD, PCII_SELREG_(bus, dev, func, reg)), \
|
||||
pci_outw(PCII_CONFDATA+((reg)&2), (val)))
|
||||
#define PCII_WREG32_(bus, dev, func, reg, val) \
|
||||
(pci_outl(PCII_CONFADD, PCII_SELREG_(bus, dev, func, reg)), \
|
||||
pci_outl(PCII_CONFDATA, (val)))
|
||||
|
||||
/* PIIX configuration registers */
|
||||
#define PIIX_PIRQRCA 0x60
|
||||
#define PIIX_IRQ_DI 0x80
|
||||
#define PIIX_IRQ_MASK 0x0F
|
||||
|
||||
/* PIIX extensions to the PIC */
|
||||
#define PIIX_ELCR1 0x4D0
|
||||
#define PIIX_ELCR2 0x4D1
|
||||
|
||||
/*
|
||||
* $PchId: pci_intel.h,v 1.1 2000/08/12 11:20:17 philip Exp $
|
||||
*/
|
||||
@@ -1,17 +0,0 @@
|
||||
/*
|
||||
pci_sis.h
|
||||
|
||||
Created: Nov 2001 by Philip Homburg <philip@cs.vu.nl>
|
||||
*/
|
||||
|
||||
/* Constants are taken from pci-irq.c in the Linux kernel source */
|
||||
#define SIS_ISABR_IRQ_A 0x41 /* IRQA routing */
|
||||
#define SIS_ISABR_IRQ_B 0x42 /* IRQB routing */
|
||||
#define SIS_ISABR_IRQ_C 0x43 /* IRQC routing */
|
||||
#define SIS_ISABR_IRQ_D 0x44 /* IRQD routing */
|
||||
#define SIS_IRQ_DISABLED 0x80
|
||||
#define SIS_IRQ_MASK 0x0F
|
||||
|
||||
/*
|
||||
* $PchId: pci_sis.h,v 1.1 2001/12/06 20:22:52 philip Exp $
|
||||
*/
|
||||
@@ -1,27 +0,0 @@
|
||||
/*
|
||||
pci_via.h
|
||||
|
||||
Created: Jun 2001 by Philip Homburg <philip@cs.vu.nl>
|
||||
*/
|
||||
|
||||
#define VIA_ISABR_EL 0x54 /* Edge or level triggered */
|
||||
#define VIA_ISABR_EL_INTA 0x08 /* Edge (1) or level (0) */
|
||||
#define VIA_ISABR_EL_INTB 0x04
|
||||
#define VIA_ISABR_EL_INTC 0x02
|
||||
#define VIA_ISABR_EL_INTD 0x01
|
||||
|
||||
#define VIA_ISABR_IRQ_R1 0x55 /* IRQ routing 1 */
|
||||
#define VIA_ISABR_IRQ_INTD 0xf0 /* routing for INTD */
|
||||
#define VIA_ISABR_IRQ_INT0 0x0f /* routing for INT0 */
|
||||
#define VIA_ISABR_IRQ_R2 0x56 /* IRQ routing 2 */
|
||||
#define VIA_ISABR_IRQ_INTA 0xf0 /* routing for INTA */
|
||||
#define VIA_ISABR_IRQ_INTB 0x0f /* routing for INTB */
|
||||
#define VIA_ISABR_IRQ_R3 0x57 /* IRQ routing 3 */
|
||||
#define VIA_ISABR_IRQ_INTC 0xf0 /* routing for INTC */
|
||||
#define VIA_ISABR_IRQ_INT1 0x0f /* routing for INT1 */
|
||||
#define VIA_ISABR_IRQ_R4 0x58 /* IRQ routing 4 */
|
||||
#define VIA_ISABR_IRQ_INT2 0x0f /* routing for INT2 */
|
||||
|
||||
/*
|
||||
* $PchId: pci_via.h,v 1.1 2001/06/20 15:50:25 philip Exp $
|
||||
*/
|
||||
@@ -1,17 +0,0 @@
|
||||
/* Addresses and magic numbers for miscellaneous ports. */
|
||||
|
||||
#ifndef _PORTS_H
|
||||
#define _PORTS_H
|
||||
|
||||
#if (CHIP == INTEL)
|
||||
|
||||
/* Miscellaneous ports. */
|
||||
#define PCR 0x65 /* Planar Control Register */
|
||||
#define PORT_B 0x61 /* I/O port for 8255 port B (kbd, beeper...) */
|
||||
#define TIMER0 0x40 /* I/O port for timer channel 0 */
|
||||
#define TIMER2 0x42 /* I/O port for timer channel 2 */
|
||||
#define TIMER_MODE 0x43 /* I/O port for timer mode control */
|
||||
|
||||
#endif /* (CHIP == INTEL) */
|
||||
|
||||
#endif /* _PORTS_H */
|
||||
@@ -1,36 +0,0 @@
|
||||
#ifndef STACK_FRAME_H
|
||||
#define STACK_FRAME_H
|
||||
|
||||
typedef unsigned reg_t; /* machine register */
|
||||
typedef reg_t segdesc_t;
|
||||
|
||||
/* The stack frame layout is determined by the software, but for efficiency
|
||||
* it is laid out so the assembly code to use it is as simple as possible.
|
||||
* 80286 protected mode and all real modes use the same frame, built with
|
||||
* 16-bit registers. Real mode lacks an automatic stack switch, so little
|
||||
* is lost by using the 286 frame for it. The 386 frame differs only in
|
||||
* having 32-bit registers and more segment registers. The same names are
|
||||
* used for the larger registers to avoid differences in the code.
|
||||
*/
|
||||
struct stackframe_s {
|
||||
u16_t gs; /* last item pushed by save */
|
||||
u16_t fs; /* ^ */
|
||||
u16_t es; /* | */
|
||||
u16_t ds; /* | */
|
||||
reg_t di; /* di through cx are not accessed in C */
|
||||
reg_t si; /* order is to match pusha/popa */
|
||||
reg_t fp; /* bp */
|
||||
reg_t st; /* hole for another copy of sp */
|
||||
reg_t bx; /* | */
|
||||
reg_t dx; /* | */
|
||||
reg_t cx; /* | */
|
||||
reg_t retreg; /* ax and above are all pushed by save */
|
||||
reg_t retadr; /* return address for assembly code save() */
|
||||
reg_t pc; /* ^ last item pushed by interrupt */
|
||||
reg_t cs; /* | */
|
||||
reg_t psw; /* | */
|
||||
reg_t sp; /* | */
|
||||
reg_t ss; /* these are pushed by CPU during interrupt */
|
||||
};
|
||||
|
||||
#endif /* #ifndef STACK_FRAME_H */
|
||||
@@ -1,98 +0,0 @@
|
||||
#ifndef __SYS_VM_386_H__
|
||||
#define __SYS_VM_386_H__
|
||||
/*
|
||||
i386/vm.h
|
||||
*/
|
||||
|
||||
#define I386_PAGE_SIZE 4096
|
||||
#define I386_BIG_PAGE_SIZE (I386_PAGE_SIZE*I386_VM_PT_ENTRIES)
|
||||
|
||||
/* i386 paging constants */
|
||||
#define I386_VM_PRESENT 0x001 /* Page is present */
|
||||
#define I386_VM_WRITE 0x002 /* Read/write access allowed */
|
||||
#define I386_VM_USER 0x004 /* User access allowed */
|
||||
#define I386_VM_PWT 0x008 /* Write through */
|
||||
#define I386_VM_PCD 0x010 /* Cache disable */
|
||||
#define I386_VM_ACC 0x020 /* Accessed */
|
||||
#define I386_VM_ADDR_MASK 0xFFFFF000 /* physical address */
|
||||
#define I386_VM_ADDR_MASK_4MB 0xFFC00000 /* physical address */
|
||||
#define I386_VM_OFFSET_MASK_4MB 0x003FFFFF /* physical address */
|
||||
|
||||
/* Page directory specific flags. */
|
||||
#define I386_VM_BIGPAGE 0x080 /* 4MB page */
|
||||
|
||||
/* Page table specific flags. */
|
||||
#define I386_VM_DIRTY (1L<< 6) /* Dirty */
|
||||
#define I386_VM_PS (1L<< 7) /* Page size. */
|
||||
#define I386_VM_GLOBAL (1L<< 8) /* Global. */
|
||||
#define I386_VM_PTAVAIL1 (1L<< 9) /* Available for use. */
|
||||
#define I386_VM_PTAVAIL2 (1L<<10) /* Available for use. */
|
||||
#define I386_VM_PTAVAIL3 (1L<<11) /* Available for use. */
|
||||
|
||||
#define I386_VM_PT_ENT_SIZE 4 /* Size of a page table entry */
|
||||
#define I386_VM_DIR_ENTRIES 1024 /* Number of entries in a page dir */
|
||||
#define I386_VM_DIR_ENT_SHIFT 22 /* Shift to get entry in page dir. */
|
||||
#define I386_VM_PT_ENT_SHIFT 12 /* Shift to get entry in page table */
|
||||
#define I386_VM_PT_ENT_MASK 0x3FF /* Mask to get entry in page table */
|
||||
#define I386_VM_PT_ENTRIES 1024 /* Number of entries in a page table */
|
||||
#define I386_VM_PFA_SHIFT 22 /* Page frame address shift */
|
||||
|
||||
/* CR0 bits */
|
||||
#define I386_CR0_PE 0x00000001 /* Protected mode */
|
||||
#define I386_CR0_MP 0x00000002 /* Monitor Coprocessor */
|
||||
#define I386_CR0_EM 0x00000004 /* Emulate */
|
||||
#define I386_CR0_TS 0x00000008 /* Task Switched */
|
||||
#define I386_CR0_ET 0x00000010 /* Extension Type */
|
||||
#define I386_CR0_WP 0x00010000 /* Enable paging */
|
||||
#define I386_CR0_PG 0x80000000 /* Enable paging */
|
||||
|
||||
/* some CR4 bits */
|
||||
#define I386_CR4_VME 0x00000001 /* Virtual 8086 */
|
||||
#define I386_CR4_PVI 0x00000002 /* Virtual ints */
|
||||
#define I386_CR4_TSD 0x00000004 /* RDTSC privileged */
|
||||
#define I386_CR4_DE 0x00000008 /* Debugging extensions */
|
||||
#define I386_CR4_PSE 0x00000010 /* Page size extensions */
|
||||
#define I386_CR4_PAE 0x00000020 /* Physical addr extens. */
|
||||
#define I386_CR4_MCE 0x00000040 /* Machine check enable */
|
||||
#define I386_CR4_PGE 0x00000080 /* Global page flag enable */
|
||||
|
||||
/* i386 paging 'functions' */
|
||||
#define I386_VM_PTE(v) (((v) >> I386_VM_PT_ENT_SHIFT) & I386_VM_PT_ENT_MASK)
|
||||
#define I386_VM_PDE(v) ( (v) >> I386_VM_DIR_ENT_SHIFT)
|
||||
#define I386_VM_PFA(e) ( (e) & I386_VM_ADDR_MASK)
|
||||
#define I386_VM_PAGE(v) ( (v) >> I386_VM_PFA_SHIFT)
|
||||
|
||||
/* i386 pagefault error code bits */
|
||||
#define I386_VM_PFE_P 0x01 /* Pagefault caused by non-present page.
|
||||
* (otherwise protection violation.)
|
||||
*/
|
||||
#define I386_VM_PFE_W 0x02 /* Caused by write (otherwise read) */
|
||||
#define I386_VM_PFE_U 0x04 /* CPU in user mode (otherwise supervisor) */
|
||||
|
||||
/* CPUID flags */
|
||||
#define CPUID1_EDX_FPU (1L) /* FPU presence */
|
||||
#define CPUID1_EDX_PSE (1L << 3) /* Page Size Extension */
|
||||
#define CPUID1_EDX_PGE (1L << 13) /* Page Global (bit) Enable */
|
||||
#define CPUID1_EDX_APIC_ON_CHIP (1L << 9) /* APIC is present on the chip */
|
||||
#define CPUID1_EDX_TSC (1L << 4) /* Timestamp counter present */
|
||||
#define CPUID1_EDX_HTT (1L << 28) /* Supports HTT */
|
||||
#define CPUID1_EDX_FXSR (1L << 24)
|
||||
#define CPUID1_EDX_SSE (1L << 25)
|
||||
#define CPUID1_EDX_SSE2 (1L << 26)
|
||||
#define CPUID1_ECX_SSE3 (1L)
|
||||
#define CPUID1_ECX_SSSE3 (1L << 9)
|
||||
#define CPUID1_ECX_SSE4_1 (1L << 19)
|
||||
#define CPUID1_ECX_SSE4_2 (1L << 20)
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#include <minix/type.h>
|
||||
|
||||
/* structure used by VM to pass data to the kernel while enabling paging */
|
||||
struct vm_ep_data {
|
||||
struct mem_map * mem_map;
|
||||
vir_bytes data_seg_limit;
|
||||
};
|
||||
#endif
|
||||
|
||||
#endif /* __SYS_VM_386_H__ */
|
||||
Reference in New Issue
Block a user