From 2124b5f5a14d0d3b2d87f5df56a9c81b7a0396b1 Mon Sep 17 00:00:00 2001 From: Kelvin Lawson Date: Tue, 16 Feb 2010 23:07:48 +0000 Subject: [PATCH] Add STM8 port (Cosmic compiler). Modify timer4 automated test now that timer API has changed to take ticks as parameter. --- ports/stm8/Doxyfile | 1161 +++++++++++ ports/stm8/Makefile | 103 + ports/stm8/atomport-asm.s | 353 ++++ ports/stm8/atomport-private.h | 39 + ports/stm8/atomport-tests.h | 50 + ports/stm8/atomport.c | 259 +++ ports/stm8/atomport.h | 59 + ports/stm8/atomthreads.lkf | 63 + ports/stm8/stm8_interrupt_vector.c | 60 + ports/stm8/stm8s-periphs/stm8s.h | 2567 +++++++++++++++++++++++++ ports/stm8/stm8s-periphs/stm8s_clk.h | 404 ++++ ports/stm8/stm8s-periphs/stm8s_gpio.c | 242 +++ ports/stm8/stm8s-periphs/stm8s_gpio.h | 149 ++ ports/stm8/stm8s-periphs/stm8s_itc.c | 316 +++ ports/stm8/stm8s-periphs/stm8s_itc.h | 168 ++ ports/stm8/stm8s-periphs/stm8s_tim1.c | 2330 ++++++++++++++++++++++ ports/stm8/stm8s-periphs/stm8s_tim1.h | 565 ++++++ ports/stm8/stm8s-periphs/stm8s_type.h | 103 + ports/stm8/stm8s_conf.h | 259 +++ ports/stm8/tests-main.c | 215 +++ 20 files changed, 9465 insertions(+) create mode 100644 ports/stm8/Doxyfile create mode 100644 ports/stm8/Makefile create mode 100644 ports/stm8/atomport-asm.s create mode 100644 ports/stm8/atomport-private.h create mode 100644 ports/stm8/atomport-tests.h create mode 100644 ports/stm8/atomport.c create mode 100644 ports/stm8/atomport.h create mode 100644 ports/stm8/atomthreads.lkf create mode 100644 ports/stm8/stm8_interrupt_vector.c create mode 100644 ports/stm8/stm8s-periphs/stm8s.h create mode 100644 ports/stm8/stm8s-periphs/stm8s_clk.h create mode 100644 ports/stm8/stm8s-periphs/stm8s_gpio.c create mode 100644 ports/stm8/stm8s-periphs/stm8s_gpio.h create mode 100644 ports/stm8/stm8s-periphs/stm8s_itc.c create mode 100644 ports/stm8/stm8s-periphs/stm8s_itc.h create mode 100644 ports/stm8/stm8s-periphs/stm8s_tim1.c create mode 100644 ports/stm8/stm8s-periphs/stm8s_tim1.h create mode 100644 ports/stm8/stm8s-periphs/stm8s_type.h create mode 100644 ports/stm8/stm8s_conf.h create mode 100644 ports/stm8/tests-main.c diff --git a/ports/stm8/Doxyfile b/ports/stm8/Doxyfile new file mode 100644 index 0000000..c810a82 --- /dev/null +++ b/ports/stm8/Doxyfile @@ -0,0 +1,1161 @@ +# Doxyfile 1.3.9.1 + +# This file describes the settings to be used by the documentation system +# doxygen (www.doxygen.org) for a project +# +# All text after a hash (#) is considered a comment and will be ignored +# The format is: +# TAG = value [value, ...] +# For lists items can also be appended using: +# TAG += value [value, ...] +# Values that contain spaces should be placed between quotes (" ") + +#--------------------------------------------------------------------------- +# Project related configuration options +#--------------------------------------------------------------------------- + +# The PROJECT_NAME tag is a single word (or a sequence of words surrounded +# by quotes) that should identify the project. + +PROJECT_NAME = atomthreads + +# The PROJECT_NUMBER tag can be used to enter a project or revision number. +# This could be handy for archiving the generated documentation or +# if some version control system is used. + +PROJECT_NUMBER = + +# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) +# base path where the generated documentation will be put. +# If a relative path is entered, it will be relative to the location +# where doxygen was started. If left blank the current directory will be used. + +OUTPUT_DIRECTORY = doxygen-stm8 + +# If the CREATE_SUBDIRS tag is set to YES, then doxygen will create +# 4096 sub-directories (in 2 levels) under the output directory of each output +# format and will distribute the generated files over these directories. +# Enabling this option can be useful when feeding doxygen a huge amount of source +# files, where putting all generated files in the same directory would otherwise +# cause performance problems for the file system. + +CREATE_SUBDIRS = NO + +# The OUTPUT_LANGUAGE tag is used to specify the language in which all +# documentation generated by doxygen is written. Doxygen will use this +# information to generate all constant output in the proper language. +# The default language is English, other supported languages are: +# Brazilian, Catalan, Chinese, Chinese-Traditional, Croatian, Czech, Danish, +# Dutch, Finnish, French, German, Greek, Hungarian, Italian, Japanese, +# Japanese-en (Japanese with English messages), Korean, Korean-en, Norwegian, +# Polish, Portuguese, Romanian, Russian, Serbian, Slovak, Slovene, Spanish, +# Swedish, and Ukrainian. + +OUTPUT_LANGUAGE = English + +# This tag can be used to specify the encoding used in the generated output. +# The encoding is not always determined by the language that is chosen, +# but also whether or not the output is meant for Windows or non-Windows users. +# In case there is a difference, setting the USE_WINDOWS_ENCODING tag to YES +# forces the Windows encoding (this is the default for the Windows binary), +# whereas setting the tag to NO uses a Unix-style encoding (the default for +# all platforms other than Windows). + +USE_WINDOWS_ENCODING = NO + +# If the BRIEF_MEMBER_DESC tag is set to YES (the default) Doxygen will +# include brief member descriptions after the members that are listed in +# the file and class documentation (similar to JavaDoc). +# Set to NO to disable this. + +BRIEF_MEMBER_DESC = YES + +# If the REPEAT_BRIEF tag is set to YES (the default) Doxygen will prepend +# the brief description of a member or function before the detailed description. +# Note: if both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the +# brief descriptions will be completely suppressed. + +REPEAT_BRIEF = YES + +# This tag implements a quasi-intelligent brief description abbreviator +# that is used to form the text in various listings. Each string +# in this list, if found as the leading text of the brief description, will be +# stripped from the text and the result after processing the whole list, is used +# as the annotated text. Otherwise, the brief description is used as-is. If left +# blank, the following values are used ("$name" is automatically replaced with the +# name of the entity): "The $name class" "The $name widget" "The $name file" +# "is" "provides" "specifies" "contains" "represents" "a" "an" "the" + +ABBREVIATE_BRIEF = + +# If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then +# Doxygen will generate a detailed section even if there is only a brief +# description. + +ALWAYS_DETAILED_SEC = NO + +# If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all inherited +# members of a class in the documentation of that class as if those members were +# ordinary class members. Constructors, destructors and assignment operators of +# the base classes will not be shown. + +INLINE_INHERITED_MEMB = NO + +# If the FULL_PATH_NAMES tag is set to YES then Doxygen will prepend the full +# path before files name in the file list and in the header files. If set +# to NO the shortest path that makes the file name unique will be used. + +FULL_PATH_NAMES = YES + +# If the FULL_PATH_NAMES tag is set to YES then the STRIP_FROM_PATH tag +# can be used to strip a user-defined part of the path. Stripping is +# only done if one of the specified strings matches the left-hand part of +# the path. The tag can be used to show relative paths in the file list. +# If left blank the directory from which doxygen is run is used as the +# path to strip. + +STRIP_FROM_PATH = + +# The STRIP_FROM_INC_PATH tag can be used to strip a user-defined part of +# the path mentioned in the documentation of a class, which tells +# the reader which header file to include in order to use a class. +# If left blank only the name of the header file containing the class +# definition is used. Otherwise one should specify the include paths that +# are normally passed to the compiler using the -I flag. + +STRIP_FROM_INC_PATH = + +# If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter +# (but less readable) file names. This can be useful is your file systems +# doesn't support long names like on DOS, Mac, or CD-ROM. + +SHORT_NAMES = NO + +# If the JAVADOC_AUTOBRIEF tag is set to YES then Doxygen +# will interpret the first line (until the first dot) of a JavaDoc-style +# comment as the brief description. If set to NO, the JavaDoc +# comments will behave just like the Qt-style comments (thus requiring an +# explicit @brief command for a brief description. + +JAVADOC_AUTOBRIEF = NO + +# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make Doxygen +# treat a multi-line C++ special comment block (i.e. a block of //! or /// +# comments) as a brief description. This used to be the default behaviour. +# The new default is to treat a multi-line C++ comment block as a detailed +# description. Set this tag to YES if you prefer the old behaviour instead. + +MULTILINE_CPP_IS_BRIEF = NO + +# If the DETAILS_AT_TOP tag is set to YES then Doxygen +# will output the detailed description near the top, like JavaDoc. +# If set to NO, the detailed description appears after the member +# documentation. + +DETAILS_AT_TOP = NO + +# If the INHERIT_DOCS tag is set to YES (the default) then an undocumented +# member inherits the documentation from any documented member that it +# re-implements. + +INHERIT_DOCS = YES + +# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC +# tag is set to YES, then doxygen will reuse the documentation of the first +# member in the group (if any) for the other members of the group. By default +# all members of a group must be documented explicitly. + +DISTRIBUTE_GROUP_DOC = NO + +# The TAB_SIZE tag can be used to set the number of spaces in a tab. +# Doxygen uses this value to replace tabs by spaces in code fragments. + +TAB_SIZE = 4 + +# This tag can be used to specify a number of aliases that acts +# as commands in the documentation. An alias has the form "name=value". +# For example adding "sideeffect=\par Side Effects:\n" will allow you to +# put the command \sideeffect (or @sideeffect) in the documentation, which +# will result in a user-defined paragraph with heading "Side Effects:". +# You can put \n's in the value part of an alias to insert newlines. + +ALIASES = + +# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C sources +# only. Doxygen will then generate output that is more tailored for C. +# For instance, some of the names that are used will be different. The list +# of all members will be omitted, etc. + +OPTIMIZE_OUTPUT_FOR_C = YES + +# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java sources +# only. Doxygen will then generate output that is more tailored for Java. +# For instance, namespaces will be presented as packages, qualified scopes +# will look different, etc. + +OPTIMIZE_OUTPUT_JAVA = NO + +# Set the SUBGROUPING tag to YES (the default) to allow class member groups of +# the same type (for instance a group of public functions) to be put as a +# subgroup of that type (e.g. under the Public Functions section). Set it to +# NO to prevent subgrouping. Alternatively, this can be done per class using +# the \nosubgrouping command. + +SUBGROUPING = YES + +#--------------------------------------------------------------------------- +# Build related configuration options +#--------------------------------------------------------------------------- + +# If the EXTRACT_ALL tag is set to YES doxygen will assume all entities in +# documentation are documented, even if no documentation was available. +# Private class members and static file members will be hidden unless +# the EXTRACT_PRIVATE and EXTRACT_STATIC tags are set to YES + +EXTRACT_ALL = YES + +# If the EXTRACT_PRIVATE tag is set to YES all private members of a class +# will be included in the documentation. + +EXTRACT_PRIVATE = YES + +# If the EXTRACT_STATIC tag is set to YES all static members of a file +# will be included in the documentation. + +EXTRACT_STATIC = NO + +# If the EXTRACT_LOCAL_CLASSES tag is set to YES classes (and structs) +# defined locally in source files will be included in the documentation. +# If set to NO only classes defined in header files are included. + +EXTRACT_LOCAL_CLASSES = YES + +# This flag is only useful for Objective-C code. When set to YES local +# methods, which are defined in the implementation section but not in +# the interface are included in the documentation. +# If set to NO (the default) only methods in the interface are included. + +EXTRACT_LOCAL_METHODS = NO + +# If the HIDE_UNDOC_MEMBERS tag is set to YES, Doxygen will hide all +# undocumented members of documented classes, files or namespaces. +# If set to NO (the default) these members will be included in the +# various overviews, but no documentation section is generated. +# This option has no effect if EXTRACT_ALL is enabled. + +HIDE_UNDOC_MEMBERS = NO + +# If the HIDE_UNDOC_CLASSES tag is set to YES, Doxygen will hide all +# undocumented classes that are normally visible in the class hierarchy. +# If set to NO (the default) these classes will be included in the various +# overviews. This option has no effect if EXTRACT_ALL is enabled. + +HIDE_UNDOC_CLASSES = NO + +# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, Doxygen will hide all +# friend (class|struct|union) declarations. +# If set to NO (the default) these declarations will be included in the +# documentation. + +HIDE_FRIEND_COMPOUNDS = NO + +# If the HIDE_IN_BODY_DOCS tag is set to YES, Doxygen will hide any +# documentation blocks found inside the body of a function. +# If set to NO (the default) these blocks will be appended to the +# function's detailed documentation block. + +HIDE_IN_BODY_DOCS = NO + +# The INTERNAL_DOCS tag determines if documentation +# that is typed after a \internal command is included. If the tag is set +# to NO (the default) then the documentation will be excluded. +# Set it to YES to include the internal documentation. + +INTERNAL_DOCS = NO + +# If the CASE_SENSE_NAMES tag is set to NO then Doxygen will only generate +# file names in lower-case letters. If set to YES upper-case letters are also +# allowed. This is useful if you have classes or files whose names only differ +# in case and if your file system supports case sensitive file names. Windows +# and Mac users are advised to set this option to NO. + +CASE_SENSE_NAMES = YES + +# If the HIDE_SCOPE_NAMES tag is set to NO (the default) then Doxygen +# will show members with their full class and namespace scopes in the +# documentation. If set to YES the scope will be hidden. + +HIDE_SCOPE_NAMES = NO + +# If the SHOW_INCLUDE_FILES tag is set to YES (the default) then Doxygen +# will put a list of the files that are included by a file in the documentation +# of that file. + +SHOW_INCLUDE_FILES = YES + +# If the INLINE_INFO tag is set to YES (the default) then a tag [inline] +# is inserted in the documentation for inline members. + +INLINE_INFO = YES + +# If the SORT_MEMBER_DOCS tag is set to YES (the default) then doxygen +# will sort the (detailed) documentation of file and class members +# alphabetically by member name. If set to NO the members will appear in +# declaration order. + +SORT_MEMBER_DOCS = YES + +# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the +# brief documentation of file, namespace and class members alphabetically +# by member name. If set to NO (the default) the members will appear in +# declaration order. + +SORT_BRIEF_DOCS = NO + +# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be +# sorted by fully-qualified names, including namespaces. If set to +# NO (the default), the class list will be sorted only by class name, +# not including the namespace part. +# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES. +# Note: This option applies only to the class list, not to the +# alphabetical list. + +SORT_BY_SCOPE_NAME = NO + +# The GENERATE_TODOLIST tag can be used to enable (YES) or +# disable (NO) the todo list. This list is created by putting \todo +# commands in the documentation. + +GENERATE_TODOLIST = YES + +# The GENERATE_TESTLIST tag can be used to enable (YES) or +# disable (NO) the test list. This list is created by putting \test +# commands in the documentation. + +GENERATE_TESTLIST = YES + +# The GENERATE_BUGLIST tag can be used to enable (YES) or +# disable (NO) the bug list. This list is created by putting \bug +# commands in the documentation. + +GENERATE_BUGLIST = YES + +# The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or +# disable (NO) the deprecated list. This list is created by putting +# \deprecated commands in the documentation. + +GENERATE_DEPRECATEDLIST= YES + +# The ENABLED_SECTIONS tag can be used to enable conditional +# documentation sections, marked by \if sectionname ... \endif. + +ENABLED_SECTIONS = + +# The MAX_INITIALIZER_LINES tag determines the maximum number of lines +# the initial value of a variable or define consists of for it to appear in +# the documentation. If the initializer consists of more lines than specified +# here it will be hidden. Use a value of 0 to hide initializers completely. +# The appearance of the initializer of individual variables and defines in the +# documentation can be controlled using \showinitializer or \hideinitializer +# command in the documentation regardless of this setting. + +MAX_INITIALIZER_LINES = 30 + +# Set the SHOW_USED_FILES tag to NO to disable the list of files generated +# at the bottom of the documentation of classes and structs. If set to YES the +# list will mention the files that were used to generate the documentation. + +SHOW_USED_FILES = YES + +# If the sources in your project are distributed over multiple directories +# then setting the SHOW_DIRECTORIES tag to YES will show the directory hierarchy +# in the documentation. + +SHOW_DIRECTORIES = YES + +#--------------------------------------------------------------------------- +# configuration options related to warning and progress messages +#--------------------------------------------------------------------------- + +# The QUIET tag can be used to turn on/off the messages that are generated +# by doxygen. Possible values are YES and NO. If left blank NO is used. + +QUIET = NO + +# The WARNINGS tag can be used to turn on/off the warning messages that are +# generated by doxygen. Possible values are YES and NO. If left blank +# NO is used. + +WARNINGS = YES + +# If WARN_IF_UNDOCUMENTED is set to YES, then doxygen will generate warnings +# for undocumented members. If EXTRACT_ALL is set to YES then this flag will +# automatically be disabled. + +WARN_IF_UNDOCUMENTED = YES + +# If WARN_IF_DOC_ERROR is set to YES, doxygen will generate warnings for +# potential errors in the documentation, such as not documenting some +# parameters in a documented function, or documenting parameters that +# don't exist or using markup commands wrongly. + +WARN_IF_DOC_ERROR = YES + +# The WARN_FORMAT tag determines the format of the warning messages that +# doxygen can produce. The string should contain the $file, $line, and $text +# tags, which will be replaced by the file and line number from which the +# warning originated and the warning text. + +WARN_FORMAT = "$file:$line: $text" + +# The WARN_LOGFILE tag can be used to specify a file to which warning +# and error messages should be written. If left blank the output is written +# to stderr. + +WARN_LOGFILE = + +#--------------------------------------------------------------------------- +# configuration options related to the input files +#--------------------------------------------------------------------------- + +# The INPUT tag can be used to specify the files and/or directories that contain +# documented source files. You may enter file names like "myfile.cpp" or +# directories like "/usr/src/myproject". Separate the files or directories +# with spaces. + +INPUT = + +# If the value of the INPUT tag contains directories, you can use the +# FILE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp +# and *.h) to filter out the source-files in the directories. If left +# blank the following patterns are tested: +# *.c *.cc *.cxx *.cpp *.c++ *.java *.ii *.ixx *.ipp *.i++ *.inl *.h *.hh *.hxx *.hpp +# *.h++ *.idl *.odl *.cs *.php *.php3 *.inc *.m *.mm + +FILE_PATTERNS = + +# The RECURSIVE tag can be used to turn specify whether or not subdirectories +# should be searched for input files as well. Possible values are YES and NO. +# If left blank NO is used. + +RECURSIVE = NO + +# The EXCLUDE tag can be used to specify files and/or directories that should +# excluded from the INPUT source files. This way you can easily exclude a +# subdirectory from a directory tree whose root is specified with the INPUT tag. + +EXCLUDE = + +# The EXCLUDE_SYMLINKS tag can be used select whether or not files or directories +# that are symbolic links (a Unix filesystem feature) are excluded from the input. + +EXCLUDE_SYMLINKS = NO + +# If the value of the INPUT tag contains directories, you can use the +# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude +# certain files from those directories. + +EXCLUDE_PATTERNS = + +# The EXAMPLE_PATH tag can be used to specify one or more files or +# directories that contain example code fragments that are included (see +# the \include command). + +EXAMPLE_PATH = + +# If the value of the EXAMPLE_PATH tag contains directories, you can use the +# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp +# and *.h) to filter out the source-files in the directories. If left +# blank all files are included. + +EXAMPLE_PATTERNS = + +# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be +# searched for input files to be used with the \include or \dontinclude +# commands irrespective of the value of the RECURSIVE tag. +# Possible values are YES and NO. If left blank NO is used. + +EXAMPLE_RECURSIVE = NO + +# The IMAGE_PATH tag can be used to specify one or more files or +# directories that contain image that are included in the documentation (see +# the \image command). + +IMAGE_PATH = + +# The INPUT_FILTER tag can be used to specify a program that doxygen should +# invoke to filter for each input file. Doxygen will invoke the filter program +# by executing (via popen()) the command , where +# is the value of the INPUT_FILTER tag, and is the name of an +# input file. Doxygen will then use the output that the filter program writes +# to standard output. If FILTER_PATTERNS is specified, this tag will be +# ignored. + +INPUT_FILTER = + +# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern +# basis. Doxygen will compare the file name with each pattern and apply the +# filter if there is a match. The filters are a list of the form: +# pattern=filter (like *.cpp=my_cpp_filter). See INPUT_FILTER for further +# info on how filters are used. If FILTER_PATTERNS is empty, INPUT_FILTER +# is applied to all files. + +FILTER_PATTERNS = + +# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using +# INPUT_FILTER) will be used to filter the input files when producing source +# files to browse (i.e. when SOURCE_BROWSER is set to YES). + +FILTER_SOURCE_FILES = NO + +#--------------------------------------------------------------------------- +# configuration options related to source browsing +#--------------------------------------------------------------------------- + +# If the SOURCE_BROWSER tag is set to YES then a list of source files will +# be generated. Documented entities will be cross-referenced with these sources. +# Note: To get rid of all source code in the generated output, make sure also +# VERBATIM_HEADERS is set to NO. + +SOURCE_BROWSER = NO + +# Setting the INLINE_SOURCES tag to YES will include the body +# of functions and classes directly in the documentation. + +INLINE_SOURCES = NO + +# Setting the STRIP_CODE_COMMENTS tag to YES (the default) will instruct +# doxygen to hide any special comment blocks from generated source code +# fragments. Normal C and C++ comments will always remain visible. + +STRIP_CODE_COMMENTS = YES + +# If the REFERENCED_BY_RELATION tag is set to YES (the default) +# then for each documented function all documented +# functions referencing it will be listed. + +REFERENCED_BY_RELATION = YES + +# If the REFERENCES_RELATION tag is set to YES (the default) +# then for each documented function all documented entities +# called/used by that function will be listed. + +REFERENCES_RELATION = YES + +# If the VERBATIM_HEADERS tag is set to YES (the default) then Doxygen +# will generate a verbatim copy of the header file for each class for +# which an include is specified. Set to NO to disable this. + +VERBATIM_HEADERS = YES + +#--------------------------------------------------------------------------- +# configuration options related to the alphabetical class index +#--------------------------------------------------------------------------- + +# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index +# of all compounds will be generated. Enable this if the project +# contains a lot of classes, structs, unions or interfaces. + +ALPHABETICAL_INDEX = NO + +# If the alphabetical index is enabled (see ALPHABETICAL_INDEX) then +# the COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns +# in which this list will be split (can be a number in the range [1..20]) + +COLS_IN_ALPHA_INDEX = 5 + +# In case all classes in a project start with a common prefix, all +# classes will be put under the same header in the alphabetical index. +# The IGNORE_PREFIX tag can be used to specify one or more prefixes that +# should be ignored while generating the index headers. + +IGNORE_PREFIX = + +#--------------------------------------------------------------------------- +# configuration options related to the HTML output +#--------------------------------------------------------------------------- + +# If the GENERATE_HTML tag is set to YES (the default) Doxygen will +# generate HTML output. + +GENERATE_HTML = YES + +# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. +# If a relative path is entered the value of OUTPUT_DIRECTORY will be +# put in front of it. If left blank `html' will be used as the default path. + +HTML_OUTPUT = html + +# The HTML_FILE_EXTENSION tag can be used to specify the file extension for +# each generated HTML page (for example: .htm,.php,.asp). If it is left blank +# doxygen will generate files with .html extension. + +HTML_FILE_EXTENSION = .html + +# The HTML_HEADER tag can be used to specify a personal HTML header for +# each generated HTML page. If it is left blank doxygen will generate a +# standard header. + +HTML_HEADER = + +# The HTML_FOOTER tag can be used to specify a personal HTML footer for +# each generated HTML page. If it is left blank doxygen will generate a +# standard footer. + +HTML_FOOTER = + +# The HTML_STYLESHEET tag can be used to specify a user-defined cascading +# style sheet that is used by each HTML page. It can be used to +# fine-tune the look of the HTML output. If the tag is left blank doxygen +# will generate a default style sheet. Note that doxygen will try to copy +# the style sheet file to the HTML output directory, so don't put your own +# stylesheet in the HTML output directory as well, or it will be erased! + +HTML_STYLESHEET = + +# If the HTML_ALIGN_MEMBERS tag is set to YES, the members of classes, +# files or namespaces will be aligned in HTML using tables. If set to +# NO a bullet list will be used. + +HTML_ALIGN_MEMBERS = YES + +# If the GENERATE_HTMLHELP tag is set to YES, additional index files +# will be generated that can be used as input for tools like the +# Microsoft HTML help workshop to generate a compressed HTML help file (.chm) +# of the generated HTML documentation. + +GENERATE_HTMLHELP = NO + +# If the GENERATE_HTMLHELP tag is set to YES, the CHM_FILE tag can +# be used to specify the file name of the resulting .chm file. You +# can add a path in front of the file if the result should not be +# written to the html output directory. + +CHM_FILE = + +# If the GENERATE_HTMLHELP tag is set to YES, the HHC_LOCATION tag can +# be used to specify the location (absolute path including file name) of +# the HTML help compiler (hhc.exe). If non-empty doxygen will try to run +# the HTML help compiler on the generated index.hhp. + +HHC_LOCATION = + +# If the GENERATE_HTMLHELP tag is set to YES, the GENERATE_CHI flag +# controls if a separate .chi index file is generated (YES) or that +# it should be included in the master .chm file (NO). + +GENERATE_CHI = NO + +# If the GENERATE_HTMLHELP tag is set to YES, the BINARY_TOC flag +# controls whether a binary table of contents is generated (YES) or a +# normal table of contents (NO) in the .chm file. + +BINARY_TOC = NO + +# The TOC_EXPAND flag can be set to YES to add extra items for group members +# to the contents of the HTML help documentation and to the tree view. + +TOC_EXPAND = NO + +# The DISABLE_INDEX tag can be used to turn on/off the condensed index at +# top of each HTML page. The value NO (the default) enables the index and +# the value YES disables it. + +DISABLE_INDEX = NO + +# This tag can be used to set the number of enum values (range [1..20]) +# that doxygen will group on one line in the generated HTML documentation. + +ENUM_VALUES_PER_LINE = 4 + +# If the GENERATE_TREEVIEW tag is set to YES, a side panel will be +# generated containing a tree-like index structure (just like the one that +# is generated for HTML Help). For this to work a browser that supports +# JavaScript, DHTML, CSS and frames is required (for instance Mozilla 1.0+, +# Netscape 6.0+, Internet explorer 5.0+, or Konqueror). Windows users are +# probably better off using the HTML help feature. + +GENERATE_TREEVIEW = NO + +# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be +# used to set the initial width (in pixels) of the frame in which the tree +# is shown. + +TREEVIEW_WIDTH = 250 + +#--------------------------------------------------------------------------- +# configuration options related to the LaTeX output +#--------------------------------------------------------------------------- + +# If the GENERATE_LATEX tag is set to YES (the default) Doxygen will +# generate Latex output. + +GENERATE_LATEX = NO + +# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put. +# If a relative path is entered the value of OUTPUT_DIRECTORY will be +# put in front of it. If left blank `latex' will be used as the default path. + +LATEX_OUTPUT = latex + +# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be +# invoked. If left blank `latex' will be used as the default command name. + +LATEX_CMD_NAME = latex + +# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to +# generate index for LaTeX. If left blank `makeindex' will be used as the +# default command name. + +MAKEINDEX_CMD_NAME = makeindex + +# If the COMPACT_LATEX tag is set to YES Doxygen generates more compact +# LaTeX documents. This may be useful for small projects and may help to +# save some trees in general. + +COMPACT_LATEX = NO + +# The PAPER_TYPE tag can be used to set the paper type that is used +# by the printer. Possible values are: a4, a4wide, letter, legal and +# executive. If left blank a4wide will be used. + +PAPER_TYPE = a4wide + +# The EXTRA_PACKAGES tag can be to specify one or more names of LaTeX +# packages that should be included in the LaTeX output. + +EXTRA_PACKAGES = + +# The LATEX_HEADER tag can be used to specify a personal LaTeX header for +# the generated latex document. The header should contain everything until +# the first chapter. If it is left blank doxygen will generate a +# standard header. Notice: only use this tag if you know what you are doing! + +LATEX_HEADER = + +# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated +# is prepared for conversion to pdf (using ps2pdf). The pdf file will +# contain links (just like the HTML output) instead of page references +# This makes the output suitable for online browsing using a pdf viewer. + +PDF_HYPERLINKS = NO + +# If the USE_PDFLATEX tag is set to YES, pdflatex will be used instead of +# plain latex in the generated Makefile. Set this option to YES to get a +# higher quality PDF documentation. + +USE_PDFLATEX = NO + +# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\batchmode. +# command to the generated LaTeX files. This will instruct LaTeX to keep +# running if errors occur, instead of asking the user for help. +# This option is also used when generating formulas in HTML. + +LATEX_BATCHMODE = NO + +# If LATEX_HIDE_INDICES is set to YES then doxygen will not +# include the index chapters (such as File Index, Compound Index, etc.) +# in the output. + +LATEX_HIDE_INDICES = NO + +#--------------------------------------------------------------------------- +# configuration options related to the RTF output +#--------------------------------------------------------------------------- + +# If the GENERATE_RTF tag is set to YES Doxygen will generate RTF output +# The RTF output is optimized for Word 97 and may not look very pretty with +# other RTF readers or editors. + +GENERATE_RTF = NO + +# The RTF_OUTPUT tag is used to specify where the RTF docs will be put. +# If a relative path is entered the value of OUTPUT_DIRECTORY will be +# put in front of it. If left blank `rtf' will be used as the default path. + +RTF_OUTPUT = rtf + +# If the COMPACT_RTF tag is set to YES Doxygen generates more compact +# RTF documents. This may be useful for small projects and may help to +# save some trees in general. + +COMPACT_RTF = NO + +# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated +# will contain hyperlink fields. The RTF file will +# contain links (just like the HTML output) instead of page references. +# This makes the output suitable for online browsing using WORD or other +# programs which support those fields. +# Note: wordpad (write) and others do not support links. + +RTF_HYPERLINKS = NO + +# Load stylesheet definitions from file. Syntax is similar to doxygen's +# config file, i.e. a series of assignments. You only have to provide +# replacements, missing definitions are set to their default value. + +RTF_STYLESHEET_FILE = + +# Set optional variables used in the generation of an rtf document. +# Syntax is similar to doxygen's config file. + +RTF_EXTENSIONS_FILE = + +#--------------------------------------------------------------------------- +# configuration options related to the man page output +#--------------------------------------------------------------------------- + +# If the GENERATE_MAN tag is set to YES (the default) Doxygen will +# generate man pages + +GENERATE_MAN = NO + +# The MAN_OUTPUT tag is used to specify where the man pages will be put. +# If a relative path is entered the value of OUTPUT_DIRECTORY will be +# put in front of it. If left blank `man' will be used as the default path. + +MAN_OUTPUT = man + +# The MAN_EXTENSION tag determines the extension that is added to +# the generated man pages (default is the subroutine's section .3) + +MAN_EXTENSION = .3 + +# If the MAN_LINKS tag is set to YES and Doxygen generates man output, +# then it will generate one additional man file for each entity +# documented in the real man page(s). These additional files +# only source the real man page, but without them the man command +# would be unable to find the correct page. The default is NO. + +MAN_LINKS = NO + +#--------------------------------------------------------------------------- +# configuration options related to the XML output +#--------------------------------------------------------------------------- + +# If the GENERATE_XML tag is set to YES Doxygen will +# generate an XML file that captures the structure of +# the code including all documentation. + +GENERATE_XML = NO + +# The XML_OUTPUT tag is used to specify where the XML pages will be put. +# If a relative path is entered the value of OUTPUT_DIRECTORY will be +# put in front of it. If left blank `xml' will be used as the default path. + +XML_OUTPUT = xml + +# The XML_SCHEMA tag can be used to specify an XML schema, +# which can be used by a validating XML parser to check the +# syntax of the XML files. + +XML_SCHEMA = + +# The XML_DTD tag can be used to specify an XML DTD, +# which can be used by a validating XML parser to check the +# syntax of the XML files. + +XML_DTD = + +# If the XML_PROGRAMLISTING tag is set to YES Doxygen will +# dump the program listings (including syntax highlighting +# and cross-referencing information) to the XML output. Note that +# enabling this will significantly increase the size of the XML output. + +XML_PROGRAMLISTING = YES + +#--------------------------------------------------------------------------- +# configuration options for the AutoGen Definitions output +#--------------------------------------------------------------------------- + +# If the GENERATE_AUTOGEN_DEF tag is set to YES Doxygen will +# generate an AutoGen Definitions (see autogen.sf.net) file +# that captures the structure of the code including all +# documentation. Note that this feature is still experimental +# and incomplete at the moment. + +GENERATE_AUTOGEN_DEF = NO + +#--------------------------------------------------------------------------- +# configuration options related to the Perl module output +#--------------------------------------------------------------------------- + +# If the GENERATE_PERLMOD tag is set to YES Doxygen will +# generate a Perl module file that captures the structure of +# the code including all documentation. Note that this +# feature is still experimental and incomplete at the +# moment. + +GENERATE_PERLMOD = NO + +# If the PERLMOD_LATEX tag is set to YES Doxygen will generate +# the necessary Makefile rules, Perl scripts and LaTeX code to be able +# to generate PDF and DVI output from the Perl module output. + +PERLMOD_LATEX = NO + +# If the PERLMOD_PRETTY tag is set to YES the Perl module output will be +# nicely formatted so it can be parsed by a human reader. This is useful +# if you want to understand what is going on. On the other hand, if this +# tag is set to NO the size of the Perl module output will be much smaller +# and Perl will parse it just the same. + +PERLMOD_PRETTY = YES + +# The names of the make variables in the generated doxyrules.make file +# are prefixed with the string contained in PERLMOD_MAKEVAR_PREFIX. +# This is useful so different doxyrules.make files included by the same +# Makefile don't overwrite each other's variables. + +PERLMOD_MAKEVAR_PREFIX = + +#--------------------------------------------------------------------------- +# Configuration options related to the preprocessor +#--------------------------------------------------------------------------- + +# If the ENABLE_PREPROCESSING tag is set to YES (the default) Doxygen will +# evaluate all C-preprocessor directives found in the sources and include +# files. + +ENABLE_PREPROCESSING = YES + +# If the MACRO_EXPANSION tag is set to YES Doxygen will expand all macro +# names in the source code. If set to NO (the default) only conditional +# compilation will be performed. Macro expansion can be done in a controlled +# way by setting EXPAND_ONLY_PREDEF to YES. + +MACRO_EXPANSION = NO + +# If the EXPAND_ONLY_PREDEF and MACRO_EXPANSION tags are both set to YES +# then the macro expansion is limited to the macros specified with the +# PREDEFINED and EXPAND_AS_PREDEFINED tags. + +EXPAND_ONLY_PREDEF = NO + +# If the SEARCH_INCLUDES tag is set to YES (the default) the includes files +# in the INCLUDE_PATH (see below) will be search if a #include is found. + +SEARCH_INCLUDES = YES + +# The INCLUDE_PATH tag can be used to specify one or more directories that +# contain include files that are not input files but should be processed by +# the preprocessor. + +INCLUDE_PATH = + +# You can use the INCLUDE_FILE_PATTERNS tag to specify one or more wildcard +# patterns (like *.h and *.hpp) to filter out the header-files in the +# directories. If left blank, the patterns specified with FILE_PATTERNS will +# be used. + +INCLUDE_FILE_PATTERNS = + +# The PREDEFINED tag can be used to specify one or more macro names that +# are defined before the preprocessor is started (similar to the -D option of +# gcc). The argument of the tag is a list of macros of the form: name +# or name=definition (no spaces). If the definition and the = are +# omitted =1 is assumed. To prevent a macro definition from being +# undefined via #undef or recursively expanded use the := operator +# instead of the = operator. + +PREDEFINED = + +# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then +# this tag can be used to specify a list of macro names that should be expanded. +# The macro definition that is found in the sources will be used. +# Use the PREDEFINED tag if you want to use a different macro definition. + +EXPAND_AS_DEFINED = + +# If the SKIP_FUNCTION_MACROS tag is set to YES (the default) then +# doxygen's preprocessor will remove all function-like macros that are alone +# on a line, have an all uppercase name, and do not end with a semicolon. Such +# function macros are typically used for boiler-plate code, and will confuse the +# parser if not removed. + +SKIP_FUNCTION_MACROS = YES + +#--------------------------------------------------------------------------- +# Configuration::additions related to external references +#--------------------------------------------------------------------------- + +# The TAGFILES option can be used to specify one or more tagfiles. +# Optionally an initial location of the external documentation +# can be added for each tagfile. The format of a tag file without +# this location is as follows: +# TAGFILES = file1 file2 ... +# Adding location for the tag files is done as follows: +# TAGFILES = file1=loc1 "file2 = loc2" ... +# where "loc1" and "loc2" can be relative or absolute paths or +# URLs. If a location is present for each tag, the installdox tool +# does not have to be run to correct the links. +# Note that each tag file must have a unique name +# (where the name does NOT include the path) +# If a tag file is not located in the directory in which doxygen +# is run, you must also specify the path to the tagfile here. + +TAGFILES = + +# When a file name is specified after GENERATE_TAGFILE, doxygen will create +# a tag file that is based on the input files it reads. + +GENERATE_TAGFILE = + +# If the ALLEXTERNALS tag is set to YES all external classes will be listed +# in the class index. If set to NO only the inherited external classes +# will be listed. + +ALLEXTERNALS = NO + +# If the EXTERNAL_GROUPS tag is set to YES all external groups will be listed +# in the modules index. If set to NO, only the current project's groups will +# be listed. + +EXTERNAL_GROUPS = YES + +# The PERL_PATH should be the absolute path and name of the perl script +# interpreter (i.e. the result of `which perl'). + +PERL_PATH = /usr/bin/perl + +#--------------------------------------------------------------------------- +# Configuration options related to the dot tool +#--------------------------------------------------------------------------- + +# If the CLASS_DIAGRAMS tag is set to YES (the default) Doxygen will +# generate a inheritance diagram (in HTML, RTF and LaTeX) for classes with base or +# super classes. Setting the tag to NO turns the diagrams off. Note that this +# option is superseded by the HAVE_DOT option below. This is only a fallback. It is +# recommended to install and use dot, since it yields more powerful graphs. + +CLASS_DIAGRAMS = YES + +# If set to YES, the inheritance and collaboration graphs will hide +# inheritance and usage relations if the target is undocumented +# or is not a class. + +HIDE_UNDOC_RELATIONS = YES + +# If you set the HAVE_DOT tag to YES then doxygen will assume the dot tool is +# available from the path. This tool is part of Graphviz, a graph visualization +# toolkit from AT&T and Lucent Bell Labs. The other options in this section +# have no effect if this option is set to NO (the default) + +HAVE_DOT = NO + +# If the CLASS_GRAPH and HAVE_DOT tags are set to YES then doxygen +# will generate a graph for each documented class showing the direct and +# indirect inheritance relations. Setting this tag to YES will force the +# the CLASS_DIAGRAMS tag to NO. + +CLASS_GRAPH = YES + +# If the COLLABORATION_GRAPH and HAVE_DOT tags are set to YES then doxygen +# will generate a graph for each documented class showing the direct and +# indirect implementation dependencies (inheritance, containment, and +# class references variables) of the class with other documented classes. + +COLLABORATION_GRAPH = YES + +# If the UML_LOOK tag is set to YES doxygen will generate inheritance and +# collaboration diagrams in a style similar to the OMG's Unified Modeling +# Language. + +UML_LOOK = NO + +# If set to YES, the inheritance and collaboration graphs will show the +# relations between templates and their instances. + +TEMPLATE_RELATIONS = NO + +# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDE_GRAPH, and HAVE_DOT +# tags are set to YES then doxygen will generate a graph for each documented +# file showing the direct and indirect include dependencies of the file with +# other documented files. + +INCLUDE_GRAPH = YES + +# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDED_BY_GRAPH, and +# HAVE_DOT tags are set to YES then doxygen will generate a graph for each +# documented header file showing the documented files that directly or +# indirectly include this file. + +INCLUDED_BY_GRAPH = YES + +# If the CALL_GRAPH and HAVE_DOT tags are set to YES then doxygen will +# generate a call dependency graph for every global function or class method. +# Note that enabling this option will significantly increase the time of a run. +# So in most cases it will be better to enable call graphs for selected +# functions only using the \callgraph command. + +CALL_GRAPH = NO + +# If the GRAPHICAL_HIERARCHY and HAVE_DOT tags are set to YES then doxygen +# will graphical hierarchy of all classes instead of a textual one. + +GRAPHICAL_HIERARCHY = YES + +# The DOT_IMAGE_FORMAT tag can be used to set the image format of the images +# generated by dot. Possible values are png, jpg, or gif +# If left blank png will be used. + +DOT_IMAGE_FORMAT = png + +# The tag DOT_PATH can be used to specify the path where the dot tool can be +# found. If left blank, it is assumed the dot tool can be found on the path. + +DOT_PATH = + +# The DOTFILE_DIRS tag can be used to specify one or more directories that +# contain dot files that are included in the documentation (see the +# \dotfile command). + +DOTFILE_DIRS = + +# The MAX_DOT_GRAPH_WIDTH tag can be used to set the maximum allowed width +# (in pixels) of the graphs generated by dot. If a graph becomes larger than +# this value, doxygen will try to truncate the graph, so that it fits within +# the specified constraint. Beware that most browsers cannot cope with very +# large images. + +MAX_DOT_GRAPH_WIDTH = 1024 + +# The MAX_DOT_GRAPH_HEIGHT tag can be used to set the maximum allows height +# (in pixels) of the graphs generated by dot. If a graph becomes larger than +# this value, doxygen will try to truncate the graph, so that it fits within +# the specified constraint. Beware that most browsers cannot cope with very +# large images. + +MAX_DOT_GRAPH_HEIGHT = 1024 + +# The MAX_DOT_GRAPH_DEPTH tag can be used to set the maximum depth of the +# graphs generated by dot. A depth value of 3 means that only nodes reachable +# from the root by following a path via at most 3 edges will be shown. Nodes that +# lay further from the root node will be omitted. Note that setting this option to +# 1 or 2 may greatly reduce the computation time needed for large code bases. Also +# note that a graph may be further truncated if the graph's image dimensions are +# not sufficient to fit the graph (see MAX_DOT_GRAPH_WIDTH and MAX_DOT_GRAPH_HEIGHT). +# If 0 is used for the depth value (the default), the graph is not depth-constrained. + +MAX_DOT_GRAPH_DEPTH = 0 + +# If the GENERATE_LEGEND tag is set to YES (the default) Doxygen will +# generate a legend page explaining the meaning of the various boxes and +# arrows in the dot generated graphs. + +GENERATE_LEGEND = YES + +# If the DOT_CLEANUP tag is set to YES (the default) Doxygen will +# remove the intermediate dot files that are used to generate +# the various graphs. + +DOT_CLEANUP = YES + +#--------------------------------------------------------------------------- +# Configuration::additions related to the search engine +#--------------------------------------------------------------------------- + +# The SEARCHENGINE tag specifies whether or not a search engine should be +# used. If set to NO the values of all tags below this one will be ignored. + +SEARCHENGINE = NO diff --git a/ports/stm8/Makefile b/ports/stm8/Makefile new file mode 100644 index 0000000..5552b5f --- /dev/null +++ b/ports/stm8/Makefile @@ -0,0 +1,103 @@ +############ +# Settings # +############ + +# Build all test applications: +# make + +# Location of build tools and atomthreads sources +KERNEL_DIR=../../kernel +TESTS_DIR=../../tests +PERIPHS_DIR=stm8s-periphs +LIBS_DIR="C:\Program Files\COSMIC\CXSTM8_16K\Lib" +CC=cxstm8 +ASM=castm8 +LINK=clnk +CHEX=chex + +# Directory for built objects +BUILD_DIR=build + +# Port/application object files +APP_OBJECTS = atomport.o tests-main.o stm8_interrupt_vector.o +APP_ASM_OBJECTS = atomport-asm.o + +# STM8S Peripheral driver object files +PERIPH_OBJECTS = stm8s_gpio.o stm8s_tim1.o + +# Kernel object files +KERNEL_OBJECTS = atomkernel.o atomsem.o atommutex.o atomtimer.o atomqueue.o + +# Collection of built objects (excluding test applications) +ALL_OBJECTS = $(APP_OBJECTS) $(APP_ASM_OBJECTS) $(PERIPH_OBJECTS) $(KERNEL_OBJECTS) +BUILT_OBJECTS = $(patsubst %,$(BUILD_DIR)/%,$(ALL_OBJECTS)) + +# Test object files (dealt with separately as only one per application build) +TEST_OBJECTS = $(notdir $(patsubst %.c,%.o,$(wildcard $(TESTS_DIR)/*.c))) + +# Target application filenames (.elf and .hex) for each test object +TEST_STM8S = $(patsubst %.o,%.stm8,$(TEST_OBJECTS)) +TEST_S19S = $(patsubst %.o,%.s19,$(TEST_OBJECTS)) + +# Search build/output directory for dependencies +vpath %.o .\$(BUILD_DIR) +vpath %.elf .\$(BUILD_DIR) +vpath %.hex .\$(BUILD_DIR) + +# Compiler/Assembler flags +CFLAGS=+modsl0 -pp +DBG_CFLAGS=+modsl0 +debug -pxp -no -pp -l +ASMFLAGS= +DBG_ASMFLAGS=-xx -u + + +################# +# Build targets # +################# + +# All tests +all: $(BUILD_DIR) $(TEST_S19S) Makefile + +# Make build/output directory +$(BUILD_DIR): + mkdir $(BUILD_DIR) + +# Test HEX files (one application build for each test) +$(TEST_S19S): %.s19: %.stm8 + @echo Building $@ + $(CHEX) -fm -o $(BUILD_DIR)/$@ $(BUILD_DIR)/$< + +# Test ELF files (one application build for each test) +$(TEST_STM8S): %.stm8: %.o $(KERNEL_OBJECTS) $(PERIPH_OBJECTS) $(APP_OBJECTS) $(APP_ASM_OBJECTS) + $(LINK) -l$(LIBS_DIR) -o $(BUILD_DIR)/$@ atomthreads.lkf $(BUILD_DIR)/$(notdir $<) + +# Kernel objects builder +$(KERNEL_OBJECTS): %.o: $(KERNEL_DIR)/%.c + $(CC) $(CFLAGS) -i. -i$(PERIPHS_DIR) -co$(BUILD_DIR) $< + +# Test objects builder +$(TEST_OBJECTS): %.o: $(TESTS_DIR)/%.c + $(CC) $(CFLAGS) -i. -i$(KERNEL_DIR) -i$(PERIPHS_DIR) -co$(BUILD_DIR) $< + +# Kernel objects builder +$(PERIPH_OBJECTS): %.o: $(PERIPHS_DIR)/%.c + $(CC) $(CFLAGS) -i. -i$(PERIPHS_DIR) -co$(BUILD_DIR) $< + +# Application C objects builder +$(APP_OBJECTS): %.o: ./%.c + $(CC) $(CFLAGS) -i. -i$(KERNEL_DIR) -i$(TESTS_DIR) -i$(PERIPHS_DIR) -co$(BUILD_DIR) $< + +# Application asm objects builder +$(APP_ASM_OBJECTS): %.o: ./%.s + $(ASM) $(ASMFLAGS) -i. -i$(KERNEL_DIR) -o$(BUILD_DIR)/$(notdir $@) $< + +# Clean +clean: + rm -f *.o *.elf *.map *.hex *.bin *.lst *.stm8 *.s19 + rm -rf doxygen-kernel + rm -rf doxygen-stm8 + rm -rf build + +doxygen: + doxygen $(KERNEL_DIR)/Doxyfile + doxygen ./Doxyfile diff --git a/ports/stm8/atomport-asm.s b/ports/stm8/atomport-asm.s new file mode 100644 index 0000000..a29ac27 --- /dev/null +++ b/ports/stm8/atomport-asm.s @@ -0,0 +1,353 @@ +; +; Copyright (c) 2005, Atomthreads Project. All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; Modification, are permitted provided that the following conditions +; are met: +; +; 1. Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the distribution. +; 3. No personal names or organizations' names associated with the +; Atomthreads project may be used to endorse or promote products +; derived from this software without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS +; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +; TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +; PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE +; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +; POSSIBILITY OF SUCH DAMAGE. +; + + +; Export functions to other modules +xdef _archContextSwitch, _archFirstThreadRestore + + +; \b archContextSwitch +; +; Architecture-specific context switch routine. +; +; Note that interrupts are always locked out when this routine is +; called. For cooperative switches, the scheduler will have entered +; a critical region. For preemptions (called from an ISR), the +; ISR will have disabled interrupts on entry. +; +; @param[in] old_tcb_ptr Pointer to the thread being scheduled out +; @param[in] new_tcb_ptr Pointer to the thread being scheduled in +; +; @return None +; +; void archContextSwitch (ATOM_TCB *old_tcb_ptr, ATOM_TCB *new_tcb_ptr) +_archContextSwitch: + + ; Parameter locations: + ; old_tcb_ptr = X register (word-width) + ; new_tcb_ptr = stack (word-width) + + ; STM8 CPU Registers: + ; + ; A, X, Y: Standard working registers + ; SP: Stack pointer + ; PC: Program counter + ; CC: Code condition register + ; + ; + ; If this is a cooperative context switch (a thread has called us + ; to schedule itself out), the Cosmic compiler will have saved any + ; of the registers which it does not want us to clobber. There are + ; no registers which are expected to retain their value across a + ; function call, hence for cooperative context switches with this + ; compiler we do not actually need to save any registers at all. + ; + ; If we were called from an interrupt routine (because a thread + ; is being preemptively scheduled out), the situation is exactly + ; the same. Any ISR which calls out to a subroutine will have + ; similarly saved all registers which it needs us not to clobber + ; which in the case of this compiler is all registers. Again, we + ; do not need to save any registers because no registers are + ; expected to be unclobbered by a subroutine. + ; + ; This is an unusual context switch routine, because it does not + ; need to actually save any registers. Instead, the act of + ; calling this function causes all registers which must not be + ; clobbered to be saved on the stack anyway in the case of + ; cooperative context switches. For preemptive switches, the + ; interrupt service routine which calls out to here causes all + ; registers to be saved in a similar fashion. + + ; We do have to do some work in here though: we need to store + ; the current stack pointer to the current thread's TCB, and + ; switch in the new thread by taking the stack pointer from + ; the new thread's TCB and making that our new stack pointer. + + ; The parameter pointing to the the old TCB (a word-width + ; pointer) is still untouched in the X register. + + ; Store current stack pointer as first entry in old_tcb_ptr + ldw Y, SP ; Move current stack pointer into Y register + ldw (X), Y ; Store current stack pointer at first offset in TCB + + + ; At this point, all of the current thread's context has been saved + ; so we no longer care about keeping the contents of any registers. + ; We do still need the first two bytes on the current thread's stack, + ; however, which contain new_tcb_ptr (a pointer to the TCB of the + ; thread which we wish to switch in). + ; + ; Our stack frame now contains all registers (if this is a preemptive + ; switch due to an interrupt handler) or those registers which the + ; calling function did not wish to be clobbered (if this is a + ; cooperative context switch). It also contains the return address + ; which will be either a function called via an ISR (for preemptive + ; switches) or a function called from thread context (for cooperative + ; switches). Finally, the stack also contains the aforementioned + ; word which is the new_tcb_ptr parameter passed via the stack. + ; + ; In addition, the thread's stack pointer (after context-save) is + ; stored in the thread's TCB. + + ; We are now ready to restore the new thread's context. In most + ; architecture ports we would typically switch our stack pointer + ; to the new thread's stack pointer, and pop all of its context + ; off the stack, before returning to the caller (the original + ; caller when the new thread was last scheduled out). In this + ; port, however, we do not need to actually restore any + ; registers here because none are saved when we switch out (at + ; least not by this function). We switch to the new thread's + ; stack pointer and then return to the original caller, which + ; will restore any registers which had to be saved. + + ; Get the new thread's stack pointer off the TCB (new_tcb_ptr). + ; new_tcb_ptr is still stored in the previous thread's stack. + ; We are free to use any registers here. + + ; Pull the new_tcb_ptr parameter from the stack into X register + ldw X,($3,SP) + + ; Pull the first entry out of new_tcb_ptr (the new thread's + ; stack pointer) into X register. + ldw X,(X) + + ; Switch our current stack pointer to that of the new thread. + ldw SP,X + + ; Normally we would start restoring registers from the new + ; thread's stack here, but we don't save/restore any. We're + ; almost done. + + ; The return address on the stack will now be the new thread's return + ; address - i.e. although we just entered this function from a + ; function called by the old thread, now that we have restored the new + ; thread's stack, we actually return from this function to wherever + ; the new thread was when it was previously scheduled out. This could + ; be either a regular C routine if the new thread previously scheduled + ; itself out cooperatively, or it could be an ISR if this new thread was + ; previously preempted (on exiting the ISR, execution will return to + ; wherever the new thread was originally interrupted). + + ; Return to the caller. Note that we always use a regular RET here + ; because this is a subroutine regardless of whether we were called + ; during an ISR or by a thread cooperatively switching out. The + ; difference between RET and IRET on the STM8 architecture is that + ; RET only pops the return address off the stack, while IRET also + ; pops from the stack all of the CPU registers saved when the ISR + ; started, including restoring the interrupt-enable bits from the CC + ; register. + ; + ; It is important that whenever we call this function (whether from + ; an ISR for preemptive switches or from thread context for + ; cooperative switches) interrupts are always disabled. This means + ; that whichever method by which we leave this routine we always + ; have to reenable interrupts, so we can use the same context-switch + ; routine for preemptive and cooperative switches. + ; + ; The possible call/return paths are as follows: + ; + ; Scenario 1 (cooperative -> cooperative): + ; Thread A: cooperatively switches out + ; * Thread A relinquishes control / cooperatively switches out + ; * Interrupts already disabled by kernel for cooperative reschedules + ; * Partial register context saved by calling function + ; * Call here at thread context + ; * Switch to Thread B + ; Thread B (was previously cooperatively switched out): + ; * Stack context for Thread B contains its return address + ; * Return to function which was called at thread context + ; * Interrupts are reenabled by CRITICAL_END() call in kernel + ; * Return to Thread B application code + ; + ; Scenario 2 (preemptive -> preemptive): + ; Thread A: preemptively switches out + ; * ISR occurs + ; * Interrupts disabled by CPU at ISR entry (assume no nesting allowed) + ; * Full register context saved by CPU at ISR entry + ; * Call here at ISR context + ; * Switch to Thread B + ; Thread B (was previously preemptively switched out): + ; * Stack context for Thread B contains its return address + ; and all context saved by the CPU on ISR entry + ; * Return to function which was called at ISR context + ; * Eventually returns to calling ISR which calls IRET + ; * IRET performs full register context restore + ; * IRET reenables interrupts + ; * Return to Thread B application code + ; + ; Scenario 3 (cooperative -> preemptive): + ; Thread A: cooperatively switches out + ; * Thread A relinquishes control / cooperatively switches out + ; * Interrupts already disabled by kernel for cooperative reschedules + ; * Partial register context saved by calling function + ; * Call here at thread context + ; * Switch to Thread B + ; Thread B (was previously preemptively switched out): + ; * Stack context for Thread B contains its return address + ; and all context saved by the CPU on ISR entry + ; * Return to function which was called at ISR context + ; * Eventually returns to calling ISR which calls IRET + ; * IRET performs full register context restore + ; * IRET reenables interrupts + ; * Return to Thread B application code + ; + ; Scenario 4 (preemptive -> cooperative): + ; Thread A: preemptively switches out + ; * ISR occurs + ; * Interrupts disabled by CPU at ISR entry (assume no nesting allowed) + ; * Full register context saved by CPU at ISR entry + ; * Call here at ISR context + ; * Switch to Thread B + ; Thread B (was previously cooperatively switched out): + ; * Stack context for Thread B contains its return address + ; * Return to function which was called at thread context + ; * Interrupts are reenabled by CRITICAL_END() call in kernel + ; * Return to Thread B application code + ; + ; The above shows that it does not matter whether we are rescheduling + ; from/to thread context or ISR context. It is perfectly valid to + ; enter here at ISR context but leave via a thread which previously + ; cooperatively switched out because: + ; 1. Although the CPU handles ISRs differently by automatically + ; stacking all 6 CPU registers, and restoring them on an IRET, + ; we handle this because we switch the stack pointer to a + ; different thread's stack. Because the stack pointer is + ; switched, it does not matter that on entry via ISRs more + ; registers are saved on the original thread's stack than entries + ; via non-ISRs. Those extra registers will be restored properly + ; by an IRET when the thread is eventually scheduled back in + ; (which could be a long way off). This assumes that the CPU does + ; not have hidden behaviour that occurs on interrupts, and we can + ; in fact trick it into leaving via another thread's call stack, + ; and performing the IRET much later. + ; 2. Although the CPU handles ISRs differently by setting the CC + ; register interrupt-enable bits on entry/exit, we handle this + ; anyway by always assuming interrupts are disabled on entry + ; and exit regardless of the call path. + + ; Return from subroutine + ret + + +; \b archFirstThreadRestore +; +; Architecture-specific function to restore and start the first thread. +; This is called by atomOSStart() when the OS is starting. Its job is to +; restore the context for the first thread and start running at its +; entry point. +; +; All new threads have a stack context pre-initialised with suitable +; data for being restored by either this function or the normal +; function used for scheduling threads in, archContextSwitch(). Only +; the first thread run by the system is launched via this function, +; after which all other new threads will first be run by +; archContextSwitch(). +; +; Typically ports will implement something similar here to the +; latter half of archContextSwitch(). In this port the context +; switch does not restore many registers, and instead relies on the +; fact that returning from any function which called +; archContextSwitch() will restore any of the necessary registers. +; For new threads which have never been run there is no calling +; function which will restore context on return, therefore we +; do not restore many register values here. It is not necessary +; for the new threads to have initialised values for the scratch +; registers A, X and Y or the code condition register CC which +; leaves SP and PC. SP is restored because this is always needed to +; switch to a new thread's stack context. It is not necessary to +; restore PC, because the thread's entry point is in the stack +; context (when this function returns using RET the PC is +; automatically changed to the thread's entry point because the +; entry point is stored in the preinitialised stack). +; +; When new threads are started interrupts must be enabled, so there +; is some scope for enabling interrupts in the CC here. It must be +; done for all new threads, however, not just the first thread, so +; we use a different system. We instead use a thread shell routine +; which all functions run when they are first started, and +; interrupts are enabled in there. This allows us to avoid having +; to enable interrupts both in here and in the normal context +; switch routine (archContextSwitch()). For the normal context +; switch routine we would otherwise need to pass in notification of +; and implement special handling for the first time a thread is +; restored. +; +; In summary, first threads do not require a set of CPU registers +; to be initialised to known values, so we only set SP to the new +; thread's stack pointer. PC is restored for free because the RET +; call at the end of this function pops the return address off the +; stack. +; +; Note that you can create more than one thread before starting +; the OS - only one thread is restored using this function, so +; all other threads are actually restored by archContextSwitch(). +; This is another reminder that the initial context set up by +; archThreadContextInit() must look the same whether restored by +; archFirstThreadRestore() or archContextSwitch(). +; +; @param[in] new_tcb_ptr Pointer to the thread being scheduled in +; +; @return None +; +; void archFirstThreadRestore (ATOM_TCB *new_tcb_ptr) +_archFirstThreadRestore: + + ; Parameter locations: + ; new_tcb_ptr = X register (word-width) + + ; As described above, first thread restores in this port do not + ; expect any initial register context to be pre-initialised in + ; the thread's stack area. The thread's initial stack need only + ; contain the thread's initial entry point, and we do not even + ; "restore" that within this function. We leave the thread's entry + ; point in the stack, and RET at the end of the function pops it + ; off and "returns" to the entry point as if we were called from + ; there. + ; + ; The one thing we do need to set in here, though, is the thread's + ; stack pointer. This is available from the passed thread TCB + ; structure. + + ; Get the new thread's stack pointer off the TCB (new_tcb_ptr). + ; new_tcb_ptr is stored in the parameter register X. The stack + ; pointer it conveniently located at the top of the TCB so no + ; indexing is required to pull it out. + ldw X,(X) + + ; Switch our current stack pointer to that of the new thread. + ldw SP,X + + ; The "return address" left on the stack now will be the new + ; thread's entry point. RET will take us there as if we had + ; actually been there before calling this subroutine, whereas + ; the return address was actually set up by archThreadContextInit(). + ret + + + end \ No newline at end of file diff --git a/ports/stm8/atomport-private.h b/ports/stm8/atomport-private.h new file mode 100644 index 0000000..ec90536 --- /dev/null +++ b/ports/stm8/atomport-private.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2010, Kelvin Lawson. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. No personal names or organizations' names associated with the + * Atomthreads project may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __ATOM_PORT_PRIVATE_H +#define __ATOM_PORT_PRIVATE_H + + +/* Function prototypes */ +void archInitSystemTickTimer (void); +@far @interrupt void TIM1_SystemTickISR (void); + + +#endif /* __ATOM_PORT_PRIVATE_H */ diff --git a/ports/stm8/atomport-tests.h b/ports/stm8/atomport-tests.h new file mode 100644 index 0000000..5c0bf5f --- /dev/null +++ b/ports/stm8/atomport-tests.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2010, Kelvin Lawson. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. No personal names or organizations' names associated with the + * Atomthreads project may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __ATOM_PORT_TESTS_H +#define __ATOM_PORT_TESTS_H + +/* Include Atomthreads kernel API */ +#include "atom.h" + +/* Logger macro for viewing test results (UART not used on this platform) */ +#define ATOMLOG + +/* + * String location macro: for platforms which need to place strings in + * alternative locations. Not used on this platform. + */ +#define _STR + +/* Default thread stack size (in bytes) */ +#define TEST_THREAD_STACK_SIZE 196 + + +#endif /* __ATOM_PORT_TESTS_H */ + diff --git a/ports/stm8/atomport.c b/ports/stm8/atomport.c new file mode 100644 index 0000000..0c2898d --- /dev/null +++ b/ports/stm8/atomport.c @@ -0,0 +1,259 @@ +/* + * Copyright (c) 2010, Kelvin Lawson. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. No personal names or organizations' names associated with the + * Atomthreads project may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + + +#include "atom.h" +#include "atomport-private.h" +#include "stm8s_tim1.h" + + +/** Forward declarations */ +static void thread_shell (void); + + +/** + * \b thread_shell + * + * Shell routine which is used to call all thread entry points. + * + * This routine is called whenever a new thread is starting, and is + * responsible for taking the entry point parameter off the TCB + * and passing this into the thread entry point, as well as enabling + * interrupts. + * + * This is an optional function for a port, because interrupts could + * be enabled by the first-thread and normal context restore routines, + * but that would require special handling in the normal context + * switch routine (archContextSwitch()) that is only needed the first + * time a thread is started. A much neater method is to direct all + * threads through this shell routine first, so that interrupts will + * always be enabled at thread startup, and no special first-time-run + * handling is required in the context restore routines (i.e. we + * don't affect normal context switch times just for the benefit of + * the first time a thread is restored by adding extra complication + * to the thread restore routines). + * + * Other ports are free to implement whatever scheme they wish. In + * particular if you save all necessary registers (including the + * interrupt enable register) on a context switch then you need not + * worry about any special requirements for starting threads for the + * first time because you can preinitialise the stack context with + * a suitable register value that will enable interrupts. + * + * @return None + */ +static void thread_shell (void) +{ + ATOM_TCB *curr_tcb; + + /* Get the TCB of the thread being started */ + curr_tcb = atomCurrentContext(); + + /** + * Enable interrupts - these will not be enabled when a thread + * is first restored. + */ + _asm("rim"); + + /* Call the thread entry point */ + if (curr_tcb && curr_tcb->entry_point) + { + curr_tcb->entry_point(curr_tcb->entry_param); + } + + /* Not reached - threads should never return from the entry point */ + +} + + +/** + * \b archThreadContextInit + * + * Architecture-specific thread context initialisation routine. + * + * This function must set up a thread's context ready for restoring + * and running the thread via archFirstThreadRestore() or + * archContextSwitch(). + * + * On this port we take advantage of the fact that when the context + * switch routine is called the compiler will automatically stack + * all registers which should not be clobbered. This means that the + * context switch need only save and restore the stack pointer, + * which is stored in the thread's TCB. Because of this, it is not + * necessary to prefill a new thread's stack with any register + * values here. The only entry we need to make in the stack is the + * thread's entry point - this is not exactly restored when the + * the thread is context switched in, but rather is popped off the + * stack by the context switch routine's RET call. That is used to + * direct the program counter to our thread's entry point - we are + * faking a return to a caller which never actually existed. + * + * We could pre-initialise the stack so that the RET call goes + * directly to the thread entry point, with the thread entry + * parameter filled in. On this architecture, however, we use an + * outer thread shell routine which is used to call all threads. + * The thread entry point and parameter are stored in the thread's + * TCB which the thread shell uses to make the actual call to the + * entry point. We don't therefore need to store the actual thread + * entry and parameter within the stack. + * + * Note that interrupts must be enabled the first time a thread is + * run. On some architectures this might be done by setting an + * initial value for the interrupt-enable register within the stack + * area. In this port, however, we use the thread shell to enable + * interrupts at the start of any thread. + * + * @param[in] tcb_ptr Pointer to the TCB of the thread being created + * @param[in] stack_top Pointer to the top of the new thread's stack + * @param[in] entry_point Pointer to the thread entry point function + * @param[in] entry_param Parameter to be passed to the thread entry point + * + * @return None + */ +void archThreadContextInit (ATOM_TCB *tcb_ptr, void *stack_top, void (*entry_point)(uint32_t), uint32_t entry_param) +{ + uint8_t *stack_ptr; + + /** Start at stack top */ + stack_ptr = (uint8_t *)stack_top; + + /** + * The thread restore routines will perform a RET which expects to + * find the address of the calling routine on the stack. In this case + * (the first time a thread is run) we "return" to the entry point for + * the thread. That is, we store the thread entry point in the + * place that RET will look for the return address: the stack. + * + * Note that we are using the thread_shell() routine to start all + * threads, so we actually store the address of thread_shell() + * here. Other ports may store the real thread entry point here + * and call it directly from the thread restore routines. + * + * Because we are filling the stack from top to bottom, this goes + * on the stack first (at the top). + */ + *stack_ptr-- = (uint8_t)((uint16_t)thread_shell & 0xFF); + *stack_ptr-- = (uint8_t)(((uint16_t)thread_shell >> 8) & 0xFF); + + /** + * Because we are using a thread shell which is responsible for + * calling the real entry point, it also passes the parameters + * to entry point and we need not stack the entry parameter here. + * + * Other ports may wish to store entry_param in the appropriate + * parameter registers when creating a thread's context, + * particularly if that port saves those registers anyway. + */ + + /** + * In this port we do not initialise any registers via the initial + * stack context at all. All thread context has now been + * initialised. All that is left is to save the current stack + * pointer to the thread's TCB so that it knows where to start + * looking when the thread is started. + */ + tcb_ptr->sp_save_ptr = stack_ptr; + +} + + +/** + * \b archInitSystemTickTimer + * + * Initialise the system tick timer. Uses the STM8's TIM1 facility. + * + * @return None + */ +void archInitSystemTickTimer ( void ) +{ + /* Reset TIM1 */ + TIM1_DeInit(); + + /* Configure a 10ms tick */ + TIM1_TimeBaseInit(10000, TIM1_COUNTERMODE_UP, 1, 0); + + /* Generate an interrupt on timer count overflow */ + TIM1_ITConfig(TIM1_IT_UPDATE, ENABLE); + + /* Enable TIM1 */ + TIM1_Cmd(ENABLE); + +} + + +/** + * + * System tick ISR. + * + * This is responsible for regularly calling the OS system tick handler. + * The system tick handler checks if any timer callbacks are necessary, + * and runs the scheduler. + * + * The CPU automatically saves all registers before calling out to an + * interrupt handler like this. + * + * The system may decide to schedule in a new thread during the call to + * atomTimerTick(), in which case the program counter will be redirected + * to the new thread's running location during atomIntExit(). This ISR + * function will not actually complete until the thread we interrupted is + * scheduled back in, at which point the end of this function will be + * reached (after atomIntExit()) and the IRET call by the compiler will + * return us to the interrupted thread as if we hadn't run any other + * thread in the meantime. In other words the interrupted thread can be + * scheduled out by atomIntExit() and several threads could run before we + * actually reach the end of this function. When this function does + * finally complete, the return address (the PC of the thread which was + * interrupted) will be on the interrupted thread's stack because it was + * saved on there by the CPU when the interrupt triggered. + * + * As with all interrupts, the ISR should call atomIntEnter() and + * atomIntExit() on entry and exit. This serves two purposes: + * + * a) To notify the OS that it is running in interrupt context + * b) To defer the scheduler until after the ISR is completed + * + * We defer all scheduling decisions until after the ISR has completed + * in case the interrupt handler makes more than one thread ready. + * + * @return None + */ +void TIM1_SystemTickISR (void) +{ + /* Call the interrupt entry routine */ + atomIntEnter(); + + /* Call the OS system tick handler */ + atomTimerTick(); + + /* Ack the interrupt */ + TIM1_ClearITPendingBit(TIM1_IT_UPDATE); + + /* Call the interrupt exit routine */ + atomIntExit(TRUE); +} diff --git a/ports/stm8/atomport.h b/ports/stm8/atomport.h new file mode 100644 index 0000000..4464cb2 --- /dev/null +++ b/ports/stm8/atomport.h @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2010, Kelvin Lawson. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. No personal names or organizations' names associated with the + * Atomthreads project may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __ATOM_PORT_H +#define __ATOM_PORT_H + + +#include "stm8s_type.h" + + +/* Required number of system ticks per second (normally 100 for 10ms tick) */ +#define SYSTEM_TICKS_PER_SEC 100 + + +/** + * Architecture-specific types. + */ +#define int8_t s8 +#define int16_t s16 +#define int32_t s32 +#define uint8_t u8 +#define uint16_t u16 +#define uint32_t u32 +#define POINTER void * + + +/* Critical region protection */ +#define CRITICAL_STORE uint8_t ccr +#define CRITICAL_START() _asm ("push CC\npop a\nld (X),A\nsim", &ccr) +#define CRITICAL_END() _asm ("ld A,(X)\npush A\npop CC", &ccr) + + +#endif /* __ATOM_PORT_H */ diff --git a/ports/stm8/atomthreads.lkf b/ports/stm8/atomthreads.lkf new file mode 100644 index 0000000..3058a9f --- /dev/null +++ b/ports/stm8/atomthreads.lkf @@ -0,0 +1,63 @@ +# Segment configuration +# +# Segment Code,Constants: ++seg .const -b 0x8080 -m 0x7f80 -n .const -it ++seg .text -a .const -n .text +# Segment Eeprom: ++seg .eeprom -b 0x4000 -m 0x400 -n .eeprom +# Segment Zero Page (this deliberately avoids 0x0 to avoid +# NULL pointers to real data): ++seg .bsct -b 0x2 -m 0xfe -n .bsct ++seg .ubsct -a .bsct -n .ubsct ++seg .bit -a .ubsct -n .bit -id ++seg .share -a .bit -n .share -is +# Segment Ram: ++seg .data -b 0x100 -m 0x500 -n .data ++seg .bss -a .data -n .bss +# + + +# Startup file +# +crtsi0.sm8 +# + + +# Object files list - section reserved for STVD +# +build\atomkernel.o +build\atommutex.o +build\atomqueue.o +build\atomsem.o +build\atomtimer.o +build\stm8s_gpio.o +build\stm8s_tim1.o +build\tests-main.o +build\atomport.o +build\atomport-asm.o +# Caller passes in test application object name as param1 +@1 +# + + +# Library list +# +libis0.sm8 +libm0.sm8 +# + + +# Interrupt vectors file +# ++seg .const -b 0x8000 -k +build/stm8_interrupt_vector.o +# + +# Defines +# ++def __endzp=@.ubsct # end of uninitialized zpage ++def __memory=@.bss # end of bss segment ++def __startmem=@.bss ++def __endmem=0x5ff ++def __stack=0x7ff +# diff --git a/ports/stm8/stm8_interrupt_vector.c b/ports/stm8/stm8_interrupt_vector.c new file mode 100644 index 0000000..a858eec --- /dev/null +++ b/ports/stm8/stm8_interrupt_vector.c @@ -0,0 +1,60 @@ +/* BASIC INTERRUPT VECTOR TABLE FOR STM8 devices + * Copyright (c) 2007 STMicroelectronics + */ + + +/* Import Atomthreads system tick ISR prototype */ +#include "atomport-private.h" + + +typedef void @far (*interrupt_handler_t)(void); + +struct interrupt_vector { + unsigned char interrupt_instruction; + interrupt_handler_t interrupt_handler; +}; + +@far @interrupt void NonHandledInterrupt (void) +{ + /* in order to detect unexpected events during development, + it is recommended to set a breakpoint on the following instruction + */ + return; +} + +extern void _stext(); /* startup routine */ + +struct interrupt_vector const _vectab[] = { + {0x82, (interrupt_handler_t)_stext}, /* reset */ + {0x82, NonHandledInterrupt}, /* trap */ + {0x82, NonHandledInterrupt}, /* irq0 */ + {0x82, NonHandledInterrupt}, /* irq1 */ + {0x82, NonHandledInterrupt}, /* irq2 */ + {0x82, NonHandledInterrupt}, /* irq3 */ + {0x82, NonHandledInterrupt}, /* irq4 */ + {0x82, NonHandledInterrupt}, /* irq5 */ + {0x82, NonHandledInterrupt}, /* irq6 */ + {0x82, NonHandledInterrupt}, /* irq7 */ + {0x82, NonHandledInterrupt}, /* irq8 */ + {0x82, NonHandledInterrupt}, /* irq9 */ + {0x82, NonHandledInterrupt}, /* irq10 */ + {0x82, (interrupt_handler_t)TIM1_SystemTickISR}, /* irq11 */ + {0x82, NonHandledInterrupt}, /* irq12 */ + {0x82, NonHandledInterrupt}, /* irq13 */ + {0x82, NonHandledInterrupt}, /* irq14 */ + {0x82, NonHandledInterrupt}, /* irq15 */ + {0x82, NonHandledInterrupt}, /* irq16 */ + {0x82, NonHandledInterrupt}, /* irq17 */ + {0x82, NonHandledInterrupt}, /* irq18 */ + {0x82, NonHandledInterrupt}, /* irq19 */ + {0x82, NonHandledInterrupt}, /* irq20 */ + {0x82, NonHandledInterrupt}, /* irq21 */ + {0x82, NonHandledInterrupt}, /* irq22 */ + {0x82, NonHandledInterrupt}, /* irq23 */ + {0x82, NonHandledInterrupt}, /* irq24 */ + {0x82, NonHandledInterrupt}, /* irq25 */ + {0x82, NonHandledInterrupt}, /* irq26 */ + {0x82, NonHandledInterrupt}, /* irq27 */ + {0x82, NonHandledInterrupt}, /* irq28 */ + {0x82, NonHandledInterrupt}, /* irq29 */ +}; diff --git a/ports/stm8/stm8s-periphs/stm8s.h b/ports/stm8/stm8s-periphs/stm8s.h new file mode 100644 index 0000000..155cfae --- /dev/null +++ b/ports/stm8/stm8s-periphs/stm8s.h @@ -0,0 +1,2567 @@ +/** + ****************************************************************************** + * @file stm8s.h + * @brief This file contains all HW registers definitions and memory mapping. + * @author STMicroelectronics - MCD Application Team + * @version V1.1.1 + * @date 06/05/2009 + ****************************************************************************** + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ * @image html logo.bmp + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM8S_H +#define __STM8S_H + +/******************************************************************************/ +/* Library configuration section */ +/******************************************************************************/ +/* Check the used compiler */ +#if defined(__CSMC__) + #undef _RAISONANCE_ + #define _COSMIC_ +#elif defined(__RCST7__) + #undef _COSMIC_ + #define _RAISONANCE_ +#else + #error "Unsupported Compiler!" /* Compiler defines not found */ +#endif + +/* Uncomment the line below according to the target STM8S device used in your + application. + Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. */ +#if !defined (STM8S208) && !defined (STM8S207) && !defined (STM8S105) && !defined (STM8S103) && !defined (STM8S903) + #define STM8S208 + /* #define STM8S207 */ + /* #define STM8S105 */ + /* #define STM8S103 */ + /* #define STM8S903 */ +#endif + + +#if !defined USE_STDPERIPH_DRIVER +/* Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will be + based on direct access to peripherals registers */ + #define USE_STDPERIPH_DRIVER +#endif + +/* For FLASH routines, select whether pointer will be declared as near (2 bytes, handle + code smaller than 64KB) or far (3 bytes, handle code larger than 64K) */ +/*#define PointerAttr_Near 1 */ /*!< Used with memory Models for code smaller than 64K */ +#define PointerAttr_Far 2 /*!< Used with memory Models for code larger than 64K */ + +#ifdef _COSMIC_ + #define FAR @far + #define NEAR @near + #define TINY @tiny + #define __CONST const +#else /* __RCST7__ */ + #define FAR far + #define NEAR data + #define TINY page0 + #define __CONST code +#endif /* __CSMC__ */ + +#ifdef PointerAttr_Far + #define PointerAttr FAR +#else /* PointerAttr_Near */ + #define PointerAttr NEAR +#endif /* PointerAttr_Far */ + + +/* Uncomment the line below to use the cosmic section */ +#if defined(_COSMIC_) +/* #define USE_COSMIC_SECTIONS (1)*/ +#endif + +/******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "stm8s_type.h" + +/* Exported types and constants-----------------------------------------------*/ +/** @addtogroup MAP_FILE_Exported_Types_and_Constants + * @{ + */ + +/******************************************************************************/ +/* IP registers structures */ +/******************************************************************************/ +/*----------------------------------------------------------------------------*/ +/** + * @brief General Purpose I/Os (GPIO) + */ + +typedef struct GPIO_struct +{ + vu8 ODR; /*!< Output Data Register */ + vu8 IDR; /*!< Input Data Register */ + vu8 DDR; /*!< Data Direction Register */ + vu8 CR1; /*!< Configuration Register 1 */ + vu8 CR2; /*!< Configuration Register 2 */ +} +GPIO_TypeDef; + +/** @addtogroup GPIO_Registers_Reset_Value + * @{ + */ + +#define GPIO_ODR_RESET_VALUE ((u8)0x00) +#define GPIO_DDR_RESET_VALUE ((u8)0x00) +#define GPIO_CR1_RESET_VALUE ((u8)0x00) +#define GPIO_CR2_RESET_VALUE ((u8)0x00) + +/** + * @} + */ + +/*----------------------------------------------------------------------------*/ +#if defined(STM8S105) || defined(STM8S103) || defined(STM8S903) +/** + * @brief Analog to Digital Converter (ADC1) + */ +typedef struct ADC1_struct +{ + vu8 DB0RH; /*!< ADC1 Data Buffer Register (MSB) */ + vu8 DB0RL; /*!< ADC1 Data Buffer Register (LSB) */ + vu8 DB1RH; /*!< ADC1 Data Buffer Register (MSB) */ + vu8 DB1RL; /*!< ADC1 Data Buffer Register (LSB) */ + vu8 DB2RH; /*!< ADC1 Data Buffer Register (MSB) */ + vu8 DB2RL; /*!< ADC1 Data Buffer Register (LSB) */ + vu8 DB3RH; /*!< ADC1 Data Buffer Register (MSB) */ + vu8 DB3RL; /*!< ADC1 Data Buffer Register (LSB) */ + vu8 DB4RH; /*!< ADC1 Data Buffer Register (MSB) */ + vu8 DB4RL; /*!< ADC1 Data Buffer Register (LSB) */ + vu8 DB5RH; /*!< ADC1 Data Buffer Register (MSB) */ + vu8 DB5RL; /*!< ADC1 Data Buffer Register (LSB) */ + vu8 DB6RH; /*!< ADC1 Data Buffer Register (MSB) */ + vu8 DB6RL; /*!< ADC1 Data Buffer Register (LSB) */ + vu8 DB7RH; /*!< ADC1 Data Buffer Register (MSB) */ + vu8 DB7RL; /*!< ADC1 Data Buffer Register (LSB) */ + vu8 DB8RH; /*!< ADC1 Data Buffer Register (MSB) */ + vu8 DB8RL; /*!< ADC1 Data Buffer Register (LSB) */ + vu8 DB9RH; /*!< ADC1 Data Buffer Register (MSB) */ + vu8 DB9RL; /*!< ADC1 Data Buffer Register (LSB) */ + vu8 RESERVED[12]; /*!< Reserved byte */ + vu8 CSR; /*!< ADC1 control status register */ + vu8 CR1; /*!< ADC1 configuration register 1 */ + vu8 CR2; /*!< ADC1 configuration register 2 */ + vu8 CR3; /*!< ADC1 configuration register 3 */ + vu8 DRH; /*!< ADC1 Data high */ + vu8 DRL; /*!< ADC1 Data low */ + vu8 TDRH; /*!< ADC1 Schmitt trigger disable register high */ + vu8 TDRL; /*!< ADC1 Schmitt trigger disable register low */ + vu8 HTRH; /*!< ADC1 high threshold register High*/ + vu8 HTRL; /*!< ADC1 high threshold register Low*/ + vu8 LTRH; /*!< ADC1 low threshold register high */ + vu8 LTRL; /*!< ADC1 low threshold register low */ + vu8 AWSRH; /*!< ADC1 watchdog status register high */ + vu8 AWSRL; /*!< ADC1 watchdog status register low */ + vu8 AWCRH; /*!< ADC1 watchdog control register high */ + vu8 AWCRL; /*!< ADC1 watchdog control register low */ +} +ADC1_TypeDef; + +/** @addtogroup ADC1_Registers_Reset_Value + * @{ + */ + +#define ADC1_CSR_RESET_VALUE ((u8)0x00) +#define ADC1_CR1_RESET_VALUE ((u8)0x00) +#define ADC1_CR2_RESET_VALUE ((u8)0x00) +#define ADC1_CR3_RESET_VALUE ((u8)0x00) +#define ADC1_TDRL_RESET_VALUE ((u8)0x00) +#define ADC1_TDRH_RESET_VALUE ((u8)0x00) +#define ADC1_HTRL_RESET_VALUE ((u8)0x03) +#define ADC1_HTRH_RESET_VALUE ((u8)0xFF) +#define ADC1_LTRH_RESET_VALUE ((u8)0x00) +#define ADC1_LTRL_RESET_VALUE ((u8)0x00) +#define ADC1_AWCRH_RESET_VALUE ((u8)0x00) +#define ADC1_AWCRL_RESET_VALUE ((u8)0x00) + +/** + * @} + */ + +/** @addtogroup ADC1_Registers_Bits_Definition + * @{ + */ + +#define ADC1_CSR_EOC ((u8)0x80) /*!< End of Conversion mask */ +#define ADC1_CSR_AWD ((u8)0x40) /*!< Analog Watch Dog Status mask */ +#define ADC1_CSR_EOCIE ((u8)0x20) /*!< Interrupt Enable for EOC mask */ +#define ADC1_CSR_AWDIE ((u8)0x10) /*!< Analog Watchdog interrupt enable mask */ +#define ADC1_CSR_CH ((u8)0x0F) /*!< Channel selection bits mask */ + +#define ADC1_CR1_SPSEL ((u8)0x70) /*!< Prescaler selectiont mask */ +#define ADC1_CR1_CONT ((u8)0x02) /*!< Continuous conversion mask */ +#define ADC1_CR1_ADON ((u8)0x01) /*!< A/D Converter on/off mask */ + +#define ADC1_CR2_EXTTRIG ((u8)0x40) /*!< External trigger enable mask */ +#define ADC1_CR2_EXTSEL ((u8)0x30) /*!< External event selection mask */ +#define ADC1_CR2_ALIGN ((u8)0x08) /*!< Data Alignment mask */ +#define ADC1_CR2_SCAN ((u8)0x02) /*!< Scan mode mask */ + +#define ADC1_CR3_DBUF ((u8)0x80) /*!< Data Buffer Enable mask */ +#define ADC1_CR3_OVR ((u8)0x40) /*!< Overrun Status Flag mask */ + +#endif /* (STM8S105) ||(STM8S103) || (STM8S903) */ +/** + * @} + */ + +/*----------------------------------------------------------------------------*/ +/** + * @brief Analog to Digital Converter (ADC2) + */ +#if defined(STM8S208) || defined(STM8S207) +typedef struct ADC2_struct +{ + vu8 CSR; /*!< ADC2 control status register */ + vu8 CR1; /*!< ADC2 configuration register 1 */ + vu8 CR2; /*!< ADC2 configuration register 2 */ + vu8 RESERVED; /*!< Reserved byte */ + vu8 DRH; /*!< ADC2 Data high */ + vu8 DRL; /*!< ADC2 Data low */ + vu8 TDRH; /*!< ADC2 Schmitt trigger disable register high */ + vu8 TDRL; /*!< ADC2 Schmitt trigger disable register low */ +} +ADC2_TypeDef; + +/** @addtogroup ADC2_Registers_Reset_Value + * @{ + */ + +#define ADC2_CSR_RESET_VALUE ((u8)0x00) +#define ADC2_CR1_RESET_VALUE ((u8)0x00) +#define ADC2_CR2_RESET_VALUE ((u8)0x00) +#define ADC2_TDRL_RESET_VALUE ((u8)0x00) +#define ADC2_TDRH_RESET_VALUE ((u8)0x00) + +/** + * @} + */ + +/** @addtogroup ADC2_Registers_Bits_Definition + * @{ + */ + +#define ADC2_CSR_EOC ((u8)0x80) /*!< End of Conversion mask */ +#define ADC2_CSR_EOCIE ((u8)0x20) /*!< Interrupt Enable for EOC mask */ +#define ADC2_CSR_CH ((u8)0x0F) /*!< Channel selection bits mask */ + +#define ADC2_CR1_SPSEL ((u8)0x70) /*!< Prescaler selectiont mask */ +#define ADC2_CR1_CONT ((u8)0x02) /*!< Continuous conversion mask */ +#define ADC2_CR1_ADON ((u8)0x01) /*!< A/D Converter on/off mask */ + +#define ADC2_CR2_EXTTRIG ((u8)0x40) /*!< External trigger enable mask */ +#define ADC2_CR2_EXTSEL ((u8)0x30) /*!< External event selection mask */ +#define ADC2_CR2_ALIGN ((u8)0x08) /*!< Data Alignment mask */ + +#endif /* (STM8S208) ||(STM8S207) */ +/** + * @} + */ +/*----------------------------------------------------------------------------*/ +/** + * @brief Auto Wake Up (AWU) peripheral registers. + */ + +typedef struct AWU_struct +{ + vu8 CSR; /*!< AWU Control status register */ + vu8 APR; /*!< AWU Asynchronous prescalar buffer */ + vu8 TBR; /*!< AWU Time base selection register */ +} +AWU_TypeDef; + +/** @addtogroup AWU_Registers_Reset_Value + * @{ + */ + +#define AWU_CSR_RESET_VALUE ((u8)0x00) +#define AWU_APR_RESET_VALUE ((u8)0x3F) +#define AWU_TBR_RESET_VALUE ((u8)0x00) + +/** + * @} + */ + +/** @addtogroup AWU_Registers_Bits_Definition + * @{ + */ + +#define AWU_CSR_AWUF ((u8)0x20) /*!< Interrupt flag mask */ +#define AWU_CSR_AWUEN ((u8)0x10) /*!< Auto Wake-up enable mask */ +#define AWU_CSR_MR ((u8)0x02) /*!< Master Reset mask */ +#define AWU_CSR_MSR ((u8)0x01) /*!< Measurement enable mask */ + +#define AWU_APR_APR ((u8)0x3F) /*!< Asynchronous Prescaler divider mask */ + +#define AWU_TBR_AWUTB ((u8)0x0F) /*!< Timebase selection mask */ + +/** + * @} + */ + +/*----------------------------------------------------------------------------*/ +/** + * @brief Beeper (BEEP) peripheral registers. + */ + +typedef struct BEEP_struct +{ + vu8 CSR; /*!< BEEP Control status register */ +} +BEEP_TypeDef; + +/** @addtogroup BEEP_Registers_Reset_Value + * @{ + */ + +#define BEEP_CSR_RESET_VALUE ((u8)0x1F) + +/** + * @} + */ + +/** @addtogroup BEEP_Registers_Bits_Definition + * @{ + */ + +#define BEEP_CSR_BEEPSEL ((u8)0xC0) /*!< Beeper frequency selection mask */ +#define BEEP_CSR_BEEPEN ((u8)0x20) /*!< Beeper enable mask */ +#define BEEP_CSR_BEEPDIV ((u8)0x1F) /*!< Beeper Divider prescalar mask */ + +/** + * @} + */ + +/*----------------------------------------------------------------------------*/ +/** + * @brief Clock Controller (CLK) + */ + +typedef struct CLK_struct +{ + vu8 ICKR; /*!< Internal Clocks Control Register */ + vu8 ECKR; /*!< External Clocks Control Register */ + u8 RESERVED; /*!< Reserved byte */ + vu8 CMSR; /*!< Clock Master Status Register */ + vu8 SWR; /*!< Clock Master Switch Register */ + vu8 SWCR; /*!< Switch Control Register */ + vu8 CKDIVR; /*!< Clock Divider Register */ + vu8 PCKENR1; /*!< Peripheral Clock Gating Register 1 */ + vu8 CSSR; /*!< Clock Security Sytem Register */ + vu8 CCOR; /*!< Configurable Clock Output Register */ + vu8 PCKENR2; /*!< Peripheral Clock Gating Register 2 */ + vu8 CANCCR; /*!< CAN external clock control Register (exist only in STM8S208 otherwise it is reserved) */ + vu8 HSITRIMR; /*!< HSI Calibration Trimmer Register */ + vu8 SWIMCCR; /*!< SWIM clock control register */ +} +CLK_TypeDef; + +/** @addtogroup CLK_Registers_Reset_Value + * @{ + */ + +#define CLK_ICKR_RESET_VALUE ((u8)0x01) +#define CLK_ECKR_RESET_VALUE ((u8)0x00) +#define CLK_CMSR_RESET_VALUE ((u8)0xE1) +#define CLK_SWR_RESET_VALUE ((u8)0xE1) +#define CLK_SWCR_RESET_VALUE ((u8)0x00) +#define CLK_CKDIVR_RESET_VALUE ((u8)0x18) +#define CLK_PCKENR1_RESET_VALUE ((u8)0xFF) +#define CLK_PCKENR2_RESET_VALUE ((u8)0xFF) +#define CLK_CSSR_RESET_VALUE ((u8)0x00) +#define CLK_CCOR_RESET_VALUE ((u8)0x00) +#define CLK_CANCCR_RESET_VALUE ((u8)0x00) +#define CLK_HSITRIMR_RESET_VALUE ((u8)0x00) +#define CLK_SWIMCCR_RESET_VALUE ((u8)0x00) + +/** + * @} + */ + +/** @addtogroup CLK_Registers_Bits_Definition + * @{ + */ + +#define CLK_ICKR_SWUAH ((u8)0x20) /*!< Slow Wake-up from Active Halt/Halt modes */ +#define CLK_ICKR_LSIRDY ((u8)0x10) /*!< Low speed internal oscillator ready */ +#define CLK_ICKR_LSIEN ((u8)0x08) /*!< Low speed internal RC oscillator enable */ +#define CLK_ICKR_FHWU ((u8)0x04) /*!< Fast Wake-up from Active Halt/Halt mode */ +#define CLK_ICKR_HSIRDY ((u8)0x02) /*!< High speed internal RC oscillator ready */ +#define CLK_ICKR_HSIEN ((u8)0x01) /*!< High speed internal RC oscillator enable */ + +#define CLK_ECKR_HSERDY ((u8)0x02) /*!< High speed external crystal oscillator ready */ +#define CLK_ECKR_HSEEN ((u8)0x01) /*!< High speed external crystal oscillator enable */ + +#define CLK_CMSR_CKM ((u8)0xFF) /*!< Clock master status bits */ + +#define CLK_SWR_SWI ((u8)0xFF) /*!< Clock master selection bits */ + +#define CLK_SWCR_SWIF ((u8)0x08) /*!< Clock switch interrupt flag */ +#define CLK_SWCR_SWIEN ((u8)0x04) /*!< Clock switch interrupt enable */ +#define CLK_SWCR_SWEN ((u8)0x02) /*!< Switch start/stop */ +#define CLK_SWCR_SWBSY ((u8)0x01) /*!< Switch busy */ + +#define CLK_CKDIVR_HSIDIV ((u8)0x18) /*!< High speed internal clock prescaler */ +#define CLK_CKDIVR_CPUDIV ((u8)0x07) /*!< CPU clock prescaler */ + +#define CLK_PCKENR1_TIM1 ((u8)0x80) /*!< Timer 1 clock enable */ +#define CLK_PCKENR1_TIM3 ((u8)0x40) /*!< Timer 3 clock enable */ +#define CLK_PCKENR1_TIM2 ((u8)0x20) /*!< Timer 2 clock enable */ +#define CLK_PCKENR1_TIM5 ((u8)0x20) /*!< Timer 5 clock enable */ +#define CLK_PCKENR1_TIM4 ((u8)0x10) /*!< Timer 4 clock enable */ +#define CLK_PCKENR1_TIM6 ((u8)0x10) /*!< Timer 6 clock enable */ +#define CLK_PCKENR1_UART3 ((u8)0x08) /*!< UART3 clock enable */ +#define CLK_PCKENR1_UART2 ((u8)0x08) /*!< UART2 clock enable */ +#define CLK_PCKENR1_UART1 ((u8)0x04) /*!< UART1 clock enable */ +#define CLK_PCKENR1_SPI ((u8)0x02) /*!< SPI clock enable */ +#define CLK_PCKENR1_I2C ((u8)0x01) /*!< I2C clock enable */ + +#define CLK_PCKENR2_CAN ((u8)0x80) /*!< CAN clock enable */ +#define CLK_PCKENR2_ADC ((u8)0x08) /*!< ADC clock enable */ +#define CLK_PCKENR2_AWU ((u8)0x04) /*!< AWU clock enable */ + +#define CLK_CSSR_CSSD ((u8)0x08) /*!< Clock security sytem detection */ +#define CLK_CSSR_CSSDIE ((u8)0x04) /*!< Clock security system detection interrupt enable */ +#define CLK_CSSR_AUX ((u8)0x02) /*!< Auxiliary oscillator connected to master clock */ +#define CLK_CSSR_CSSEN ((u8)0x01) /*!< Clock security system enable */ + +#define CLK_CCOR_CCOBSY ((u8)0x40) /*!< Configurable clock output busy */ +#define CLK_CCOR_CCORDY ((u8)0x20) /*!< Configurable clock output ready */ +#define CLK_CCOR_CCOSEL ((u8)0x1E) /*!< Configurable clock output selection */ +#define CLK_CCOR_CCOEN ((u8)0x01) /*!< Configurable clock output enable */ + +#define CLK_CANCCR_CANDIV ((u8)0x07) /*!< External CAN clock divider */ + +#define CLK_HSITRIMR_HSITRIM ((u8)0x07) /*!< High speed internal oscillator trimmer */ + +#define CLK_SWIMCCR_SWIMDIV ((u8)0x01) /*!< SWIM Clock Dividing Factor */ + +/** + * @} + */ + +/*----------------------------------------------------------------------------*/ +/** + * @brief 16-bit timer with complementary PWM outputs (TIM1) + */ + +typedef struct TIM1_struct +{ + vu8 CR1; /*!< control register 1 */ + vu8 CR2; /*!< control register 2 */ + vu8 SMCR; /*!< Synchro mode control register */ + vu8 ETR; /*!< external trigger register */ + vu8 IER; /*!< interrupt enable register*/ + vu8 SR1; /*!< status register 1 */ + vu8 SR2; /*!< status register 2 */ + vu8 EGR; /*!< event generation register */ + vu8 CCMR1; /*!< CC mode register 1 */ + vu8 CCMR2; /*!< CC mode register 2 */ + vu8 CCMR3; /*!< CC mode register 3 */ + vu8 CCMR4; /*!< CC mode register 4 */ + vu8 CCER1; /*!< CC enable register 1 */ + vu8 CCER2; /*!< CC enable register 2 */ + vu8 CNTRH; /*!< counter high */ + vu8 CNTRL; /*!< counter low */ + vu8 PSCRH; /*!< prescaler high */ + vu8 PSCRL; /*!< prescaler low */ + vu8 ARRH; /*!< auto-reload register high */ + vu8 ARRL; /*!< auto-reload register low */ + vu8 RCR; /*!< Repetition Counter register */ + vu8 CCR1H; /*!< capture/compare register 1 high */ + vu8 CCR1L; /*!< capture/compare register 1 low */ + vu8 CCR2H; /*!< capture/compare register 2 high */ + vu8 CCR2L; /*!< capture/compare register 2 low */ + vu8 CCR3H; /*!< capture/compare register 3 high */ + vu8 CCR3L; /*!< capture/compare register 3 low */ + vu8 CCR4H; /*!< capture/compare register 3 high */ + vu8 CCR4L; /*!< capture/compare register 3 low */ + vu8 BKR; /*!< Break Register */ + vu8 DTR; /*!< dead-time register */ + vu8 OISR; /*!< Output idle register */ +} +TIM1_TypeDef; + +/** @addtogroup TIM1_Registers_Reset_Value + * @{ + */ + +#define TIM1_CR1_RESET_VALUE ((u8)0x00) +#define TIM1_CR2_RESET_VALUE ((u8)0x00) +#define TIM1_SMCR_RESET_VALUE ((u8)0x00) +#define TIM1_ETR_RESET_VALUE ((u8)0x00) +#define TIM1_IER_RESET_VALUE ((u8)0x00) +#define TIM1_SR1_RESET_VALUE ((u8)0x00) +#define TIM1_SR2_RESET_VALUE ((u8)0x00) +#define TIM1_EGR_RESET_VALUE ((u8)0x00) +#define TIM1_CCMR1_RESET_VALUE ((u8)0x00) +#define TIM1_CCMR2_RESET_VALUE ((u8)0x00) +#define TIM1_CCMR3_RESET_VALUE ((u8)0x00) +#define TIM1_CCMR4_RESET_VALUE ((u8)0x00) +#define TIM1_CCER1_RESET_VALUE ((u8)0x00) +#define TIM1_CCER2_RESET_VALUE ((u8)0x00) +#define TIM1_CNTRH_RESET_VALUE ((u8)0x00) +#define TIM1_CNTRL_RESET_VALUE ((u8)0x00) +#define TIM1_PSCRH_RESET_VALUE ((u8)0x00) +#define TIM1_PSCRL_RESET_VALUE ((u8)0x00) +#define TIM1_ARRH_RESET_VALUE ((u8)0xFF) +#define TIM1_ARRL_RESET_VALUE ((u8)0xFF) +#define TIM1_RCR_RESET_VALUE ((u8)0x00) +#define TIM1_CCR1H_RESET_VALUE ((u8)0x00) +#define TIM1_CCR1L_RESET_VALUE ((u8)0x00) +#define TIM1_CCR2H_RESET_VALUE ((u8)0x00) +#define TIM1_CCR2L_RESET_VALUE ((u8)0x00) +#define TIM1_CCR3H_RESET_VALUE ((u8)0x00) +#define TIM1_CCR3L_RESET_VALUE ((u8)0x00) +#define TIM1_CCR4H_RESET_VALUE ((u8)0x00) +#define TIM1_CCR4L_RESET_VALUE ((u8)0x00) +#define TIM1_BKR_RESET_VALUE ((u8)0x00) +#define TIM1_DTR_RESET_VALUE ((u8)0x00) +#define TIM1_OISR_RESET_VALUE ((u8)0x00) + +/** + * @} + */ + +/** @addtogroup TIM1_Registers_Bits_Definition + * @{ + */ +/* CR1*/ +#define TIM1_CR1_ARPE ((u8)0x80) /*!< Auto-Reload Preload Enable mask. */ +#define TIM1_CR1_CMS ((u8)0x60) /*!< Center-aligned Mode Selection mask. */ +#define TIM1_CR1_DIR ((u8)0x10) /*!< Direction mask. */ +#define TIM1_CR1_OPM ((u8)0x08) /*!< One Pulse Mode mask. */ +#define TIM1_CR1_URS ((u8)0x04) /*!< Update Request Source mask. */ +#define TIM1_CR1_UDIS ((u8)0x02) /*!< Update DIsable mask. */ +#define TIM1_CR1_CEN ((u8)0x01) /*!< Counter Enable mask. */ +/* CR2*/ +#define TIM1_CR2_TI1S ((u8)0x80) /*!< TI1S Selection mask. */ +#define TIM1_CR2_MMS ((u8)0x70) /*!< MMS Selection mask. */ +#define TIM1_CR2_COMS ((u8)0x04) /*!< Capture/Compare Control Update Selection mask. */ +#define TIM1_CR2_CCPC ((u8)0x01) /*!< Capture/Compare Preloaded Control mask. */ +/* SMCR*/ +#define TIM1_SMCR_MSM ((u8)0x80) /*!< Master/Slave Mode mask. */ +#define TIM1_SMCR_TS ((u8)0x70) /*!< Trigger Selection mask. */ +#define TIM1_SMCR_SMS ((u8)0x07) /*!< Slave Mode Selection mask. */ +/*ETR*/ +#define TIM1_ETR_ETP ((u8)0x80) /*!< External Trigger Polarity mask. */ +#define TIM1_ETR_ECE ((u8)0x40)/*!< External Clock mask. */ +#define TIM1_ETR_ETPS ((u8)0x30) /*!< External Trigger Prescaler mask. */ +#define TIM1_ETR_ETF ((u8)0x0F) /*!< External Trigger Filter mask. */ +/*IER*/ +#define TIM1_IER_BIE ((u8)0x80) /*!< Break Interrupt Enable mask. */ +#define TIM1_IER_TIE ((u8)0x40) /*!< Trigger Interrupt Enable mask. */ +#define TIM1_IER_COMIE ((u8)0x20) /*!< Commutation Interrupt Enable mask.*/ +#define TIM1_IER_CC4IE ((u8)0x10) /*!< Capture/Compare 4 Interrupt Enable mask. */ +#define TIM1_IER_CC3IE ((u8)0x08) /*!< Capture/Compare 3 Interrupt Enable mask. */ +#define TIM1_IER_CC2IE ((u8)0x04) /*!< Capture/Compare 2 Interrupt Enable mask. */ +#define TIM1_IER_CC1IE ((u8)0x02) /*!< Capture/Compare 1 Interrupt Enable mask. */ +#define TIM1_IER_UIE ((u8)0x01) /*!< Update Interrupt Enable mask. */ +/*SR1*/ +#define TIM1_SR1_BIF ((u8)0x80) /*!< Break Interrupt Flag mask. */ +#define TIM1_SR1_TIF ((u8)0x40) /*!< Trigger Interrupt Flag mask. */ +#define TIM1_SR1_COMIF ((u8)0x20) /*!< Commutation Interrupt Flag mask. */ +#define TIM1_SR1_CC4IF ((u8)0x10) /*!< Capture/Compare 4 Interrupt Flag mask. */ +#define TIM1_SR1_CC3IF ((u8)0x08) /*!< Capture/Compare 3 Interrupt Flag mask. */ +#define TIM1_SR1_CC2IF ((u8)0x04) /*!< Capture/Compare 2 Interrupt Flag mask. */ +#define TIM1_SR1_CC1IF ((u8)0x02) /*!< Capture/Compare 1 Interrupt Flag mask. */ +#define TIM1_SR1_UIF ((u8)0x01) /*!< Update Interrupt Flag mask. */ +/*SR2*/ +#define TIM1_SR2_CC4OF ((u8)0x10) /*!< Capture/Compare 4 Overcapture Flag mask. */ +#define TIM1_SR2_CC3OF ((u8)0x08) /*!< Capture/Compare 3 Overcapture Flag mask. */ +#define TIM1_SR2_CC2OF ((u8)0x04) /*!< Capture/Compare 2 Overcapture Flag mask. */ +#define TIM1_SR2_CC1OF ((u8)0x02) /*!< Capture/Compare 1 Overcapture Flag mask. */ +/*EGR*/ +#define TIM1_EGR_BG ((u8)0x80) /*!< Break Generation mask. */ +#define TIM1_EGR_TG ((u8)0x40) /*!< Trigger Generation mask. */ +#define TIM1_EGR_COMG ((u8)0x20) /*!< Capture/Compare Control Update Generation mask. */ +#define TIM1_EGR_CC4G ((u8)0x10) /*!< Capture/Compare 4 Generation mask. */ +#define TIM1_EGR_CC3G ((u8)0x08) /*!< Capture/Compare 3 Generation mask. */ +#define TIM1_EGR_CC2G ((u8)0x04) /*!< Capture/Compare 2 Generation mask. */ +#define TIM1_EGR_CC1G ((u8)0x02) /*!< Capture/Compare 1 Generation mask. */ +#define TIM1_EGR_UG ((u8)0x01) /*!< Update Generation mask. */ +/*CCMR*/ +#define TIM1_CCMR_ICxPSC ((u8)0x0C) /*!< Input Capture x Prescaler mask. */ +#define TIM1_CCMR_ICxF ((u8)0xF0) /*!< Input Capture x Filter mask. */ +#define TIM1_CCMR_OCM ((u8)0x70) /*!< Output Compare x Mode mask. */ +#define TIM1_CCMR_OCxPE ((u8)0x08) /*!< Output Compare x Preload Enable mask. */ +#define TIM1_CCMR_OCxFE ((u8)0x04) /*!< Output Compare x Fast Enable mask. */ +#define TIM1_CCMR_CCxS ((u8)0x03) /*!< Capture/Compare x Selection mask. */ + +#define CCMR_TIxDirect_Set ((u8)0x01) +/*CCER1*/ +#define TIM1_CCER1_CC2NP ((u8)0x80) /*!< Capture/Compare 2 Complementary output Polarity mask. */ +#define TIM1_CCER1_CC2NE ((u8)0x40) /*!< Capture/Compare 2 Complementary output enable mask. */ +#define TIM1_CCER1_CC2P ((u8)0x20) /*!< Capture/Compare 2 output Polarity mask. */ +#define TIM1_CCER1_CC2E ((u8)0x10) /*!< Capture/Compare 2 output enable mask. */ +#define TIM1_CCER1_CC1NP ((u8)0x08) /*!< Capture/Compare 1 Complementary output Polarity mask. */ +#define TIM1_CCER1_CC1NE ((u8)0x04) /*!< Capture/Compare 1 Complementary output enable mask. */ +#define TIM1_CCER1_CC1P ((u8)0x02) /*!< Capture/Compare 1 output Polarity mask. */ +#define TIM1_CCER1_CC1E ((u8)0x01) /*!< Capture/Compare 1 output enable mask. */ +/*CCER2*/ +#define TIM1_CCER2_CC4P ((u8)0x20) /*!< Capture/Compare 4 output Polarity mask. */ +#define TIM1_CCER2_CC4E ((u8)0x10) /*!< Capture/Compare 4 output enable mask. */ +#define TIM1_CCER2_CC3NP ((u8)0x08) /*!< Capture/Compare 3 Complementary output Polarity mask. */ +#define TIM1_CCER2_CC3NE ((u8)0x04) /*!< Capture/Compare 3 Complementary output enable mask. */ +#define TIM1_CCER2_CC3P ((u8)0x02) /*!< Capture/Compare 3 output Polarity mask. */ +#define TIM1_CCER2_CC3E ((u8)0x01) /*!< Capture/Compare 3 output enable mask. */ +/*CNTRH*/ +#define TIM1_CNTRH_CNT ((u8)0xFF) /*!< Counter Value (MSB) mask. */ +/*CNTRL*/ +#define TIM1_CNTRL_CNT ((u8)0xFF) /*!< Counter Value (LSB) mask. */ +/*PSCH*/ +#define TIM1_PSCH_PSC ((u8)0xFF) /*!< Prescaler Value (MSB) mask. */ +/*PSCL*/ +#define TIM1_PSCL_PSC ((u8)0xFF) /*!< Prescaler Value (LSB) mask. */ +/*ARR*/ +#define TIM1_ARRH_ARR ((u8)0xFF) /*!< Autoreload Value (MSB) mask. */ +#define TIM1_ARRL_ARR ((u8)0xFF) /*!< Autoreload Value (LSB) mask. */ +/*RCR*/ +#define TIM1_RCR_REP ((u8)0xFF) /*!< Repetition Counter Value mask. */ +/*CCR1*/ +#define TIM1_CCR1H_CCR1 ((u8)0xFF) /*!< Capture/Compare 1 Value (MSB) mask. */ +#define TIM1_CCR1L_CCR1 ((u8)0xFF) /*!< Capture/Compare 1 Value (LSB) mask. */ +/*CCR2*/ +#define TIM1_CCR2H_CCR2 ((u8)0xFF) /*!< Capture/Compare 2 Value (MSB) mask. */ +#define TIM1_CCR2L_CCR2 ((u8)0xFF) /*!< Capture/Compare 2 Value (LSB) mask. */ +/*CCR3*/ +#define TIM1_CCR3H_CCR3 ((u8)0xFF) /*!< Capture/Compare 3 Value (MSB) mask. */ +#define TIM1_CCR3L_CCR3 ((u8)0xFF) /*!< Capture/Compare 3 Value (LSB) mask. */ +/*CCR4*/ +#define TIM1_CCR4H_CCR4 ((u8)0xFF) /*!< Capture/Compare 4 Value (MSB) mask. */ +#define TIM1_CCR4L_CCR4 ((u8)0xFF) /*!< Capture/Compare 4 Value (LSB) mask. */ +/*BKR*/ +#define TIM1_BKR_MOE ((u8)0x80) /*!< Main Output Enable mask. */ +#define TIM1_BKR_AOE ((u8)0x40) /*!< Automatic Output Enable mask. */ +#define TIM1_BKR_BKP ((u8)0x20) /*!< Break Polarity mask. */ +#define TIM1_BKR_BKE ((u8)0x10) /*!< Break Enable mask. */ +#define TIM1_BKR_OSSR ((u8)0x08) /*!< Off-State Selection for Run mode mask. */ +#define TIM1_BKR_OSSI ((u8)0x04) /*!< Off-State Selection for Idle mode mask. */ +#define TIM1_BKR_LOCK ((u8)0x03) /*!< Lock Configuration mask. */ +/*DTR*/ +#define TIM1_DTR_DTG ((u8)0xFF) /*!< Dead-Time Generator set-up mask. */ +/*OISR*/ +#define TIM1_OISR_OIS4 ((u8)0x40) /*!< Output Idle state 4 (OC4 output) mask. */ +#define TIM1_OISR_OIS3N ((u8)0x20) /*!< Output Idle state 3 (OC3N output) mask. */ +#define TIM1_OISR_OIS3 ((u8)0x10) /*!< Output Idle state 3 (OC3 output) mask. */ +#define TIM1_OISR_OIS2N ((u8)0x08) /*!< Output Idle state 2 (OC2N output) mask. */ +#define TIM1_OISR_OIS2 ((u8)0x04) /*!< Output Idle state 2 (OC2 output) mask. */ +#define TIM1_OISR_OIS1N ((u8)0x02) /*!< Output Idle state 1 (OC1N output) mask. */ +#define TIM1_OISR_OIS1 ((u8)0x01) /*!< Output Idle state 1 (OC1 output) mask. */ + +/** + * @} + */ + +/*----------------------------------------------------------------------------*/ +/** + * @brief 16-bit timer (TIM2) + */ + +typedef struct TIM2_struct +{ + vu8 CR1; /*!< control register 1 */ +#if defined STM8S103 + vu8 RESERVED1; /*!< Reserved register */ + vu8 RESERVED2; /*!< Reserved register */ +#endif + vu8 IER; /*!< interrupt enable register */ + vu8 SR1; /*!< status register 1 */ + vu8 SR2; /*!< status register 2 */ + vu8 EGR; /*!< event generation register */ + vu8 CCMR1; /*!< CC mode register 1 */ + vu8 CCMR2; /*!< CC mode register 2 */ + vu8 CCMR3; /*!< CC mode register 3 */ + vu8 CCER1; /*!< CC enable register 1 */ + vu8 CCER2; /*!< CC enable register 2 */ + vu8 CNTRH; /*!< counter high */ + vu8 CNTRL; /*!< counter low */ + vu8 PSCR; /*!< prescaler register */ + vu8 ARRH; /*!< auto-reload register high */ + vu8 ARRL; /*!< auto-reload register low */ + vu8 CCR1H; /*!< capture/compare register 1 high */ + vu8 CCR1L; /*!< capture/compare register 1 low */ + vu8 CCR2H; /*!< capture/compare register 2 high */ + vu8 CCR2L; /*!< capture/compare register 2 low */ + vu8 CCR3H; /*!< capture/compare register 3 high */ + vu8 CCR3L; /*!< capture/compare register 3 low */ +} +TIM2_TypeDef; + +/** @addtogroup TIM2_Registers_Reset_Value + * @{ + */ + +#define TIM2_CR1_RESET_VALUE ((u8)0x00) +#define TIM2_IER_RESET_VALUE ((u8)0x00) +#define TIM2_SR1_RESET_VALUE ((u8)0x00) +#define TIM2_SR2_RESET_VALUE ((u8)0x00) +#define TIM2_EGR_RESET_VALUE ((u8)0x00) +#define TIM2_CCMR1_RESET_VALUE ((u8)0x00) +#define TIM2_CCMR2_RESET_VALUE ((u8)0x00) +#define TIM2_CCMR3_RESET_VALUE ((u8)0x00) +#define TIM2_CCER1_RESET_VALUE ((u8)0x00) +#define TIM2_CCER2_RESET_VALUE ((u8)0x00) +#define TIM2_CNTRH_RESET_VALUE ((u8)0x00) +#define TIM2_CNTRL_RESET_VALUE ((u8)0x00) +#define TIM2_PSCR_RESET_VALUE ((u8)0x00) +#define TIM2_ARRH_RESET_VALUE ((u8)0xFF) +#define TIM2_ARRL_RESET_VALUE ((u8)0xFF) +#define TIM2_CCR1H_RESET_VALUE ((u8)0x00) +#define TIM2_CCR1L_RESET_VALUE ((u8)0x00) +#define TIM2_CCR2H_RESET_VALUE ((u8)0x00) +#define TIM2_CCR2L_RESET_VALUE ((u8)0x00) +#define TIM2_CCR3H_RESET_VALUE ((u8)0x00) +#define TIM2_CCR3L_RESET_VALUE ((u8)0x00) + +/** + * @} + */ + +/** @addtogroup TIM2_Registers_Bits_Definition + * @{ + */ +/*CR1*/ +#define TIM2_CR1_ARPE ((u8)0x80) /*!< Auto-Reload Preload Enable mask. */ +#define TIM2_CR1_OPM ((u8)0x08) /*!< One Pulse Mode mask. */ +#define TIM2_CR1_URS ((u8)0x04) /*!< Update Request Source mask. */ +#define TIM2_CR1_UDIS ((u8)0x02) /*!< Update DIsable mask. */ +#define TIM2_CR1_CEN ((u8)0x01) /*!< Counter Enable mask. */ +/*IER*/ +#define TIM2_IER_CC3IE ((u8)0x08) /*!< Capture/Compare 3 Interrupt Enable mask. */ +#define TIM2_IER_CC2IE ((u8)0x04) /*!< Capture/Compare 2 Interrupt Enable mask. */ +#define TIM2_IER_CC1IE ((u8)0x02) /*!< Capture/Compare 1 Interrupt Enable mask. */ +#define TIM2_IER_UIE ((u8)0x01) /*!< Update Interrupt Enable mask. */ +/*SR1*/ +#define TIM2_SR1_CC3IF ((u8)0x08) /*!< Capture/Compare 3 Interrupt Flag mask. */ +#define TIM2_SR1_CC2IF ((u8)0x04) /*!< Capture/Compare 2 Interrupt Flag mask. */ +#define TIM2_SR1_CC1IF ((u8)0x02) /*!< Capture/Compare 1 Interrupt Flag mask. */ +#define TIM2_SR1_UIF ((u8)0x01) /*!< Update Interrupt Flag mask. */ +/*SR2*/ +#define TIM2_SR2_CC3OF ((u8)0x08) /*!< Capture/Compare 3 Overcapture Flag mask. */ +#define TIM2_SR2_CC2OF ((u8)0x04) /*!< Capture/Compare 2 Overcapture Flag mask. */ +#define TIM2_SR2_CC1OF ((u8)0x02) /*!< Capture/Compare 1 Overcapture Flag mask. */ +/*EGR*/ +#define TIM2_EGR_CC3G ((u8)0x08) /*!< Capture/Compare 3 Generation mask. */ +#define TIM2_EGR_CC2G ((u8)0x04) /*!< Capture/Compare 2 Generation mask. */ +#define TIM2_EGR_CC1G ((u8)0x02) /*!< Capture/Compare 1 Generation mask. */ +#define TIM2_EGR_UG ((u8)0x01) /*!< Update Generation mask. */ +/*CCMR*/ +#define TIM2_CCMR_ICxPSC ((u8)0x0C) /*!< Input Capture x Prescaler mask. */ +#define TIM2_CCMR_ICxF ((u8)0xF0) /*!< Input Capture x Filter mask. */ +#define TIM2_CCMR_OCM ((u8)0x70) /*!< Output Compare x Mode mask. */ +#define TIM2_CCMR_OCxPE ((u8)0x08) /*!< Output Compare x Preload Enable mask. */ +#define TIM2_CCMR_CCxS ((u8)0x03) /*!< Capture/Compare x Selection mask. */ +/*CCER1*/ +#define TIM2_CCER1_CC2P ((u8)0x20) /*!< Capture/Compare 2 output Polarity mask. */ +#define TIM2_CCER1_CC2E ((u8)0x10) /*!< Capture/Compare 2 output enable mask. */ +#define TIM2_CCER1_CC1P ((u8)0x02) /*!< Capture/Compare 1 output Polarity mask. */ +#define TIM2_CCER1_CC1E ((u8)0x01) /*!< Capture/Compare 1 output enable mask. */ +/*CCER2*/ +#define TIM2_CCER2_CC3P ((u8)0x02) /*!< Capture/Compare 3 output Polarity mask. */ +#define TIM2_CCER2_CC3E ((u8)0x01) /*!< Capture/Compare 3 output enable mask. */ +/*CNTR*/ +#define TIM2_CNTRH_CNT ((u8)0xFF) /*!< Counter Value (MSB) mask. */ +#define TIM2_CNTRL_CNT ((u8)0xFF) /*!< Counter Value (LSB) mask. */ +/*PSCR*/ +#define TIM2_PSCR_PSC ((u8)0xFF) /*!< Prescaler Value (MSB) mask. */ +/*ARR*/ +#define TIM2_ARRH_ARR ((u8)0xFF) /*!< Autoreload Value (MSB) mask. */ +#define TIM2_ARRL_ARR ((u8)0xFF) /*!< Autoreload Value (LSB) mask. */ +/*CCR1*/ +#define TIM2_CCR1H_CCR1 ((u8)0xFF) /*!< Capture/Compare 1 Value (MSB) mask. */ +#define TIM2_CCR1L_CCR1 ((u8)0xFF) /*!< Capture/Compare 1 Value (LSB) mask. */ +/*CCR2*/ +#define TIM2_CCR2H_CCR2 ((u8)0xFF) /*!< Capture/Compare 2 Value (MSB) mask. */ +#define TIM2_CCR2L_CCR2 ((u8)0xFF) /*!< Capture/Compare 2 Value (LSB) mask. */ +/*CCR3*/ +#define TIM2_CCR3H_CCR3 ((u8)0xFF) /*!< Capture/Compare 3 Value (MSB) mask. */ +#define TIM2_CCR3L_CCR3 ((u8)0xFF) /*!< Capture/Compare 3 Value (LSB) mask. */ + +/** + * @} + */ + +/*----------------------------------------------------------------------------*/ +/** + * @brief 16-bit timer (TIM3) + */ +typedef struct TIM3_struct +{ + vu8 CR1; /*!< control register 1 */ + vu8 IER; /*!< interrupt enable register */ + vu8 SR1; /*!< status register 1 */ + vu8 SR2; /*!< status register 2 */ + vu8 EGR; /*!< event generation register */ + vu8 CCMR1; /*!< CC mode register 1 */ + vu8 CCMR2; /*!< CC mode register 2 */ + vu8 CCER1; /*!< CC enable register 1 */ + vu8 CNTRH; /*!< counter high */ + vu8 CNTRL; /*!< counter low */ + vu8 PSCR; /*!< prescaler register */ + vu8 ARRH; /*!< auto-reload register high */ + vu8 ARRL; /*!< auto-reload register low */ + vu8 CCR1H; /*!< capture/compare register 1 high */ + vu8 CCR1L; /*!< capture/compare register 1 low */ + vu8 CCR2H; /*!< capture/compare register 2 high */ + vu8 CCR2L; /*!< capture/compare register 2 low */ +} +TIM3_TypeDef; + +/** @addtogroup TIM3_Registers_Reset_Value + * @{ + */ + +#define TIM3_CR1_RESET_VALUE ((u8)0x00) +#define TIM3_IER_RESET_VALUE ((u8)0x00) +#define TIM3_SR1_RESET_VALUE ((u8)0x00) +#define TIM3_SR2_RESET_VALUE ((u8)0x00) +#define TIM3_EGR_RESET_VALUE ((u8)0x00) +#define TIM3_CCMR1_RESET_VALUE ((u8)0x00) +#define TIM3_CCMR2_RESET_VALUE ((u8)0x00) +#define TIM3_CCER1_RESET_VALUE ((u8)0x00) +#define TIM3_CNTRH_RESET_VALUE ((u8)0x00) +#define TIM3_CNTRL_RESET_VALUE ((u8)0x00) +#define TIM3_PSCR_RESET_VALUE ((u8)0x00) +#define TIM3_ARRH_RESET_VALUE ((u8)0xFF) +#define TIM3_ARRL_RESET_VALUE ((u8)0xFF) +#define TIM3_CCR1H_RESET_VALUE ((u8)0x00) +#define TIM3_CCR1L_RESET_VALUE ((u8)0x00) +#define TIM3_CCR2H_RESET_VALUE ((u8)0x00) +#define TIM3_CCR2L_RESET_VALUE ((u8)0x00) + +/** + * @} + */ + +/** @addtogroup TIM3_Registers_Bits_Definition + * @{ + */ +/*CR1*/ +#define TIM3_CR1_ARPE ((u8)0x80) /*!< Auto-Reload Preload Enable mask. */ +#define TIM3_CR1_OPM ((u8)0x08) /*!< One Pulse Mode mask. */ +#define TIM3_CR1_URS ((u8)0x04) /*!< Update Request Source mask. */ +#define TIM3_CR1_UDIS ((u8)0x02) /*!< Update DIsable mask. */ +#define TIM3_CR1_CEN ((u8)0x01) /*!< Counter Enable mask. */ +/*IER*/ +#define TIM3_IER_CC2IE ((u8)0x04) /*!< Capture/Compare 2 Interrupt Enable mask. */ +#define TIM3_IER_CC1IE ((u8)0x02) /*!< Capture/Compare 1 Interrupt Enable mask. */ +#define TIM3_IER_UIE ((u8)0x01) /*!< Update Interrupt Enable mask. */ +/*SR1*/ +#define TIM3_SR1_CC2IF ((u8)0x04) /*!< Capture/Compare 2 Interrupt Flag mask. */ +#define TIM3_SR1_CC1IF ((u8)0x02) /*!< Capture/Compare 1 Interrupt Flag mask. */ +#define TIM3_SR1_UIF ((u8)0x01) /*!< Update Interrupt Flag mask. */ +/*SR2*/ +#define TIM3_SR2_CC2OF ((u8)0x04) /*!< Capture/Compare 2 Overcapture Flag mask. */ +#define TIM3_SR2_CC1OF ((u8)0x02) /*!< Capture/Compare 1 Overcapture Flag mask. */ +/*EGR*/ +#define TIM3_EGR_CC2G ((u8)0x04) /*!< Capture/Compare 2 Generation mask. */ +#define TIM3_EGR_CC1G ((u8)0x02) /*!< Capture/Compare 1 Generation mask. */ +#define TIM3_EGR_UG ((u8)0x01) /*!< Update Generation mask. */ +/*CCMR*/ +#define TIM3_CCMR_ICxPSC ((u8)0x0C) /*!< Input Capture x Prescaler mask. */ +#define TIM3_CCMR_ICxF ((u8)0xF0) /*!< Input Capture x Filter mask. */ +#define TIM3_CCMR_OCM ((u8)0x70) /*!< Output Compare x Mode mask. */ +#define TIM3_CCMR_OCxPE ((u8)0x08) /*!< Output Compare x Preload Enable mask. */ +#define TIM3_CCMR_CCxS ((u8)0x03) /*!< Capture/Compare x Selection mask. */ +/*CCER1*/ +#define TIM3_CCER1_CC2P ((u8)0x20) /*!< Capture/Compare 2 output Polarity mask. */ +#define TIM3_CCER1_CC2E ((u8)0x10) /*!< Capture/Compare 2 output enable mask. */ +#define TIM3_CCER1_CC1P ((u8)0x02) /*!< Capture/Compare 1 output Polarity mask. */ +#define TIM3_CCER1_CC1E ((u8)0x01) /*!< Capture/Compare 1 output enable mask. */ +/*CNTR*/ +#define TIM3_CNTRH_CNT ((u8)0xFF) /*!< Counter Value (MSB) mask. */ +#define TIM3_CNTRL_CNT ((u8)0xFF) /*!< Counter Value (LSB) mask. */ +/*PSCR*/ +#define TIM3_PSCR_PSC ((u8)0xFF) /*!< Prescaler Value (MSB) mask. */ +/*ARR*/ +#define TIM3_ARRH_ARR ((u8)0xFF) /*!< Autoreload Value (MSB) mask. */ +#define TIM3_ARRL_ARR ((u8)0xFF) /*!< Autoreload Value (LSB) mask. */ +/*CCR1*/ +#define TIM3_CCR1H_CCR1 ((u8)0xFF) /*!< Capture/Compare 1 Value (MSB) mask. */ +#define TIM3_CCR1L_CCR1 ((u8)0xFF) /*!< Capture/Compare 1 Value (LSB) mask. */ +/*CCR2*/ +#define TIM3_CCR2H_CCR2 ((u8)0xFF) /*!< Capture/Compare 2 Value (MSB) mask. */ +#define TIM3_CCR2L_CCR2 ((u8)0xFF) /*!< Capture/Compare 2 Value (LSB) mask. */ + +/** + * @} + */ + +/*----------------------------------------------------------------------------*/ +/** + * @brief 8-bit system timer (TIM4) + */ + +typedef struct TIM4_struct +{ + vu8 CR1; /*!< control register 1 */ +#if defined STM8S103 + vu8 RESERVED1; /*!< Reserved register */ + vu8 RESERVED2; /*!< Reserved register */ +#endif + vu8 IER; /*!< interrupt enable register */ + vu8 SR1; /*!< status register 1 */ + vu8 EGR; /*!< event generation register */ + vu8 CNTR; /*!< counter register */ + vu8 PSCR; /*!< prescaler register */ + vu8 ARR; /*!< auto-reload register */ +} +TIM4_TypeDef; + +/** @addtogroup TIM4_Registers_Reset_Value + * @{ + */ + +#define TIM4_CR1_RESET_VALUE ((u8)0x00) +#define TIM4_IER_RESET_VALUE ((u8)0x00) +#define TIM4_SR1_RESET_VALUE ((u8)0x00) +#define TIM4_EGR_RESET_VALUE ((u8)0x00) +#define TIM4_CNTR_RESET_VALUE ((u8)0x00) +#define TIM4_PSCR_RESET_VALUE ((u8)0x00) +#define TIM4_ARR_RESET_VALUE ((u8)0xFF) + +/** + * @} + */ + +/** @addtogroup TIM4_Registers_Bits_Definition + * @{ + */ +/*CR1*/ +#define TIM4_CR1_ARPE ((u8)0x80) /*!< Auto-Reload Preload Enable mask. */ +#define TIM4_CR1_OPM ((u8)0x08) /*!< One Pulse Mode mask. */ +#define TIM4_CR1_URS ((u8)0x04) /*!< Update Request Source mask. */ +#define TIM4_CR1_UDIS ((u8)0x02) /*!< Update DIsable mask. */ +#define TIM4_CR1_CEN ((u8)0x01) /*!< Counter Enable mask. */ +/*IER*/ +#define TIM4_IER_UIE ((u8)0x01) /*!< Update Interrupt Enable mask. */ +/*SR1*/ +#define TIM4_SR1_UIF ((u8)0x01) /*!< Update Interrupt Flag mask. */ +/*EGR*/ +#define TIM4_EGR_UG ((u8)0x01) /*!< Update Generation mask. */ +/*CNTR*/ +#define TIM4_CNTR_CNT ((u8)0xFF) /*!< Counter Value (LSB) mask. */ +/*PSCR*/ +#define TIM4_PSCR_PSC ((u8)0x07) /*!< Prescaler Value mask. */ +/*ARR*/ +#define TIM4_ARR_ARR ((u8)0xFF) /*!< Autoreload Value mask. */ + +/** + * @} + */ + +/*----------------------------------------------------------------------------*/ +/** + * @brief 16-bit timer with synchro module (TIM5) + */ + +typedef struct TIM5_struct +{ + vu8 CR1; /*! + #define enableInterrupts() _rim_() /* enable interrupts */ + #define disableInterrupts() _sim_() /* disable interrupts */ + #define rim() _rim_() /* enable interrupts */ + #define sim() _sim_() /* disable interrupts */ + #define nop() _nop_() /* No Operation */ + #define trap() _trap_() /* Trap (soft IT) */ + #define wfi() _wfi_() /* Wait For Interrupt */ + #define halt() _halt_() /* Halt */ +#else /* COSMIC */ + #define enableInterrupts() {_asm("rim\n");} /* enable interrupts */ + #define disableInterrupts() {_asm("sim\n");} /* disable interrupts */ + #define rim() {_asm("rim\n");} /* enable interrupts */ + #define sim() {_asm("sim\n");} /* disable interrupts */ + #define nop() {_asm("nop\n");} /* No Operation */ + #define trap() {_asm("trap\n");} /* Trap (soft IT) */ + #define wfi() {_asm("wfi\n");} /* Wait For Interrupt */ + #define halt() {_asm("halt\n");} /* Halt */ +#endif + +/*============================== Handling bits ====================================*/ +/*----------------------------------------------------------------------------- +Method : I +Description : Handle the bit from the character variables. +Comments : The different parameters of commands are + - VAR : Name of the character variable where the bit is located. + - Place : Bit position in the variable (7 6 5 4 3 2 1 0) + - Value : Can be 0 (reset bit) or not 0 (set bit) + The "MskBit" command allows to select some bits in a source + variables and copy it in a destination var (return the value). + The "ValBit" command returns the value of a bit in a char + variable: the bit is reseted if it returns 0 else the bit is set. + This method generates not an optimised code yet. +-----------------------------------------------------------------------------*/ +#define SetBit(VAR,Place) ( (VAR) |= (u8)((u8)1<<(u8)(Place)) ) +#define ClrBit(VAR,Place) ( (VAR) &= (u8)((u8)((u8)1<<(u8)(Place))^(u8)255) ) + +#define ChgBit(VAR,Place) ( (VAR) ^= (u8)((u8)1<<(u8)(Place)) ) +#define AffBit(VAR,Place,Value) ((Value) ? \ + ((VAR) |= ((u8)1<<(Place))) : \ + ((VAR) &= (((u8)1<<(Place))^(u8)255))) +#define MskBit(Dest,Msk,Src) ( (Dest) = ((Msk) & (Src)) | ((~(Msk)) & (Dest)) ) + +#define ValBit(VAR,Place) ((u8)(VAR) & (u8)((u8)1<<(u8)(Place))) + +#define BYTE_0(n) ((u8)((n) & (u8)0xFF)) /*!< Returns the low byte of the 32-bit value */ +#define BYTE_1(n) ((u8)(BYTE_0((n) >> (u8)8))) /*!< Returns the second byte of the 32-bit value */ +#define BYTE_2(n) ((u8)(BYTE_0((n) >> (u8)16))) /*!< Returns the third byte of the 32-bit value */ +#define BYTE_3(n) ((u8)(BYTE_0((n) >> (u8)24))) /*!< Returns the high byte of the 32-bit value */ + +/*============================== Assert Macros ====================================*/ +#define IS_STATE_VALUE_OK(SensitivityValue) \ + (((SensitivityValue) == ENABLE) || \ + ((SensitivityValue) == DISABLE)) + +/*----------------------------------------------------------------------------- +Method : II +Description : Handle directly the bit. +Comments : The idea is to handle directly with the bit name. For that, it is + necessary to have RAM area descriptions (example: HW register...) + and the following command line for each area. + This method generates the most optimized code. +-----------------------------------------------------------------------------*/ + +#define AREA 0x00 /* The area of bits begins at address 0x10. */ + +#define BitClr(BIT) ( *((unsigned char *) (AREA+(BIT)/8)) &= (~(1<<(7-(BIT)%8))) ) +#define BitSet(BIT) ( *((unsigned char *) (AREA+(BIT)/8)) |= (1<<(7-(BIT)%8)) ) +#define BitVal(BIT) ( *((unsigned char *) (AREA+(BIT)/8)) & (1<<(7-(BIT)%8)) ) + +/* Exported functions ------------------------------------------------------- */ + +#endif /* __STM8S_H */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/ports/stm8/stm8s-periphs/stm8s_clk.h b/ports/stm8/stm8s-periphs/stm8s_clk.h new file mode 100644 index 0000000..4cbb896 --- /dev/null +++ b/ports/stm8/stm8s-periphs/stm8s_clk.h @@ -0,0 +1,404 @@ +/** + ****************************************************************************** + * @file stm8s_clk.h + * @brief This file contains all functions prototype and macros for the CLK peripheral. + * @author STMicroelectronics - MCD Application Team + * @version V1.1.1 + * @date 06/05/2009 + ****************************************************************************** + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ * @image html logo.bmp + ****************************************************************************** + */ + + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM8S_CLK_H +#define __STM8S_CLK_H + +/* Includes ------------------------------------------------------------------*/ +/* Contains the description of all STM8 hardware registers */ +#include "stm8s.h" + +/* Exported types ------------------------------------------------------------*/ +/** @addtogroup CLK_Exported_Types + * @{ + */ + +/** + * @brief Switch Mode Auto, Manual. + */ +typedef enum { + CLK_SWITCHMODE_MANUAL = (u8)0x00, /*!< Enable the manual clock switching mode */ + CLK_SWITCHMODE_AUTO = (u8)0x01 /*!< Enable the automatic clock switching mode */ +} CLK_SwitchMode_TypeDef; + +/** + * @brief Current Clock State. + */ +typedef enum { + CLK_CURRENTCLOCKSTATE_DISABLE = (u8)0x00, /*!< Current clock disable */ + CLK_CURRENTCLOCKSTATE_ENABLE = (u8)0x01 /*!< Current clock enable */ +} CLK_CurrentClockState_TypeDef; + +/** + * @brief Clock security system configuration. + */ +typedef enum { + CLK_CSSCONFIG_ENABLEWITHIT = (u8)0x05, /*!< Enable CSS with detection interrupt */ + CLK_CSSCONFIG_ENABLE = (u8)0x01, /*!< Enable CSS without detection interrupt */ + CLK_CSSCONFIG_DISABLE = (u8)0x00 /*!< Leave CSS desactivated (to be used in CLK_Init() function) */ +} CLK_CSSConfig_TypeDef; + +/** + * @brief CLK Clock Source. + */ +typedef enum { + CLK_SOURCE_HSI = (u8)0xE1, /*!< Clock Source HSI. */ + CLK_SOURCE_LSI = (u8)0xD2, /*!< Clock Source LSI. */ + CLK_SOURCE_HSE = (u8)0xB4 /*!< Clock Source HSE. */ +} CLK_Source_TypeDef; + +/** + * @brief CLK HSI Calibration Value. + */ +typedef enum { + CLK_HSITRIMVALUE_0 = (u8)0x00, /*!< HSI Calibtation Value 0 */ + CLK_HSITRIMVALUE_1 = (u8)0x01, /*!< HSI Calibtation Value 1 */ + CLK_HSITRIMVALUE_2 = (u8)0x02, /*!< HSI Calibtation Value 2 */ + CLK_HSITRIMVALUE_3 = (u8)0x03, /*!< HSI Calibtation Value 3 */ + CLK_HSITRIMVALUE_4 = (u8)0x04, /*!< HSI Calibtation Value 4 */ + CLK_HSITRIMVALUE_5 = (u8)0x05, /*!< HSI Calibtation Value 5 */ + CLK_HSITRIMVALUE_6 = (u8)0x06, /*!< HSI Calibtation Value 6 */ + CLK_HSITRIMVALUE_7 = (u8)0x07 /*!< HSI Calibtation Value 7 */ +} CLK_HSITrimValue_TypeDef; + +/** + * @brief CLK Clock Output + */ +typedef enum { + CLK_OUTPUT_HSI = (u8)0x00, /*!< Clock Output HSI */ + CLK_OUTPUT_LSI = (u8)0x02, /*!< Clock Output LSI */ + CLK_OUTPUT_HSE = (u8)0x04, /*!< Clock Output HSE */ + CLK_OUTPUT_CPU = (u8)0x08, /*!< Clock Output CPU */ + CLK_OUTPUT_CPUDIV2 = (u8)0x0A, /*!< Clock Output CPU/2 */ + CLK_OUTPUT_CPUDIV4 = (u8)0x0C, /*!< Clock Output CPU/4 */ + CLK_OUTPUT_CPUDIV8 = (u8)0x0E, /*!< Clock Output CPU/8 */ + CLK_OUTPUT_CPUDIV16 = (u8)0x10, /*!< Clock Output CPU/16 */ + CLK_OUTPUT_CPUDIV32 = (u8)0x12, /*!< Clock Output CPU/32 */ + CLK_OUTPUT_CPUDIV64 = (u8)0x14, /*!< Clock Output CPU/64 */ + CLK_OUTPUT_HSIRC = (u8)0x16, /*!< Clock Output HSI RC */ + CLK_OUTPUT_MASTER = (u8)0x18, /*!< Clock Output Master */ + CLK_OUTPUT_OTHERS = (u8)0x1A /*!< Clock Output OTHER */ +} CLK_Output_TypeDef; + +/** + * @brief CLK Enable peripheral + */ +/* Elements values convention: 0xXY + X = choice between the peripheral registers + X = 0 : PCKENR1 + X = 1 : PCKENR2 + Y = Peripheral position in the register +*/ +typedef enum { + CLK_PERIPHERAL_I2C = (u8)0x00, /*!< Peripheral Clock Enable 1, I2C */ + CLK_PERIPHERAL_SPI = (u8)0x01, /*!< Peripheral Clock Enable 1, SPI */ +#if defined(STM8S208) || defined(STM8S207) + CLK_PERIPHERAL_UART1 = (u8)0x02, /*!< Peripheral Clock Enable 1, UART1 */ +#else + CLK_PERIPHERAL_UART1 = (u8)0x03, /*!< Peripheral Clock Enable 1, UART1 */ +#endif + CLK_PERIPHERAL_UART2 = (u8)0x03, /*!< Peripheral Clock Enable 1, UART2 */ + CLK_PERIPHERAL_UART3 = (u8)0x03, /*!< Peripheral Clock Enable 1, UART3 */ + CLK_PERIPHERAL_TIMER6 = (u8)0x04, /*!< Peripheral Clock Enable 1, Timer6 */ + CLK_PERIPHERAL_TIMER4 = (u8)0x04, /*!< Peripheral Clock Enable 1, Timer4 */ + CLK_PERIPHERAL_TIMER5 = (u8)0x05, /*!< Peripheral Clock Enable 1, Timer5 */ + CLK_PERIPHERAL_TIMER2 = (u8)0x05, /*!< Peripheral Clock Enable 1, Timer2 */ + CLK_PERIPHERAL_TIMER3 = (u8)0x06, /*!< Peripheral Clock Enable 1, Timer3 */ + CLK_PERIPHERAL_TIMER1 = (u8)0x07, /*!< Peripheral Clock Enable 1, Timer1 */ + CLK_PERIPHERAL_AWU = (u8)0x12, /*!< Peripheral Clock Enable 2, AWU */ + CLK_PERIPHERAL_ADC = (u8)0x13, /*!< Peripheral Clock Enable 2, ADC */ + CLK_PERIPHERAL_CAN = (u8)0x17 /*!< Peripheral Clock Enable 2, CAN */ +} CLK_Peripheral_TypeDef; + +/** + * @brief CLK Flags. + */ +/* Elements values convention: 0xXZZ + X = choice between the flags registers + X = 1 : ICKR + X = 2 : ECKR + X = 3 : SWCR + X = 4 : CSSR + X = 5 : CCOR + ZZ = flag mask in the register (same as map file) +*/ +typedef enum { + CLK_FLAG_LSIRDY = (u16)0x0110, /*!< Low speed internal oscillator ready Flag */ + CLK_FLAG_HSIRDY = (u16)0x0102, /*!< High speed internal oscillator ready Flag */ + CLK_FLAG_HSERDY = (u16)0x0202, /*!< High speed external oscillator ready Flag */ + CLK_FLAG_SWIF = (u16)0x0308, /*!< Clock switch interrupt Flag */ + CLK_FLAG_SWBSY = (u16)0x0301, /*!< Switch busy Flag */ + CLK_FLAG_CSSD = (u16)0x0408, /*!< Clock security system detection Flag */ + CLK_FLAG_AUX = (u16)0x0402, /*!< Auxiliary oscillator connected to master clock */ + CLK_FLAG_CCOBSY = (u16)0x0504, /*!< Configurable clock output busy */ + CLK_FLAG_CCORDY = (u16)0x0502 /*!< Configurable clock output ready */ + +}CLK_Flag_TypeDef; + +/** + * @brief CLK interrupt configuration and Flags cleared by software. + */ +typedef enum { + CLK_IT_CSSD = (u8)0x0C, /*!< Clock security system detection Flag */ + CLK_IT_SWIF = (u8)0x1C /*!< Clock switch interrupt Flag */ +}CLK_IT_TypeDef; + +/** + * @brief CLK Clock Divisor. + */ +/* Warning: + 0xxxxxx = HSI divider + 1xxxxxx = CPU divider + Other bits correspond to the divider's bits mapping +*/ +typedef enum { + CLK_PRESCALER_HSIDIV1 = (u8)0x00, /*!< High speed internal clock prescaler: 1 */ + CLK_PRESCALER_HSIDIV2 = (u8)0x08, /*!< High speed internal clock prescaler: 2 */ + CLK_PRESCALER_HSIDIV4 = (u8)0x10, /*!< High speed internal clock prescaler: 4 */ + CLK_PRESCALER_HSIDIV8 = (u8)0x18, /*!< High speed internal clock prescaler: 8 */ + CLK_PRESCALER_CPUDIV1 = (u8)0x80, /*!< CPU clock division factors 1 */ + CLK_PRESCALER_CPUDIV2 = (u8)0x81, /*!< CPU clock division factors 2 */ + CLK_PRESCALER_CPUDIV4 = (u8)0x82, /*!< CPU clock division factors 4 */ + CLK_PRESCALER_CPUDIV8 = (u8)0x83, /*!< CPU clock division factors 8 */ + CLK_PRESCALER_CPUDIV16 = (u8)0x84, /*!< CPU clock division factors 16 */ + CLK_PRESCALER_CPUDIV32 = (u8)0x85, /*!< CPU clock division factors 32 */ + CLK_PRESCALER_CPUDIV64 = (u8)0x86, /*!< CPU clock division factors 64 */ + CLK_PRESCALER_CPUDIV128 = (u8)0x87 /*!< CPU clock division factors 128 */ +} CLK_Prescaler_TypeDef; + +/** + * @brief SWIM Clock divider. + */ +typedef enum { + CLK_SWIMDIVIDER_2 = (u8)0x00, /*!< SWIM clock is divided by 2 */ + CLK_SWIMDIVIDER_OTHER = (u8)0x01 /*!< SWIM clock is not divided by 2 */ +}CLK_SWIMDivider_TypeDef; + +/** + * @brief External CAN clock dividern. + */ +typedef enum{ + CLK_CANDIVIDER_1 = (u8)0x00, /*!< External CAN clock = HSE/1 */ + CLK_CANDIVIDER_2 = (u8)0x01, /*!< External CAN clock = HSE/2 */ + CLK_CANDIVIDER_3 = (u8)0x02, /*!< External CAN clock = HSE/3 */ + CLK_CANDIVIDER_4 = (u8)0x03, /*!< External CAN clock = HSE/4 */ + CLK_CANDIVIDER_5 = (u8)0x04, /*!< External CAN clock = HSE/5 */ + CLK_CANDIVIDER_6 = (u8)0x05, /*!< External CAN clock = HSE/6 */ + CLK_CANDIVIDER_7 = (u8)0x06, /*!< External CAN clock = HSE/7 */ + CLK_CANDIVIDER_8 = (u8)0x07 /*!< External CAN clock = HSE/8 */ +}CLK_CANDivider_TypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @addtogroup CLK_Exported_Constants + * @{ + */ + +#define HSI_VALUE ((u32)16000000) /*!< Typical Value of the HSI in Hz */ +#define LSI_VALUE ((u32)128000) /*!< Typical Value of the LSI in Hz */ +#define CLK_TIMEOUT ((u16)0x491) /*!< Timeout for the clock switch operation. */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup CLK_Private_Macros + * @{ + */ + +/** + * @brief Macros used by the assert function in order to check the different functions parameters. + */ + +/** + * @brief Macros used by the assert function in order to check the clock switching modes. + */ +#define IS_CLK_SWITCHMODE_OK(MODE) (((MODE) == CLK_SWITCHMODE_MANUAL) || ((MODE) == CLK_SWITCHMODE_AUTO)) + +/** + * @brief Macros used by the assert function in order to check the current clock state. + */ +#define IS_CLK_CURRENTCLOCKSTATE_OK(STATE) (((STATE) == CLK_CURRENTCLOCKSTATE_DISABLE) || ((STATE) == CLK_CURRENTCLOCKSTATE_ENABLE)) + +/** + * @brief Macros used by the assert function in order to check the CSS configuration. + */ +#define IS_CLK_CSSCONFIG_OK(CSSVALUE) (((CSSVALUE) == CLK_CSSCONFIG_ENABLEWITHIT) ||\ + ((CSSVALUE) == CLK_CSSCONFIG_ENABLE) ||\ + ((CSSVALUE) == CLK_CSSCONFIG_DISABLE)) + +/** + * @brief Macros used by the assert function in order to check the different clock sources. + */ +#define IS_CLK_SOURCE_OK(SOURCE) (((SOURCE) == CLK_SOURCE_HSI) ||\ + ((SOURCE) == CLK_SOURCE_LSI) ||\ + ((SOURCE) == CLK_SOURCE_HSE)) + +/** + * @brief Macros used by the assert function in order to check the different HSI trimming values. + */ +#define IS_CLK_HSITRIMVALUE_OK(TRIMVALUE) (((TRIMVALUE) == CLK_HSITRIMVALUE_0) ||\ + ((TRIMVALUE) == CLK_HSITRIMVALUE_1) ||\ + ((TRIMVALUE) == CLK_HSITRIMVALUE_2) ||\ + ((TRIMVALUE) == CLK_HSITRIMVALUE_3) ||\ + ((TRIMVALUE) == CLK_HSITRIMVALUE_4) ||\ + ((TRIMVALUE) == CLK_HSITRIMVALUE_5) ||\ + ((TRIMVALUE) == CLK_HSITRIMVALUE_6) ||\ + ((TRIMVALUE) == CLK_HSITRIMVALUE_7)) + +/** + * @brief Macros used by the assert function in order to check the different clocks to output. + */ +#define IS_CLK_OUTPUT_OK(OUTPUT) (((OUTPUT) == CLK_OUTPUT_HSI) ||\ + ((OUTPUT) == CLK_OUTPUT_HSE) ||\ + ((OUTPUT) == CLK_OUTPUT_LSI) ||\ + ((OUTPUT) == CLK_OUTPUT_CPU) ||\ + ((OUTPUT) == CLK_OUTPUT_CPUDIV2) ||\ + ((OUTPUT) == CLK_OUTPUT_CPUDIV4) ||\ + ((OUTPUT) == CLK_OUTPUT_CPUDIV8) ||\ + ((OUTPUT) == CLK_OUTPUT_CPUDIV16) ||\ + ((OUTPUT) == CLK_OUTPUT_CPUDIV32) ||\ + ((OUTPUT) == CLK_OUTPUT_CPUDIV64) ||\ + ((OUTPUT) == CLK_OUTPUT_HSIRC) ||\ + ((OUTPUT) == CLK_OUTPUT_MASTER) ||\ + ((OUTPUT) == CLK_OUTPUT_OTHERS)) + +/** + * @brief Macros used by the assert function in order to check the different peripheral's clock. + */ +#define IS_CLK_PERIPHERAL_OK(PERIPHERAL) (((PERIPHERAL) == CLK_PERIPHERAL_I2C) ||\ + ((PERIPHERAL) == CLK_PERIPHERAL_SPI) ||\ + ((PERIPHERAL) == CLK_PERIPHERAL_UART3) ||\ + ((PERIPHERAL) == CLK_PERIPHERAL_UART2) ||\ + ((PERIPHERAL) == CLK_PERIPHERAL_UART1) ||\ + ((PERIPHERAL) == CLK_PERIPHERAL_TIMER4) ||\ + ((PERIPHERAL) == CLK_PERIPHERAL_TIMER2) ||\ + ((PERIPHERAL) == CLK_PERIPHERAL_TIMER5) ||\ + ((PERIPHERAL) == CLK_PERIPHERAL_TIMER6) ||\ + ((PERIPHERAL) == CLK_PERIPHERAL_TIMER3) ||\ + ((PERIPHERAL) == CLK_PERIPHERAL_TIMER1) ||\ + ((PERIPHERAL) == CLK_PERIPHERAL_CAN) ||\ + ((PERIPHERAL) == CLK_PERIPHERAL_ADC) ||\ + ((PERIPHERAL) == CLK_PERIPHERAL_AWU)) + +/** + * @brief Macros used by the assert function in order to check the different clock flags. + */ +#define IS_CLK_FLAG_OK(FLAG) (((FLAG) == CLK_FLAG_LSIRDY) ||\ + ((FLAG) == CLK_FLAG_HSIRDY) ||\ + ((FLAG) == CLK_FLAG_HSERDY) ||\ + ((FLAG) == CLK_FLAG_SWIF) ||\ + ((FLAG) == CLK_FLAG_SWBSY) ||\ + ((FLAG) == CLK_FLAG_CSSD) ||\ + ((FLAG) == CLK_FLAG_AUX) ||\ + ((FLAG) == CLK_FLAG_CCOBSY) ||\ + ((FLAG) == CLK_FLAG_CCORDY)) + +/** + * @brief Macros used by the assert function in order to check the different clock IT pending bits. + */ +#define IS_CLK_IT_OK(IT) (((IT) == CLK_IT_CSSD) || ((IT) == CLK_IT_SWIF)) + +/** + * @brief Macros used by the assert function in order to check the different HSI prescaler values. + */ +#define IS_CLK_HSIPRESCALER_OK(PRESCALER) (((PRESCALER) == CLK_PRESCALER_HSIDIV1) ||\ + ((PRESCALER) == CLK_PRESCALER_HSIDIV2) ||\ + ((PRESCALER) == CLK_PRESCALER_HSIDIV4) ||\ + ((PRESCALER) == CLK_PRESCALER_HSIDIV8)) + +/** + * @brief Macros used by the assert function in order to check the different clock prescaler values. + */ +#define IS_CLK_PRESCALER_OK(PRESCALER) (((PRESCALER) == CLK_PRESCALER_HSIDIV1) ||\ + ((PRESCALER) == CLK_PRESCALER_HSIDIV2) ||\ + ((PRESCALER) == CLK_PRESCALER_HSIDIV4) ||\ + ((PRESCALER) == CLK_PRESCALER_HSIDIV8) ||\ + ((PRESCALER) == CLK_PRESCALER_CPUDIV1) ||\ + ((PRESCALER) == CLK_PRESCALER_CPUDIV2) ||\ + ((PRESCALER) == CLK_PRESCALER_CPUDIV4) ||\ + ((PRESCALER) == CLK_PRESCALER_CPUDIV8) ||\ + ((PRESCALER) == CLK_PRESCALER_CPUDIV16) ||\ + ((PRESCALER) == CLK_PRESCALER_CPUDIV32) ||\ + ((PRESCALER) == CLK_PRESCALER_CPUDIV64) ||\ + ((PRESCALER) == CLK_PRESCALER_CPUDIV128)) + +/** + * @brief Macros used by the assert function in order to check the different SWIM dividers values. + */ +#define IS_CLK_SWIMDIVIDER_OK(SWIMDIVIDER) (((SWIMDIVIDER) == CLK_SWIMDIVIDER_2) || ((SWIMDIVIDER) == CLK_SWIMDIVIDER_OTHER)) + +/** + * @brief Macros used by the assert function in order to check the different CAN dividers values. + */ +#define IS_CLK_CANDIVIDER_OK(CANDIVIDER) (((CANDIVIDER) == CLK_CANDIVIDER_1) ||\ + ((CANDIVIDER) == CLK_CANDIVIDER_2) ||\ + ((CANDIVIDER) == CLK_CANDIVIDER_3) ||\ + ((CANDIVIDER) == CLK_CANDIVIDER_4) ||\ + ((CANDIVIDER) == CLK_CANDIVIDER_5) ||\ + ((CANDIVIDER) == CLK_CANDIVIDER_6) ||\ + ((CANDIVIDER) == CLK_CANDIVIDER_7) ||\ + ((CANDIVIDER) == CLK_CANDIVIDER_8)) + +/** + * @} + */ + +/** @addtogroup CLK_Exported_functions + * @{ + */ +void CLK_DeInit(void); +void CLK_HSECmd(FunctionalState NewState); +void CLK_HSICmd(FunctionalState NewState); +void CLK_LSICmd(FunctionalState NewState); +void CLK_CCOCmd(FunctionalState NewState); +void CLK_ClockSwitchCmd(FunctionalState NewState); +void CLK_FastHaltWakeUpCmd(FunctionalState NewState); +void CLK_SlowActiveHaltWakeUpCmd(FunctionalState NewState); +void CLK_PeripheralClockConfig(CLK_Peripheral_TypeDef CLK_Peripheral, FunctionalState NewState); +ErrorStatus CLK_ClockSwitchConfig(CLK_SwitchMode_TypeDef CLK_SwitchMode, CLK_Source_TypeDef CLK_NewClock, FunctionalState ITState, CLK_CurrentClockState_TypeDef CLK_CurrentClockState); +void CLK_HSIPrescalerConfig(CLK_Prescaler_TypeDef HSIPrescaler); +void CLK_CCOConfig(CLK_Output_TypeDef CLK_CCO); +void CLK_ITConfig(CLK_IT_TypeDef CLK_IT, FunctionalState NewState); +void CLK_SYSCLKConfig(CLK_Prescaler_TypeDef CLK_Prescaler); +void CLK_SWIMConfig(CLK_SWIMDivider_TypeDef CLK_SWIMDivider); +void CLK_CANConfig(CLK_CANDivider_TypeDef CLK_CANDivider); +void CLK_ClockSecuritySystemEnable(void); +void CLK_SYSCLKEmergencyClear(void); +void CLK_AdjustHSICalibrationValue(CLK_HSITrimValue_TypeDef CLK_HSICalibrationValue); +u32 CLK_GetClockFreq(void); +CLK_Source_TypeDef CLK_GetSYSCLKSource(void); +FlagStatus CLK_GetFlagStatus(CLK_Flag_TypeDef CLK_FLAG); +ITStatus CLK_GetITStatus(CLK_IT_TypeDef CLK_IT); +void CLK_ClearITPendingBit(CLK_IT_TypeDef CLK_IT); + +/** + * @} + */ +#endif /* __STM8S_CLK_H */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/ports/stm8/stm8s-periphs/stm8s_gpio.c b/ports/stm8/stm8s-periphs/stm8s_gpio.c new file mode 100644 index 0000000..1478dd4 --- /dev/null +++ b/ports/stm8/stm8s-periphs/stm8s_gpio.c @@ -0,0 +1,242 @@ +/** + ****************************************************************************** + * @file stm8s_gpio.c + * @brief This file contains all the functions for the GPIO peripheral. + * @author STMicroelectronics - MCD Application Team + * @version V1.1.1 + * @date 06/05/2009 + ****************************************************************************** + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ * @image html logo.bmp + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm8s_gpio.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/* Public functions ----------------------------------------------------------*/ + +/** + * @addtogroup GPIO_Public_Functions + * @{ + */ + +/** + * @brief Deinitializes the GPIOx peripheral registers to their default reset + * values. + * @param[in] GPIOx : Select the GPIO peripheral number (x = A to I). + * @retval None + */ +void GPIO_DeInit(GPIO_TypeDef* GPIOx) +{ + GPIOx->ODR = GPIO_ODR_RESET_VALUE; /* Reset Output Data Register */ + GPIOx->DDR = GPIO_DDR_RESET_VALUE; /* Reset Data Direction Register */ + GPIOx->CR1 = GPIO_CR1_RESET_VALUE; /* Reset Control Register 1 */ + GPIOx->CR2 = GPIO_CR2_RESET_VALUE; /* Reset Control Register 2 */ +} + +/** + * @brief Initializes the GPIOx according to the specified parameters. + * @param[in] GPIOx : Select the GPIO peripheral number (x = A to I). + * @param[in] GPIO_Pin : This parameter contains the pin number, it can be one or many members + * of the @ref GPIO_Pin_TypeDef enumeration. + * @param[in] GPIO_Mode : This parameter can be any of the @Ref GPIO_Mode_TypeDef enumeration. + * @retval None + */ + +void GPIO_Init(GPIO_TypeDef* GPIOx, + GPIO_Pin_TypeDef GPIO_Pin, + GPIO_Mode_TypeDef GPIO_Mode) +{ + /*----------------------*/ + /* Check the parameters */ + /*----------------------*/ + + assert_param(IS_GPIO_MODE_OK(GPIO_Mode)); + assert_param(IS_GPIO_PIN_OK(GPIO_Pin)); + + /*-----------------------------*/ + /* Input/Output mode selection */ + /*-----------------------------*/ + + if ((((u8)(GPIO_Mode)) & (u8)0x80) != (u8)0x00) /* Output mode */ + { + if ((((u8)(GPIO_Mode)) & (u8)0x10) != (u8)0x00) /* High level */ + { + GPIOx->ODR |= (u8)GPIO_Pin; + } else /* Low level */ + { + GPIOx->ODR &= (u8)(~(GPIO_Pin)); + } + /* Set Output mode */ + GPIOx->DDR |= (u8)GPIO_Pin; + } else /* Input mode */ + { + /* Set Input mode */ + GPIOx->DDR &= (u8)(~(GPIO_Pin)); + } + + /*------------------------------------------------------------------------*/ + /* Pull-Up/Float (Input) or Push-Pull/Open-Drain (Output) modes selection */ + /*------------------------------------------------------------------------*/ + + if ((((u8)(GPIO_Mode)) & (u8)0x40) != (u8)0x00) /* Pull-Up or Push-Pull */ + { + GPIOx->CR1 |= (u8)GPIO_Pin; + } else /* Float or Open-Drain */ + { + GPIOx->CR1 &= (u8)(~(GPIO_Pin)); + } + + /*-----------------------------------------------------*/ + /* Interrupt (Input) or Slope (Output) modes selection */ + /*-----------------------------------------------------*/ + + if ((((u8)(GPIO_Mode)) & (u8)0x20) != (u8)0x00) /* Interrupt or Slow slope */ + { + GPIOx->CR2 |= (u8)GPIO_Pin; + } else /* No external interrupt or No slope control */ + { + GPIOx->CR2 &= (u8)(~(GPIO_Pin)); + } + +} + +/** + * @brief Writes data to the specified GPIO data port. + * @param[in] GPIOx : Select the GPIO peripheral number (x = A to I). + * @param[in] PortVal : Specifies the value to be written to the port output. + * data register. + * @retval None + * @par Required preconditions: + * The port must be configured in output mode. + */ +void GPIO_Write(GPIO_TypeDef* GPIOx, u8 PortVal) +{ + GPIOx->ODR = PortVal; +} + +/** + * @brief Writes high level to the specified GPIO pins. + * @param[in] GPIOx : Select the GPIO peripheral number (x = A to I). + * @param[in] PortPins : Specifies the pins to be turned high to the port output. + * data register. + * @retval None + * @par Required preconditions: + * The port must be configured in output mode. + */ +void GPIO_WriteHigh(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef PortPins) +{ + GPIOx->ODR |= (u8)PortPins; +} + +/** + * @brief Writes low level to the specified GPIO pins. + * @param[in] GPIOx : Select the GPIO peripheral number (x = A to I). + * @param[in] PortPins : Specifies the pins to be turned low to the port output. + * data register. + * @retval None + * @par Required preconditions: + * The port must be configured in output mode. + */ +void GPIO_WriteLow(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef PortPins) +{ + GPIOx->ODR &= (u8)(~PortPins); +} + +/** + * @brief Writes reverse level to the specified GPIO pins. + * @param[in] GPIOx : Select the GPIO peripheral number (x = A to I). + * @param[in] PortPins : Specifies the pins to be reversed to the port output. + * data register. + * @retval None + * @par Required preconditions: + * The port must be configured in output mode. + */ +void GPIO_WriteReverse(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef PortPins) +{ + GPIOx->ODR ^= (u8)PortPins; +} + +/** + * @brief Reads the specified GPIO output data port. + * @param[in] GPIOx : Select the GPIO peripheral number (x = A to I). + * @retval u8 : GPIO output data port value. + * @par Required preconditions: + * The port must be configured in input mode. + */ +u8 GPIO_ReadOutputData(GPIO_TypeDef* GPIOx) +{ + return ((u8)GPIOx->ODR); +} + +/** + * @brief Reads the specified GPIO input data port. + * @param[in] GPIOx : Select the GPIO peripheral number (x = A to I). + * @retval u8 : GPIO input data port value. + * @par Required preconditions: + * The port must be configured in input mode. + */ +u8 GPIO_ReadInputData(GPIO_TypeDef* GPIOx) +{ + return ((u8)GPIOx->IDR); +} + +/** + * @brief Reads the specified GPIO input data pin. + * @param[in] GPIOx : Select the GPIO peripheral number (x = A to I). + * @param[in] GPIO_Pin : This parameter contains the pin number, it can be one member + * of the @ref GPIO_Pin_TypeDef enumeration. + * @retval BitStatus : GPIO input pin status. + * This parameter can be any of the @ref BitStatus enumeration. + * @par Required preconditions: + * The port must be configured in input mode. + */ +BitStatus GPIO_ReadInputPin(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef GPIO_Pin) +{ + return ((BitStatus)(GPIOx->IDR & (vu8)GPIO_Pin)); +} +/** + * @brief Configures the external pull-up on GPIOx pins. + * @param[in] GPIOx : Select the GPIO peripheral number (x = A to I). + * @param[in] GPIO_Pin : This parameter contains the pin number, it can be one or many members + * of the @ref GPIO_Pin_TypeDef enumeration. + * @param[in] NewState : The new state of the pull up pin. + * This parameter can be any of the @ref FunctionalState enumeration. + * @retval None + */ +void GPIO_ExternalPullUpConfig(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef GPIO_Pin, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_GPIO_PIN_OK(GPIO_Pin)); + assert_param(IS_FUNCTIONALSTATE_OK(NewState)); + + if (NewState != DISABLE) /* External Pull-Up Set*/ + { + GPIOx->CR1 |= (u8)GPIO_Pin; + } else /* External Pull-Up Reset*/ + { + GPIOx->CR1 &= (u8)(~(GPIO_Pin)); + } +} + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/ports/stm8/stm8s-periphs/stm8s_gpio.h b/ports/stm8/stm8s-periphs/stm8s_gpio.h new file mode 100644 index 0000000..4688804 --- /dev/null +++ b/ports/stm8/stm8s-periphs/stm8s_gpio.h @@ -0,0 +1,149 @@ +/** + ****************************************************************************** + * @file stm8s_gpio.h + * @brief This file contains all functions prototype and macros for the GPIO peripheral. + * @author STMicroelectronics - MCD Application Team + * @version V1.1.1 + * @date 06/05/2009 + ****************************************************************************** + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ * @image html logo.bmp + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM8S_GPIO_H +#define __STM8S_GPIO_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm8s.h" + +/* Exported variables ------------------------------------------------------- */ +/* Exported types ------------------------------------------------------------*/ + +/** @addtogroup GPIO_Exported_Types + * @{ + */ + +/** + * @brief GPIO modes + * + * Bits definitions: + * - Bit 7: 0 = INPUT mode + * 1 = OUTPUT mode + * 1 = PULL-UP (input) or PUSH-PULL (output) + * - Bit 5: 0 = No external interrupt (input) or No slope control (output) + * 1 = External interrupt (input) or Slow control enabled (output) + * - Bit 4: 0 = Low level (output) + * 1 = High level (output push-pull) or HI-Z (output open-drain) + */ +typedef enum +{ + GPIO_MODE_IN_FL_NO_IT = (u8)0b00000000, /*!< Input floating, no external interrupt */ + GPIO_MODE_IN_PU_NO_IT = (u8)0b01000000, /*!< Input pull-up, no external interrupt */ + GPIO_MODE_IN_FL_IT = (u8)0b00100000, /*!< Input floating, external interrupt */ + GPIO_MODE_IN_PU_IT = (u8)0b01100000, /*!< Input pull-up, external interrupt */ + GPIO_MODE_OUT_OD_LOW_FAST = (u8)0b10100000, /*!< Output open-drain, low level, 10MHz */ + GPIO_MODE_OUT_PP_LOW_FAST = (u8)0b11100000, /*!< Output push-pull, low level, 10MHz */ + GPIO_MODE_OUT_OD_LOW_SLOW = (u8)0b10000000, /*!< Output open-drain, low level, 2MHz */ + GPIO_MODE_OUT_PP_LOW_SLOW = (u8)0b11000000, /*!< Output push-pull, low level, 2MHz */ + GPIO_MODE_OUT_OD_HIZ_FAST = (u8)0b10110000, /*!< Output open-drain, high-impedance level,10MHz */ + GPIO_MODE_OUT_PP_HIGH_FAST = (u8)0b11110000, /*!< Output push-pull, high level, 10MHz */ + GPIO_MODE_OUT_OD_HIZ_SLOW = (u8)0b10010000, /*!< Output open-drain, high-impedance level, 2MHz */ + GPIO_MODE_OUT_PP_HIGH_SLOW = (u8)0b11010000 /*!< Output push-pull, high level, 2MHz */ +}GPIO_Mode_TypeDef; + +/** + * @brief Definition of the GPIO pins. Used by the @ref GPIO_Init function in + * order to select the pins to be initialized. + */ + +typedef enum +{ + GPIO_PIN_0 = ((u8)0x01), /*!< Pin 0 selected */ + GPIO_PIN_1 = ((u8)0x02), /*!< Pin 1 selected */ + GPIO_PIN_2 = ((u8)0x04), /*!< Pin 2 selected */ + GPIO_PIN_3 = ((u8)0x08), /*!< Pin 3 selected */ + GPIO_PIN_4 = ((u8)0x10), /*!< Pin 4 selected */ + GPIO_PIN_5 = ((u8)0x20), /*!< Pin 5 selected */ + GPIO_PIN_6 = ((u8)0x40), /*!< Pin 6 selected */ + GPIO_PIN_7 = ((u8)0x80), /*!< Pin 7 selected */ + GPIO_PIN_LNIB = ((u8)0x0F), /*!< Low nibble pins selected */ + GPIO_PIN_HNIB = ((u8)0xF0), /*!< High nibble pins selected */ + GPIO_PIN_ALL = ((u8)0xFF) /*!< All pins selected */ +}GPIO_Pin_TypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/* Exported macros -----------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ + +/** @addtogroup GPIO_Private_Macros + * @{ + */ + +/** + * @brief Macro used by the assert function to check the different functions parameters. + */ + +/** + * @brief Macro used by the assert function in order to check the different + * values of GPIOMode_TypeDef. + */ +#define IS_GPIO_MODE_OK(MODE) \ + (((MODE) == GPIO_MODE_IN_FL_NO_IT) || \ + ((MODE) == GPIO_MODE_IN_PU_NO_IT) || \ + ((MODE) == GPIO_MODE_IN_FL_IT) || \ + ((MODE) == GPIO_MODE_IN_PU_IT) || \ + ((MODE) == GPIO_MODE_OUT_OD_LOW_FAST) || \ + ((MODE) == GPIO_MODE_OUT_PP_LOW_FAST) || \ + ((MODE) == GPIO_MODE_OUT_OD_LOW_SLOW) || \ + ((MODE) == GPIO_MODE_OUT_PP_LOW_SLOW) || \ + ((MODE) == GPIO_MODE_OUT_OD_HIZ_FAST) || \ + ((MODE) == GPIO_MODE_OUT_PP_HIGH_FAST) || \ + ((MODE) == GPIO_MODE_OUT_OD_HIZ_SLOW) || \ + ((MODE) == GPIO_MODE_OUT_PP_HIGH_SLOW)) + +/** + * @brief Macro used by the assert function in order to check the different + * values of GPIO_Pins. + */ +#define IS_GPIO_PIN_OK(PIN) ((PIN) != (u8)0x00) + +/** + * @} + */ + +/* Exported functions ------------------------------------------------------- */ +/** @addtogroup GPIO_Exported_Functions + * @{ + */ + +void GPIO_DeInit(GPIO_TypeDef* GPIOx); +void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef GPIO_Pin, GPIO_Mode_TypeDef GPIO_Mode); +void GPIO_Write(GPIO_TypeDef* GPIOx, u8 PortVal); +void GPIO_WriteHigh(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef PortPins); +void GPIO_WriteLow(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef PortPins); +void GPIO_WriteReverse(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef PortPins); +u8 GPIO_ReadInputData(GPIO_TypeDef* GPIOx); +u8 GPIO_ReadOutputData(GPIO_TypeDef* GPIOx); +BitStatus GPIO_ReadInputPin(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef GPIO_Pin); +void GPIO_ExternalPullUpConfig(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef GPIO_Pin, FunctionalState NewState); +/** + * @} + */ + +#endif /* __STM8L_GPIO_H */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/ports/stm8/stm8s-periphs/stm8s_itc.c b/ports/stm8/stm8s-periphs/stm8s_itc.c new file mode 100644 index 0000000..28d505f --- /dev/null +++ b/ports/stm8/stm8s-periphs/stm8s_itc.c @@ -0,0 +1,316 @@ +/** + ****************************************************************************** + * @file stm8s_itc.c + * @brief This file contains all the functions for the ITC peripheral. + * @author STMicroelectronics - MCD Application Team + * @version V1.1.1 + * @date 06/05/2009 + ****************************************************************************** + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ * @image html logo.bmp + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm8s_itc.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @addtogroup ITC_Private_Functions + * @{ + */ + +/** +* @brief Utility function used to read CC register. +* @par Parameters: +* None +* @retval u8 Content of CC register (in A register). + */ +u8 ITC_GetCPUCC(void) +{ +#ifdef _COSMIC_ + _asm("push cc"); + _asm("pop a"); + return; /* Ignore compiler warning, the returned value is in A register */ +#else /* _RAISONANCE_ */ + return _getCC_(); +#endif /* _COSMIC_*/ +} + + +/** + * @} + */ + +/* Public functions ----------------------------------------------------------*/ + +/** @addtogroup ITC_Public_Functions + * @{ + */ + +/** +* @brief Deinitializes the ITC registers to their default reset value. +* @par Parameters: +* None +* @retval +* None + */ +void ITC_DeInit(void) +{ + ITC->ISPR1 = ITC_SPRX_RESET_VALUE; + ITC->ISPR2 = ITC_SPRX_RESET_VALUE; + ITC->ISPR3 = ITC_SPRX_RESET_VALUE; + ITC->ISPR4 = ITC_SPRX_RESET_VALUE; + ITC->ISPR5 = ITC_SPRX_RESET_VALUE; + ITC->ISPR6 = ITC_SPRX_RESET_VALUE; + ITC->ISPR7 = ITC_SPRX_RESET_VALUE; + ITC->ISPR8 = ITC_SPRX_RESET_VALUE; +} + +/** +* @brief Get the software interrupt priority bits (I1, I0) value from CPU CC register. +* @par Parameters: +* None +* @retval u8 The software interrupt priority bits value. + */ +u8 ITC_GetSoftIntStatus(void) +{ + return (u8)(ITC_GetCPUCC() & CPU_CC_I1I0); +} + +/** +* @brief Get the software priority of the specified interrupt source. +* @param[in] IrqNum The IRQ number to access. +* @retval ITC_PriorityLevel_TypeDef The software priority of the interrupt source. + */ +ITC_PriorityLevel_TypeDef ITC_GetSoftwarePriority(ITC_Irq_TypeDef IrqNum) +{ + + u8 Value = 0; + u8 Mask; + + /* Check function parameters */ + assert_param(IS_ITC_IRQ_OK((u8)IrqNum)); + + /* Define the mask corresponding to the bits position in the SPR register */ + Mask = (u8)(0x03U << (((u8)IrqNum % 4U) * 2U)); + + switch (IrqNum) + { + case ITC_IRQ_TLI: /* TLI software priority can be read but has no meaning */ + case ITC_IRQ_AWU: + case ITC_IRQ_CLK: + case ITC_IRQ_PORTA: + Value = (u8)(ITC->ISPR1 & Mask); /* Read software priority */ + break; + case ITC_IRQ_PORTB: + case ITC_IRQ_PORTC: + case ITC_IRQ_PORTD: + case ITC_IRQ_PORTE: + Value = (u8)(ITC->ISPR2 & Mask); /* Read software priority */ + break; +#ifdef STM8S208 + case ITC_IRQ_CAN_RX: + case ITC_IRQ_CAN_TX: +#endif /*STM8S208*/ + +#ifdef STM8S903 + case ITC_IRQ_PORTF: +#endif /*STM8S903*/ + + case ITC_IRQ_SPI: + case ITC_IRQ_TIM1_OVF: + Value = (u8)(ITC->ISPR3 & Mask); /* Read software priority */ + break; + case ITC_IRQ_TIM1_CAPCOM: +#ifdef STM8S903 + case ITC_IRQ_TIM5_OVFTRI: + case ITC_IRQ_TIM5_CAPCOM: +#else + case ITC_IRQ_TIM2_OVF: + case ITC_IRQ_TIM2_CAPCOM: +#endif /*STM8S903*/ + + case ITC_IRQ_TIM3_OVF: + Value = (u8)(ITC->ISPR4 & Mask); /* Read software priority */ + break; + case ITC_IRQ_TIM3_CAPCOM: + case ITC_IRQ_UART1_TX: + case ITC_IRQ_UART1_RX: + case ITC_IRQ_I2C: + Value = (u8)(ITC->ISPR5 & Mask); /* Read software priority */ + break; +#ifdef STM8S105 + case ITC_IRQ_UART2_TX: + case ITC_IRQ_UART2_RX: +#endif /*STM8S105*/ + +#if defined(STM8S208) ||defined(STM8S207) + case ITC_IRQ_UART3_TX: + case ITC_IRQ_UART3_RX: + case ITC_IRQ_ADC2: +#endif /*STM8S208 or STM8S207*/ + +#if defined(STM8S105) ||defined(STM8S103) ||defined(STM8S905) + case ITC_IRQ_ADC1: +#endif /*STM8S105, STM8S103 or STM8S905 */ + +#ifdef STM8S903 + case ITC_IRQ_TIM6_OVFTRI: +#else + case ITC_IRQ_TIM4_OVF: +#endif /*STM8S903*/ + Value = (u8)(ITC->ISPR6 & Mask); /* Read software priority */ + break; + case ITC_IRQ_EEPROM_EEC: + Value = (u8)(ITC->ISPR7 & Mask); /* Read software priority */ + break; + default: + break; + } + + Value >>= (u8)(((u8)IrqNum % 4u) * 2u); + + return((ITC_PriorityLevel_TypeDef)Value); + +} + +/** +* @brief Set the software priority of the specified interrupt source. +* @param[in] IrqNum The interrupt source to access. +* @param[in] PriorityValue The software priority value to set. +* @retval ITC_PriorityLevel_TypeDef The software priority of the interrupt source. +* @par Required preconditions: +* - The modification of the software priority is only possible when the interrupts are disabled. +* - The normal behavior is to disable the interrupts before calling this function, and re-enable it after. +* - The priority level 0 cannot be set (see product specification for more details). +*/ +void ITC_SetSoftwarePriority(ITC_Irq_TypeDef IrqNum, ITC_PriorityLevel_TypeDef PriorityValue) +{ + + u8 Mask; + u8 NewPriority; + + /* Check function parameters */ + assert_param(IS_ITC_IRQ_OK((u8)IrqNum)); + assert_param(IS_ITC_PRIORITY_OK(PriorityValue)); + + /* Check if interrupts are disabled */ + assert_param(IS_ITC_INTERRUPTS_DISABLED); + + /* Define the mask corresponding to the bits position in the SPR register */ + /* The mask is reversed in order to clear the 2 bits after more easily */ + Mask = (u8)(~(u8)(0x03U << (((u8)IrqNum % 4U) * 2U))); + + /* Define the new priority to write */ + NewPriority = (u8)((u8)(PriorityValue) << (((u8)IrqNum % 4U) * 2U)); + + switch (IrqNum) + { + + case ITC_IRQ_TLI: /* TLI software priority can be written but has no meaning */ + case ITC_IRQ_AWU: + case ITC_IRQ_CLK: + case ITC_IRQ_PORTA: + ITC->ISPR1 &= Mask; + ITC->ISPR1 |= NewPriority; + break; + + case ITC_IRQ_PORTB: + case ITC_IRQ_PORTC: + case ITC_IRQ_PORTD: + case ITC_IRQ_PORTE: + ITC->ISPR2 &= Mask; + ITC->ISPR2 |= NewPriority; + break; + +#ifdef STM8S208 + case ITC_IRQ_CAN_RX: + case ITC_IRQ_CAN_TX: +#endif /*STM8S208*/ + +#ifdef STM8S903 + case ITC_IRQ_PORTF: +#endif /*STM8S903*/ + case ITC_IRQ_SPI: + case ITC_IRQ_TIM1_OVF: + ITC->ISPR3 &= Mask; + ITC->ISPR3 |= NewPriority; + break; + + case ITC_IRQ_TIM1_CAPCOM: +#ifdef STM8S903 + case ITC_IRQ_TIM5_OVFTRI: + case ITC_IRQ_TIM5_CAPCOM: +#else + case ITC_IRQ_TIM2_OVF: + case ITC_IRQ_TIM2_CAPCOM: +#endif /*STM8S903*/ + + case ITC_IRQ_TIM3_OVF: + ITC->ISPR4 &= Mask; + ITC->ISPR4 |= NewPriority; + break; + + case ITC_IRQ_TIM3_CAPCOM: + case ITC_IRQ_UART1_TX: + case ITC_IRQ_UART1_RX: + case ITC_IRQ_I2C: + ITC->ISPR5 &= Mask; + ITC->ISPR5 |= NewPriority; + break; + +#ifdef STM8S105 + case ITC_IRQ_UART2_TX: + case ITC_IRQ_UART2_RX: +#endif /*STM8S105*/ + +#if defined(STM8S208) ||defined(STM8S207) + case ITC_IRQ_UART3_TX: + case ITC_IRQ_UART3_RX: + case ITC_IRQ_ADC2: +#endif /*STM8S208 or STM8S207*/ + +#if defined(STM8S105) ||defined(STM8S103) ||defined(STM8S905) + case ITC_IRQ_ADC1: +#endif /*STM8S105, STM8S103 or STM8S905 */ + +#ifdef STM8S903 + case ITC_IRQ_TIM6_OVFTRI: +#else + case ITC_IRQ_TIM4_OVF: +#endif /*STM8S903*/ + ITC->ISPR6 &= Mask; + ITC->ISPR6 |= NewPriority; + break; + + case ITC_IRQ_EEPROM_EEC: + ITC->ISPR7 &= Mask; + ITC->ISPR7 |= NewPriority; + break; + + default: + break; + + } + +} + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/ports/stm8/stm8s-periphs/stm8s_itc.h b/ports/stm8/stm8s-periphs/stm8s_itc.h new file mode 100644 index 0000000..31a7659 --- /dev/null +++ b/ports/stm8/stm8s-periphs/stm8s_itc.h @@ -0,0 +1,168 @@ +/** + ****************************************************************************** + * @file stm8s_itc.h + * @brief This file contains all functions prototype and macros for the ITC peripheral. + * @author STMicroelectronics - MCD Application Team + * @version V1.1.1 + * @date 06/05/2009 + ****************************************************************************** + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ * @image html logo.bmp + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM8S_ITC_H__ +#define __STM8S_ITC_H__ + +/* Includes ------------------------------------------------------------------*/ +#include "stm8s.h" + +/* Exported types ------------------------------------------------------------*/ + +/** @addtogroup ITC_Exported_Types + * @{ + */ + +/** + * @brief ITC Interrupt Lines selection + */ +typedef enum { + ITC_IRQ_TLI = (u8)0, + ITC_IRQ_AWU = (u8)1, + ITC_IRQ_CLK = (u8)2, + ITC_IRQ_PORTA = (u8)3, + ITC_IRQ_PORTB = (u8)4, + ITC_IRQ_PORTC = (u8)5, + ITC_IRQ_PORTD = (u8)6, + ITC_IRQ_PORTE = (u8)7, + +#ifdef STM8S208 + ITC_IRQ_CAN_RX = (u8)8, + ITC_IRQ_CAN_TX = (u8)9, +#endif /*STM8S208*/ + +#ifdef STM8S903 + ITC_IRQ_PORTF = (u8)8, +#endif /*STM8S903*/ + + ITC_IRQ_SPI = (u8)10, + ITC_IRQ_TIM1_OVF = (u8)11, + ITC_IRQ_TIM1_CAPCOM = (u8)12, + +#ifdef STM8S903 + ITC_IRQ_TIM5_OVFTRI = (u8)13, + ITC_IRQ_TIM5_CAPCOM = (u8)14, +#else + ITC_IRQ_TIM2_OVF = (u8)13, + ITC_IRQ_TIM2_CAPCOM = (u8)14, +#endif /*STM8S903*/ + + ITC_IRQ_TIM3_OVF = (u8)15, + ITC_IRQ_TIM3_CAPCOM = (u8)16, + ITC_IRQ_UART1_TX = (u8)17, + ITC_IRQ_UART1_RX = (u8)18, + ITC_IRQ_I2C = (u8)19, + +#ifdef STM8S105 + ITC_IRQ_UART2_TX = (u8)20, + ITC_IRQ_UART2_RX = (u8)21, +#endif /*STM8S105*/ + +#if defined(STM8S208) ||defined(STM8S207) + ITC_IRQ_UART3_TX = (u8)20, + ITC_IRQ_UART3_RX = (u8)21, + ITC_IRQ_ADC2 = (u8)22, +#endif /*STM8S208 or STM8S207*/ + +#if defined(STM8S105) ||defined(STM8S103) ||defined(STM8S905) + ITC_IRQ_ADC1 = (u8)22, +#endif /*STM8S105, STM8S103 or STM8S905 */ + +#ifdef STM8S903 + ITC_IRQ_TIM6_OVFTRI = (u8)23, +#else + ITC_IRQ_TIM4_OVF = (u8)23, +#endif /*STM8S903*/ + + ITC_IRQ_EEPROM_EEC = (u8)24 +} ITC_Irq_TypeDef; + +/** + * @brief ITC Priority Levels selection + */ +typedef enum { + ITC_PRIORITYLEVEL_0 = (u8)0x02, /*!< Software priority level 0 (cannot be written) */ + ITC_PRIORITYLEVEL_1 = (u8)0x01, /*!< Software priority level 1 */ + ITC_PRIORITYLEVEL_2 = (u8)0x00, /*!< Software priority level 2 */ + ITC_PRIORITYLEVEL_3 = (u8)0x03 /*!< Software priority level 3 */ +} ITC_PriorityLevel_TypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @addtogroup ITC_Exported_Constants + * @{ + */ + +#define CPU_SOFT_INT_DISABLED ((u8)0x28) /*!< Mask for I1 and I0 bits in CPU_CC register */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ + +/** + * @brief Macros used by the assert function in order to check the different functions parameters. + * @addtogroup ITC_Private_Macros + * @{ + */ + +/* Used by assert function */ +#define IS_ITC_IRQ_OK(IRQ) ((IRQ) <= (u8)24) + +/* Used by assert function */ +#define IS_ITC_PRIORITY_OK(PriorityValue) \ + (((PriorityValue) == ITC_PRIORITYLEVEL_0) || \ + ((PriorityValue) == ITC_PRIORITYLEVEL_1) || \ + ((PriorityValue) == ITC_PRIORITYLEVEL_2) || \ + ((PriorityValue) == ITC_PRIORITYLEVEL_3)) + +/* Used by assert function */ +#define IS_ITC_INTERRUPTS_DISABLED (ITC_GetSoftIntStatus() == CPU_SOFT_INT_DISABLED) + +/** + * @} + */ + +/* Exported functions ------------------------------------------------------- */ + +/** @addtogroup ITC_Exported_Functions + * @{ + */ + +u8 ITC_GetCPUCC(void); +void ITC_DeInit(void); +u8 ITC_GetSoftIntStatus(void); +void ITC_SetSoftwarePriority(ITC_Irq_TypeDef IrqNum, ITC_PriorityLevel_TypeDef PriorityValue); +ITC_PriorityLevel_TypeDef ITC_GetSoftwarePriority(ITC_Irq_TypeDef IrqNum); + +/** + * @} + */ + +#endif /* __STM8S_ITC_H__ */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/ports/stm8/stm8s-periphs/stm8s_tim1.c b/ports/stm8/stm8s-periphs/stm8s_tim1.c new file mode 100644 index 0000000..3405286 --- /dev/null +++ b/ports/stm8/stm8s-periphs/stm8s_tim1.c @@ -0,0 +1,2330 @@ +/** + ****************************************************************************** + * @file stm8s_tim1.c + * @brief This file contains all the functions for the TIM1 peripheral. + * @author STMicroelectronics - MCD Application Team + * @version V1.1.1 + * @date 06/05/2009 + ****************************************************************************** + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ * @image html logo.bmp + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm8s_tim1.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +static void TI1_Config(u8 TIM1_ICPolarity, u8 TIM1_ICSelection, + u8 TIM1_ICFilter); +static void TI2_Config(u8 TIM1_ICPolarity, u8 TIM1_ICSelection, + u8 TIM1_ICFilter); +static void TI3_Config(u8 TIM1_ICPolarity, u8 TIM1_ICSelection, + u8 TIM1_ICFilter); +static void TI4_Config(u8 TIM1_ICPolarity, u8 TIM1_ICSelection, + u8 TIM1_ICFilter); + +/** + * @addtogroup TIM1_Public_Functions + * @{ + */ + +/** + * @brief Deinitializes the TIM1 peripheral registers to their default reset values. + * @par Parameters: + * None + * @retval None + */ +void TIM1_DeInit(void) +{ + TIM1->CR1 = TIM1_CR1_RESET_VALUE; + TIM1->CR2 = TIM1_CR2_RESET_VALUE; + TIM1->SMCR = TIM1_SMCR_RESET_VALUE; + TIM1->ETR = TIM1_ETR_RESET_VALUE; + TIM1->IER = TIM1_IER_RESET_VALUE; + TIM1->SR2 = TIM1_SR2_RESET_VALUE; + /* Disable channels */ + TIM1->CCER1 = TIM1_CCER1_RESET_VALUE; + TIM1->CCER2 = TIM1_CCER2_RESET_VALUE; + /* Configure channels as inputs: it is necessary if lock level is equal to 2 or 3 */ + TIM1->CCMR1 = 0x01; + TIM1->CCMR2 = 0x01; + TIM1->CCMR3 = 0x01; + TIM1->CCMR4 = 0x01; + /* Then reset channel registers: it also works if lock level is equal to 2 or 3 */ + TIM1->CCER1 = TIM1_CCER1_RESET_VALUE; + TIM1->CCER2 = TIM1_CCER2_RESET_VALUE; + TIM1->CCMR1 = TIM1_CCMR1_RESET_VALUE; + TIM1->CCMR2 = TIM1_CCMR2_RESET_VALUE; + TIM1->CCMR3 = TIM1_CCMR3_RESET_VALUE; + TIM1->CCMR4 = TIM1_CCMR4_RESET_VALUE; + TIM1->CNTRH = TIM1_CNTRH_RESET_VALUE; + TIM1->CNTRL = TIM1_CNTRL_RESET_VALUE; + TIM1->PSCRH = TIM1_PSCRH_RESET_VALUE; + TIM1->PSCRL = TIM1_PSCRL_RESET_VALUE; + TIM1->ARRH = TIM1_ARRH_RESET_VALUE; + TIM1->ARRL = TIM1_ARRL_RESET_VALUE; + TIM1->CCR1H = TIM1_CCR1H_RESET_VALUE; + TIM1->CCR1L = TIM1_CCR1L_RESET_VALUE; + TIM1->CCR2H = TIM1_CCR2H_RESET_VALUE; + TIM1->CCR2L = TIM1_CCR2L_RESET_VALUE; + TIM1->CCR3H = TIM1_CCR3H_RESET_VALUE; + TIM1->CCR3L = TIM1_CCR3L_RESET_VALUE; + TIM1->CCR4H = TIM1_CCR4H_RESET_VALUE; + TIM1->CCR4L = TIM1_CCR4L_RESET_VALUE; + TIM1->OISR = TIM1_OISR_RESET_VALUE; + TIM1->EGR = 0x01; /* TIM1_EGR_UG */ + TIM1->DTR = TIM1_DTR_RESET_VALUE; + TIM1->BKR = TIM1_BKR_RESET_VALUE; + TIM1->RCR = TIM1_RCR_RESET_VALUE; + TIM1->SR1 = TIM1_SR1_RESET_VALUE; +} + +/** + * @brief Initializes the TIM1 Time Base Unit according to the specified parameters. + * @param[in] TIM1_Prescaler specifies the Prescaler value. + * @param[in] TIM1_CounterMode specifies the counter mode from @ref TIM1_CounterMode_TypeDef . + * @param[in] TIM1_Period specifies the Period value. + * @param[in] TIM1_RepetitionCounter specifies the Repetition counter value + * @retval None + */ +void TIM1_TimeBaseInit(u16 TIM1_Prescaler, + TIM1_CounterMode_TypeDef TIM1_CounterMode, + u16 TIM1_Period, + u8 TIM1_RepetitionCounter) +{ + + /* Check parameters */ + assert_param(IS_TIM1_COUNTER_MODE_OK(TIM1_CounterMode)); + + /* Set the Autoreload value */ + TIM1->ARRH = (u8)(TIM1_Period >> 8); + TIM1->ARRL = (u8)(TIM1_Period); + + /* Set the Prescaler value */ + TIM1->PSCRH = (u8)(TIM1_Prescaler >> 8); + TIM1->PSCRL = (u8)(TIM1_Prescaler); + + /* Select the Counter Mode */ + TIM1->CR1 = (u8)(((TIM1->CR1) & (u8)(~(TIM1_CR1_CMS | TIM1_CR1_DIR))) | (u8)(TIM1_CounterMode)); + + /* Set the Repetition Counter value */ + TIM1->RCR = TIM1_RepetitionCounter; + +} + +/** + * @brief Initializes the TIM1 Channel1 according to the specified parameters. + * @param[in] TIM1_OCMode specifies the Output Compare mode from @ref TIM1_OCMode_TypeDef. + * @param[in] TIM1_OutputState specifies the Output State from @ref TIM1_OutputState_TypeDef. + * @param[in] TIM1_OutputNState specifies the Complementary Output State from @ref TIM1_OutputNState_TypeDef. + * @param[in] TIM1_Pulse specifies the Pulse width value. + * @param[in] TIM1_OCPolarity specifies the Output Compare Polarity from @ref TIM1_OCPolarity_TypeDef. + * @param[in] TIM1_OCNPolarity specifies the Complementary Output Compare Polarity from @ref TIM1_OCNPolarity_TypeDef. + * @param[in] TIM1_OCIdleState specifies the Output Compare Idle State from @ref TIM1_OCIdleState_TypeDef. + * @param[in] TIM1_OCNIdleState specifies the Complementary Output Compare Idle State from @ref TIM1_OCIdleState_TypeDef. + * @retval None + */ +void TIM1_OC1Init(TIM1_OCMode_TypeDef TIM1_OCMode, + TIM1_OutputState_TypeDef TIM1_OutputState, + TIM1_OutputNState_TypeDef TIM1_OutputNState, + u16 TIM1_Pulse, + TIM1_OCPolarity_TypeDef TIM1_OCPolarity, + TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity, + TIM1_OCIdleState_TypeDef TIM1_OCIdleState, + TIM1_OCNIdleState_TypeDef TIM1_OCNIdleState) +{ + /* Check the parameters */ + assert_param(IS_TIM1_OC_MODE_OK(TIM1_OCMode)); + assert_param(IS_TIM1_OUTPUT_STATE_OK(TIM1_OutputState)); + assert_param(IS_TIM1_OUTPUTN_STATE_OK(TIM1_OutputNState)); + assert_param(IS_TIM1_OC_POLARITY_OK(TIM1_OCPolarity)); + assert_param(IS_TIM1_OCN_POLARITY_OK(TIM1_OCNPolarity)); + assert_param(IS_TIM1_OCIDLE_STATE_OK(TIM1_OCIdleState)); + assert_param(IS_TIM1_OCNIDLE_STATE_OK(TIM1_OCNIdleState)); + + /* Disable the Channel 1: Reset the CCE Bit, Set the Output State , the Output N State, the Output Polarity & the Output N Polarity*/ + TIM1->CCER1 &= (u8)(~( TIM1_CCER1_CC1E | TIM1_CCER1_CC1NE | TIM1_CCER1_CC1P | TIM1_CCER1_CC1NP)); + /* Set the Output State & Set the Output N State & Set the Output Polarity & Set the Output N Polarity */ + TIM1->CCER1 |= (u8)((TIM1_OutputState & TIM1_CCER1_CC1E ) | (TIM1_OutputNState & TIM1_CCER1_CC1NE ) | (TIM1_OCPolarity & TIM1_CCER1_CC1P ) | (TIM1_OCNPolarity & TIM1_CCER1_CC1NP )); + + /* Reset the Output Compare Bits & Set the Ouput Compare Mode */ + TIM1->CCMR1 = (u8)((TIM1->CCMR1 & (u8)(~TIM1_CCMR_OCM)) | (u8)TIM1_OCMode); + + /* Reset the Output Idle state & the Output N Idle state bits */ + TIM1->OISR &= (u8)(~(TIM1_OISR_OIS1 | TIM1_OISR_OIS1N)); + /* Set the Output Idle state & the Output N Idle state configuration */ + TIM1->OISR |= (u8)(( TIM1_OCIdleState & TIM1_OISR_OIS1 ) | ( TIM1_OCNIdleState & TIM1_OISR_OIS1N )); + + /* Set the Pulse value */ + TIM1->CCR1H = (u8)(TIM1_Pulse >> 8); + TIM1->CCR1L = (u8)(TIM1_Pulse); +} + +/** + * @brief Initializes the TIM1 Channel2 according to the specified parameters. + * @param[in] TIM1_OCMode specifies the Output Compare mode from @ref TIM1_OCMode_TypeDef. + * @param[in] TIM1_OutputState specifies the Output State from @ref TIM1_OutputState_TypeDef. + * @param[in] TIM1_OutputNState specifies the Complementary Output State from @ref TIM1_OutputNState_TypeDef. + * @param[in] TIM1_Pulse specifies the Pulse width value. + * @param[in] TIM1_OCPolarity specifies the Output Compare Polarity from @ref TIM1_OCPolarity_TypeDef. + * @param[in] TIM1_OCNPolarity specifies the Complementary Output Compare Polarity from @ref TIM1_OCNPolarity_TypeDef. + * @param[in] TIM1_OCIdleState specifies the Output Compare Idle State from @ref TIM1_OCIdleState_TypeDef. + * @param[in] TIM1_OCNIdleState specifies the Complementary Output Compare Idle State from @ref TIM1_OCIdleState_TypeDef. + * @retval None + */ +void TIM1_OC2Init(TIM1_OCMode_TypeDef TIM1_OCMode, + TIM1_OutputState_TypeDef TIM1_OutputState, + TIM1_OutputNState_TypeDef TIM1_OutputNState, + u16 TIM1_Pulse, + TIM1_OCPolarity_TypeDef TIM1_OCPolarity, + TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity, + TIM1_OCIdleState_TypeDef TIM1_OCIdleState, + TIM1_OCNIdleState_TypeDef TIM1_OCNIdleState) +{ + + + /* Check the parameters */ + assert_param(IS_TIM1_OC_MODE_OK(TIM1_OCMode)); + assert_param(IS_TIM1_OUTPUT_STATE_OK(TIM1_OutputState)); + assert_param(IS_TIM1_OUTPUTN_STATE_OK(TIM1_OutputNState)); + assert_param(IS_TIM1_OC_POLARITY_OK(TIM1_OCPolarity)); + assert_param(IS_TIM1_OCN_POLARITY_OK(TIM1_OCNPolarity)); + assert_param(IS_TIM1_OCIDLE_STATE_OK(TIM1_OCIdleState)); + assert_param(IS_TIM1_OCNIDLE_STATE_OK(TIM1_OCNIdleState)); + + /* Disable the Channel 1: Reset the CCE Bit, Set the Output State , the Output N State, the Output Polarity & the Output N Polarity*/ + TIM1->CCER1 &= (u8)(~( TIM1_CCER1_CC2E | TIM1_CCER1_CC2NE | TIM1_CCER1_CC2P | TIM1_CCER1_CC2NP)); + /* Set the Output State & Set the Output N State & Set the Output Polarity & Set the Output N Polarity */ + TIM1->CCER1 |= (u8)((TIM1_OutputState & TIM1_CCER1_CC2E ) | (TIM1_OutputNState & TIM1_CCER1_CC2NE ) | (TIM1_OCPolarity & TIM1_CCER1_CC2P ) | (TIM1_OCNPolarity & TIM1_CCER1_CC2NP )); + + + /* Reset the Output Compare Bits & Set the Ouput Compare Mode */ + TIM1->CCMR2 = (u8)((TIM1->CCMR2 & (u8)(~TIM1_CCMR_OCM)) | (u8)TIM1_OCMode); + + /* Reset the Output Idle state & the Output N Idle state bits */ + TIM1->OISR &= (u8)(~(TIM1_OISR_OIS2 | TIM1_OISR_OIS2N)); + /* Set the Output Idle state & the Output N Idle state configuration */ + TIM1->OISR |= (u8)((TIM1_OISR_OIS2 & TIM1_OCIdleState) | (TIM1_OISR_OIS2N & TIM1_OCNIdleState)); + + /* Set the Pulse value */ + TIM1->CCR2H = (u8)(TIM1_Pulse >> 8); + TIM1->CCR2L = (u8)(TIM1_Pulse); + +} + +/** + * @brief Initializes the TIM1 Channel3 according to the specified parameters. + * @param[in] TIM1_OCMode specifies the Output Compare mode from @ref TIM1_OCMode_TypeDef. + * @param[in] TIM1_OutputState specifies the Output State from @ref TIM1_OutputState_TypeDef. + * @param[in] TIM1_OutputNState specifies the Complementary Output State from @ref TIM1_OutputNState_TypeDef. + * @param[in] TIM1_Pulse specifies the Pulse width value. + * @param[in] TIM1_OCPolarity specifies the Output Compare Polarity from @ref TIM1_OCPolarity_TypeDef. + * @param[in] TIM1_OCNPolarity specifies the Complementary Output Compare Polarity from @ref TIM1_OCNPolarity_TypeDef. + * @param[in] TIM1_OCIdleState specifies the Output Compare Idle State from @ref TIM1_OCIdleState_TypeDef. + * @param[in] TIM1_OCNIdleState specifies the Complementary Output Compare Idle State from @ref TIM1_OCIdleState_TypeDef. + * @retval None + */ +void TIM1_OC3Init(TIM1_OCMode_TypeDef TIM1_OCMode, + TIM1_OutputState_TypeDef TIM1_OutputState, + TIM1_OutputNState_TypeDef TIM1_OutputNState, + u16 TIM1_Pulse, + TIM1_OCPolarity_TypeDef TIM1_OCPolarity, + TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity, + TIM1_OCIdleState_TypeDef TIM1_OCIdleState, + TIM1_OCNIdleState_TypeDef TIM1_OCNIdleState) +{ + + /* Check the parameters */ + assert_param(IS_TIM1_OC_MODE_OK(TIM1_OCMode)); + assert_param(IS_TIM1_OUTPUT_STATE_OK(TIM1_OutputState)); + assert_param(IS_TIM1_OUTPUTN_STATE_OK(TIM1_OutputNState)); + assert_param(IS_TIM1_OC_POLARITY_OK(TIM1_OCPolarity)); + assert_param(IS_TIM1_OCN_POLARITY_OK(TIM1_OCNPolarity)); + assert_param(IS_TIM1_OCIDLE_STATE_OK(TIM1_OCIdleState)); + assert_param(IS_TIM1_OCNIDLE_STATE_OK(TIM1_OCNIdleState)); + + /* Disable the Channel 1: Reset the CCE Bit, Set the Output State , the Output N State, the Output Polarity & the Output N Polarity*/ + TIM1->CCER2 &= (u8)(~( TIM1_CCER2_CC3E | TIM1_CCER2_CC3NE | TIM1_CCER2_CC3P | TIM1_CCER2_CC3NP)); + /* Set the Output State & Set the Output N State & Set the Output Polarity & Set the Output N Polarity */ + TIM1->CCER2 |= (u8)((TIM1_OutputState & TIM1_CCER2_CC3E ) | (TIM1_OutputNState & TIM1_CCER2_CC3NE ) | (TIM1_OCPolarity & TIM1_CCER2_CC3P ) | (TIM1_OCNPolarity & TIM1_CCER2_CC3NP )); + + + + /* Reset the Output Compare Bits & Set the Ouput Compare Mode */ + TIM1->CCMR3 = (u8)((TIM1->CCMR3 & (u8)(~TIM1_CCMR_OCM)) | (u8)TIM1_OCMode); + + /* Reset the Output Idle state & the Output N Idle state bits */ + TIM1->OISR &= (u8)(~(TIM1_OISR_OIS3 | TIM1_OISR_OIS3N)); + /* Set the Output Idle state & the Output N Idle state configuration */ + TIM1->OISR |= (u8)((TIM1_OISR_OIS3 & TIM1_OCIdleState) | (TIM1_OISR_OIS3N & TIM1_OCNIdleState)); + + /* Set the Pulse value */ + TIM1->CCR3H = (u8)(TIM1_Pulse >> 8); + TIM1->CCR3L = (u8)(TIM1_Pulse); + +} + +/** + * @brief Initializes the TIM1 Channel4 according to the specified parameters. + * @param[in] TIM1_OCMode specifies the Output Compare mode from @ref TIM1_OCMode_TypeDef. + * @param[in] TIM1_OutputState specifies the Output State from @ref TIM1_OutputState_TypeDef. + * @param[in] TIM1_Pulse specifies the Pulse width value. + * @param[in] TIM1_OCPolarity specifies the Output Compare Polarity from @ref TIM1_OCPolarity_TypeDef. + * @param[in] TIM1_OCIdleState specifies the Output Compare Idle State from @ref TIM1_OCIdleState_TypeDef. + * @retval None + */ +void TIM1_OC4Init(TIM1_OCMode_TypeDef TIM1_OCMode, + TIM1_OutputState_TypeDef TIM1_OutputState, + u16 TIM1_Pulse, + TIM1_OCPolarity_TypeDef TIM1_OCPolarity, + TIM1_OCIdleState_TypeDef TIM1_OCIdleState) +{ + + /* Check the parameters */ + assert_param(IS_TIM1_OC_MODE_OK(TIM1_OCMode)); + assert_param(IS_TIM1_OUTPUT_STATE_OK(TIM1_OutputState)); + assert_param(IS_TIM1_OC_POLARITY_OK(TIM1_OCPolarity)); + assert_param(IS_TIM1_OCIDLE_STATE_OK(TIM1_OCIdleState)); + + + + /* Disable the Channel 4: Reset the CCE Bit */ + TIM1->CCER2 &= (u8)(~(TIM1_CCER2_CC4E | TIM1_CCER2_CC4P)); + /* Set the Output State & the Output Polarity */ + TIM1->CCER2 |= (u8)((TIM1_OutputState & TIM1_CCER2_CC4E ) | (TIM1_OCPolarity & TIM1_CCER2_CC4P )); + + /* Reset the Output Compare Bit and Set the Ouput Compare Mode */ + TIM1->CCMR4 = (u8)((TIM1->CCMR4 & (u8)(~TIM1_CCMR_OCM)) | (TIM1_OCMode)); + + /* Set the Output Idle state */ + if (TIM1_OCIdleState != TIM1_OCIDLESTATE_RESET) + { + TIM1->OISR |= (u8)(~TIM1_CCER2_CC4P); + } + else + { + TIM1->OISR &= (u8)(~TIM1_OISR_OIS4); + } + + /* Set the Pulse value */ + TIM1->CCR4H = (u8)(TIM1_Pulse >> 8); + TIM1->CCR4L = (u8)(TIM1_Pulse); + +} + +/** + * @brief Configures the Break feature, dead time, Lock level, the OSSI, + * and the AOE(automatic output enable). + * @param[in] TIM1_OSSIState specifies the OSSIS State from @ref TIM1_OSSIState_TypeDef. + * @param[in] TIM1_LockLevel specifies the lock level from @ref TIM1_LockLevel_TypeDef. + * @param[in] TIM1_DeadTime specifies the dead time value. + * @param[in] TIM1_Break specifies the Break state @ref TIM1_BreakState_TypeDef. + * @param[in] TIM1_BreakPolarity specifies the Break polarity from @ref TIM1_BreakPolarity_TypeDef. + * @param[in] TIM1_AutomaticOutput specifies the Automatic Output configuration from @ref TIM1_AutomaticOutput_TypeDef. + * @retval None + */ +void TIM1_BDTRConfig(TIM1_OSSIState_TypeDef TIM1_OSSIState, + TIM1_LockLevel_TypeDef TIM1_LockLevel, + u8 TIM1_DeadTime, + TIM1_BreakState_TypeDef TIM1_Break, + TIM1_BreakPolarity_TypeDef TIM1_BreakPolarity, + TIM1_AutomaticOutput_TypeDef TIM1_AutomaticOutput) +{ + + + /* Check the parameters */ + assert_param(IS_TIM1_OSSI_STATE_OK(TIM1_OSSIState)); + assert_param(IS_TIM1_LOCK_LEVEL_OK(TIM1_LockLevel)); + assert_param(IS_TIM1_BREAK_STATE_OK(TIM1_Break)); + assert_param(IS_TIM1_BREAK_POLARITY_OK(TIM1_BreakPolarity)); + assert_param(IS_TIM1_AUTOMATIC_OUTPUT_STATE_OK(TIM1_AutomaticOutput)); + + + TIM1->DTR = (u8)(TIM1_DeadTime); + /* Set the Lock level, the Break enable Bit and the Ploarity, the OSSI State, + the dead time value and the Automatic Output Enable Bit */ + + TIM1->BKR = (u8)((u8)TIM1_OSSIState | \ + (u8)TIM1_LockLevel | \ + (u8)TIM1_Break | \ + (u8)TIM1_BreakPolarity | \ + (u8)TIM1_AutomaticOutput); + +} + +/** + * @brief Initializes the TIM1 peripheral according to the specified parameters. + * @param[in] TIM1_Channel specifies the input capture channel from TIM1_Channel_TypeDef. + * @param[in] TIM1_ICPolarity specifies the Input capture polarity from TIM1_ICPolarity_TypeDef . + * @param[in] TIM1_ICSelection specifies the Input capture source selection from TIM1_ICSelection_TypeDef. + * @param[in] TIM1_ICPrescaler specifies the Input capture Prescaler from TIM1_ICPSC_TypeDef. + * @param[in] TIM1_ICFilter specifies the Input capture filter value. + * @retval None + */ + +void TIM1_ICInit(TIM1_Channel_TypeDef TIM1_Channel, + TIM1_ICPolarity_TypeDef TIM1_ICPolarity, + TIM1_ICSelection_TypeDef TIM1_ICSelection, + TIM1_ICPSC_TypeDef TIM1_ICPrescaler, + u8 TIM1_ICFilter) +{ + + /* Check the parameters */ + assert_param(IS_TIM1_CHANNEL_OK(TIM1_Channel)); + assert_param(IS_TIM1_IC_POLARITY_OK(TIM1_ICPolarity)); + assert_param(IS_TIM1_IC_SELECTION_OK(TIM1_ICSelection)); + assert_param(IS_TIM1_IC_PRESCALER_OK(TIM1_ICPrescaler)); + assert_param(IS_TIM1_IC_FILTER_OK(TIM1_ICFilter)); + + if (TIM1_Channel == TIM1_CHANNEL_1) + { + /* TI1 Configuration */ + TI1_Config((u8)TIM1_ICPolarity, + (u8)TIM1_ICSelection, + (u8)TIM1_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM1_SetIC1Prescaler(TIM1_ICPrescaler); + } + else if (TIM1_Channel == TIM1_CHANNEL_2) + { + /* TI2 Configuration */ + TI2_Config((u8)TIM1_ICPolarity, + (u8)TIM1_ICSelection, + (u8)TIM1_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM1_SetIC2Prescaler(TIM1_ICPrescaler); + } + else if (TIM1_Channel == TIM1_CHANNEL_3) + { + /* TI3 Configuration */ + TI3_Config((u8)TIM1_ICPolarity, + (u8)TIM1_ICSelection, + (u8)TIM1_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM1_SetIC3Prescaler(TIM1_ICPrescaler); + } + else + { + /* TI4 Configuration */ + TI4_Config((u8)TIM1_ICPolarity, + (u8)TIM1_ICSelection, + (u8)TIM1_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM1_SetIC4Prescaler(TIM1_ICPrescaler); + } + +} + +/** + * @brief Configures the TIM1 peripheral in PWM Input Mode according to the specified parameters. + * @param[in] TIM1_Channel specifies the input capture channel from TIM1_Channel_TypeDef. + * @param[in] TIM1_ICPolarity specifies the Input capture polarity from TIM1_ICPolarity_TypeDef . + * @param[in] TIM1_ICSelection specifies the Input capture source selection from TIM1_ICSelection_TypeDef. + * @param[in] TIM1_ICPrescaler specifies the Input capture Prescaler from TIM1_ICPSC_TypeDef. + * @param[in] TIM1_ICFilter specifies the Input capture filter value. + * @retval None + */ +void TIM1_PWMIConfig(TIM1_Channel_TypeDef TIM1_Channel, + TIM1_ICPolarity_TypeDef TIM1_ICPolarity, + TIM1_ICSelection_TypeDef TIM1_ICSelection, + TIM1_ICPSC_TypeDef TIM1_ICPrescaler, + u8 TIM1_ICFilter) +{ + u8 icpolarity = TIM1_ICPOLARITY_RISING; + u8 icselection = TIM1_ICSELECTION_DIRECTTI; + + /* Check the parameters */ + assert_param(IS_TIM1_PWMI_CHANNEL_OK(TIM1_Channel)); + assert_param(IS_TIM1_IC_POLARITY_OK(TIM1_ICPolarity)); + assert_param(IS_TIM1_IC_SELECTION_OK(TIM1_ICSelection)); + assert_param(IS_TIM1_IC_PRESCALER_OK(TIM1_ICPrescaler)); + + /* Select the Opposite Input Polarity */ + if (TIM1_ICPolarity != TIM1_ICPOLARITY_FALLING) + { + icpolarity = TIM1_ICPOLARITY_FALLING; + } + else + { + icpolarity = TIM1_ICPOLARITY_RISING; + } + + /* Select the Opposite Input */ + if (TIM1_ICSelection == TIM1_ICSELECTION_DIRECTTI) + { + icselection = TIM1_ICSELECTION_INDIRECTTI; + } + else + { + icselection = TIM1_ICSELECTION_DIRECTTI; + } + + if (TIM1_Channel == TIM1_CHANNEL_1) + { + /* TI1 Configuration */ + TI1_Config((u8)TIM1_ICPolarity, (u8)TIM1_ICSelection, + (u8)TIM1_ICFilter); + + /* Set the Input Capture Prescaler value */ + TIM1_SetIC1Prescaler(TIM1_ICPrescaler); + + /* TI2 Configuration */ + TI2_Config(icpolarity, icselection, TIM1_ICFilter); + + /* Set the Input Capture Prescaler value */ + TIM1_SetIC2Prescaler(TIM1_ICPrescaler); + } + else + { + /* TI2 Configuration */ + TI2_Config((u8)TIM1_ICPolarity, (u8)TIM1_ICSelection, + (u8)TIM1_ICFilter); + + /* Set the Input Capture Prescaler value */ + TIM1_SetIC2Prescaler(TIM1_ICPrescaler); + + /* TI1 Configuration */ + TI1_Config(icpolarity, icselection, TIM1_ICFilter); + + /* Set the Input Capture Prescaler value */ + TIM1_SetIC1Prescaler(TIM1_ICPrescaler); + } +} + + +/** + * @brief Enables or disables the TIM1 peripheral. + * @param[in] NewState new state of the TIM1 peripheral. + * This parameter can be ENABLE or DISABLE. + * @retval None + */ +void TIM1_Cmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONALSTATE_OK(NewState)); + + /* set or Reset the CEN Bit */ + if (NewState != DISABLE) + { + TIM1->CR1 |= TIM1_CR1_CEN; + } + else + { + TIM1->CR1 &= (u8)(~TIM1_CR1_CEN); + } +} + + +/** + * @brief Enables or disables the TIM1 peripheral Main Outputs. + * @param[in] NewState new state of the TIM1 peripheral. + * This parameter can be ENABLE or DISABLE. + * @retval None + */ +void TIM1_CtrlPWMOutputs(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONALSTATE_OK(NewState)); + + /* Set or Reset the MOE Bit */ + + if (NewState != DISABLE) + { + TIM1->BKR |= TIM1_BKR_MOE; + } + else + { + TIM1->BKR &= (u8)(~TIM1_BKR_MOE); + } +} + + +/** + * @brief Enables or disables the specified TIM1 interrupts. + * @param[in] NewState new state of the TIM1 peripheral. + * This parameter can be: ENABLE or DISABLE. + * @param[in] TIM1_IT specifies the TIM1 interrupts sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * - TIM1_IT_UPDATE: TIM1 update Interrupt source + * - TIM1_IT_CC1: TIM1 Capture Compare 1 Interrupt source + * - TIM1_IT_CC2: TIM1 Capture Compare 2 Interrupt source + * - TIM1_IT_CC3: TIM1 Capture Compare 3 Interrupt source + * - TIM1_IT_CC4: TIM1 Capture Compare 4 Interrupt source + * - TIM1_IT_CCUpdate: TIM1 Capture Compare Update Interrupt source + * - TIM1_IT_TRIGGER: TIM1 Trigger Interrupt source + * - TIM1_IT_BREAK: TIM1 Break Interrupt source + * @param[in] NewState new state of the TIM1 peripheral. + * @retval None + */ +void TIM1_ITConfig(TIM1_IT_TypeDef TIM1_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM1_IT_OK(TIM1_IT)); + assert_param(IS_FUNCTIONALSTATE_OK(NewState)); + + if (NewState != DISABLE) + { + /* Enable the Interrupt sources */ + TIM1->IER |= (u8)TIM1_IT; + } + else + { + /* Disable the Interrupt sources */ + TIM1->IER &= (u8)(~(u8)TIM1_IT); + } +} + + +/** + * @brief Configures the TIM1 internal Clock. + * @param[in] : + * None + * @retval None + */ +void TIM1_InternalClockConfig(void) +{ + /* Disable slave mode to clock the prescaler directly with the internal clock */ + TIM1->SMCR &= (u8)(~TIM1_SMCR_SMS); +} + + +/** + * @brief Configures the TIM1 External clock Mode1. + * @param[in] TIM1_ExtTRGPrescaler specifies the external Trigger Prescaler. + * This parameter can be one of the following values: + * - TIM1_EXTTRGPSC_OFF + * - TIM1_EXTTRGPSC_DIV2 + * - TIM1_EXTTRGPSC_DIV4 + * - TIM1_EXTTRGPSC_DIV8. + * @param[in] TIM1_ExtTRGPolarity specifies the external Trigger Polarity. + * This parameter can be one of the following values: + * - TIM1_EXTTRGPOLARITY_INVERTED + * - TIM1_EXTTRGPOLARITY_NONINVERTED + * @param[in] ExtTRGFilter specifies the External Trigger Filter. + * This parameter must be a value between 0x00 and 0x0F + * @retval None + */ +void TIM1_ETRClockMode1Config(TIM1_ExtTRGPSC_TypeDef TIM1_ExtTRGPrescaler, + TIM1_ExtTRGPolarity_TypeDef TIM1_ExtTRGPolarity, + u8 ExtTRGFilter) +{ + /* Check the parameters */ + assert_param(IS_TIM1_EXT_PRESCALER_OK(TIM1_ExtTRGPrescaler)); + assert_param(IS_TIM1_EXT_POLARITY_OK(TIM1_ExtTRGPolarity)); + + /* Configure the ETR Clock source */ + TIM1_ETRConfig(TIM1_ExtTRGPrescaler, TIM1_ExtTRGPolarity, ExtTRGFilter); + + /* Select the External clock mode1 & Select the Trigger selection : ETRF */ + TIM1->SMCR = (u8)((TIM1->SMCR & (u8)(~(TIM1_SMCR_SMS | TIM1_SMCR_TS ))) | (u8)( TIM1_SLAVEMODE_EXTERNAL1 | TIM1_TS_ETRF )); +} + + +/** + * @brief Configures the TIM1 External clock Mode2. + * @param[in] TIM1_ExtTRGPrescaler specifies the external Trigger Prescaler. + * This parameter can be one of the following values: + * - TIM1_EXTTRGPSC_OFF + * - TIM1_EXTTRGPSC_DIV2 + * - TIM1_EXTTRGPSC_DIV4 + * - TIM1_EXTTRGPSC_DIV8. + * @param[in] TIM1_ExtTRGPolarity specifies the external Trigger Polarity. + * This parameter can be one of the following values: + * - TIM1_EXTTRGPOLARITY_INVERTED + * - TIM1_EXTTRGPOLARITY_NONINVERTED + * @param[in] ExtTRGFilter specifies the External Trigger Filter. + * This parameter must be a value between 0x00 and 0x0F + * @retval None + */ +void TIM1_ETRClockMode2Config(TIM1_ExtTRGPSC_TypeDef TIM1_ExtTRGPrescaler, + TIM1_ExtTRGPolarity_TypeDef TIM1_ExtTRGPolarity, + u8 ExtTRGFilter) +{ + /* Check the parameters */ + assert_param(IS_TIM1_EXT_PRESCALER_OK(TIM1_ExtTRGPrescaler)); + assert_param(IS_TIM1_EXT_POLARITY_OK(TIM1_ExtTRGPolarity)); + + /* Configure the ETR Clock source */ + TIM1_ETRConfig(TIM1_ExtTRGPrescaler, TIM1_ExtTRGPolarity, ExtTRGFilter); + + /* Enable the External clock mode2 */ + TIM1->ETR |= TIM1_ETR_ECE; +} + + +/** + * @brief Configures the TIM1 External Trigger. + * @param[in] TIM1_ExtTRGPrescaler specifies the external Trigger Prescaler. + * This parameter can be one of the following values: + * - TIM1_EXTTRGPSC_OFF + * - TIM1_EXTTRGPSC_DIV2 + * - TIM1_EXTTRGPSC_DIV4 + * - TIM1_EXTTRGPSC_DIV8. + * @param[in] TIM1_ExtTRGPolarity specifies the external Trigger Polarity. + * This parameter can be one of the following values: + * - TIM1_EXTTRGPOLARITY_INVERTED + * - TIM1_EXTTRGPOLARITY_NONINVERTED + * @param[in] ExtTRGFilter specifies the External Trigger Filter. + * This parameter must be a value between 0x00 and 0x0F + * @retval None + */ +void TIM1_ETRConfig(TIM1_ExtTRGPSC_TypeDef TIM1_ExtTRGPrescaler, + TIM1_ExtTRGPolarity_TypeDef TIM1_ExtTRGPolarity, + u8 ExtTRGFilter) +{ + /* Check the parameters */ + assert_param(IS_TIM1_EXT_TRG_FILTER_OK(ExtTRGFilter)); + /* Set the Prescaler, the Filter value and the Polarity */ + TIM1->ETR |= (u8)((u8)TIM1_ExtTRGPrescaler | + (u8)TIM1_ExtTRGPolarity | + (u8)ExtTRGFilter ); +} + + +/** + * @brief Configures the TIM1 Trigger as External Clock. + * @param[in] TIM1_TIxExternalCLKSource specifies Trigger source. + * This parameter can be one of the following values: + * - TIM1_TIXEXTERNALCLK1SOURCE_TI1: TI1 Edge Detector + * - TIM1_TIXEXTERNALCLK1SOURCE_TI2: Filtered TIM1 Input 1 + * - TIM1_TIXEXTERNALCLK1SOURCE_TI1ED: Filtered TIM1 Input 2 + * @param[in] TIM1_ICPolarity specifies the TIx Polarity. + * This parameter can be: + * - TIM1_ICPOLARITY_RISING + * - TIM1_ICPOLARITY_FALLING + * @param[in] ICFilter specifies the filter value. + * This parameter must be a value between 0x00 and 0x0F + * @retval None + * @par Required preconditions: + * TI1_Config + * TI2_Config + * TIM1_SelectInputTrigger + */ +void TIM1_TIxExternalClockConfig(TIM1_TIxExternalCLK1Source_TypeDef TIM1_TIxExternalCLKSource, + TIM1_ICPolarity_TypeDef TIM1_ICPolarity, + u8 ICFilter) +{ + /* Check the parameters */ + assert_param(IS_TIM1_TIXCLK_SOURCE_OK(TIM1_TIxExternalCLKSource)); + assert_param(IS_TIM1_IC_POLARITY_OK(TIM1_ICPolarity)); + assert_param(IS_TIM1_IC_FILTER_OK(ICFilter)); + + /* Configure the TIM1 Input Clock Source */ + if (TIM1_TIxExternalCLKSource == TIM1_TIXEXTERNALCLK1SOURCE_TI2) + { + TI2_Config((u8)TIM1_ICPolarity, (u8)TIM1_ICSELECTION_DIRECTTI, (u8)ICFilter); + } + else + { + TI1_Config((u8)TIM1_ICPolarity, (u8)TIM1_ICSELECTION_DIRECTTI, (u8)ICFilter); + } + + /* Select the Trigger source */ + TIM1_SelectInputTrigger(TIM1_TIxExternalCLKSource); + + /* Select the External clock mode1 */ + TIM1->SMCR |= (u8)(TIM1_SLAVEMODE_EXTERNAL1); +} + +/** + * @brief Selects the TIM1 Input Trigger source. + * @param[in] TIM1_InputTriggerSource specifies Input Trigger source. + * This parameter can be one of the following values: + * - TIM1_TS_TI1F_ED: TI1 Edge Detector + * - TIM1_TS_TI1FP1: Filtered Timer Input 1 + * - TIM1_TS_TI2FP2: Filtered Timer Input 2 + * - TIM1_TS_ETRF: External Trigger input + * @retval None + */ +void TIM1_SelectInputTrigger(TIM1_TS_TypeDef TIM1_InputTriggerSource) +{ + /* Check the parameters */ + assert_param(IS_TIM1_TRIGGER_SELECTION_OK(TIM1_InputTriggerSource)); + + /* Select the Tgigger Source */ + TIM1->SMCR = (u8)((TIM1->SMCR & (u8)(~TIM1_SMCR_TS)) | (u8)TIM1_InputTriggerSource); +} + + +/** + * @brief Enables or Disables the TIM1 Update event. + * @param[in] NewState new state of the TIM1 peripheral Preload register. This parameter can + * be ENABLE or DISABLE. + * @retval None + */ + +void TIM1_UpdateDisableConfig(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONALSTATE_OK(NewState)); + + /* Set or Reset the UDIS Bit */ + if (NewState != DISABLE) + { + TIM1->CR1 |= TIM1_CR1_UDIS; + } + else + { + TIM1->CR1 &= (u8)(~TIM1_CR1_UDIS); + } +} + +/** + * @brief Selects the TIM1 Update Request Interrupt source. + * @param[in] TIM1_UpdateSource specifies the Update source. + * This parameter can be one of the following values + * - TIM1_UPDATESOURCE_REGULAR + * - TIM1_UPDATESOURCE_GLOBAL + * @retval None + */ +void TIM1_UpdateRequestConfig(TIM1_UpdateSource_TypeDef TIM1_UpdateSource) +{ + /* Check the parameters */ + assert_param(IS_TIM1_UPDATE_SOURCE_OK(TIM1_UpdateSource)); + + /* Set or Reset the URS Bit */ + if (TIM1_UpdateSource != TIM1_UPDATESOURCE_GLOBAL) + { + TIM1->CR1 |= TIM1_CR1_URS; + } + else + { + TIM1->CR1 &= (u8)(~TIM1_CR1_URS); + } +} + + +/** + * @brief Enables or Disables the TIM1’s Hall sensor interface. + * @param[in] NewState new state of the TIM1 Hall sensor interface.This parameter can + * be ENABLE or DISABLE. + * @retval None + */ +void TIM1_SelectHallSensor(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONALSTATE_OK(NewState)); + + /* Set or Reset the TI1S Bit */ + if (NewState != DISABLE) + { + TIM1->CR2 |= TIM1_CR2_TI1S; + } + else + { + TIM1->CR2 &= (u8)(~TIM1_CR2_TI1S); + } +} + + +/** + * @brief Selects the TIM1’s One Pulse Mode. + * @param[in] TIM1_OPMode specifies the OPM Mode to be used. + * This parameter can be one of the following values + * - TIM1_OPMODE_SINGLE + * - TIM1_OPMODE_REPETITIVE + * @retval None + */ +void TIM1_SelectOnePulseMode(TIM1_OPMode_TypeDef TIM1_OPMode) +{ + /* Check the parameters */ + assert_param(IS_TIM1_OPM_MODE_OK(TIM1_OPMode)); + + /* Set or Reset the OPM Bit */ + if (TIM1_OPMode != TIM1_OPMODE_REPETITIVE) + { + TIM1->CR1 |= TIM1_CR1_OPM; + } + else + { + TIM1->CR1 &= (u8)(~TIM1_CR1_OPM); + } + +} + + +/** + * @brief Selects the TIM1 Trigger Output Mode. + * @param[in] TIM1_TRGOSource specifies the Trigger Output source. + * This parameter can be one of the following values + * - TIM1_TRGOSOURCE_RESET + * - TIM1_TRGOSOURCE_ENABLE + * - TIM1_TRGOSOURCE_UPDATE + * - TIM1_TRGOSource_OC1 + * - TIM1_TRGOSOURCE_OC1REF + * - TIM1_TRGOSOURCE_OC2REF + * - TIM1_TRGOSOURCE_OC3REF + * @retval None + */ +void TIM1_SelectOutputTrigger(TIM1_TRGOSource_TypeDef TIM1_TRGOSource) +{ + + /* Check the parameters */ + assert_param(IS_TIM1_TRGO_SOURCE_OK(TIM1_TRGOSource)); + /* Reset the MMS Bits & Select the TRGO source */ + TIM1->CR2 = (u8)((TIM1->CR2 & (u8)(~TIM1_CR2_MMS )) | (u8) TIM1_TRGOSource); +} + +/** + * @brief Selects the TIM1 Slave Mode. + * @param[in] TIM1_SlaveMode specifies the TIM1 Slave Mode. + * This parameter can be one of the following values + * - TIM1_SLAVEMODE_RESET + * - TIM1_SLAVEMODE_GATED + * - TIM1_SLAVEMODE_TRIGGER + * - TIM1_SLAVEMODE_EXTERNAL1 + * @retval None + */ +void TIM1_SelectSlaveMode(TIM1_SlaveMode_TypeDef TIM1_SlaveMode) +{ + + /* Check the parameters */ + assert_param(IS_TIM1_SLAVE_MODE_OK(TIM1_SlaveMode)); + + /* Reset the SMS Bits */ /* Select the Slave Mode */ + TIM1->SMCR = (u8)((TIM1->SMCR & (u8)(~TIM1_SMCR_SMS)) | (u8)TIM1_SlaveMode); + +} + +/** + * @brief Sets or Resets the TIM1 Master/Slave Mode. + * @param[in] NewState new state of the synchronization between TIM1 and its slaves + * (through TRGO). This parameter can be ENABLE or DISABLE. + * @retval None + */ +void TIM1_SelectMasterSlaveMode(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONALSTATE_OK(NewState)); + + /* Set or Reset the MSM Bit */ + if (NewState != DISABLE) + { + TIM1->SMCR |= TIM1_SMCR_MSM; + } + else + { + TIM1->SMCR &= (u8)(~TIM1_SMCR_MSM); + } +} + +/** + * @brief Configures the TIM1 Encoder Interface. + * @param[in] TIM1_EncoderMode specifies the TIM1 Encoder Mode. + * This parameter can be one of the following values + * - TIM1_ENCODERMODE_TI1: Counter counts on TI1FP1 edge + * depending on TI2FP2 level. + * - TIM1_ENCODERMODE_TI2: Counter counts on TI2FP2 edge + * depending on TI1FP1 level. + * - TIM1_ENCODERMODE_TI12: Counter counts on both TI1FP1 and + * TI2FP2 edges depending on the level of the other input. + * @param[in] TIM1_IC1Polarity specifies the IC1 Polarity. + * This parameter can be one of the following values + * - TIM1_ICPOLARITY_FALLING + * - TIM1_ICPOLARITY_RISING + * @param[in] TIM1_IC2Polarity specifies the IC2 Polarity. + * This parameter can be one of the following values + * - TIM1_ICPOLARITY_FALLING + * - TIM1_ICPOLARITY_RISING + * @retval None + */ +void TIM1_EncoderInterfaceConfig(TIM1_EncoderMode_TypeDef TIM1_EncoderMode, + TIM1_ICPolarity_TypeDef TIM1_IC1Polarity, + TIM1_ICPolarity_TypeDef TIM1_IC2Polarity) +{ + + + /* Check the parameters */ + assert_param(IS_TIM1_ENCODER_MODE_OK(TIM1_EncoderMode)); + assert_param(IS_TIM1_IC_POLARITY_OK(TIM1_IC1Polarity)); + assert_param(IS_TIM1_IC_POLARITY_OK(TIM1_IC2Polarity)); + + /* Set the TI1 and the TI2 Polarities */ + if (TIM1_IC1Polarity != TIM1_ICPOLARITY_RISING) + { + TIM1->CCER1 |= TIM1_CCER1_CC1P; + } + else + { + TIM1->CCER1 &= (u8)(~TIM1_CCER1_CC1P); + } + + if (TIM1_IC2Polarity != TIM1_ICPOLARITY_RISING) + { + TIM1->CCER1 |= TIM1_CCER1_CC2P; + } + else + { + TIM1->CCER1 &= (u8)(~TIM1_CCER1_CC2P); + } + /* Set the encoder Mode */ + TIM1->SMCR = (u8)((TIM1->SMCR & (u8)(TIM1_SMCR_MSM | TIM1_SMCR_TS)) | (u8) TIM1_EncoderMode); + + /* Select the Capture Compare 1 and the Capture Compare 2 as input */ + TIM1->CCMR1 = (u8)((TIM1->CCMR1 & (u8)(~TIM1_CCMR_CCxS)) | (u8) CCMR_TIxDirect_Set); + TIM1->CCMR2 = (u8)((TIM1->CCMR2 & (u8)(~TIM1_CCMR_CCxS)) | (u8) CCMR_TIxDirect_Set); + +} + +/** + * @brief Configures the TIM1 Prescaler. + * @param[in] Prescaler specifies the Prescaler Register value + * This parameter must be a value between 0x0000 and 0xFFFF + * @param[in] TIM1_PSCReloadMode specifies the TIM1 Prescaler Reload mode. + * This parameter can be one of the following values + * - TIM1_PSCRELOADMODE_IMMEDIATE: The Prescaler is loaded immediately. + * - TIM1_PSCRELOADMODE_UPDATE: The Prescaler is loaded at the update event. + * @retval None + */ + +void TIM1_PrescalerConfig(u16 Prescaler, + TIM1_PSCReloadMode_TypeDef TIM1_PSCReloadMode) +{ + /* Check the parameters */ + assert_param(IS_TIM1_PRESCALER_RELOAD_OK(TIM1_PSCReloadMode)); + + /* Set the Prescaler value */ + TIM1->PSCRH = (u8)(Prescaler >> 8); + TIM1->PSCRL = (u8)(Prescaler); + + /* Set or reset the UG Bit */ + TIM1->EGR = (u8)TIM1_PSCReloadMode; + +} + +/** + * @brief Specifies the TIM1 Counter Mode to be used. + * @param[in] TIM1_CounterMode specifies the Counter Mode to be used + * This parameter can be one of the following values: + * - TIM1_COUNTERMODE_UP: TIM1 Up Counting Mode + * - TIM1_COUNTERMODE_DOWN: TIM1 Down Counting Mode + * - TIM1_COUNTERMODE_CENTERALIGNED1: TIM1 Center Aligned Mode1 + * - TIM1_CounterMode_CenterAligned2: TIM1 Center Aligned Mode2 + * - TIM1_COUNTERMODE_CENTERALIGNED3: TIM1 Center Aligned Mode3 + * @retval None + */ +void TIM1_CounterModeConfig(TIM1_CounterMode_TypeDef TIM1_CounterMode) +{ + /* Check the parameters */ + assert_param(IS_TIM1_COUNTER_MODE_OK(TIM1_CounterMode)); + + + /* Reset the CMS and DIR Bits & Set the Counter Mode */ + TIM1->CR1 = (u8)((TIM1->CR1 & (u8)((u8)(~TIM1_CR1_CMS) & (u8)(~TIM1_CR1_DIR))) | (u8)TIM1_CounterMode); +} + + +/** + * @brief Forces the TIM1 Channel1 output waveform to active or inactive level. + * @param[in] TIM1_ForcedAction specifies the forced Action to be set to the output waveform. + * This parameter can be one of the following values: + * - TIM1_FORCEDACTION_ACTIVE: Force active level on OC1REF + * - TIM1_FORCEDACTION_INACTIVE: Force inactive level on OC1REF. + * @retval None + */ +void TIM1_ForcedOC1Config(TIM1_ForcedAction_TypeDef TIM1_ForcedAction) +{ + /* Check the parameters */ + assert_param(IS_TIM1_FORCED_ACTION_OK(TIM1_ForcedAction)); + + /* Reset the OCM Bits & Configure the Forced output Mode */ + TIM1->CCMR1 = (u8)((TIM1->CCMR1 & (u8)(~TIM1_CCMR_OCM)) | (u8)TIM1_ForcedAction); +} + + +/** + * @brief Forces the TIM1 Channel2 output waveform to active or inactive level. + * @param[in] TIM1_ForcedAction specifies the forced Action to be set to the output waveform. + * This parameter can be one of the following values: + * - TIM1_FORCEDACTION_ACTIVE: Force active level on OC2REF + * - TIM1_FORCEDACTION_INACTIVE: Force inactive level on OC2REF. + * @retval None + */ +void TIM1_ForcedOC2Config(TIM1_ForcedAction_TypeDef TIM1_ForcedAction) +{ + /* Check the parameters */ + assert_param(IS_TIM1_FORCED_ACTION_OK(TIM1_ForcedAction)); + + /* Reset the OCM Bits & Configure the Forced output Mode */ + TIM1->CCMR2 = (u8)((TIM1->CCMR2 & (u8)(~TIM1_CCMR_OCM)) | (u8)TIM1_ForcedAction); +} + + +/** + * @brief Forces the TIM1 Channel3 output waveform to active or inactive level. + * @param[in] TIM1_ForcedAction specifies the forced Action to be set to the output waveform. + * This parameter can be one of the following values: + * - TIM1_FORCEDACTION_ACTIVE: Force active level on OC3REF + * - TIM1_FORCEDACTION_INACTIVE: Force inactive level on + * OC3REF. + * @retval None + */ +void TIM1_ForcedOC3Config(TIM1_ForcedAction_TypeDef TIM1_ForcedAction) +{ + /* Check the parameters */ + assert_param(IS_TIM1_FORCED_ACTION_OK(TIM1_ForcedAction)); + + /* Reset the OCM Bits */ /* Configure The Forced output Mode */ + TIM1->CCMR3 = (u8)((TIM1->CCMR3 & (u8)(~TIM1_CCMR_OCM)) | (u8)TIM1_ForcedAction); +} + + +/** + * @brief Forces the TIM1 Channel4 output waveform to active or inactive level. + * @param[in] TIM1_ForcedAction specifies the forced Action to be set to the output waveform. + * This parameter can be one of the following values: + * - TIM1_FORCEDACTION_ACTIVE: Force active level on OC4REF + * - TIM1_FORCEDACTION_INACTIVE: Force inactive level on + * OC4REF. + * @retval None + */ +void TIM1_ForcedOC4Config(TIM1_ForcedAction_TypeDef TIM1_ForcedAction) +{ + /* Check the parameters */ + assert_param(IS_TIM1_FORCED_ACTION_OK(TIM1_ForcedAction)); + + /* Reset the OCM Bits & Configure the Forced output Mode */ + TIM1->CCMR4 = (u8)((TIM1->CCMR4 & (u8)(~TIM1_CCMR_OCM)) | (u8)TIM1_ForcedAction); +} + + +/** + * @brief Enables or disables TIM1 peripheral Preload register on ARR. + * @param[in] NewState new state of the TIM1 peripheral Preload register. + * This parameter can be ENABLE or DISABLE. + * @retval None + */ +void TIM1_ARRPreloadConfig(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONALSTATE_OK(NewState)); + + /* Set or Reset the ARPE Bit */ + if (NewState != DISABLE) + { + TIM1->CR1 |= TIM1_CR1_ARPE; + } + else + { + TIM1->CR1 &= (u8)(~TIM1_CR1_ARPE); + } +} + + +/** + * @brief Selects the TIM1 peripheral Commutation event. + * @param[in] NewState new state of the Commutation event. + * This parameter can be ENABLE or DISABLE. + * @retval None + */ +void TIM1_SelectCOM(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONALSTATE_OK(NewState)); + + /* Set or Reset the COMS Bit */ + if (NewState != DISABLE) + { + TIM1->CR2 |= TIM1_CR2_COMS; + } + else + { + TIM1->CR2 &= (u8)(~TIM1_CR2_COMS); + } +} + +/** + * @brief Sets or Resets the TIM1 peripheral Capture Compare Preload Control bit. + * @param[in] NewState new state of the Capture Compare Preload Control bit. + * This parameter can be ENABLE or DISABLE. + * @retval None + */ +void TIM1_CCPreloadControl(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONALSTATE_OK(NewState)); + + /* Set or Reset the CCPC Bit */ + if (NewState != DISABLE) + { + TIM1->CR2 |= TIM1_CR2_CCPC; + } + else + { + TIM1->CR2 &= (u8)(~TIM1_CR2_CCPC); + } +} + + +/** + * @brief Enables or disables the TIM1 peripheral Preload Register on CCR1. + * @param[in] NewState new state of the Capture Compare Preload register. + * This parameter can be ENABLE or DISABLE. + * @retval None + */ +void TIM1_OC1PreloadConfig(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONALSTATE_OK(NewState)); + + /* Set or Reset the OC1PE Bit */ + if (NewState != DISABLE) + { + TIM1->CCMR1 |= TIM1_CCMR_OCxPE; + } + else + { + TIM1->CCMR1 &= (u8)(~TIM1_CCMR_OCxPE); + } +} + + +/** + * @brief Enables or disables the TIM1 peripheral Preload Register on CCR2. + * @param[in] NewState new state of the Capture Compare Preload register. + * This parameter can be ENABLE or DISABLE. + * @retval None + */ +void TIM1_OC2PreloadConfig(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONALSTATE_OK(NewState)); + + /* Set or Reset the OC2PE Bit */ + if (NewState != DISABLE) + { + TIM1->CCMR2 |= TIM1_CCMR_OCxPE; + } + else + { + TIM1->CCMR2 &= (u8)(~TIM1_CCMR_OCxPE); + } +} + + +/** + * @brief Enables or disables the TIM1 peripheral Preload Register on CCR3. + * @param[in] NewState new state of the Capture Compare Preload register. + * This parameter can be ENABLE or DISABLE. + * @retval None + */ +void TIM1_OC3PreloadConfig(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONALSTATE_OK(NewState)); + + /* Set or Reset the OC3PE Bit */ + if (NewState != DISABLE) + { + TIM1->CCMR3 |= TIM1_CCMR_OCxPE; + } + else + { + TIM1->CCMR3 &= (u8)(~TIM1_CCMR_OCxPE); + } +} + + +/** + * @brief Enables or disables the TIM1 peripheral Preload Register on CCR4. + * @param[in] NewState new state of the Capture Compare Preload register. + * This parameter can be ENABLE or DISABLE. + * @retval None + */ + +void TIM1_OC4PreloadConfig(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONALSTATE_OK(NewState)); + + /* Set or Reset the OC4PE Bit */ + if (NewState != DISABLE) + { + TIM1->CCMR4 |= TIM1_CCMR_OCxPE; + } + else + { + TIM1->CCMR4 &= (u8)(~TIM1_CCMR_OCxPE); + } +} + +/** + * @brief Configures the TIM1 Capture Compare 1 Fast feature. + * @param[in] NewState new state of the Output Compare Fast Enable bit. + * This parameter can be ENABLE or DISABLE. + * @retval None + */ +void TIM1_OC1FastConfig(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONALSTATE_OK(NewState)); + + /* Set or Reset the OC1FE Bit */ + if (NewState != DISABLE) + { + TIM1->CCMR1 |= TIM1_CCMR_OCxFE; + } + else + { + TIM1->CCMR1 &= (u8)(~TIM1_CCMR_OCxFE); + } +} + + +/** + * @brief Configures the TIM1 Capture Compare 2 Fast feature. + * @param[in] NewState new state of the Output Compare Fast Enable bit. + * This parameter can be ENABLE or DISABLE. + * @retval None + */ + +void TIM1_OC2FastConfig(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONALSTATE_OK(NewState)); + + /* Set or Reset the OC2FE Bit */ + if (NewState != DISABLE) + { + TIM1->CCMR2 |= TIM1_CCMR_OCxFE; + } + else + { + TIM1->CCMR2 &= (u8)(~TIM1_CCMR_OCxFE); + } +} + + +/** + * @brief Configures the TIM1 Capture Compare 3 Fast feature. + * @param[in] NewState new state of the Output Compare Fast Enable bit. + * This parameter can be ENABLE or DISABLE. + * @retval None + */ +void TIM1_OC3FastConfig(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONALSTATE_OK(NewState)); + + /* Set or Reset the OC3FE Bit */ + if (NewState != DISABLE) + { + TIM1->CCMR3 |= TIM1_CCMR_OCxFE; + } + else + { + TIM1->CCMR3 &= (u8)(~TIM1_CCMR_OCxFE); + } +} + + +/** + * @brief Configures the TIM1 Capture Compare 4 Fast feature. + * @param[in] NewState new state of the Output Compare Fast Enable bit. + * This parameter can be ENABLE or DISABLE. + * @retval None + */ +void TIM1_OC4FastConfig(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONALSTATE_OK(NewState)); + + /* Set or Reset the OC4FE Bit */ + if (NewState != DISABLE) + { + TIM1->CCMR4 |= TIM1_CCMR_OCxFE; + } + else + { + TIM1->CCMR4 &= (u8)(~TIM1_CCMR_OCxFE); + } +} + + +/** + * @brief Configures the TIM1 event to be generated by software. + * @param[in] TIM1_EventSource specifies the event source. + * This parameter can be one of the following values: + * - TIM1_EVENTSOURCE_UPDATE: TIM1 update Event source + * - TIM1_EVENTSOURCE_CC1: TIM1 Capture Compare 1 Event source + * - TIM1_EVENTSOURCE_CC2: TIM1 Capture Compare 2 Event source + * - TIM1_EVENTSOURCE_CC3: TIM1 Capture Compare 3 Event source + * - TIM1_EVENTSOURCE_CC4: TIM1 Capture Compare 4 Event source + * - TIM1_EVENTSOURCE_COM: TIM1 COM Event source + * - TIM1_EVENTSOURCE_TRIGGER: TIM1 Trigger Event source + * - TIM1_EventSourceBreak: TIM1 Break Event source + * @retval None + */ +void TIM1_GenerateEvent(TIM1_EventSource_TypeDef TIM1_EventSource) +{ + /* Check the parameters */ + assert_param(IS_TIM1_EVENT_SOURCE_OK(TIM1_EventSource)); + + /* Set the event sources */ + TIM1->EGR = (u8)TIM1_EventSource; +} + + +/** + * @brief Configures the TIM1 Channel 1 polarity. + * @param[in] TIM1_OCPolarity specifies the OC1 Polarity. + * This parameter can be one of the following values: + * - TIM1_OCPOLARITY_LOW: Output Compare active low + * - TIM1_OCPOLARITY_HIGH: Output Compare active high + * @retval None + */ +void TIM1_OC1PolarityConfig(TIM1_OCPolarity_TypeDef TIM1_OCPolarity) +{ + /* Check the parameters */ + assert_param(IS_TIM1_OC_POLARITY_OK(TIM1_OCPolarity)); + + /* Set or Reset the CC1P Bit */ + if (TIM1_OCPolarity != TIM1_OCPOLARITY_HIGH) + { + TIM1->CCER1 |= TIM1_CCER1_CC1P; + } + else + { + TIM1->CCER1 &= (u8)(~TIM1_CCER1_CC1P); + } +} + + +/** + * @brief Configures the TIM1 Channel 1N polarity. + * @param[in] TIM1_OCNPolarity specifies the OC1N Polarity. + * This parameter can be one of the following values: + * - TIM1_OCNPOLARITY_LOW: Output Compare active low + * - TIM1_OCNPOLARITY_HIGH: Output Compare active high + * @retval None + */ +void TIM1_OC1NPolarityConfig(TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity) +{ + /* Check the parameters */ + assert_param(IS_TIM1_OCN_POLARITY_OK(TIM1_OCNPolarity)); + + /* Set or Reset the CC3P Bit */ + if (TIM1_OCNPolarity != TIM1_OCNPOLARITY_HIGH) + { + TIM1->CCER1 |= TIM1_CCER1_CC1NP; + } + else + { + TIM1->CCER1 &= (u8)(~TIM1_CCER1_CC1NP); + } +} + + +/** + * @brief Configures the TIM1 Channel 2 polarity. + * @param[in] TIM1_OCPolarity specifies the OC2 Polarity. + * This parameter can be one of the following values: + * - TIM1_OCPOLARITY_LOW: Output Compare active low + * - TIM1_OCPOLARITY_HIGH: Output Compare active high + * @retval None + */ +void TIM1_OC2PolarityConfig(TIM1_OCPolarity_TypeDef TIM1_OCPolarity) +{ + /* Check the parameters */ + assert_param(IS_TIM1_OC_POLARITY_OK(TIM1_OCPolarity)); + + /* Set or Reset the CC2P Bit */ + if (TIM1_OCPolarity != TIM1_OCPOLARITY_HIGH) + { + TIM1->CCER1 |= TIM1_CCER1_CC2P; + } + else + { + TIM1->CCER1 &= (u8)(~TIM1_CCER1_CC2P); + } +} + +/** + * @brief Configures the TIM1 Channel 2N polarity. + * @param[in] TIM1_OCNPolarity specifies the OC2N Polarity. + * This parameter can be one of the following values: + * - TIM1_OCNPOLARITY_LOW: Output Compare active low + * - TIM1_OCNPOLARITY_HIGH: Output Compare active high + * @retval None + */ +void TIM1_OC2NPolarityConfig(TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity) +{ + /* Check the parameters */ + assert_param(IS_TIM1_OCN_POLARITY_OK(TIM1_OCNPolarity)); + + /* Set or Reset the CC3P Bit */ + if (TIM1_OCNPolarity != TIM1_OCNPOLARITY_HIGH) + { + TIM1->CCER1 |= TIM1_CCER1_CC2NP; + } + else + { + TIM1->CCER1 &= (u8)(~TIM1_CCER1_CC2NP); + } +} + + +/** + * @brief Configures the TIM1 Channel 3 polarity. + * @param[in] TIM1_OCPolarity specifies the OC3 Polarity. + * This parameter can be one of the following values: + * - TIM1_OCPOLARITY_LOW: Output Compare active low + * - TIM1_OCPOLARITY_HIGH: Output Compare active high + * @retval None + */ +void TIM1_OC3PolarityConfig(TIM1_OCPolarity_TypeDef TIM1_OCPolarity) +{ + /* Check the parameters */ + assert_param(IS_TIM1_OC_POLARITY_OK(TIM1_OCPolarity)); + + /* Set or Reset the CC3P Bit */ + if (TIM1_OCPolarity != TIM1_OCPOLARITY_HIGH) + { + TIM1->CCER2 |= TIM1_CCER2_CC3P; + } + else + { + TIM1->CCER2 &= (u8)(~TIM1_CCER2_CC3P); + } +} + + +/** + * @brief Configures the TIM1 Channel 3N polarity. + * @param[in] TIM1_OCNPolarity specifies the OC3N Polarity. + * This parameter can be one of the following values: + * - TIM1_OCNPOLARITY_LOW: Output Compare active low + * - TIM1_OCNPOLARITY_HIGH: Output Compare active high + * @retval None + */ +void TIM1_OC3NPolarityConfig(TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity) +{ + /* Check the parameters */ + assert_param(IS_TIM1_OCN_POLARITY_OK(TIM1_OCNPolarity)); + + /* Set or Reset the CC3P Bit */ + if (TIM1_OCNPolarity != TIM1_OCNPOLARITY_HIGH) + { + TIM1->CCER2 |= TIM1_CCER2_CC3NP; + } + else + { + TIM1->CCER2 &= (u8)(~TIM1_CCER2_CC3NP); + } +} + +/** + * @brief Configures the TIM1 Channel 4 polarity. + * @param[in] TIM1_OCPolarity specifies the OC4 Polarity. + * This parameter can be one of the following values: + * - TIM1_OCPOLARITY_LOW: Output Compare active low + * - TIM1_OCPOLARITY_HIGH: Output Compare active high + * @retval None + */ +void TIM1_OC4PolarityConfig(TIM1_OCPolarity_TypeDef TIM1_OCPolarity) +{ + /* Check the parameters */ + assert_param(IS_TIM1_OC_POLARITY_OK(TIM1_OCPolarity)); + + /* Set or Reset the CC4P Bit */ + if (TIM1_OCPolarity != TIM1_OCPOLARITY_HIGH) + { + TIM1->CCER2 |= TIM1_CCER2_CC4P; + } + else + { + TIM1->CCER2 &= (u8)(~TIM1_CCER2_CC4P); + } +} + + +/** + * @brief Enables or disables the TIM1 Capture Compare Channel x (x=1,..,4). + * @param[in] TIM1_Channel specifies the TIM1 Channel. + * This parameter can be one of the following values: + * - TIM1_CHANNEL_1: TIM1 Channel1 + * - TIM1_CHANNEL_2: TIM1 Channel2 + * - TIM1_CHANNEL_3: TIM1 Channel3 + * - TIM1_CHANNEL_4: TIM1 Channel4 + * @param[in] NewState specifies the TIM1 Channel CCxE bit new state. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM1_CCxCmd(TIM1_Channel_TypeDef TIM1_Channel, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM1_CHANNEL_OK(TIM1_Channel)); + assert_param(IS_FUNCTIONALSTATE_OK(NewState)); + + if (TIM1_Channel == TIM1_CHANNEL_1) + { + /* Set or Reset the CC1E Bit */ + if (NewState != DISABLE) + { + TIM1->CCER1 |= TIM1_CCER1_CC1E; + } + else + { + TIM1->CCER1 &= (u8)(~TIM1_CCER1_CC1E); + } + + } + else if (TIM1_Channel == TIM1_CHANNEL_2) + { + /* Set or Reset the CC2E Bit */ + if (NewState != DISABLE) + { + TIM1->CCER1 |= TIM1_CCER1_CC2E; + } + else + { + TIM1->CCER1 &= (u8)(~TIM1_CCER1_CC2E); + } + } + else if (TIM1_Channel == TIM1_CHANNEL_3) + { + /* Set or Reset the CC3E Bit */ + if (NewState != DISABLE) + { + TIM1->CCER2 |= TIM1_CCER2_CC3E; + } + else + { + TIM1->CCER2 &= (u8)(~TIM1_CCER2_CC3E); + } + } + else + { + /* Set or Reset the CC4E Bit */ + if (NewState != DISABLE) + { + TIM1->CCER2 |= TIM1_CCER2_CC4E; + } + else + { + TIM1->CCER2 &= (u8)(~TIM1_CCER2_CC4E); + } + } +} + +/** + * @brief Enables or disables the TIM1 Capture Compare Channel xN (xN=1,..,3). + * @param[in] TIM1_Channel specifies the TIM1 Channel. + * This parameter can be one of the following values: + * - TIM1_CHANNEL_1: TIM1 Channel1 + * - TIM1_CHANNEL_2: TIM1 Channel2 + * - TIM1_CHANNEL_3: TIM1 Channel3 + * @param[in] NewState specifies the TIM1 Channel CCxNE bit new state. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM1_CCxNCmd(TIM1_Channel_TypeDef TIM1_Channel, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM1_COMPLEMENTARY_CHANNEL_OK(TIM1_Channel)); + assert_param(IS_FUNCTIONALSTATE_OK(NewState)); + + if (TIM1_Channel == TIM1_CHANNEL_1) + { + /* Set or Reset the CC1NE Bit */ + if (NewState != DISABLE) + { + TIM1->CCER1 |= TIM1_CCER1_CC1NE; + } + else + { + TIM1->CCER1 &= (u8)(~TIM1_CCER1_CC1NE); + } + } + else if (TIM1_Channel == TIM1_CHANNEL_2) + { + /* Set or Reset the CC2NE Bit */ + if (NewState != DISABLE) + { + TIM1->CCER1 |= TIM1_CCER1_CC2NE; + } + else + { + TIM1->CCER1 &= (u8)(~TIM1_CCER1_CC2NE); + } + } + else + { + /* Set or Reset the CC3NE Bit */ + if (NewState != DISABLE) + { + TIM1->CCER2 |= TIM1_CCER2_CC3NE; + } + else + { + TIM1->CCER2 &= (u8)(~TIM1_CCER2_CC3NE); + } + } +} + + +/** + * @brief Selects the TIM1 Ouput Compare Mode. This function disables the + * selected channel before changing the Ouput Compare Mode. User has to + * enable this channel using TIM1_CCxCmd and TIM1_CCxNCmd functions. + * @param[in] TIM1_Channel specifies the TIM1 Channel. + * This parameter can be one of the following values: + * - TIM1_CHANNEL_1: TIM1 Channel1 + * - TIM1_CHANNEL_2: TIM1 Channel2 + * - TIM1_CHANNEL_3: TIM1 Channel3 + * - TIM1_CHANNEL_4: TIM1 Channel4 + * @param[in] TIM1_OCMode specifies the TIM1 Output Compare Mode. + * This paramter can be one of the following values: + * - TIM1_OCMODE_TIMING + * - TIM1_OCMODE_ACTIVE + * - TIM1_OCMODE_TOGGLE + * - TIM1_OCMODE_PWM1 + * - TIM1_OCMODE_PWM2 + * - TIM1_FORCEDACTION_ACTIVE + * - TIM1_FORCEDACTION_INACTIVE + * @retval None + */ +void TIM1_SelectOCxM(TIM1_Channel_TypeDef TIM1_Channel, TIM1_OCMode_TypeDef TIM1_OCMode) +{ + /* Check the parameters */ + assert_param(IS_TIM1_CHANNEL_OK(TIM1_Channel)); + assert_param(IS_TIM1_OCM_OK(TIM1_OCMode)); + + if (TIM1_Channel == TIM1_CHANNEL_1) + { + /* Disable the Channel 1: Reset the CCE Bit */ + TIM1->CCER1 &= (u8)(~TIM1_CCER1_CC1E); + + /* Reset the Output Compare Bits & Set the Output Compare Mode */ + TIM1->CCMR1 = (u8)((TIM1->CCMR1 & (u8)(~TIM1_CCMR_OCM)) | (u8)TIM1_OCMode); + } + else if (TIM1_Channel == TIM1_CHANNEL_2) + { + /* Disable the Channel 2: Reset the CCE Bit */ + TIM1->CCER1 &= (u8)(~TIM1_CCER1_CC2E); + + /* Reset the Output Compare Bits & Set the Output Compare Mode */ + TIM1->CCMR2 = (u8)((TIM1->CCMR2 & (u8)(~TIM1_CCMR_OCM)) | (u8)TIM1_OCMode); + } + else if (TIM1_Channel == TIM1_CHANNEL_3) + { + /* Disable the Channel 3: Reset the CCE Bit */ + TIM1->CCER2 &= (u8)(~TIM1_CCER2_CC3E); + + /* Reset the Output Compare Bits & Set the Output Compare Mode */ + TIM1->CCMR3 = (u8)((TIM1->CCMR3 & (u8)(~TIM1_CCMR_OCM)) | (u8)TIM1_OCMode); + } + else + { + /* Disable the Channel 4: Reset the CCE Bit */ + TIM1->CCER2 &= (u8)(~TIM1_CCER2_CC4E); + + /* Reset the Output Compare Bits & Set the Output Compare Mode */ + TIM1->CCMR4 = (u8)((TIM1->CCMR4 & (u8)(~TIM1_CCMR_OCM)) | (u8)TIM1_OCMode); + } +} + + +/** + * @brief Sets the TIM1 Counter Register value. + * @param[in] Counter specifies the Counter register new value. + * This parameter is between 0x0000 and 0xFFFF. + * @retval None + */ +void TIM1_SetCounter(u16 Counter) +{ + /* Set the Counter Register value */ + TIM1->CNTRH = (u8)(Counter >> 8); + TIM1->CNTRL = (u8)(Counter); + +} + + +/** + * @brief Sets the TIM1 Autoreload Register value. + * @param[in] Autoreload specifies the Autoreload register new value. + * This parameter is between 0x0000 and 0xFFFF. + * @retval None + */ +void TIM1_SetAutoreload(u16 Autoreload) +{ + + /* Set the Autoreload Register value */ + TIM1->ARRH = (u8)(Autoreload >> 8); + TIM1->ARRL = (u8)(Autoreload); + +} + + +/** + * @brief Sets the TIM1 Capture Compare1 Register value. + * @param[in] Compare1 specifies the Capture Compare1 register new value. + * This parameter is between 0x0000 and 0xFFFF. + * @retval None + */ +void TIM1_SetCompare1(u16 Compare1) +{ + /* Set the Capture Compare1 Register value */ + TIM1->CCR1H = (u8)(Compare1 >> 8); + TIM1->CCR1L = (u8)(Compare1); + +} + + +/** + * @brief Sets the TIM1 Capture Compare2 Register value. + * @param[in] Compare2 specifies the Capture Compare2 register new value. + * This parameter is between 0x0000 and 0xFFFF. + * @retval None + */ +void TIM1_SetCompare2(u16 Compare2) +{ + /* Set the Capture Compare2 Register value */ + TIM1->CCR2H = (u8)(Compare2 >> 8); + TIM1->CCR2L = (u8)(Compare2); + +} + + +/** + * @brief Sets the TIM1 Capture Compare3 Register value. + * @param[in] Compare3 specifies the Capture Compare3 register new value. + * This parameter is between 0x0000 and 0xFFFF. + * @retval None + */ +void TIM1_SetCompare3(u16 Compare3) +{ + /* Set the Capture Compare3 Register value */ + TIM1->CCR3H = (u8)(Compare3 >> 8); + TIM1->CCR3L = (u8)(Compare3); + +} + + +/** + * @brief Sets the TIM1 Capture Compare4 Register value. + * @param[in] Compare4 specifies the Capture Compare4 register new value. + * This parameter is between 0x0000 and 0xFFFF. + * @retval None + */ +void TIM1_SetCompare4(u16 Compare4) +{ + /* Set the Capture Compare4 Register value */ + TIM1->CCR4H = (u8)(Compare4 >> 8); + TIM1->CCR4L = (u8)(Compare4); +} + + +/** + * @brief Sets the TIM1 Input Capture 1 prescaler. + * @param[in] TIM1_IC1Prescaler specifies the Input Capture prescaler new value + * This parameter can be one of the following values: + * - TIM1_ICPSC_DIV1: no prescaler + * - TIM1_ICPSC_DIV2: capture is done once every 2 events + * - TIM1_ICPSC_DIV4: capture is done once every 4 events + * - TIM1_ICPSC_DIV8: capture is done once every 8 events + * @retval None + */ +void TIM1_SetIC1Prescaler(TIM1_ICPSC_TypeDef TIM1_IC1Prescaler) +{ + /* Check the parameters */ + assert_param(IS_TIM1_IC_PRESCALER_OK(TIM1_IC1Prescaler)); + + /* Reset the IC1PSC Bits */ /* Set the IC1PSC value */ + TIM1->CCMR1 = (u8)((TIM1->CCMR1 & (u8)(~TIM1_CCMR_ICxPSC)) | (u8)TIM1_IC1Prescaler); + +} + +/** + * @brief Sets the TIM1 Input Capture 2 prescaler. + * @param[in] TIM1_IC2Prescaler specifies the Input Capture prescaler new value + * This parameter can be one of the following values: + * - TIM1_ICPSC_DIV1: no prescaler + * - TIM1_ICPSC_DIV2: capture is done once every 2 events + * - TIM1_ICPSC_DIV4: capture is done once every 4 events + * - TIM1_ICPSC_DIV8: capture is done once every 8 events + * @retval None + */ +void TIM1_SetIC2Prescaler(TIM1_ICPSC_TypeDef TIM1_IC2Prescaler) +{ + + /* Check the parameters */ + assert_param(IS_TIM1_IC_PRESCALER_OK(TIM1_IC2Prescaler)); + + /* Reset the IC1PSC Bits */ /* Set the IC1PSC value */ + TIM1->CCMR2 = (u8)((TIM1->CCMR2 & (u8)(~TIM1_CCMR_ICxPSC)) | (u8)TIM1_IC2Prescaler); +} + + +/** + * @brief Sets the TIM1 Input Capture 3 prescaler. + * @param[in] TIM1_IC3Prescaler specifies the Input Capture prescaler new value + * This parameter can be one of the following values: + * - TIM1_ICPSC_DIV1: no prescaler + * - TIM1_ICPSC_DIV2: capture is done once every 2 events + * - TIM1_ICPSC_DIV4: capture is done once every 4 events + * - TIM1_ICPSC_DIV8: capture is done once every 8 events + * @retval None + */ +void TIM1_SetIC3Prescaler(TIM1_ICPSC_TypeDef TIM1_IC3Prescaler) +{ + + /* Check the parameters */ + assert_param(IS_TIM1_IC_PRESCALER_OK(TIM1_IC3Prescaler)); + + /* Reset the IC1PSC Bits & Set the IC1PSC value */ + TIM1->CCMR3 = (u8)((TIM1->CCMR3 & (u8)(~TIM1_CCMR_ICxPSC)) | (u8)TIM1_IC3Prescaler); +} + + +/** + * @brief Sets the TIM1 Input Capture 4 prescaler. + * @param[in] TIM1_IC4Prescaler specifies the Input Capture prescaler new value + * This parameter can be one of the following values: + * - TIM1_ICPSC_DIV1: no prescaler + * - TIM1_ICPSC_DIV2: capture is done once every 2 events + * - TIM1_ICPSC_DIV4: capture is done once every 4 events + * - TIM1_ICPSC_DIV8: capture is done once every 8 events + * @retval None + */ +void TIM1_SetIC4Prescaler(TIM1_ICPSC_TypeDef TIM1_IC4Prescaler) +{ + + /* Check the parameters */ + assert_param(IS_TIM1_IC_PRESCALER_OK(TIM1_IC4Prescaler)); + + /* Reset the IC1PSC Bits & Set the IC1PSC value */ + TIM1->CCMR4 = (u8)((TIM1->CCMR4 & (u8)(~TIM1_CCMR_ICxPSC)) | (u8)TIM1_IC4Prescaler); +} + + +/** + * @brief Gets the TIM1 Input Capture 1 value. + * @param[in] : + * None + * @retval Capture Compare 1 Register value. + */ +u16 TIM1_GetCapture1(void) +{ + /* Get the Capture 1 Register value */ + + u16 tmpccr1 = 0; + u8 tmpccr1l=0, tmpccr1h=0; + + tmpccr1h = TIM1->CCR1H; + tmpccr1l = TIM1->CCR1L; + + tmpccr1 = (u16)(tmpccr1l); + tmpccr1 |= (u16)((u16)tmpccr1h << 8); + /* Get the Capture 1 Register value */ + return (u16)tmpccr1; +} + +/** + * @brief Gets the TIM1 Input Capture 2 value. + * @param[in] : + * None + * @retval Capture Compare 2 Register value. + */ +u16 TIM1_GetCapture2(void) +{ + /* Get the Capture 2 Register value */ + + u16 tmpccr2 = 0; + u8 tmpccr2l=0, tmpccr2h=0; + + tmpccr2h = TIM1->CCR2H; + tmpccr2l = TIM1->CCR2L; + + tmpccr2 = (u16)(tmpccr2l); + tmpccr2 |= (u16)((u16)tmpccr2h << 8); + /* Get the Capture 2 Register value */ + return (u16)tmpccr2; +} + +/** + * @brief Gets the TIM1 Input Capture 3 value. + * @param[in] : + * None + * @retval Capture Compare 3 Register value. + */ +u16 TIM1_GetCapture3(void) +{ + /* Get the Capture 3 Register value */ + u16 tmpccr3 = 0; + u8 tmpccr3l=0, tmpccr3h=0; + + tmpccr3h = TIM1->CCR3H; + tmpccr3l = TIM1->CCR3L; + + tmpccr3 = (u16)(tmpccr3l); + tmpccr3 |= (u16)((u16)tmpccr3h << 8); + /* Get the Capture 3 Register value */ + return (u16)tmpccr3; +} + +/** + * @brief Gets the TIM1 Input Capture 4 value. + * @param[in] : + * None + * @retval Capture Compare 4 Register value. + */ +u16 TIM1_GetCapture4(void) +{ + /* Get the Capture 4 Register value */ + u16 tmpccr4 = 0; + u8 tmpccr4l=0, tmpccr4h=0; + + tmpccr4h = TIM1->CCR4H; + tmpccr4l = TIM1->CCR4L; + + tmpccr4 = (u16)(tmpccr4l); + tmpccr4 |= (u16)((u16)tmpccr4h << 8); + /* Get the Capture 4 Register value */ + return (u16)tmpccr4; +} + + +/** + * @brief Gets the TIM1 Counter value. + * @param[in] : + * None + * @retval Counter Register value. + */ +u16 TIM1_GetCounter(void) +{ + /* Get the Counter Register value */ + return (u16)(((u16)TIM1->CNTRH << 8) | (u16)(TIM1->CNTRL)); +} + + +/** + * @brief Gets the TIM1 Prescaler value. + * @param[in] : + * None + * @retval Prescaler Register value. + */ +u16 TIM1_GetPrescaler(void) +{ + /* Get the Prescaler Register value */ + return (u16)(((u16)TIM1->PSCRH << 8) | (u16)(TIM1->PSCRL)); +} + + +/** + * @brief Checks whether the specified TIM1 flag is set or not. + * @param[in] TIM1_FLAG specifies the flag to check. + * This parameter can be one of the following values: + * - TIM1_FLAG_UPDATE: TIM1 update Flag + * - TIM1_FLAG_CC1: TIM1 Capture Compare 1 Flag + * - TIM1_FLAG_CC2: TIM1 Capture Compare 2 Flag + * - TIM1_FLAG_CC3: TIM1 Capture Compare 3 Flag + * - TIM1_FLAG_CC4: TIM1 Capture Compare 4 Flag + * - TIM1_FLAG_COM: TIM1 Commutation Flag + * - TIM1_FLAG_TRIGGER: TIM1 Trigger Flag + * - TIM1_FLAG_BREAK: TIM1 Break Flag + * - TIM1_FLAG_CC1OF: TIM1 Capture Compare 1 overcapture Flag + * - TIM1_FLAG_CC2OF: TIM1 Capture Compare 2 overcapture Flag + * - TIM1_FLAG_CC3OF: TIM1 Capture Compare 3 overcapture Flag + * - TIM1_FLAG_CC4OF: TIM1 Capture Compare 4 overcapture Flag + * @retval FlagStatus The new state of TIM1_FLAG (SET or RESET). + */ +FlagStatus TIM1_GetFlagStatus(TIM1_FLAG_TypeDef TIM1_FLAG) +{ + volatile FlagStatus bitstatus = RESET; + vu8 tim1_flag_l, tim1_flag_h; + + /* Check the parameters */ + assert_param(IS_TIM1_GET_FLAG_OK(TIM1_FLAG)); + + tim1_flag_l = (u8)(TIM1_FLAG); + tim1_flag_h = (u8)((u16)TIM1_FLAG >> 8); + + if (((TIM1->SR1 & tim1_flag_l) | (TIM1->SR2 & tim1_flag_h)) != 0) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return (FlagStatus)(bitstatus); +} + + +/** + * @brief Clears the TIM1’s pending flags. + * @param[in] TIM1_FLAG specifies the flag to clear. + * This parameter can be one of the following values: + * - TIM1_FLAG_UPDATE: TIM1 update Flag + * - TIM1_FLAG_CC1: TIM1 Capture Compare 1 Flag + * - TIM1_FLAG_CC2: TIM1 Capture Compare 2 Flag + * - TIM1_FLAG_CC3: TIM1 Capture Compare 3 Flag + * - TIM1_FLAG_CC4: TIM1 Capture Compare 4 Flag + * - TIM1_FLAG_COM: TIM1 Commutation Flag + * - TIM1_FLAG_TRIGGER: TIM1 Trigger Flag + * - TIM1_FLAG_BREAK: TIM1 Break Flag + * - TIM1_FLAG_CC1OF: TIM1 Capture Compare 1 overcapture Flag + * - TIM1_FLAG_CC2OF: TIM1 Capture Compare 2 overcapture Flag + * - TIM1_FLAG_CC3OF: TIM1 Capture Compare 3 overcapture Flag + * - TIM1_FLAG_CC4OF: TIM1 Capture Compare 4 overcapture Flag + * @retval None. + */ +void TIM1_ClearFlag(TIM1_FLAG_TypeDef TIM1_FLAG) +{ + /* Check the parameters */ + assert_param(IS_TIM1_CLEAR_FLAG_OK(TIM1_FLAG)); + + /* Clear the flags (rc_w0) clear this bit by writing 0. Writing ‘1’ has no effect*/ + TIM1->SR1 = (u8)(~(u8)(TIM1_FLAG)); + TIM1->SR2 = (u8)((u8)(~((u8)((u16)TIM1_FLAG >> 8))) & (u8)0x1E); +} + + +/** + * @brief Checks whether the TIM1 interrupt has occurred or not. + * @param[in] TIM1_IT specifies the TIM1 interrupt source to check. + * This parameter can be one of the following values: + * - TIM1_IT_UPDATE: TIM1 update Interrupt source + * - TIM1_IT_CC1: TIM1 Capture Compare 1 Interrupt source + * - TIM1_IT_CC2: TIM1 Capture Compare 2 Interrupt source + * - TIM1_IT_CC3: TIM1 Capture Compare 3 Interrupt source + * - TIM1_IT_CC4: TIM1 Capture Compare 4 Interrupt source + * - TIM1_IT_COM: TIM1 Commutation Interrupt source + * - TIM1_IT_TRIGGER: TIM1 Trigger Interrupt source + * - TIM1_IT_BREAK: TIM1 Break Interrupt source + * @retval ITStatus The new state of the TIM1_IT(SET or RESET). + */ + +ITStatus TIM1_GetITStatus(TIM1_IT_TypeDef TIM1_IT) +{ + volatile ITStatus bitstatus = RESET; + vu8 TIM1_itStatus = 0, TIM1_itEnable = 0; + + /* Check the parameters */ + assert_param(IS_TIM1_GET_IT_OK(TIM1_IT)); + + TIM1_itStatus = (u8)(TIM1->SR1 & (u8)TIM1_IT); + + TIM1_itEnable = (u8)(TIM1->IER & (u8)TIM1_IT); + + if ((TIM1_itStatus != (u8)RESET ) && (TIM1_itEnable != (u8)RESET )) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return (ITStatus)(bitstatus); +} + + +/** + * @brief Clears the TIM1's interrupt pending bits. + * @param[in] TIM1_IT specifies the pending bit to clear. + * This parameter can be one of the following values: + * - TIM1_IT_UPDATE: TIM1 update Interrupt source + * - TIM1_IT_CC1: TIM1 Capture Compare 1 Interrupt source + * - TIM1_IT_CC2: TIM1 Capture Compare 2 Interrupt source + * - TIM1_IT_CC3: TIM1 Capture Compare 3 Interrupt source + * - TIM1_IT_CC4: TIM1 Capture Compare 4 Interrupt source + * - TIM1_IT_COM: TIM1 Commutation Interrupt source + * - TIM1_IT_TRIGGER: TIM1 Trigger Interrupt source + * - TIM1_IT_BREAK: TIM1 Break Interrupt source + * @retval None. + */ +void TIM1_ClearITPendingBit(TIM1_IT_TypeDef TIM1_IT) +{ + /* Check the parameters */ + assert_param(IS_TIM1_IT_OK(TIM1_IT)); + + /* Clear the IT pending Bit */ + TIM1->SR1 = (u8)(~(u8)TIM1_IT); +} + + +/** + * @brief Configure the TI1 as Input. + * @param[in] TIM1_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * - TIM1_ICPOLARITY_FALLING + * - TIM1_ICPOLARITY_RISING + * @param[in] TIM1_ICSelection specifies the input to be used. + * This parameter can be one of the following values: + * - TIM1_ICSELECTION_DIRECTTI: TIM1 Input 1 is selected to + * be connected to IC1. + * - TIM1_ICSELECTION_INDIRECTTI: TIM1 Input 1 is selected to + * be connected to IC2. + * @param[in] TIM1_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TI1_Config(u8 TIM1_ICPolarity, + u8 TIM1_ICSelection, + u8 TIM1_ICFilter) +{ + + /* Disable the Channel 1: Reset the CCE Bit */ + TIM1->CCER1 &= (u8)(~TIM1_CCER1_CC1E); + + /* Select the Input and set the filter */ + TIM1->CCMR1 = (u8)((TIM1->CCMR1 & (u8)(~( TIM1_CCMR_CCxS | TIM1_CCMR_ICxF ))) | (u8)(( (TIM1_ICSelection)) | ((u8)( TIM1_ICFilter << 4)))); + + + + /* Select the Polarity */ + if (TIM1_ICPolarity != TIM1_ICPOLARITY_RISING) + { + TIM1->CCER1 |= TIM1_CCER1_CC1P; + } + else + { + TIM1->CCER1 &= (u8)(~TIM1_CCER1_CC1P); + } + + /* Set the CCE Bit */ + TIM1->CCER1 |= TIM1_CCER1_CC1E; +} + + +/** + * @brief Configure the TI2 as Input. + * @param[in] TIM1_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * - TIM1_ICPOLARITY_FALLING + * - TIM1_ICPOLARITY_RISING + * @param[in] TIM1_ICSelection specifies the input to be used. + * This parameter can be one of the following values: + * - TIM1_ICSELECTION_DIRECTTI: TIM1 Input 2 is selected to + * be connected to IC2. + * - TIM1_ICSELECTION_INDIRECTTI: TIM1 Input 2 is selected to + * be connected to IC1. + * @param[in] TIM1_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TI2_Config(u8 TIM1_ICPolarity, + u8 TIM1_ICSelection, + u8 TIM1_ICFilter) +{ + /* Disable the Channel 2: Reset the CCE Bit */ + TIM1->CCER1 &= (u8)(~TIM1_CCER1_CC2E); + + /* Select the Input and set the filter */ + TIM1->CCMR2 = (u8)((TIM1->CCMR2 & (u8)(~( TIM1_CCMR_CCxS | TIM1_CCMR_ICxF ))) | (u8)(( (TIM1_ICSelection)) | ((u8)( TIM1_ICFilter << 4)))); + /* Select the Polarity */ + if (TIM1_ICPolarity != TIM1_ICPOLARITY_RISING) + { + TIM1->CCER1 |= TIM1_CCER1_CC2P; + } + else + { + TIM1->CCER1 &= (u8)(~TIM1_CCER1_CC2P); + } + /* Set the CCE Bit */ + TIM1->CCER1 |= TIM1_CCER1_CC2E; +} + +/** + * @brief Configure the TI3 as Input. + * @param[in] TIM1_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * - TIM1_ICPOLARITY_FALLING + * - TIM1_ICPOLARITY_RISING + * @param[in] TIM1_ICSelection specifies the input to be used. + * This parameter can be one of the following values: + * - TIM1_ICSELECTION_DIRECTTI: TIM1 Input 3 is selected to + * be connected to IC3. + * - TIM1_ICSELECTION_INDIRECTTI: TIM1 Input 3 is selected to + * be connected to IC4. + * @param[in] TIM1_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TI3_Config(u8 TIM1_ICPolarity, + u8 TIM1_ICSelection, + u8 TIM1_ICFilter) +{ + /* Disable the Channel 3: Reset the CCE Bit */ + TIM1->CCER2 &= (u8)(~TIM1_CCER2_CC3E); + + /* Select the Input and set the filter */ + TIM1->CCMR3 = (u8)((TIM1->CCMR3 & (u8)(~( TIM1_CCMR_CCxS | TIM1_CCMR_ICxF ))) | (u8)(( (TIM1_ICSelection)) | ((u8)( TIM1_ICFilter << 4)))); + + /* Select the Polarity */ + if (TIM1_ICPolarity != TIM1_ICPOLARITY_RISING) + { + TIM1->CCER2 |= TIM1_CCER2_CC3P; + } + else + { + TIM1->CCER2 &= (u8)(~TIM1_CCER2_CC3P); + } + /* Set the CCE Bit */ + TIM1->CCER2 |= TIM1_CCER2_CC3E; +} + + +/** + * @brief Configure the TI4 as Input. + * @param[in] TIM1_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * - TIM1_ICPOLARITY_FALLING + * - TIM1_ICPOLARITY_RISING + * @param[in] TIM1_ICSelection specifies the input to be used. + * This parameter can be one of the following values: + * - TIM1_ICSELECTION_DIRECTTI: TIM1 Input 4 is selected to + * be connected to IC4. + * - TIM1_ICSELECTION_INDIRECTTI: TIM1 Input 4 is selected to + * be connected to IC3. + * @param[in] TIM1_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TI4_Config(u8 TIM1_ICPolarity, + u8 TIM1_ICSelection, + u8 TIM1_ICFilter) +{ + + /* Disable the Channel 4: Reset the CCE Bit */ + TIM1->CCER2 &= (u8)(~TIM1_CCER2_CC4E); + + /* Select the Input and set the filter */ + TIM1->CCMR4 = (u8)((TIM1->CCMR4 & (u8)(~( TIM1_CCMR_CCxS | TIM1_CCMR_ICxF ))) | (u8)(( (TIM1_ICSelection)) | ((u8)( TIM1_ICFilter << 4)))); + + + + /* Select the Polarity */ + if (TIM1_ICPolarity != TIM1_ICPOLARITY_RISING) + { + TIM1->CCER2 |= TIM1_CCER2_CC4P; + } + else + { + TIM1->CCER2 &= (u8)(~TIM1_CCER2_CC4P); + } + + /* Set the CCE Bit */ + TIM1->CCER2 |= TIM1_CCER2_CC4E; +} + + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/ports/stm8/stm8s-periphs/stm8s_tim1.h b/ports/stm8/stm8s-periphs/stm8s_tim1.h new file mode 100644 index 0000000..ede2349 --- /dev/null +++ b/ports/stm8/stm8s-periphs/stm8s_tim1.h @@ -0,0 +1,565 @@ +/** + ****************************************************************************** + * @file stm8s_tim1.h + * @brief This file contains all functions prototype and macros for the TIM1 peripheral. + * @author STMicroelectronics - MCD Application Team + * @version V1.1.1 + * @date 06/05/2009 + ****************************************************************************** + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ * @image html logo.bmp + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM8S_TIM1_H +#define __STM8S_TIM1_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm8s.h" + +/* Exported types ------------------------------------------------------------*/ + + + +/** TIM1 Output Compare and PWM modes */ + +typedef enum +{ + TIM1_OCMODE_TIMING = ((u8)0x00), + TIM1_OCMODE_ACTIVE = ((u8)0x10), + TIM1_OCMODE_INACTIVE = ((u8)0x20), + TIM1_OCMODE_TOGGLE = ((u8)0x30), + TIM1_OCMODE_PWM1 = ((u8)0x60), + TIM1_OCMODE_PWM2 = ((u8)0x70) +}TIM1_OCMode_TypeDef; + +#define IS_TIM1_OC_MODE_OK(MODE) (((MODE) == TIM1_OCMODE_TIMING) || \ + ((MODE) == TIM1_OCMODE_ACTIVE) || \ + ((MODE) == TIM1_OCMODE_INACTIVE) || \ + ((MODE) == TIM1_OCMODE_TOGGLE)|| \ + ((MODE) == TIM1_OCMODE_PWM1) || \ + ((MODE) == TIM1_OCMODE_PWM2)) + +#define IS_TIM1_OCM_OK(MODE)(((MODE) == TIM1_OCMODE_TIMING) || \ + ((MODE) == TIM1_OCMODE_ACTIVE) || \ + ((MODE) == TIM1_OCMODE_INACTIVE) || \ + ((MODE) == TIM1_OCMODE_TOGGLE)|| \ + ((MODE) == TIM1_OCMODE_PWM1) || \ + ((MODE) == TIM1_OCMODE_PWM2) || \ + ((MODE) == TIM1_FORCEDACTION_ACTIVE) || \ + ((MODE) == TIM1_FORCEDACTION_INACTIVE)) + +/** TIM1 One Pulse Mode */ +typedef enum +{ + TIM1_OPMODE_SINGLE = ((u8)0x01), + TIM1_OPMODE_REPETITIVE = ((u8)0x00) +}TIM1_OPMode_TypeDef; + +#define IS_TIM1_OPM_MODE_OK(MODE) (((MODE) == TIM1_OPMODE_SINGLE) || \ + ((MODE) == TIM1_OPMODE_REPETITIVE)) + +/** TIM1 Channel */ + +typedef enum +{ + TIM1_CHANNEL_1 = ((u8)0x00), + TIM1_CHANNEL_2 = ((u8)0x01), + TIM1_CHANNEL_3 = ((u8)0x02), + TIM1_CHANNEL_4 = ((u8)0x03) +}TIM1_Channel_TypeDef; + + +#define IS_TIM1_CHANNEL_OK(CHANNEL) (((CHANNEL) == TIM1_CHANNEL_1) || \ + ((CHANNEL) == TIM1_CHANNEL_2) || \ + ((CHANNEL) == TIM1_CHANNEL_3) || \ + ((CHANNEL) == TIM1_CHANNEL_4)) + +#define IS_TIM1_PWMI_CHANNEL_OK(CHANNEL) (((CHANNEL) == TIM1_CHANNEL_1) || \ + ((CHANNEL) == TIM1_CHANNEL_2)) + +#define IS_TIM1_COMPLEMENTARY_CHANNEL_OK(CHANNEL) (((CHANNEL) == TIM1_CHANNEL_1) || \ + ((CHANNEL) == TIM1_CHANNEL_2) || \ + ((CHANNEL) == TIM1_CHANNEL_3)) + + +/** TIM1 Counter Mode */ +typedef enum +{ + TIM1_COUNTERMODE_UP = ((u8)0x00), + TIM1_COUNTERMODE_DOWN = ((u8)0x10), + TIM1_COUNTERMODE_CENTERALIGNED1 = ((u8)0x20), + TIM1_COUNTERMODE_CENTERALIGNED2 = ((u8)0x40), + TIM1_COUNTERMODE_CENTERALIGNED3 = ((u8)0x60) +}TIM1_CounterMode_TypeDef; + +#define IS_TIM1_COUNTER_MODE_OK(MODE) (((MODE) == TIM1_COUNTERMODE_UP) || \ + ((MODE) == TIM1_COUNTERMODE_DOWN) || \ + ((MODE) == TIM1_COUNTERMODE_CENTERALIGNED1) || \ + ((MODE) == TIM1_COUNTERMODE_CENTERALIGNED2) || \ + ((MODE) == TIM1_COUNTERMODE_CENTERALIGNED3)) + +/** TIM1 Output Compare Polarity */ +typedef enum +{ + TIM1_OCPOLARITY_HIGH = ((u8)0x00), + TIM1_OCPOLARITY_LOW = ((u8)0x22) +}TIM1_OCPolarity_TypeDef; + +#define IS_TIM1_OC_POLARITY_OK(POLARITY) (((POLARITY) == TIM1_OCPOLARITY_HIGH) || \ + ((POLARITY) == TIM1_OCPOLARITY_LOW)) + +/** TIM1 Output Compare N Polarity */ +typedef enum +{ + TIM1_OCNPOLARITY_HIGH = ((u8)0x00), + TIM1_OCNPOLARITY_LOW = ((u8)0x88) +}TIM1_OCNPolarity_TypeDef; + +#define IS_TIM1_OCN_POLARITY_OK(POLARITY) (((POLARITY) == TIM1_OCNPOLARITY_HIGH) || \ + ((POLARITY) == TIM1_OCNPOLARITY_LOW)) + +/** TIM1 Output Compare states */ +typedef enum +{ + TIM1_OUTPUTSTATE_DISABLE = ((u8)0x00), + TIM1_OUTPUTSTATE_ENABLE = ((u8)0x11) +}TIM1_OutputState_TypeDef; + +#define IS_TIM1_OUTPUT_STATE_OK(STATE) (((STATE) == TIM1_OUTPUTSTATE_DISABLE) || \ + ((STATE) == TIM1_OUTPUTSTATE_ENABLE)) + +/** TIM1 Output Compare N States */ +typedef enum +{ + TIM1_OUTPUTNSTATE_DISABLE = ((u8)0x00), + TIM1_OUTPUTNSTATE_ENABLE = ((u8)0x44) +} TIM1_OutputNState_TypeDef; + +#define IS_TIM1_OUTPUTN_STATE_OK(STATE) (((STATE) == TIM1_OUTPUTNSTATE_DISABLE) ||\ + ((STATE) == TIM1_OUTPUTNSTATE_ENABLE)) + +/** TIM1 Break Input enable/disable */ +typedef enum +{ + TIM1_BREAK_ENABLE = ((u8)0x10), + TIM1_BREAK_DISABLE = ((u8)0x00) +}TIM1_BreakState_TypeDef; +#define IS_TIM1_BREAK_STATE_OK(STATE) (((STATE) == TIM1_BREAK_ENABLE) || \ + ((STATE) == TIM1_BREAK_DISABLE)) + +/** TIM1 Break Polarity */ +typedef enum +{ + TIM1_BREAKPOLARITY_LOW = ((u8)0x00), + TIM1_BREAKPOLARITY_HIGH = ((u8)0x20) +}TIM1_BreakPolarity_TypeDef; +#define IS_TIM1_BREAK_POLARITY_OK(POLARITY) (((POLARITY) == TIM1_BREAKPOLARITY_LOW) || \ + ((POLARITY) == TIM1_BREAKPOLARITY_HIGH)) + +/** TIM1 AOE Bit Set/Reset */ +typedef enum +{ + TIM1_AUTOMATICOUTPUT_ENABLE = ((u8)0x40), + TIM1_AUTOMATICOUTPUT_DISABLE = ((u8)0x00) +}TIM1_AutomaticOutput_TypeDef; + +#define IS_TIM1_AUTOMATIC_OUTPUT_STATE_OK(STATE) (((STATE) == TIM1_AUTOMATICOUTPUT_ENABLE) || \ + ((STATE) == TIM1_AUTOMATICOUTPUT_DISABLE)) + +/** TIM1 Lock levels */ +typedef enum +{ + TIM1_LOCKLEVEL_OFF = ((u8)0x00), + TIM1_LOCKLEVEL_1 = ((u8)0x01), + TIM1_LOCKLEVEL_2 = ((u8)0x02), + TIM1_LOCKLEVEL_3 = ((u8)0x03) +}TIM1_LockLevel_TypeDef; + +#define IS_TIM1_LOCK_LEVEL_OK(LEVEL) (((LEVEL) == TIM1_LOCKLEVEL_OFF) || \ + ((LEVEL) == TIM1_LOCKLEVEL_1) || \ + ((LEVEL) == TIM1_LOCKLEVEL_2) || \ + ((LEVEL) == TIM1_LOCKLEVEL_3)) + +/** TIM1 OSSI: Off-State Selection for Idle mode states */ +typedef enum +{ + TIM1_OSSISTATE_ENABLE = ((u8)0x04), + TIM1_OSSISTATE_DISABLE = ((u8)0x00) +}TIM1_OSSIState_TypeDef; + +#define IS_TIM1_OSSI_STATE_OK(STATE) (((STATE) == TIM1_OSSISTATE_ENABLE) || \ + ((STATE) == TIM1_OSSISTATE_DISABLE)) + +/** TIM1 Output Compare Idle State */ +typedef enum +{ + TIM1_OCIDLESTATE_SET = ((u8)0x55), + TIM1_OCIDLESTATE_RESET = ((u8)0x00) +}TIM1_OCIdleState_TypeDef; + +#define IS_TIM1_OCIDLE_STATE_OK(STATE) (((STATE) == TIM1_OCIDLESTATE_SET) || \ + ((STATE) == TIM1_OCIDLESTATE_RESET)) + +/** TIM1 Output Compare N Idle State */ +typedef enum +{ + TIM1_OCNIDLESTATE_SET = ((u8)0x2A), + TIM1_OCNIDLESTATE_RESET = ((u8)0x00) +}TIM1_OCNIdleState_TypeDef; + +#define IS_TIM1_OCNIDLE_STATE_OK(STATE) (((STATE) == TIM1_OCNIDLESTATE_SET) || \ + ((STATE) == TIM1_OCNIDLESTATE_RESET)) + +/** TIM1 Input Capture Polarity */ +typedef enum +{ + TIM1_ICPOLARITY_RISING = ((u8)0x00), + TIM1_ICPOLARITY_FALLING = ((u8)0x01) +}TIM1_ICPolarity_TypeDef; + +#define IS_TIM1_IC_POLARITY_OK(POLARITY) (((POLARITY) == TIM1_ICPOLARITY_RISING) || \ + ((POLARITY) == TIM1_ICPOLARITY_FALLING)) + +/** TIM1 Input Capture Selection */ +typedef enum +{ + TIM1_ICSELECTION_DIRECTTI = ((u8)0x01), + TIM1_ICSELECTION_INDIRECTTI = ((u8)0x02), + TIM1_ICSELECTION_TRGI = ((u8)0x03) +}TIM1_ICSelection_TypeDef; + +#define IS_TIM1_IC_SELECTION_OK(SELECTION) (((SELECTION) == TIM1_ICSELECTION_DIRECTTI) || \ + ((SELECTION) == TIM1_ICSELECTION_INDIRECTTI) || \ + ((SELECTION) == TIM1_ICSELECTION_TRGI)) + +/** TIM1 Input Capture Prescaler */ +typedef enum +{ + TIM1_ICPSC_DIV1 = ((u8)0x00), + TIM1_ICPSC_DIV2 = ((u8)0x04), + TIM1_ICPSC_DIV4 = ((u8)0x08), + TIM1_ICPSC_DIV8 = ((u8)0x0C) +}TIM1_ICPSC_TypeDef; + +#define IS_TIM1_IC_PRESCALER_OK(PRESCALER) (((PRESCALER) == TIM1_ICPSC_DIV1) || \ + ((PRESCALER) == TIM1_ICPSC_DIV2) || \ + ((PRESCALER) == TIM1_ICPSC_DIV4) || \ + ((PRESCALER) == TIM1_ICPSC_DIV8)) + +/** TIM1 Input Capture Filer Value */ + +#define IS_TIM1_IC_FILTER_OK(ICFILTER) (ICFILTER <= 0x0F) + +/** TIM1 External Trigger Filer Value */ +#define IS_TIM1_EXT_TRG_FILTER_OK(FILTER) (FILTER <= 0x0F) + +/** TIM1 interrupt sources */ +typedef enum +{ + TIM1_IT_UPDATE = ((u8)0x01), + TIM1_IT_CC1 = ((u8)0x02), + TIM1_IT_CC2 = ((u8)0x04), + TIM1_IT_CC3 = ((u8)0x08), + TIM1_IT_CC4 = ((u8)0x10), + TIM1_IT_COM = ((u8)0x20), + TIM1_IT_TRIGGER = ((u8)0x40), + TIM1_IT_BREAK = ((u8)0x80) +}TIM1_IT_TypeDef; + +#define IS_TIM1_IT_OK(IT) (IT != 0x00) + +#define IS_TIM1_GET_IT_OK(IT) (((IT) == TIM1_IT_UPDATE) || \ + ((IT) == TIM1_IT_CC1) || \ + ((IT) == TIM1_IT_CC2) || \ + ((IT) == TIM1_IT_CC3) || \ + ((IT) == TIM1_IT_CC4) || \ + ((IT) == TIM1_IT_COM) || \ + ((IT) == TIM1_IT_TRIGGER) || \ + ((IT) == TIM1_IT_BREAK)) + + +/** TIM1 External Trigger Prescaler */ +typedef enum +{ + TIM1_EXTTRGPSC_OFF = ((u8)0x00), + TIM1_EXTTRGPSC_DIV2 = ((u8)0x10), + TIM1_EXTTRGPSC_DIV4 = ((u8)0x20), + TIM1_EXTTRGPSC_DIV8 = ((u8)0x30) +}TIM1_ExtTRGPSC_TypeDef; + +#define IS_TIM1_EXT_PRESCALER_OK(PRESCALER) (((PRESCALER) == TIM1_EXTTRGPSC_OFF) || \ + ((PRESCALER) == TIM1_EXTTRGPSC_DIV2) || \ + ((PRESCALER) == TIM1_EXTTRGPSC_DIV4) || \ + ((PRESCALER) == TIM1_EXTTRGPSC_DIV8)) + +/** TIM1 Internal Trigger Selection */ +typedef enum +{ + TIM1_TS_TIM6 = ((u8)0x00), /*!< TRIG Input source = TIM6 TRIG Output */ + TIM1_TS_TIM5 = ((u8)0x30), /*!< TRIG Input source = TIM5 TRIG Output */ + TIM1_TS_TI1F_ED = ((u8)0x40), + TIM1_TS_TI1FP1 = ((u8)0x50), + TIM1_TS_TI2FP2 = ((u8)0x60), + TIM1_TS_ETRF = ((u8)0x70) +}TIM1_TS_TypeDef; + +#define IS_TIM1_TRIGGER_SELECTION_OK(SELECTION) (((SELECTION) == TIM1_TS_TI1F_ED) || \ + ((SELECTION) == TIM1_TS_TI1FP1) || \ + ((SELECTION) == TIM1_TS_TI2FP2) || \ + ((SELECTION) == TIM1_TS_ETRF) || \ + ((SELECTION) == TIM1_TS_TIM5) || \ + ((SELECTION) == TIM1_TS_TIM6)) + + +#define IS_TIM1_TIX_TRIGGER_SELECTION_OK(SELECTION) (((SELECTION) == TIM1_TS_TI1F_ED) || \ + ((SELECTION) == TIM1_TS_TI1FP1) || \ + ((SELECTION) == TIM1_TS_TI2FP2)) + +/** TIM1 TIx External Clock Source */ +typedef enum +{ + TIM1_TIXEXTERNALCLK1SOURCE_TI1ED = ((u8)0x40), + TIM1_TIXEXTERNALCLK1SOURCE_TI1 = ((u8)0x50), + TIM1_TIXEXTERNALCLK1SOURCE_TI2 = ((u8)0x60) +}TIM1_TIxExternalCLK1Source_TypeDef; + +#define IS_TIM1_TIXCLK_SOURCE_OK(SOURCE) (((SOURCE) == TIM1_TIXEXTERNALCLK1SOURCE_TI1ED) || \ + ((SOURCE) == TIM1_TIXEXTERNALCLK1SOURCE_TI2) || \ + ((SOURCE) == TIM1_TIXEXTERNALCLK1SOURCE_TI1)) + +/** TIM1 External Trigger Polarity */ +typedef enum +{ + TIM1_EXTTRGPOLARITY_INVERTED = ((u8)0x80), + TIM1_EXTTRGPOLARITY_NONINVERTED = ((u8)0x00) +}TIM1_ExtTRGPolarity_TypeDef; + +#define IS_TIM1_EXT_POLARITY_OK(POLARITY) (((POLARITY) == TIM1_EXTTRGPOLARITY_INVERTED) || \ + ((POLARITY) == TIM1_EXTTRGPOLARITY_NONINVERTED)) + +/** TIM1 Prescaler Reload Mode */ +typedef enum +{ + TIM1_PSCRELOADMODE_UPDATE = ((u8)0x00), + TIM1_PSCRELOADMODE_IMMEDIATE = ((u8)0x01) +}TIM1_PSCReloadMode_TypeDef; + +#define IS_TIM1_PRESCALER_RELOAD_OK(RELOAD) (((RELOAD) == TIM1_PSCRELOADMODE_UPDATE) || \ + ((RELOAD) == TIM1_PSCRELOADMODE_IMMEDIATE)) + +/** TIM1 Encoder Mode */ +typedef enum +{ + TIM1_ENCODERMODE_TI1 = ((u8)0x01), + TIM1_ENCODERMODE_TI2 = ((u8)0x02), + TIM1_ENCODERMODE_TI12 = ((u8)0x03) +}TIM1_EncoderMode_TypeDef; + +#define IS_TIM1_ENCODER_MODE_OK(MODE) (((MODE) == TIM1_ENCODERMODE_TI1) || \ + ((MODE) == TIM1_ENCODERMODE_TI2) || \ + ((MODE) == TIM1_ENCODERMODE_TI12)) + +/** TIM1 Event Source */ +typedef enum +{ + TIM1_EVENTSOURCE_UPDATE = ((u8)0x01), + TIM1_EVENTSOURCE_CC1 = ((u8)0x02), + TIM1_EVENTSOURCE_CC2 = ((u8)0x04), + TIM1_EVENTSOURCE_CC3 = ((u8)0x08), + TIM1_EVENTSOURCE_CC4 = ((u8)0x10), + TIM1_EVENTSOURCE_COM = ((u8)0x20), + TIM1_EVENTSOURCE_TRIGGER = ((u8)0x40), + TIM1_EVENTSOURCE_BREAK = ((u8)0x80) +}TIM1_EventSource_TypeDef; + +#define IS_TIM1_EVENT_SOURCE_OK(SOURCE) ((SOURCE) != 0x00) + +/** TIM1 Update Source */ +typedef enum +{ + TIM1_UPDATESOURCE_GLOBAL = ((u8)0x00), + TIM1_UPDATESOURCE_REGULAR = ((u8)0x01) +}TIM1_UpdateSource_TypeDef; + +#define IS_TIM1_UPDATE_SOURCE_OK(SOURCE) (((SOURCE) == TIM1_UPDATESOURCE_GLOBAL) || \ + ((SOURCE) == TIM1_UPDATESOURCE_REGULAR)) + +/** TIM1 Trigger Output Source */ +typedef enum +{ + TIM1_TRGOSOURCE_RESET = ((u8)0x00), + TIM1_TRGOSOURCE_ENABLE = ((u8)0x10), + TIM1_TRGOSOURCE_UPDATE = ((u8)0x20), + TIM1_TRGOSource_OC1 = ((u8)0x30), + TIM1_TRGOSOURCE_OC1REF = ((u8)0x40), + TIM1_TRGOSOURCE_OC2REF = ((u8)0x50), + TIM1_TRGOSOURCE_OC3REF = ((u8)0x60) +}TIM1_TRGOSource_TypeDef; + +#define IS_TIM1_TRGO_SOURCE_OK(SOURCE) (((SOURCE) == TIM1_TRGOSOURCE_RESET) || \ + ((SOURCE) == TIM1_TRGOSOURCE_ENABLE) || \ + ((SOURCE) == TIM1_TRGOSOURCE_UPDATE) || \ + ((SOURCE) == TIM1_TRGOSource_OC1) || \ + ((SOURCE) == TIM1_TRGOSOURCE_OC1REF) || \ + ((SOURCE) == TIM1_TRGOSOURCE_OC2REF) || \ + ((SOURCE) == TIM1_TRGOSOURCE_OC3REF)) + +/** TIM1 Slave Mode */ +typedef enum +{ + TIM1_SLAVEMODE_RESET = ((u8)0x04), + TIM1_SLAVEMODE_GATED = ((u8)0x05), + TIM1_SLAVEMODE_TRIGGER = ((u8)0x06), + TIM1_SLAVEMODE_EXTERNAL1 = ((u8)0x07) +}TIM1_SlaveMode_TypeDef; + +#define IS_TIM1_SLAVE_MODE_OK(MODE) (((MODE) == TIM1_SLAVEMODE_RESET) || \ + ((MODE) == TIM1_SLAVEMODE_GATED) || \ + ((MODE) == TIM1_SLAVEMODE_TRIGGER) || \ + ((MODE) == TIM1_SLAVEMODE_EXTERNAL1)) + +/** TIM1 Flags */ +typedef enum +{ + TIM1_FLAG_UPDATE = ((u16)0x0001), + TIM1_FLAG_CC1 = ((u16)0x0002), + TIM1_FLAG_CC2 = ((u16)0x0004), + TIM1_FLAG_CC3 = ((u16)0x0008), + TIM1_FLAG_CC4 = ((u16)0x0010), + TIM1_FLAG_COM = ((u16)0x0020), + TIM1_FLAG_TRIGGER = ((u16)0x0040), + TIM1_FLAG_BREAK = ((u16)0x0080), + TIM1_FLAG_CC1OF = ((u16)0x0200), + TIM1_FLAG_CC2OF = ((u16)0x0400), + TIM1_FLAG_CC3OF = ((u16)0x0800), + TIM1_FLAG_CC4OF = ((u16)0x1000) +}TIM1_FLAG_TypeDef; + +#define IS_TIM1_GET_FLAG_OK(FLAG) (((FLAG) == TIM1_FLAG_UPDATE) || \ + ((FLAG) == TIM1_FLAG_CC1) || \ + ((FLAG) == TIM1_FLAG_CC2) || \ + ((FLAG) == TIM1_FLAG_CC3) || \ + ((FLAG) == TIM1_FLAG_CC4) || \ + ((FLAG) == TIM1_FLAG_COM) || \ + ((FLAG) == TIM1_FLAG_TRIGGER) || \ + ((FLAG) == TIM1_FLAG_BREAK) || \ + ((FLAG) == TIM1_FLAG_CC1OF) || \ + ((FLAG) == TIM1_FLAG_CC2OF) || \ + ((FLAG) == TIM1_FLAG_CC3OF) || \ + ((FLAG) == TIM1_FLAG_CC4OF)) + +#define IS_TIM1_CLEAR_FLAG_OK(FLAG) ((((u16)FLAG & (u16)0xE100) == 0x0000) && (FLAG != 0x0000)) + +/** TIM1 Forced Action */ +typedef enum +{ + TIM1_FORCEDACTION_ACTIVE = ((u8)0x50), + TIM1_FORCEDACTION_INACTIVE = ((u8)0x40) +}TIM1_ForcedAction_TypeDef; + +#define IS_TIM1_FORCED_ACTION_OK(ACTION) ((ACTION == TIM1_FORCEDACTION_ACTIVE) || \ + (ACTION == TIM1_FORCEDACTION_INACTIVE)) +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup TIM1_Exported_Functions + * @{ + */ + +void TIM1_DeInit(void); +void TIM1_TimeBaseInit(u16 TIM1_Prescaler, TIM1_CounterMode_TypeDef TIM1_CounterMode, u16 TIM1_Period, u8 TIM1_RepetitionCounter); +void TIM1_OC1Init(TIM1_OCMode_TypeDef TIM1_OCMode, TIM1_OutputState_TypeDef TIM1_OutputState, TIM1_OutputNState_TypeDef TIM1_OutputNState, u16 TIM1_Pulse, TIM1_OCPolarity_TypeDef TIM1_OCPolarity, TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity, TIM1_OCIdleState_TypeDef TIM1_OCIdleState, TIM1_OCNIdleState_TypeDef TIM1_OCNIdleState); +void TIM1_OC2Init(TIM1_OCMode_TypeDef TIM1_OCMode, TIM1_OutputState_TypeDef TIM1_OutputState, TIM1_OutputNState_TypeDef TIM1_OutputNState, u16 TIM1_Pulse, TIM1_OCPolarity_TypeDef TIM1_OCPolarity, TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity, TIM1_OCIdleState_TypeDef TIM1_OCIdleState, TIM1_OCNIdleState_TypeDef TIM1_OCNIdleState); +void TIM1_OC3Init(TIM1_OCMode_TypeDef TIM1_OCMode, TIM1_OutputState_TypeDef TIM1_OutputState, TIM1_OutputNState_TypeDef TIM1_OutputNState, u16 TIM1_Pulse, TIM1_OCPolarity_TypeDef TIM1_OCPolarity, TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity, TIM1_OCIdleState_TypeDef TIM1_OCIdleState, TIM1_OCNIdleState_TypeDef TIM1_OCNIdleState); +void TIM1_OC4Init(TIM1_OCMode_TypeDef TIM1_OCMode, TIM1_OutputState_TypeDef TIM1_OutputState, u16 TIM1_Pulse, TIM1_OCPolarity_TypeDef TIM1_OCPolarity, TIM1_OCIdleState_TypeDef TIM1_OCIdleState); +void TIM1_BDTRConfig(TIM1_OSSIState_TypeDef TIM1_OSSIState, TIM1_LockLevel_TypeDef TIM1_LockLevel, u8 TIM1_DeadTime, TIM1_BreakState_TypeDef TIM1_Break, TIM1_BreakPolarity_TypeDef TIM1_BreakPolarity, TIM1_AutomaticOutput_TypeDef TIM1_AutomaticOutput); +void TIM1_ICInit(TIM1_Channel_TypeDef TIM1_Channel, TIM1_ICPolarity_TypeDef TIM1_ICPolarity, TIM1_ICSelection_TypeDef TIM1_ICSelection, TIM1_ICPSC_TypeDef TIM1_ICPrescaler, u8 TIM1_ICFilter); +void TIM1_PWMIConfig(TIM1_Channel_TypeDef TIM1_Channel, TIM1_ICPolarity_TypeDef TIM1_ICPolarity, TIM1_ICSelection_TypeDef TIM1_ICSelection, TIM1_ICPSC_TypeDef TIM1_ICPrescaler, u8 TIM1_ICFilter); +void TIM1_Cmd(FunctionalState NewState); +void TIM1_CtrlPWMOutputs(FunctionalState Newstate); +void TIM1_ITConfig(TIM1_IT_TypeDef TIM1_IT, FunctionalState NewState); +void TIM1_InternalClockConfig(void); +void TIM1_ETRClockMode1Config(TIM1_ExtTRGPSC_TypeDef TIM1_ExtTRGPrescaler, TIM1_ExtTRGPolarity_TypeDef TIM1_ExtTRGPolarity, u8 ExtTRGFilter); +void TIM1_ETRClockMode2Config(TIM1_ExtTRGPSC_TypeDef TIM1_ExtTRGPrescaler, TIM1_ExtTRGPolarity_TypeDef TIM1_ExtTRGPolarity, u8 ExtTRGFilter); +void TIM1_ETRConfig(TIM1_ExtTRGPSC_TypeDef TIM1_ExtTRGPrescaler, TIM1_ExtTRGPolarity_TypeDef TIM1_ExtTRGPolarity, u8 ExtTRGFilter); +void TIM1_TIxExternalClockConfig(TIM1_TIxExternalCLK1Source_TypeDef TIM1_TIxExternalCLKSource, TIM1_ICPolarity_TypeDef TIM1_ICPolarity, u8 ICFilter); +void TIM1_SelectInputTrigger(TIM1_TS_TypeDef TIM1_InputTriggerSource); +void TIM1_UpdateDisableConfig(FunctionalState Newstate); +void TIM1_UpdateRequestConfig(TIM1_UpdateSource_TypeDef TIM1_UpdateSource); +void TIM1_SelectHallSensor(FunctionalState Newstate); +void TIM1_SelectOnePulseMode(TIM1_OPMode_TypeDef TIM1_OPMode); +void TIM1_SelectOutputTrigger(TIM1_TRGOSource_TypeDef TIM1_TRGOSource); +void TIM1_SelectSlaveMode(TIM1_SlaveMode_TypeDef TIM1_SlaveMode); +void TIM1_SelectMasterSlaveMode(FunctionalState NewState); +void TIM1_EncoderInterfaceConfig(TIM1_EncoderMode_TypeDef TIM1_EncoderMode, TIM1_ICPolarity_TypeDef TIM1_IC1Polarity, TIM1_ICPolarity_TypeDef TIM1_IC2Polarity); +void TIM1_PrescalerConfig(u16 Prescaler, TIM1_PSCReloadMode_TypeDef TIM1_PSCReloadMode); +void TIM1_CounterModeConfig(TIM1_CounterMode_TypeDef TIM1_CounterMode); +void TIM1_ForcedOC1Config(TIM1_ForcedAction_TypeDef TIM1_ForcedAction); +void TIM1_ForcedOC2Config(TIM1_ForcedAction_TypeDef TIM1_ForcedAction); +void TIM1_ForcedOC3Config(TIM1_ForcedAction_TypeDef TIM1_ForcedAction); +void TIM1_ForcedOC4Config(TIM1_ForcedAction_TypeDef TIM1_ForcedAction); +void TIM1_ARRPreloadConfig(FunctionalState Newstate); +void TIM1_SelectCOM(FunctionalState Newstate); +void TIM1_CCPreloadControl(FunctionalState Newstate); +void TIM1_OC1PreloadConfig(FunctionalState Newstate); +void TIM1_OC2PreloadConfig(FunctionalState Newstate); +void TIM1_OC3PreloadConfig(FunctionalState Newstate); +void TIM1_OC4PreloadConfig(FunctionalState Newstate); +void TIM1_OC1FastConfig(FunctionalState Newstate); +void TIM1_OC2FastConfig(FunctionalState Newstate); +void TIM1_OC3FastConfig(FunctionalState Newstate); +void TIM1_OC4FastConfig(FunctionalState Newstate); +void TIM1_GenerateEvent(TIM1_EventSource_TypeDef TIM1_EventSource); +void TIM1_OC1PolarityConfig(TIM1_OCPolarity_TypeDef TIM1_OCPolarity); +void TIM1_OC1NPolarityConfig(TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity); +void TIM1_OC2PolarityConfig(TIM1_OCPolarity_TypeDef TIM1_OCPolarity); +void TIM1_OC2NPolarityConfig(TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity); +void TIM1_OC3PolarityConfig(TIM1_OCPolarity_TypeDef TIM1_OCPolarity); +void TIM1_OC3NPolarityConfig(TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity); +void TIM1_OC4PolarityConfig(TIM1_OCPolarity_TypeDef TIM1_OCPolarity); +void TIM1_CCxCmd(TIM1_Channel_TypeDef TIM1_Channel, FunctionalState Newstate); +void TIM1_CCxNCmd(TIM1_Channel_TypeDef TIM1_Channel, FunctionalState Newstate); +void TIM1_SelectOCxM(TIM1_Channel_TypeDef TIM1_Channel, TIM1_OCMode_TypeDef TIM1_OCMode); +void TIM1_SetCounter(u16 Counter); +void TIM1_SetAutoreload(u16 Autoreload); +void TIM1_SetCompare1(u16 Compare1); +void TIM1_SetCompare2(u16 Compare2); +void TIM1_SetCompare3(u16 Compare3); +void TIM1_SetCompare4(u16 Compare4); +void TIM1_SetIC1Prescaler(TIM1_ICPSC_TypeDef TIM1_IC1Prescaler); +void TIM1_SetIC2Prescaler(TIM1_ICPSC_TypeDef TIM1_IC2Prescaler); +void TIM1_SetIC3Prescaler(TIM1_ICPSC_TypeDef TIM1_IC3Prescaler); +void TIM1_SetIC4Prescaler(TIM1_ICPSC_TypeDef TIM1_IC4Prescaler); +u16 TIM1_GetCapture1(void); +u16 TIM1_GetCapture2(void); +u16 TIM1_GetCapture3(void); +u16 TIM1_GetCapture4(void); +u16 TIM1_GetCounter(void); +u16 TIM1_GetPrescaler(void); +FlagStatus TIM1_GetFlagStatus(TIM1_FLAG_TypeDef TIM1_FLAG); +void TIM1_ClearFlag(TIM1_FLAG_TypeDef TIM1_FLAG); +ITStatus TIM1_GetITStatus(TIM1_IT_TypeDef TIM1_IT); +void TIM1_ClearITPendingBit(TIM1_IT_TypeDef TIM1_IT); + +/** + * @} + */ + +#endif /* __STM8S_TIM1_H */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/ports/stm8/stm8s-periphs/stm8s_type.h b/ports/stm8/stm8s-periphs/stm8s_type.h new file mode 100644 index 0000000..5c80f66 --- /dev/null +++ b/ports/stm8/stm8s-periphs/stm8s_type.h @@ -0,0 +1,103 @@ +/** + ****************************************************************************** + * @file stm8s_type.h + * @brief This file contains all common data types. + * @author STMicroelectronics - MCD Application Team + * @version V1.1.1 + * @date 06/05/2009 + ****************************************************************************** + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ * @image html logo.bmp + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM8S_TYPE_H +#define __STM8S_TYPE_H + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +typedef signed long s32; +typedef signed short s16; +typedef signed char s8; + +typedef signed long const sc32; /* Read Only */ +typedef signed short const sc16; /* Read Only */ +typedef signed char const sc8; /* Read Only */ + +typedef volatile signed long vs32; +typedef volatile signed short vs16; +typedef volatile signed char vs8; + +typedef volatile signed long const vsc32; /* Read Only */ +typedef volatile signed short const vsc16; /* Read Only */ +typedef volatile signed char const vsc8; /* Read Only */ + +typedef unsigned long u32; +typedef unsigned short u16; +typedef unsigned char u8; + +typedef unsigned long const uc32; /* Read Only */ +typedef unsigned short const uc16; /* Read Only */ +typedef unsigned char const uc8; /* Read Only */ + +typedef volatile unsigned long vu32; +typedef volatile unsigned short vu16; +typedef volatile unsigned char vu8; + +typedef volatile unsigned long const vuc32; /* Read Only */ +typedef volatile unsigned short const vuc16; /* Read Only */ +typedef volatile unsigned char const vuc8; /* Read Only */ + +typedef enum +{ + FALSE = 0, + TRUE = !FALSE +} +bool; + +typedef enum { + RESET = 0, + SET = !RESET +} +FlagStatus, ITStatus, BitStatus; + +typedef enum { + DISABLE = 0, + ENABLE = !DISABLE +} +FunctionalState; + +#define IS_FUNCTIONALSTATE_OK(VALUE) ( (VALUE == ENABLE) || (VALUE == DISABLE) ) + +typedef enum { + ERROR = 0, + SUCCESS = !ERROR +} +ErrorStatus; + +#define U8_MAX ((u8)255) +#define S8_MAX ((s8)127) +#define S8_MIN ((s8)-128) +#define U16_MAX ((u16)65535u) +#define S16_MAX ((s16)32767) +#define S16_MIN ((s16)-32768) +#define U32_MAX ((u32)4294967295uL) +#define S32_MAX ((s32)2147483647) +#define S32_MIN ((s32)-2147483648) + +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +#endif /* __STM8S_TYPE_H */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/ports/stm8/stm8s_conf.h b/ports/stm8/stm8s_conf.h new file mode 100644 index 0000000..df41b86 --- /dev/null +++ b/ports/stm8/stm8s_conf.h @@ -0,0 +1,259 @@ +/** + ****************************************************************************** + * @file stm8s_conf.h + * @brief This file is used to configure the Library. + * @author STMicroelectronics - MCD Application Team + * @version V1.1.1 + * @date 06/05/2009 + ****************************************************************************** + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ * @image html logo.bmp + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM8S_CONF_H +#define __STM8S_CONF_H + +/* Atomthreads port: Use STM8S105 */ +#define STM8S105 + +/* Includes ------------------------------------------------------------------*/ +#include "stm8s.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + + +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* In the following line adjust the value of External High Speed oscillator (HSE) + used in your application */ +#if defined (STM8S208) || defined (STM8S207) + #define HSE_VALUE ((u32)24000000) /* Value of the External oscillator in Hz*/ +#else + #define HSE_VALUE ((u32)16000000) /* Value of the External oscillator in Hz*/ +#endif + +/* Uncomment the line below to enable peripheral header file inclusion */ + +/************************************* ADC ************************************/ +#if defined(STM8S105) || defined(STM8S103) || defined(STM8S903) +/* #define _ADC1 (1) */ +#endif /* (STM8S105) ||(STM8S103) || (STM8S903) */ + +#if defined(STM8S208) || defined(STM8S207) +/* #define _ADC2 (1) */ +#endif /* (STM8S208) ||(STM8S207) */ + +/************************************* AWU ************************************/ +/* #define _AWU (1) */ + +/************************************* BEEP ***********************************/ +/* #define _BEEP (1) */ + +/************************************* CLK ************************************/ +#ifdef STM8S208 + /* #define _CAN (1) */ +#endif /* (STM8S208) */ + +/************************************* CLK ************************************/ + #define _CLK (1) + +/************************************* EXTI ***********************************/ +/* #define _EXTI (1) */ + +/******************************* FLASH/DATA EEPROM ****************************/ +/* #define _FLASH (1) */ + +/********************************* OPTION BYTES *******************************/ +/* #define _OPT (1) */ + +/************************************* GPIO ***********************************/ +#define _GPIO (1) + +/************************************* I2C ************************************/ +/* #define _I2C (1) */ + +/************************************* ITC ************************************/ +/* #define _ITC (1) */ + +/************************************* IWDG ***********************************/ +/* #define _IWDG (1) */ + +/************************************* RST ************************************/ +/* #define _RST (1) */ + +/************************************* SPI ************************************/ +/* #define _SPI (1) */ + +/************************************* TIM1 ***********************************/ +/* Atomthreads port: Use TIM1 for the system tick (10ms) */ +#define _TIM1 (1) + +/************************************* TIM2 ***********************************/ +#if defined(STM8S208) ||defined(STM8S207) ||defined(STM8S103) ||defined(STM8S105) +/* #define _TIM2 (1) */ +#endif /* (STM8S208) ||(STM8S207) || (STM8S103) || (STM8S105) */ + +/************************************* TIM3 ***********************************/ +#if defined(STM8S208) ||defined(STM8S207) ||defined(STM8S105) +/* #define _TIM3 (1) */ +#endif /* (STM8S208) ||(STM8S207) || (STM8S105) */ + +/************************************* TIM4 ***********************************/ +#if defined(STM8S208) ||defined(STM8S207) ||defined(STM8S103) ||defined(STM8S105) +/* #define _TIM4 (1) */ +#endif /* (STM8S208) ||(STM8S207) || (STM8S103) || (STM8S105) */ + +/************************************* TIM5 & TIM6 ****************************/ +#ifdef STM8S903 +/* #define _TIM5 (1) */ +/* #define _TIM6 (1) */ +#endif /* STM8S903 */ + +/************************************* UARTx **********************************/ +#if defined(STM8S208) ||defined(STM8S207) ||defined(STM8S103) ||defined(STM8S903) +/* #define _UART1 (1) */ +#endif /* (STM8S208) ||(STM8S207) || (STM8S103) || (STM8S903) */ + +#ifdef STM8S105 +/* #define _UART2 (1) */ +#endif /* STM8S105 */ + +#if defined(STM8S208) ||defined(STM8S207) +/* #define _UART3 (1) */ +#endif /* (STM8S208) ||(STM8S207) */ + +/************************************* WWDG ***********************************/ +/* #define _WWDG (1) */ + +/* Exported macro ------------------------------------------------------------*/ + +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval : None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((u8 *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(u8* file, u32 line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + + +/* Peripheral header file inclusion ******************************************/ +#ifdef _ADC1 + #include "stm8s_adc1.h" +#endif /* _ADC1 */ + +#ifdef _ADC2 + #include "stm8s_adc2.h" +#endif /* _ADC2 */ + +#ifdef _AWU + #include "stm8s_awu.h" +#endif /* _AWU */ + +#ifdef _BEEP + #include "stm8s_beep.h" +#endif /* _BEEP */ + +#ifdef _CLK + #include "stm8s_clk.h" +#endif /* _CLK */ + +#ifdef _EXTI + #include "stm8s_exti.h" +#endif /* _EXTI */ + +#if defined(_FLASH) || defined(_OPT) + #include "stm8s_flash.h" +#endif /* _FLASH/OPT */ + +#ifdef _GPIO + #include "stm8s_gpio.h" +#endif /* _GPIOx */ + +#ifdef _I2C + #include "stm8s_i2c.h" +#endif /* _I2C */ + +#ifdef _ITC + #include "stm8s_itc.h" +#endif /* _ITC */ + +#ifdef _IWDG + #include "stm8s_iwdg.h" +#endif /* _IWDG */ + +#ifdef _RST + #include "stm8s_rst.h" +#endif /* _RST */ + +#ifdef _SPI + #include "stm8s_spi.h" +#endif /* _SPI */ + +#ifdef _TIM1 + #include "stm8s_tim1.h" +#endif /* _TIM1 */ + +#ifdef _TIM2 + #include "stm8s_tim2.h" +#endif /* _TIM2 */ + +#ifdef _TIM3 + #include "stm8s_tim3.h" +#endif /* _TIM3 */ + +#ifdef _TIM4 + #include "stm8s_tim4.h" +#endif /* _TIM4 */ + +#ifdef _TIM5 + #include "stm8s_tim5.h" +#endif /* _TIM5 */ + +#ifdef _TIM6 + #include "stm8s_tim6.h" +#endif /* _TIM6 */ + +#ifdef _UART1 + #include "stm8s_uart1.h" +#endif /* _UART1 */ + +#ifdef _UART2 + #include "stm8s_uart2.h" +#endif /* _UART2 */ + +#ifdef _UART3 + #include "stm8s_uart3.h" +#endif /* _UART3 */ + +#ifdef _WWDG + #include "stm8s_wwdg.h" +#endif /* _WWDG */ + +#ifdef _CAN + #include "stm8s_can.h" +#endif /* _CAN */ + +#endif /* __STM8S_CONF_H */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/ports/stm8/tests-main.c b/ports/stm8/tests-main.c new file mode 100644 index 0000000..c9356fa --- /dev/null +++ b/ports/stm8/tests-main.c @@ -0,0 +1,215 @@ +/* + * Copyright (c) 2010, Kelvin Lawson. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. No personal names or organizations' names associated with the + * Atomthreads project may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + + +#include "atom.h" +#include "atomport-private.h" +#include "atomtests.h" +#include "atomtimer.h" +#include "stm8s.h" + + +/* Constants */ + +/* + * Idle thread stack size + * + * This needs to be large enough to handle any interrupt handlers + * and callbacks called by interrupt handlers (e.g. user-created + * timer callbacks) as well as the saving of all context when + * switching away from this thread. + * + * In this case, the idle stack is allocated on the BSS via the + * idle_thread_stack[] byte array. + */ +#define IDLE_STACK_SIZE_BYTES 196 + + +/* + * Startup code stack size + * + * This defines the size of stack allowed for the main() startup + * code before the OS is actually started. This needs to be large + * enough to manage the atomOSInit(), atomOSStart() and + * atomThreadCreate() calls which occur before the OS is started. + * + * In this case we use the default startup stack location used by + * the STM8 compiler of the top of RAM above all data sections + * etc. After the OS is started this allocation is no longer required, + * therefore you could alternatively use some location which you + * know that your application will not use until the OS is started. + * Note that you cannot use the idle thread or main thread stack + * here because the stack contexts of these threads are initialised + * during OS creation. + * + * Instead of reusing some application area, here we set aside + * 64 bytes of RAM for this purpose, because we call out to + * several different test applications, and do not know of any + * particular application locations which will be free to use. + */ +#define STARTUP_STACK_SIZE_BYTES 64 + + +/* + * Main thread stack size + * + * Here we utilise the space starting at 64 bytes below the startup + * stack for the Main application thread. Note that this is not a + * required OS kernel thread - you will replace this with your own + * application thread. + * + * In this case the Main thread is responsible for calling out to the + * test routines. Once a test routine has finished, the thread remains + * running and loops flashing a LED slowly (if the test passed) or + * quickly (if the test failed). + * + * The Main thread stack generally needs to be larger than the idle + * thread stack, as not only does it need to store interrupt handler + * stack saves and context switch saves, but the application main thread + * will generally be carrying out more nested function calls and require + * stack for application code local variables etc. + * + * Care must be taken to ensure that the data section, BSS section, + * and 64 byte startup section leave enough free space for the main + * thread. You can view the linker-generated map file to view the size + * of the various data sections in your applications. For example if you + * require a 196 byte main thread stack, then the data allocations and + * startup stack combined must not exceed RAMSIZE-196 bytes. + */ + + +/* Linker-provided startup stack location (usually top of RAM) */ +extern int _stack; + + +/* Local data */ + +/* Application threads' TCBs */ +static ATOM_TCB main_tcb; + +/* Idle thread's stack area (large so place outside of the small page0 area on STM8) */ +@near static uint8_t idle_thread_stack[IDLE_STACK_SIZE_BYTES]; + + +/* Forward declarations */ +static void main_thread_func (uint32_t data); + + +/** + * \b main + * + * Program entry point. + * + * Sets up the STM8 hardware resources (system tick timer interrupt) necessary + * for the OS to be started. Creates an application thread and starts the OS. + */ +void main ( void ) +{ + int8_t status; + + /** + * Note: to protect OS structures and data during initialisation, + * interrupts must remain disabled until the first thread + * has been restored. They are reenabled at the very end of + * the first thread restore, at which point it is safe for a + * reschedule to take place. + */ + + /* Initialise the OS before creating our threads */ + status = atomOSInit(&idle_thread_stack[IDLE_STACK_SIZE_BYTES - 1]); + if (status == ATOM_OK) + { + /* Enable the system tick timer */ + archInitSystemTickTimer(); + + /* Create an application thread */ + status = atomThreadCreate(&main_tcb, + TEST_THREAD_PRIO, main_thread_func, 0, + (POINTER)(&_stack-STARTUP_STACK_SIZE_BYTES)); + if (status == ATOM_OK) + { + /** + * First application thread successfully created. It is + * now possible to start the OS. Execution will not return + * from atomOSStart(), which will restore the context of + * our application thread and start executing it. + * + * Note that interrupts are still disabled at this point. + * They will be enabled as we restore and execute our first + * thread in archFirstThreadRestore(). + */ + atomOSStart(); + } + } + + while (1) + ; + + /* There was an error starting the OS if we reach here */ + return; +} + + +/** + * \b main_thread_func + * + * Entry point for main application thread. + * + * This is the first thread that will be executed when the OS is started. + * + * @param[in] data Unused (optional thread entry parameter) + * + * @return None + */ +static void main_thread_func (uint32_t data) +{ + uint32_t test_status; + int sleep_ticks; + + /* Start test. All tests use the same start API. */ + test_status = test_start(); + + /* Flash LED once per second if passed, very quickly if failed */ + sleep_ticks = (test_status == 0) ? SYSTEM_TICKS_PER_SEC : (SYSTEM_TICKS_PER_SEC/8); + + /* Configure GPIO for flashing the STM8S Discovery LED on GPIO D0 */ + GPIO_DeInit(GPIOD); + GPIO_Init(GPIOD, GPIO_PIN_0, GPIO_MODE_OUT_PP_LOW_FAST); + + /* Test finished, flash slowly for pass, fast for fail */ + while (1) + { + /* Toggle LED on pin D0 (Discovery-specific) */ + GPIO_WriteReverse(GPIOD, GPIO_PIN_0); + + /* Sleep then toggle LED again */ + atomTimerDelay(sleep_ticks); + } +} +