diff --git a/ports/armv7/Makefile b/ports/armv7/Makefile new file mode 100644 index 0000000..87b9c17 --- /dev/null +++ b/ports/armv7/Makefile @@ -0,0 +1,19 @@ +ATOMTHREADS_PORT = $(COLOSSAL)/libraries/atomthreads/ports/armv7 +ATOMTHREADS_KERNEL = $(COLOSSAL)/libraries/atomthreads/kernel + +INCLUDES := $(INCLUDES) \ + -I$(ATOMTHREADS_KERNEL) \ + -I$(ATOMTHREADS_PORT) + +SRCS := $(SRCS) \ + $(ATOMTHREADS_KERNEL)/atomkernel.c \ + $(ATOMTHREADS_KERNEL)/atommutex.c \ + $(ATOMTHREADS_KERNEL)/atomqueue.c \ + $(ATOMTHREADS_KERNEL)/atomsem.c \ + $(ATOMTHREADS_KERNEL)/atomtimer.c \ + $(ATOMTHREADS_PORT)/atomport.c + +ASMS := $(ASMS) \ + $(ATOMTHREADS_PORT)/atomport_arm.asm + + diff --git a/ports/armv7/README b/ports/armv7/README new file mode 100644 index 0000000..f3bc0fa --- /dev/null +++ b/ports/armv7/README @@ -0,0 +1,38 @@ +--------------------------------------------------------------------------- + +Library: Atomthreads ARMv7 Port +Author: Natie van Rooyen +License: BSD Revised + +--------------------------------------------------------------------------- + +ARM ARMv7 PORT + +This folder contains a port of the Atomthreads real time kernel for the +ARMv7 processor architecture. This port was only tested on a ARMv7 but +should work on other versions of the ARM processor as well. + +To Use: + +1. From your platforms IRQ vector branch to the "__irq_context_handler()". + All interrupts from where calls to Atomthreads will be made should do + this. The "__irq_context_handler()" will call a platform specific + function called "__context_preempt_handler()" to dispatch the interrupt. + +2. Implement the function "__context_preempt_handler()" + from where your platforms interrupt cotroller will be serviced and the + interrupt will be dispatched to a specic interrupt service routine. In + the case of your platforms timer tick interrupt call the "archTickHandler()" + implemented in "atomport.c". + +3. Initialize your platforms timer tick hardware to generata an OS timer tick + interrupt. + +4. Add code to acknowledge your timer hardware's interrupt in the + function "archTickHandler()" implemented in "atomport.c". This must + be done here because "atomIntExit()" might switch the context. + +5. After your platforms c-runtime initialization has completed, start + Atomthreads from your runtime's "main()" function. + +6. Include the port's Maefile in your platform build flow. \ No newline at end of file diff --git a/ports/armv7/atomport.c b/ports/armv7/atomport.c new file mode 100644 index 0000000..bac9c17 --- /dev/null +++ b/ports/armv7/atomport.c @@ -0,0 +1,170 @@ +/* + * Copyright (c) 2012, Natie van Rooyen. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. No personal names or organizations' names associated with the + * Atomthreads project may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include "atom.h" +#include "atomport.h" +#include "types.h" + + +/* * + * + * Functions defined in atomport_arm.asm + * + */ +extern void contextInit (void) ; +extern void contextSwitch (SYSCONTEXT* save_context, SYSCONTEXT* new_context) ; +extern void contextStart (SYSCONTEXT* context) ; +extern uint32_t contextEnterCritical (void) ; +extern void contextExitCritical (uint32_t posture) ; +extern void contextEnableInterrupts (void) ; + +/** + * \b thread_shell + * + * Documented in atomThreads. + * + */ +void +thread_shell (void) +{ + ATOM_TCB *curr_tcb; + + /* Get the TCB of the thread being started */ + curr_tcb = atomCurrentContext(); + + /** + * Enable interrupts - these will not be enabled when a thread + * is first restored. + */ + // sei(); + contextEnableInterrupts () ; + + /* Call the thread entry point */ + if (curr_tcb && curr_tcb->entry_point) + { + curr_tcb->entry_point(curr_tcb->entry_param); + } + + /* Not reached - threads should never return from the entry point */ +} + + +/** + * \b archThreadContextInit + * + * Documented in atomThreads. + * + */ +void +archThreadContextInit (ATOM_TCB *tcb_ptr, void *stack_top, void (*entry_point)(uint32_t), uint32_t entry_param) +{ + uint32_t * stack_ptr ; + + tcb_ptr->sp_save_ptr = stack_top; + tcb_ptr->entry_param = entry_param ; + tcb_ptr->entry_point = entry_point ; + + stack_ptr = (uint32_t *)stack_top; //-- Load stack pointer + + *stack_ptr = ( uint32_t ) entry ; + stack_ptr--; + + *stack_ptr = ( uint32_t ) 0x00001111; /* R11 */ + stack_ptr--; + *stack_ptr = ( uint32_t ) 0x00001010; /* R10 */ + stack_ptr--; + *stack_ptr = ( uint32_t ) 0x00000909; /* R9 */ + stack_ptr--; + *stack_ptr = ( uint32_t ) 0x00000808; /* R8 */ + stack_ptr--; + *stack_ptr = ( uint32_t ) 0x00000707; /* R7 */ + stack_ptr--; + *stack_ptr = ( uint32_t ) 0x00000606; /* R6 */ + stack_ptr--; + *stack_ptr = ( uint32_t ) 0x00000505; /* R5 */ + stack_ptr--; + *stack_ptr = ( uint32_t ) 0x00000404; /* R4 */ + +// #ifdef CONTEXT_THREAD_ID + stack_ptr--; + *stack_ptr = context_thread_id++ ; /* thread_id */ +// #endif + + tcb_ptr->sp_save_ptr = stack_ptr ; +} + + +/** + * \b archFirstThreadRestore + * + * Documented in atomThreads. + * + */ +void +archFirstThreadRestore(ATOM_TCB * p_sp_new) +{ + contextStart (&p_sp_new->sp_save_ptr) ; +} + + +/** + * \b archContextSwitch + * + * Documented in atomThreads. + * + */ +void +archContextSwitch (ATOM_TCB * p_sp_old, ATOM_TCB * p_sp_new) +{ + contextSwitch (&p_sp_old->sp_save_ptr, &p_sp_new->sp_save_ptr) ; +} + + +/** + * \b archTimerTickIrqHandler + * + * System timer tick interrupt handler. + * + */ +void +archTickHandler (void) +{ + atomIntEnter(); + + /* Call the OS system tick handler */ + atomTimerTick(); + + /* ack the interrupt if needed */ + /* ... */ + + /* Call the interrupt exit routine */ + atomIntExit(TRUE); +} + + + diff --git a/ports/armv7/atomport.h b/ports/armv7/atomport.h new file mode 100644 index 0000000..2a6cf50 --- /dev/null +++ b/ports/armv7/atomport.h @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2012, Natie van Rooyen. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. No personal names or organizations' names associated with the + * Atomthreads project may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __ATOM_PORT_H__ +#define __ATOM_PORT_H__ + +#include "arch/context.h" +#include "types.h" + +#define SYSTEM_TICKS_PER_SEC 1000 + + +/** + * Architecture-specific types. + * Most of these are available from types.h on this platform, which is + * included above. + */ +#define POINTER void * + + +/* Critical region protection */ + +#define CRITICAL_STORE uint32_t __atom_critical +#define CRITICAL_START() __atom_critical = contextEnterCritical() +#define CRITICAL_END() contextExitCritical(__atom_critical) + + +#endif /* __ATOM_PORT_H__ */ diff --git a/ports/armv7/atomport_arm.asm b/ports/armv7/atomport_arm.asm new file mode 100644 index 0000000..9ba9664 --- /dev/null +++ b/ports/armv7/atomport_arm.asm @@ -0,0 +1,213 @@ +; +; Copyright (c) 2012, Natie van Rooyen. All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions +; are met: +; +; 1. Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the distribution. +; 3. No personal names or organizations' names associated with the +; Atomthreads project may be used to endorse or promote products +; derived from this software without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS +; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +; TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +; PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE +; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +; POSSIBILITY OF SUCH DAMAGE. +; + + + PRESERVE8 {TRUE} + AREA UTILS, CODE, READONLY +;-- + EXPORT contextInit + EXPORT contextSwitch + EXPORT contextStart + EXPORT contextEnableInterrupts + EXPORT contextEnterCritical + EXPORT contextExitCritical + EXPORT __irq_context_handler + + + EXTERN archTickHandler + +;-- +ARM_SVC_MODE EQU 0xd3 +ARM_IRQ_MODE EQU 0xD2 +ARM_FIQ_MODE EQU 0xD1 +ARM_MODE_MASK EQU 0x1F +ARM_FIQ_MODE_BITS EQU 0x11 +ARM_IRQ_MODE_BITS EQU 0x12 +ARM_SVC_MODE_BITS EQU 0x13 + +CONTEXT_SWITCH_MODE EQU ARM_SVC_MODE + + ARM + +;-- +; \b contextInit +; +; Architecture-specific one time initialization. +; +; @return None +; +contextInit + + BX lr + +;-- +; \b contextSwitch +; +; Architecture-specific context switch routine. +; +; Note that interrupts are always locked out when this routine is +; called. For cooperative switches, the scheduler will have entered +; a critical region. For preemptions (called from an ISR), the +; interrupts will have disabled in the tick_Handler. +; +; @param[in] [r0] -> Address to save old stack pointer +; @param[in] [r1] -> Address where new stack pointer is stored +; +; @return None +; +contextSwitch + STMFD sp!, {r4 - r11, lr} ;- Save registers + + ;- IF :DEF:CONTEXT_THREAD_ID + MRC p15,0,r3,c13,c0,2 + STMFD sp!, {r3} + ;- ENDIF + + STR sp, [r0] ;- Save old stack pointer + LDR r1, [r1] + MOV sp, r1 ;- Load new stack pointer + + ISB + + ;- IF :DEF:CONTEXT_THREAD_ID + LDMFD sp!, {r3} + MCR p15,0,r3,c13,c0,2 + ;- ENDIF + + LDMFD sp!, {r4 - r11, pc} ;- Load new registers + +;-- +; \b contextStart +; +; Architecture-specific context start routine. +; +; @param[in] [r0] -> Address where stack pointer is stored +; +; @return Does not return +; +contextStart + LDR r0, [r0] + MOV sp, r0 ;- Load new stack pointer + + ;- IF :DEF:CONTEXT_THREAD_ID + LDMFD sp!, {r3} + MCR p15,0,r3,c13,c0,2 + ;- ENDIF + + LDMFD sp!, {r4 - r11, pc} ;- Load new registers + +;-- +; \b contextId +; +; Returns a unique ID for the context +; +; @return ID +; +contextId + MRC p15,0,r0,c13,c0,2 + BX lr + +;-- +; \b contextEnableInterrupts +; +; Enables interrupts on the processor +; +; @return None +; +contextEnableInterrupts + MRS r0,CPSR + MOV r1, #0x80 + BIC r0,r0,r1 + MSR CPSR_c,r0 + BX lr + + +;-- +; \b contextExitCritical +; +; Exit critical section (restores interrupt posture) +; +; @param[in] r0 Interrupt Posture +; +; @return None +; +contextExitCritical + MSR CPSR_cxsf,r0 + BX lr + + +;-- +; \b contextEnterCritical +; +; Enter critical section (disables interrupts) +; +; @return Current interrupt posture +; +contextEnterCritical + MRS r0,CPSR + ORR r1,r0,#0x80 + MSR CPSR_cxsf,r1 + BX lr + +;-- +; \b __irq_context_handler +; +; IRQ entry point +; +; @return None +; +__irq_context_handler + + MSR cpsr_c, #CONTEXT_SWITCH_MODE ;- Save current process context + STMFD sp!, {r0 - r3, ip, lr} + + MSR cpsr_c, #ARM_IRQ_MODE ;- Save lr_irq and spsr_irq in process stack + SUB lr,lr,#4 + MOV r1, lr + MRS r2, spsr + MSR cpsr_c, #CONTEXT_SWITCH_MODE + STMFD sp!, {r1, r2} + + BL __context_preempt_handler ;- Dispatch the interrupt to archTickHandler for the timer tick interrupt or a simular function for other interrupts which might call atomthread functions. + + LDMFD sp!, {r1, r2} ;- Restore lr_irq and spsr_irq from process stack + MSR cpsr_c, #ARM_IRQ_MODE + STMFD sp!, {r1} + MSR spsr_cxsf, r2 + + MSR cpsr_c, #CONTEXT_SWITCH_MODE ;- Restore process regs + LDMFD sp!, {r0 - r3, ip, lr} + + MSR cpsr_c, #ARM_IRQ_MODE ;- Exit from ISR + + LDMFD sp!, {pc}^ + + +;-- + END diff --git a/ports/armv7/atomport_private.h b/ports/armv7/atomport_private.h new file mode 100644 index 0000000..c0dfc6d --- /dev/null +++ b/ports/armv7/atomport_private.h @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2012, Natie van Rooyen. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. No personal names or organizations' names associated with the + * Atomthreads project may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __ATOM_PORT_PRIVATE_H__ +#define __ATOM_PORT_PRIVATE_H__ + + +/* Function prototypes */ +extern void archTickHandler (void) ; + +#endif /* __ATOM_PORT_PRIVATE_H__ */ diff --git a/ports/armv7/types.h b/ports/armv7/types.h new file mode 100644 index 0000000..0fd6feb --- /dev/null +++ b/ports/armv7/types.h @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2012, Natie van Rooyen. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. No personal names or organizations' names associated with the + * Atomthreads project may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __TYPES_H__ +#define __TYPES_H__ + +typedef unsigned int uintptr_t ; +typedef int intptr_t ; +typedef unsigned long long uint64_t ; +typedef unsigned int uint32_t ; +typedef unsigned short uint16_t ; +typedef unsigned char uint8_t ; +typedef int int32_t ; +typedef short int16_t ; +typedef char int8_t ; + +typedef volatile unsigned int REG_DWORD ;// Hardware register definition + +#define UWORD64 unsigned long long +#define UWORD32 unsigned int +#define UWORD16 unsigned short +#define UWORD8 unsigned char +#define WORD32 int +#define WORD16 short +#define WORD8 char + +#ifndef OFFSETOF +#define OFFSETOF(TYPE, MEMBER) ((int) &((TYPE *)0)->MEMBER) +#endif + +#ifndef INLINE +#define INLINE __inline +#endif + + +#endif /* __TYPES_H__ */ + diff --git a/ports/cortex_m3/Makefile b/ports/cortex_m3/Makefile new file mode 100644 index 0000000..fcf84e7 --- /dev/null +++ b/ports/cortex_m3/Makefile @@ -0,0 +1,19 @@ +ATOMTHREADS_PORT = ..... /libraries/atomthreads/ports/cortex_m3 +ATOMTHREADS_KERNEL = ..... /libraries/atomthreads/kernel + +INCLUDES := $(INCLUDES) \ + -I$(ATOMTHREADS_KERNEL) \ + -I$(ATOMTHREADS_PORT) + +SRCS := $(SRCS) \ + $(ATOMTHREADS_KERNEL)/atomkernel.c \ + $(ATOMTHREADS_KERNEL)/atommutex.c \ + $(ATOMTHREADS_KERNEL)/atomqueue.c \ + $(ATOMTHREADS_KERNEL)/atomsem.c \ + $(ATOMTHREADS_KERNEL)/atomtimer.c \ + $(ATOMTHREADS_PORT)/atomport.c + +ASMS := $(ASMS) \ + $(ATOMTHREADS_PORT)/atomport_arm.asm + + diff --git a/ports/cortex_m3/README b/ports/cortex_m3/README new file mode 100644 index 0000000..6784187 --- /dev/null +++ b/ports/cortex_m3/README @@ -0,0 +1,31 @@ +--------------------------------------------------------------------------- + +Library: Atomthreads CortexM3 Port +Author: Natie van Rooyen +License: BSD Revised + +--------------------------------------------------------------------------- + +ARM CortexM3 PORT + +This folder contains a port of the Atomthreads real time kernel for the +ARM CortexM3 processor architecture. + +To Use: + +1. Install the "pendSV_Handler" and "tick_Handler" implemented in the file + "atomport_arm.asm" in your platforms interrupt vectors. + +2. Complete the function "archTickInit()" implemented in "atomport.c" to + initialize your platforms timer tick interrupt. If you use the build in + SysTick of the CortexM3 you also have to add code here to start it. + +3. If required, add code to acknowledge your timer hardware's interrupt in + the function "archTickHandler()" also implemented in "atomport.c". + +4. During your platform initialization call the function "archTickInit()" + exported from "atomport_private.h" to initialize the CortexM3 + "PendSV_Handler". + +5. After your platforms c-runtime initialization has completed, start + Atomthreads from your runtime's "main()" function. \ No newline at end of file diff --git a/ports/cortex_m3/atomport.c b/ports/cortex_m3/atomport.c new file mode 100644 index 0000000..1941305 --- /dev/null +++ b/ports/cortex_m3/atomport.c @@ -0,0 +1,194 @@ +/* + * Copyright (c) 2012, Natie van Rooyen. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. No personal names or organizations' names associated with the + * Atomthreads project may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include "atom.h" +#include "atomport.h" +#include "types.h" + + +/* * + * + * Functions defined in atomport_arm.asm + * + */ +extern void contextInit (void) ; +extern void contextSwitch (SYSCONTEXT* save_context, SYSCONTEXT* new_context) ; +extern void contextStart (SYSCONTEXT* context) ; +extern uint32_t contextCreate (SYSCONTEXT* context, uint32_t stack_top, uint32_t entry) ; +extern uint32_t contextEnterCritical (void) ; +extern void contextExitCritical (uint32_t posture) ; +extern void contextEnableInterrupts (void) ; + +/** + * \b thread_shell + * + * Documented in atomThreads. + * + */ +void +thread_shell (void) +{ + ATOM_TCB *curr_tcb; + + /* Get the TCB of the thread being started */ + curr_tcb = atomCurrentContext(); + + /** + * Enable interrupts - these will not be enabled when a thread + * is first restored. + */ + // sei(); + contextEnableInterrupts () ; + + /* Call the thread entry point */ + if (curr_tcb && curr_tcb->entry_point) + { + curr_tcb->entry_point(curr_tcb->entry_param); + } + + /* Not reached - threads should never return from the entry point */ +} + + +/** + * \b archThreadContextInit + * + * Documented in atomThreads. + * + */ +void +archThreadContextInit (ATOM_TCB *tcb_ptr, void *stack_top, void (*entry_point)(uint32_t), uint32_t entry_param) +{ + uint32_t * stack_ptr ; + + tcb_ptr->sp_save_ptr = stack_top; + tcb_ptr->entry_param = entry_param ; + tcb_ptr->entry_point = entry_point ; + + stack_ptr = (uint32_t *)stack_top; //-- Load stack pointer + + *stack_ptr = 0x01000000L; //-- xPSR + stack_ptr--; + *stack_ptr = ((uint32_t)entry_point) | 1; //-- Entry Point (1 for THUMB mode) + stack_ptr--; + *stack_ptr = ((uint32_t)/*exit*/0) | 1; //-- R14 (LR) (1 for THUMB mode) + stack_ptr--; + *stack_ptr = 0x00121212L; //-- R12 + stack_ptr--; + *stack_ptr = 0x00030303L; //-- R3 + stack_ptr--; + *stack_ptr = 0x00020202L; //-- R2 + stack_ptr--; + *stack_ptr = 0x00010101L; //-- R1 + stack_ptr--; + *stack_ptr = entry_param ; //-- R0 - task's function argument + stack_ptr--; + *stack_ptr = 0x00111111L; //-- R11 + stack_ptr--; + *stack_ptr = 0x00101010L; //-- R10 + stack_ptr--; + *stack_ptr = 0x00090909L; //-- R9 + stack_ptr--; + *stack_ptr = 0x00080808L; //-- R8 + stack_ptr--; + *stack_ptr = 0x00070707L; //-- R7 + stack_ptr--; + *stack_ptr = 0x00060606L; //-- R6 + stack_ptr--; + *stack_ptr = 0x00050505L; //-- R5 + stack_ptr--; + *stack_ptr = 0x00040404L; //-- R4 + + tcb_ptr->sp_save_ptr = stack_ptr ; +} + + +/** + * \b archFirstThreadRestore + * + * Documented in atomThreads. + * + */ +void +archFirstThreadRestore(ATOM_TCB * p_sp_new) +{ + contextStart (&p_sp_new->sp_save_ptr) ; +} + + +/** + * \b archContextSwitch + * + * Documented in atomThreads. + * + */ +void +archContextSwitch (ATOM_TCB * p_sp_old, ATOM_TCB * p_sp_new) +{ + contextSwitch (&p_sp_old->sp_save_ptr, &p_sp_new->sp_save_ptr) ; +} + + +/** + * \b archTimerTickIrqHandler + * + * System timer tick interrupt handler. + * + */ +void +archTickHandler (void) +{ + atomIntEnter(); + + /* Call the OS system tick handler */ + atomTimerTick(); + + /* ack the interrupt if needed */ + /* ... */ + + /* Call the interrupt exit routine */ + atomIntExit(TRUE); +} + +/** + * \b archTickInit + * + * System timer initialization. + * + */ +void +archTickInit (void) +{ + /* Initialize NVIC PendSV */ + contextInit () ; + + /* Initializa Timer Hardware */ + /* ... */ +} + + diff --git a/ports/cortex_m3/atomport.h b/ports/cortex_m3/atomport.h new file mode 100644 index 0000000..2a6cf50 --- /dev/null +++ b/ports/cortex_m3/atomport.h @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2012, Natie van Rooyen. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. No personal names or organizations' names associated with the + * Atomthreads project may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __ATOM_PORT_H__ +#define __ATOM_PORT_H__ + +#include "arch/context.h" +#include "types.h" + +#define SYSTEM_TICKS_PER_SEC 1000 + + +/** + * Architecture-specific types. + * Most of these are available from types.h on this platform, which is + * included above. + */ +#define POINTER void * + + +/* Critical region protection */ + +#define CRITICAL_STORE uint32_t __atom_critical +#define CRITICAL_START() __atom_critical = contextEnterCritical() +#define CRITICAL_END() contextExitCritical(__atom_critical) + + +#endif /* __ATOM_PORT_H__ */ diff --git a/ports/cortex_m3/atomport_arm.asm b/ports/cortex_m3/atomport_arm.asm new file mode 100644 index 0000000..2195db6 --- /dev/null +++ b/ports/cortex_m3/atomport_arm.asm @@ -0,0 +1,217 @@ +; +; Copyright (c) 2012, Natie van Rooyen. All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions +; are met: +; +; 1. Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the distribution. +; 3. No personal names or organizations' names associated with the +; Atomthreads project may be used to endorse or promote products +; derived from this software without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS +; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +; TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +; PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE +; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +; POSSIBILITY OF SUCH DAMAGE. +; + + + PRESERVE8 {TRUE} + AREA UTILS, CODE, READONLY +;-- + EXPORT contextInit + EXPORT contextSwitch + EXPORT contextStart + EXPORT contextEnableInterrupts + EXPORT contextEnterCritical + EXPORT contextExitCritical + EXPORT pendSV_Handler + EXPORT tick_Handler + + EXTERN archTickHandler + +;-- +NVIC_INT_CTRL EQU 0xE000ED04 ; Interrupt control state register +NVIC_PENDSVSET EQU 0x10000000 ; Value to trigger PendSV exception +NVIC_PR_12_15_ADDR EQU 0xE000ED20 ; System Handlers 12-15 Priority Register Address +NVIC_PENDS_VPRIORITY EQU 0x00FF0000 ; PendSV priority is minimal (0xFF) + +;-- +; \b contextInit +; +; Architecture-specific one time initialization. +; +; Configures PendSV priority to lowest. +; +; @return None +; +contextInit + LDR r1, =NVIC_PR_12_15_ADDR ;-- Load the System 12-15 Priority Register + LDR r0, [r1] + ORR r0, r0, #NVIC_PENDS_VPRIORITY ;-- set PRI_14 (PendSV) to 0xFF - minimal + STR r0, [r1] + + BX lr + +;-- +; \b contextSwitch +; +; Architecture-specific context switch routine. +; +; Note that interrupts are always locked out when this routine is +; called. For cooperative switches, the scheduler will have entered +; a critical region. For preemptions (called from an ISR), the +; interrupts will have disabled in the tick_Handler. +; +; @param[in] [r0] -> Address to save old stack pointer +; @param[in] [r1] -> Address where new stack pointer is stored +; +; @return None +; +contextSwitch + LDR r2, =context_new_stack_ptr + STR r1, [r2] + + LDR r2, =context_save_stack_ptr + LDR r1, [r2] + TEQ r1, #0 ; if contextSwitch is going to be called again before pend_sv + STREQ r0, [r2] + + LDR R0, =NVIC_INT_CTRL ; Trigger the PendSV exception (causes context switch) + LDR R1, =NVIC_PENDSVSET + STR R1, [R0] + + BX lr + +;-- +; \b contextStart +; +; Architecture-specific context start routine. +; +; @param[in] [r0] -> Address where stack pointer is stored +; +; @return Does not return +; +contextStart + LDR r1, =context_new_stack_ptr + STR r0, [r1] + LDR r1, =context_save_stack_ptr + MOV r0, #0 + STR r0, [r1] + LDR r0, =NVIC_INT_CTRL ; Trigger the PendSV exception (causes context switch) + LDR r1, =NVIC_PENDSVSET + STR r1, [r0] + + BX lr + +;-- +; \b contextEnableInterrupts +; +; Enables interrupts on the processor +; +; @return None +; +contextEnableInterrupts + CPSIE i + BX lr + + +;-- +; \b contextExitCritical +; +; Exit critical section (restores interrupt posture) +; +; @param[in] r0 Interrupt Posture +; +; @return None +; +contextExitCritical + MSR PRIMASK, r0 + BX lr + + +;-- +; \b contextEnterCritical +; +; Enter critical section (disables interrupts) +; +; @return Current interrupt posture +; +contextEnterCritical + MRS r0, PRIMASK + CPSID i + BX lr + +;-- +; \b PendSV_Handler +; +; CortexM3 PendSV_Handler. Switch context to a new stack. +; +; @return None +; +pendSV_Handler + CPSID i ; Disable core int + + LDR r1, =context_save_stack_ptr + LDR r0, [r1] ; Load old (current) stack pointer address + + LDR r2, =context_new_stack_ptr + LDR r2, [r2] ; Load new stack pointer address + TEQ r0, r2 + BEQ pendsv_handler_exit + + TEQ r0, #0 + BEQ pendsv_handler_new_stack + ; Save context + MRS r3, PSP ; Get PSP point + STMDB r3!, {R4-R11} ; Store r4-r11 + STR r3, [r0] ; Save old stack pointer + MOV r3, #0 + STR r3, [r1] + +pendsv_handler_new_stack + ; Restore context + LDR r2, [r2] ; Load new stack pointer + LDMIA r2!, {r4-r11} ; Restore context + MSR PSP, r2 ; Mov new stack point to PSP + +pendsv_handler_exit + CPSIE i ; Enable core int + + ORR lr, lr, #0x04 ; Ensure exception return uses process stack + BX lr ; Exit interrupt + + +;-- +; \b Tick_Handler +; +; System timer tick interrupt handler. +; +; @return None +; +tick_Handler + PUSH {r4-r11, lr} + cpsid I ; Disable core int + BL archTickHandler + cpsie I ; Enable core int + POP {r4-r11, pc} + + +;-- +context_new_stack_ptr DCD 0x00000000 +context_save_stack_ptr DCD 0x00000000 + +;-- + END diff --git a/ports/cortex_m3/atomport_private.h b/ports/cortex_m3/atomport_private.h new file mode 100644 index 0000000..0f4a004 --- /dev/null +++ b/ports/cortex_m3/atomport_private.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2012, Natie van Rooyen. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. No personal names or organizations' names associated with the + * Atomthreads project may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __ATOM_PORT_PRIVATE_H__ +#define __ATOM_PORT_PRIVATE_H__ + + +/* Function prototypes */ +extern void archTickHandler (void) ; +extern void archTickInit (void) ; + +#endif /* __ATOM_PORT_PRIVATE_H__ */ diff --git a/ports/cortex_m3/types.h b/ports/cortex_m3/types.h new file mode 100644 index 0000000..82317f7 --- /dev/null +++ b/ports/cortex_m3/types.h @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2012, Natie van Rooyen. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. No personal names or organizations' names associated with the + * Atomthreads project may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __TYPES_H__ +#define __TYPES_H__ + +typedef unsigned int uintptr_t ; +typedef int intptr_t ; +typedef unsigned long long uint64_t ; +typedef unsigned int uint32_t ; +typedef unsigned short uint16_t ; +typedef unsigned char uint8_t ; +typedef int int32_t ; +typedef short int16_t ; +typedef char int8_t ; + +#endif /* __TYPES_H__ */ +