From 648d35dbe6598bc9322267a85db072ff065a1483 Mon Sep 17 00:00:00 2001 From: Natie van Rooyen Date: Tue, 23 Oct 2012 14:23:34 +0200 Subject: [PATCH] LPC17xx platform for Cortex M port --- .../docs/CMSIS END USER LICENCE AGREEMENT.pdf | Bin 0 -> 51511 bytes .../lpc17xx/CMSISv2p00_LPC17xx/inc/LPC17xx.h | 1035 ++++++++++++++ .../lpc17xx/CMSISv2p00_LPC17xx/inc/core_cm3.h | 1236 +++++++++++++++++ .../CMSISv2p00_LPC17xx/inc/core_cmFunc.h | 844 +++++++++++ .../CMSISv2p00_LPC17xx/inc/core_cmInstr.h | 775 +++++++++++ .../CMSISv2p00_LPC17xx/inc/system_LPC17xx.h | 64 + .../lpc17xx/CMSISv2p00_LPC17xx/src/core_cm3.c | 339 +++++ .../CMSISv2p00_LPC17xx/src/system_LPC17xx.c | 532 +++++++ platforms/lpc17xx/Makefile | 95 ++ platforms/lpc17xx/atomthreads_test.out | 153 ++ platforms/lpc17xx/drivers/lpc17xx.h | 1035 ++++++++++++++ platforms/lpc17xx/drivers/lpc17xx_uart.c | 166 +++ platforms/lpc17xx/drivers/lpc17xx_uart.h | 37 + platforms/lpc17xx/main.c | 116 ++ platforms/lpc17xx/modules.c | 178 +++ platforms/lpc17xx/modules.h | 46 + platforms/lpc17xx/startup.c | 295 ++++ platforms/lpc17xx/system.ld | 148 ++ 18 files changed, 7094 insertions(+) create mode 100644 platforms/lpc17xx/CMSISv2p00_LPC17xx/docs/CMSIS END USER LICENCE AGREEMENT.pdf create mode 100644 platforms/lpc17xx/CMSISv2p00_LPC17xx/inc/LPC17xx.h create mode 100644 platforms/lpc17xx/CMSISv2p00_LPC17xx/inc/core_cm3.h create mode 100644 platforms/lpc17xx/CMSISv2p00_LPC17xx/inc/core_cmFunc.h create mode 100644 platforms/lpc17xx/CMSISv2p00_LPC17xx/inc/core_cmInstr.h create mode 100644 platforms/lpc17xx/CMSISv2p00_LPC17xx/inc/system_LPC17xx.h create mode 100644 platforms/lpc17xx/CMSISv2p00_LPC17xx/src/core_cm3.c create mode 100644 platforms/lpc17xx/CMSISv2p00_LPC17xx/src/system_LPC17xx.c create mode 100644 platforms/lpc17xx/Makefile create mode 100644 platforms/lpc17xx/atomthreads_test.out create mode 100644 platforms/lpc17xx/drivers/lpc17xx.h create mode 100644 platforms/lpc17xx/drivers/lpc17xx_uart.c create mode 100644 platforms/lpc17xx/drivers/lpc17xx_uart.h create mode 100644 platforms/lpc17xx/main.c create mode 100644 platforms/lpc17xx/modules.c create mode 100644 platforms/lpc17xx/modules.h create mode 100644 platforms/lpc17xx/startup.c create mode 100644 platforms/lpc17xx/system.ld diff --git a/platforms/lpc17xx/CMSISv2p00_LPC17xx/docs/CMSIS END USER LICENCE AGREEMENT.pdf b/platforms/lpc17xx/CMSISv2p00_LPC17xx/docs/CMSIS END USER LICENCE AGREEMENT.pdf new file mode 100644 index 0000000000000000000000000000000000000000..e04afaee6286ce461b2ab5f286c6f99b232f5ae0 GIT binary patch literal 51511 zcma&MQ;;Q0)UH`ww%ujhwry)ybzzrn+h!NKY}>YN+qN;^f8v~pn3V5h0Q_&w ze}38ilk~rR%K>f8oXv^Y|CdM!3u|YfBcp`1p)*hnX#AgR0RbmxN1&k%0<3%H68~Bv z9%t-L?5v>k-`yA?~4M`(_T_PzT`m_{Q1f!0-!3I4K{t5rMs%=t|!5hAFZDMmTD z;$SH0Vs$wtT152p@)g9iF}yNj=#^Py&9= z72H8T)%x4-hchqh4b5AedzW)jx;F3a`~}3rKD^mk{O?c8emR^SQMCrsBU|DtO&|8( zL)ZB`aVIlw5559FXK%KVe!g1(_>b?;Glt8K*9q|!yXhL&t8V@uHed6SSKY7ywhrd+ zjbgulTR(j7ak_4VTknTGwm$c9je!hu9}3G%u^+wyJ_sz~Izw4E-7%w6Coir5vEz#H zjegp;jt&sHo~^zxNq=uyq|I2QnG=JWxyug7Qd#rn0pGS?WkBSR;}t1#kuwG0G1Il^ z2y58ytGZ}nv>by=g0HSj^R>7JI)`=6FL~2^;YHM&kuJMw!p*8m8|;^buRczW0Qhax8JzpoDKQQ-wI*BP?Y zP_SARDT^Ho4{RTmLFCMA+`t?bvk(xVe`TT~9ezb_rhSAHOtW5&{H8;e98D6(QJ=5V z<-tzYSlG74#S>*bM-4u4|2FC>pMCsL&|u&6_vH%IQP--n3=d-HEVu1Maht`ysPeo; z7+t;ooEh5R$G#K9M&c?AI4d?>RkZj2@af0|G$M>r_3niLi^~X~4I{kyE>9XDikHH_ z-}K#@(ec=Znuh9-YdUr$1`{!VgO)bjxaC$7Z2N#1usIM)f%`#_xJQs+`%)0SgD8f+ z3byoY0w(V+px67A+=Q(M5?)PL7;?3`xB6Hxm1snvz&63IP^Wuj%OOoKl}|u~XMRKq zYSO(Tc{G-{X6(V^7&G%0*Kd&XS^VC`7QpUn%X{wb%`t?+g)x7KzM{ZZ_qv+~&Y&U+ zD>n&~uuwA>&MI+%(Yu`~=# zoqfTp1;@3n=+kk6Zc28+)L1w_H++r1@`)@Cs-O3B^$|HI9#c52jX z5ab0_H1;`oo5E-zwLekHcrEa04L7jgFRH!m$mw22XJR{+eL^y)&GdqnsLI#qzx=ADnglN*fa8n_Ax683F#kaF6uSY{bCW$@;hINmpK_^|A@f8bD& z+l)9m)Yr;>10NwU~fo7s!;3czDvdmMBe4iZhS z$1)I>nM%fnhYEsTJ=iz?;-1%M64Q$rP2UsH7O>kA!6LVujzGj6qacUq^NCG>TRXhi zbx>`y;_iqcv1RU*G+@5C;rume0WMrd$rqpnGQu=**dCs)kwKQ_g+B0g#&MBFY%8RD z=M>nIVZ4zVpHp_K{Ag#YNo`9K^B=V5@7!z?!c%^m}DpK@Pdq%>C`Ac+I9ndEK6uc~wa2Z+4S${=8iQW`yfAeEuqK?XN^a`OykW#9-;^q#PkS1Ddf>)5*U78B=5KB zvggVHADd$`D2jjFe!&9@Df-`yHR_gj(6D8_7NSr$OUT8xE|s$&u<3(6cT=!cC!jhv z0BMa92WdNEd zH+AcVh~bor4ZcbL)2*o@ULe9i$F;)^-yKp#H9YKZtE65dNvM)UhlXz~s`^HGrEBg1 zC{Gv~r-(E7VW}o(!F@&R`#XTq4f3looeH$TZOTFFl;VYEi492KcCaZ^lE~*KQybjs6B`dvtuX*MX`vygKoK zxRxn1*4@O1v)Gvl!KP#_(gz2QX1MCg`(c$3b!IH}KU+C0txj=)GFl-^k}BK&&MMn* zWb`w^QkVXChVKw=vsPGFDp5$))vs3o&pr{{N%tlQ>2pQ4;O%1l;pwiys%#estGgaT z4+dd~a5BE*=jZ->T+UASnwzRl8|~i|p>}>%sQ)goO^j^6X}Dj}={$FwT9D!80%!2# zDeul>&9GuF2k#U#zlX37_eR8K{H?aF%b>lV-4ET7;-Z28cBJ%E+ll4Q3tWh{ODavrgq&zb}kiD)lf@xlcq%oyB z&A;Y)%n>H7Yw>r~W{1A4NsF-lJmQk(6D~k7Icf*ztgH)f2B!=|T;$$77SEpy==Y0D z{lX^)3FT&GhG&6))5!=SB=x#1=XxZTb|$k|%N6(~rIaxoYX1f02}ZmI6TH;<%0?lI zQ+cQYJJ!siM@i0P8-+-Ij$!u1B`A72W1K#625E2L&7jZoi@x=W!rpZ@{-e<-OeiB% zZo7$qG+5~I67|bK5!t7RPk4tH0Y7lwDLikWT5W2!EOf*W%RE2#PUmVqy)fx4qoTat&q@B4R?whcfp$$ z2Np470dYZ5th-?fQVTCYL{wWQSr8~#U13dPxkYk^Al{YSjV0V_-8&t zs8@lYK%#fC-xop+bNCHL5s~Br7jt=V%G*fEbH+e$U?$bH?FO|J|B16fLA!}WO5a(K zJ)I?dg!TIwaT1=*Gf2gkU zdstamU`|fYcEy~V?JI(gC(x>IK>vP47Gq_+;PK+7gIN~Y%U0%1NRP9)!JYau6b{AK z=o|kG+~sYrqD2ZNV5Yxtm-e7i{l~smf>1v{zA#BR{%5lY znFQsDX0M`JSYdsZre&mH&3He4LP(AXtQFUJ>IoD0Wx0|v+qq8Og=kQ0Lfm~xy#zr< zA52CAeT#eW3qdttS#so)osa*-WqhH6e%OMrd*@eHO#+?>i;+1z-{&nXXQb&nrEY3z zN6v&;!MYz8WWdaqF6jz`cyz4&@1NJtJtPCNhLltuUpj!YTq>sCIqbug3yUYWR2)oFg(1oU78WZqd`Y>n{5&a&XP)CDm5c~13#f$#0^z<1(Onb+H_v1v2a{M^4 zcaXeslQwnhDMWeVLIvpQS7K4>`&=ph?9>HuT6&#QHd1%3?m^i=71r;I%gNbcW$dHs zbZ;)!WRbUZycEhJ|KAduf~&2Q=B<9NPJS|!=|npg#i*ek(L`zZ9Ar5rjSf<^*ziKSE~B^nQP)4 z5;#>eM85!IZJh6td(GOczqMi6WgC&#sE9%d*sxDMltdZhnM2T}<8;b@JINzYb_V2x zG%kIBQi%!&A_^3w2Cztzf>w~=yrw|K1`c{uqQ!61w&10!wgymuqx;yhh@9crF-VqY z|NeY~cQuk4M#Asct?uE;lACHUKHLk`9NW(JJ zq*aK*5yM1^IOj{p7uiU?pbuw^c7$_(F&4I}9nW|#1v{}43`wWp7Tr7|SvRMRQ zW2-@cvA5%q-Eg~t3*L8^9rK^yG>WeY^0Dmssz{D!YGODvr0>)>x2gs2CI=~DIEgP* zDxgaqPp=Xcb~^b>+wWN;wt;3SCFT8+3nKV6bOl_HLMKSvikZ&HB#zrs0l3UU1-)z5 z8HX_C)WOJwPEp1$tmrOUQ;|7H=F1#!i(-Y_sf5HrBE=b|SBZ&(0YMMv(E;dRUznaU z8~HFD)UT~dy^G0&8)75!?%uKawsBycCNqrRe3c@s!<87RbD<_8tU#ow%W8EKD5#eA zw{#7}oMn{JfZ0NBeM{Q;ayG=x?j}Bu7)R|;zj7O}j0>z|N1U_*5HHtnT2AR+Po=(% zY)q8MdV~4IK`Lp#?DY_2YE7BJ!E-V)*D^rFJbf#6n7x)EMxS|bQ1~&E$uJ9Qe<)4% zd9EY3U4+#X=7%^Ejbg@V5<&{LW~%y)>8& z-J@S9x~=dga`i=f;eYfo!JABvmRL>F*x9^4w6mQ4A(qc=6h9dN*?$p;PSe+*FFQMr zks3=yxj^msA1LsIY*&y`JazKkQWmdaNkaJ^Yr1_k6=u#CQlI@zS zN5kH_{@8n;vf1{2k@4`?dQgmM^?(UJkBhy*{Fj6uOD!s3_`Jm4EnGLqrPDjl677po zaa*i_O~@tawm~qr{F2Z#i5{`eg6m&zar^V>o@%e}Om>oTJgsxj|G24zyPKv8&a(&& z+oCmsC@ms@dPSjnjODEYdUqikfKE;kiN?KMA>>T2Ph#lXmZA11bv=h%I7xXuLz6h;dTcS9&SQ)}$UTUcRqv{a{*fLABeZ=Ki zWqfw_+dVepFAZ&Cu((ymZlgtT<`dd8y(VnurTtLl*Y4#PBN=>GUzJG29u2237@3CKc_@ViGG<`O(9&Cetmg*?aE4OJT|yBYTj$5%l3=@ILyfiS>Y10 zs9@DSAoTe)#nc^en zJBWCP!bfMAwLFJdvVfgs8Qz7LeljH2+5Fq}UmPjOpMNWKF@*vRV9LW_M5ZR!(w#x^l%oN z1T*8Z0cL26L80YNcBgUeyP%xO4Gy&qS@Tkq5McQyZ)DgTC);E>qC`?mMauYFHrvabmG3e!aYlKp= zoD}ZtKIsU1SF=;0g_Sa(RQS^T(UNBEzmlJ&^+%O`cuT4w*ksduc;W*V#en@eh{fnH zNlih^MZ>wl5<9#VKx~=40A3#i9mzIOjw($Lew~Ot8&z>==ZG`pma(IYKVLW0ZD2Zxp(fDJ!^A>7|p-k7;j8$V3ZTn|~b~BOa_L>)dtEu?5tj_keZ0*E=*Ht-(m_)eYt25{ z!AsX&pmz&j)h?>m@)@UGyP4=p_dhJuyqpYkwn|q-dJC#aGS{gLOznMrLd^ox`uJZ< zIh(LV^9P`Koy4cB%Kk~Ui_)Rf3S0Q5AZD>pM-6DgB#0POk?ie0W?)MxGeez)fv}ev zTmW2Nx$~rn*+mA|h9&&bNsOX2?=SBj7j$&7TA<@I_Ki*JYU=P*r6Oycmrr2h|7a`Q zD-96h&y|qn1i>Yp*G%C`JYZ<6d%a>@Jm(}_wXe8y5dh-_^w_RNa2FT(#AM2ngZoy zpbLnTJeP4sm&f>f$_@U~5AOSqQ7&>qXhKDI9gXvb?Mj-rC68wS6yOxPjimz`-aUoj z#9}A1l2dh&7F5m((FBcP?tW_3t?&moH4b1J$ZwWANoLqHGUAveEts*-J!BVlA@{Dl zk{-`B{Y-`E)!JW}rlan`XVz&G?yGK8f7qFe*AKA?bf#ufUjInNe|oyhJ)woI(;<-T zp)+?OOTr*5hx0gU_$!VN6X3}Y{|GC`$b6R*X{$}%nWbl{VsXzw&OzzCSwr!MDI_W1 zf>S#1pF@uyGl^XG<4Uy_>ohusRiJmXEI+4Ur#nPPM0rY6c}JvL4HfSR`9K<5SHTi& z-*PpPcI0}>=1sA{u)v{94)Qo(HuaR5g4xl=MFdHo53uT`>fBBVJ=`4bTeG)k?xexf zRma-aMdVD_T-~gK^oYXve9f34Cv%Cyc)Y85iNY;+zf3buHY;LmL!i!5lwzY*j#u9% z5U6zwnQP7ue48eaEt6!rPOVu5M@ITxoqvyw)8}B|jK!lt&T?+5sFKSyO+)2ZDkX*= zwW6ht83{M_lEFThEXNDIF!R2t`PKrH_RjUekbo9`9{coDT)E5Iiq*^yeS72)H&fT8 z&cNGuGf|HwCrg_bM`h(*s=>ow+{s5G2r%(-B!ii>4$yg=k((VDq65%y7R0aoTfeKt z{H7ighTgQ;IEJuW4{#Pz%M%~V9o&h3KR!<{!fF`NJ3@5PvRR8$rhdv#N~UNpEM%&& z4|}0SY6_cKz-ODeq`w#>CzFsSfO zxD+VBtwpd5u9v*;oy4#rpQ7(V`+K(5S}z4IRpkNL$#V&9^DSR-Q(KQ{tOX0!xtXv; zB@(7raeNvtW9ZV3mdM83sj$HwWkL~`utJnx15v^$zJT;E=wc14`sm;$GtyV9zAzQ1 zyp_{yad8r+l%ycY%yS4xMu~6Kzhi6S1{AK(ENs_lQPgEW(nOcp318$Fz5iDlfr~hF zj6e>Zk17ijqrFNR&_BL_(mXi?&pTmhJ9W-XhnFd{w^CEKSPE{Bj%o0N?KknJ$*Zo$ z_fT^uOq-|&iKh`3|0&GPIzxCOo51;+bS1X(%&}+u;O7b&1b2b%vTR^Wx48C3jq-mK z`%Q0h+9X%Ovuysi$ly~RQg zm)`jnMcaQ-#fq_7%kwoW0y|TE8@>pV@mk}2oNUxrn3OM-ds-=KI;Tp)h=zkFt(491 zeDJt#7DYndZGh~u-F58u+Q&U9xD-=4cG>Po91Dvx`ilixph}c_tYnX+z~e`|WVoJl zPBww6hnbco|K#suZ^AaAGWATHPYk_;HvTz)e`U+gAUxSTi^ z2^?OMHHU9x7wC@|U=G(HEi>*EV96_&KIEC%+>LqgeAky&_aQ!JaYA)lsh!+*@@UEH z(o0;JW|N7TIxy3TmZdvBnwe*OX`oK4M&u(<7iv1I)l-bJw?Iv2Au!9gV%CM>?Jl-G z>qvH52*B{K{>2Egb%86;TyQp@&(B7dE1@XR+E(0ETDtWgixQYW?Px;T?R!2}zxF4( zZz9;r9MjREP>SL0*k`fXImr;_FGLkG#Yy#1MBWp6(-Ca8T&02m99e-DaVbaMs5GuF z*W#4Dj~_p2aj;N}Vz9sic=HG z5k%9Ar-ev=9eEtUUr0;| z(~o|bqJhuDwJS$KS@ujeGXG^Kq1NWC@xjy~)$NiLhBBAErRGhLqJWx7;3=Jz@kzZ+7Phe}HBGp0ter;IL$ z-^6a=_7vs%QEndzZxswZO<(wN8z_q>9{8=QVNnx3U{QvJuk7eHp>+9 ztfOqNOtC|5tU2{lB*-%367mp9)|PmLzS&_j^YKO8|KE}DW?N!zi%LvR(hLzzj|C2e zz)?6?-dE7_hg&ddHi1wsJ;r2M9W9flH!rY0gfPb*xJ2&ZnK8KGqQNJ>@l7j5+Se`= zY!)VD-HaF#vER?6B&cej#9Ug3^a;IN|84J}px7tt8X&j%Sd?6P1C14PSQ5wB0sGCD z(H&qVnlbgE0S7wI`aM^(V;<(5J`>JUMGrb3z8tuNjJBUAY2cmq=W%rCj4gl7BtZJ6 zW-3j0-Z%tGU!GqZ+)k?P-i4I77WW)VrJ~yR#0!4VC#!yeO($RLfg7S(Y1 zMO_;cygQLCuztSR@M*;aL!s(xznP|@A6$91%%z7F6}5;aWKP3*^YY22n4Yl172}4U zyE?e7#!oPauEG@ZC?Q9)xRNaXuVgj@$ecK%v281+MVQK6Dn%3QY1_rUW$_Zv_=4nX z@}0w=WPW@^&bQ6VN)1IjchMNKV?5kJ$Ek5GyC(;=a-dZfgLU0gd8*tq3n2%T@n3b! z;yc1>-#sJt1rJ%s=A$YyGwUe{@;peML3)paOuJT0Dsf!nQ`57s(W*;vBRb>9q%N%v zQ$uhc7<_1=Ru51SK)V39Exhm!1QV|}T{2N3jwX1pWBDhKL=LXg`pL{>Y^X6^iIt8MZZlc}u2 zlA}{aGFQ(xLJ`c5Z@(lVRv?(^SNg%_=;gY;#xs<4-dCeW^BcXtG~&R5>oK$G&6C1p ztgHqYe2mpbF;KL2J{EP;31!iE^ENvuKpa$Kp<*(KF~D2C(@?r$-;io+%k9EJ7~veE zZR=(-ji^G*svI=0y7LvQ$UH>Mkdy;d(3TmvtuS(oEfXft7`7u7Ayrug7KYLZFUTLf zS}*)pHEGajkyQWVIs&l14o`N~K6rgi(7G^{zYvn72B_3Rs~H)DhyFy40})}=NoxiU z*X70y@1r&+M1~$HepBAiLhy;_Zg$$sC3Rd@h8U+8-dd)8whBcITH);#m2MXkudVB+ z+Taiuji?2A+CgbBAFg{vk_%Kt`pKtzp=4KwoiT2XBVN%6rQolMGuiH8Ie~7yry;<+s7w0|7--aB9T0gfn`G%O9THv^n8aa7fNpJ_; zWd;;thI=INIewXv>3QY+3<@>5CE2GR=i2JndGcAF)st?jPkz?Jrsl~om2^szi(Qbf z$8gP@UZxHTS>{JZx_67?d0C`BPOJJnkEf#B{+EOnDqb=)%j0urLj9&N$Xqo@Fy*4T zJEbE`a##KA3em+#9fJp<#xUbk|C>qr z-!#+zuuK0#GZAsKvNQi5#EJX=gE%oW{r_N`uK2Z`GFuXEs^|Uw90ASB2glq9FDP~L z<0_45NscOMx1q-JO(+wkF6@_oeCH@}UvH;Y3itVJipIy`O9CKgvEKU`Uj#gyZj$N* zoGA}B3C_PwaFMR;Ra(M)xjejFZvF$Df(gA{J!*IYe!6@-ZjuCj^>Y@V@+=h@3^pt7 zF5ZK~uo0i^9Ub4^w|88Zz8m=`I}H8S*`D&Y_&0N0!wlV;au64;M=HLszdgDHuaLH` z*Sh)H_83d1^47byR>C~p1iec~Zd*b_%brDF?P7kao`0O)O1w@|Uj*JJx)go;Fxal# z&7Bbj>`#j~YJ{PfE8K6dIDh^3Y5&#@GwO|D{|`uh@}b)M_>bSa75vcZyHES|uJOY& z!gNKgwjYlyW=kn(-%Fk&Q4^I+cr{ z{F;IFj>t43u76FlW8@^H>1n|5bG2y(U5`8 zE#r@>plut=@Z8a~1Os?}$Aa`UT;J_hw=L)hd}A+|qg+7IfQ7R#NHnF36O_YZ<|795 zuZ%?Odu3r;Ie<{y@fp$pKBg4u;84ms32m479CDZ)h8T(flmqHz0VGsIusXd{J^p@j7u1nX{K3}2VZ}i^$kRG)k z4t_GD(|ZFkpD5j)AFRB-uLLD$v&L4aj<9Me7{Aui1aesLK@EaVIW7n8PU#s$5we(;d z`l#c`ol|JZAj9jp!hOO)^pXhixAJKKBJv} zTv21l6#E3}I^cUagNnQp;f*>5#B+P$l~!(jc^C}9{ETFaji5H<38SSlRSayuDWTPd z{D8sO%SD@-Un#7;5eI>)nn%`rx~NL>8NfL}>xR*Tne z+Dq{SSvpD3b{VE8X|BFv_t+54k;h;L>e2HPMWF^W~~%!P5HLuT&_ybP-d?f{9JX2P!t{b`dS(yWbyg!b`G9VO%eQZNG^ zIzYe3MJhYhBQ86nsU*2+*PkKh>=|tkQe6NkT4{42sTc=YvZ;8fVx;^nn(1z12@~3a zvhM0PsH%owcE$u*`M`zEojsFm}C6YEC_-v&fPuQUtx<8elRNoiusY%AKBp#m>{tG<=g_)YCA)9y&|!L zf0B0wV%ptRdmZpVXg5EaAKLQJhjY`VR*vWaqan5&vV>tpbwx>FFn(ILLp{!v?e^u9 zgIzZSdB~=Oj#p7&NVPSsL#H=)(UU}`CJAnZ>Z6y)U7GN_;1x0CiD3ok{c`CU#Iz;2 zZs~l8y48x%6l}pdyzkaZ5Y*Nq$|EPm<|7E}EJ306HNX4G+ta=EqKN{OqBv2RjKU1R z#@!Zg))8w5&fNfsZr5%$B{c0KE1%W$&-H4fHSiV-xb*BbR??H7QJy%|9uo2y%q`zdcB;NW(-7+bMPiZN6&EZ@kAu+nzk7d zOe;RAkG~y6Fvr{#2Z4=3O|-2V3=VxnD02|ns0?sDQ2Y4=QhyfJp-ebQCt$#01zOrg z=0bP5T07i0zoLS1{GCmZgs_Qg`Y3WC*8_jlit^^tMiz||>E{!7TqLcxTr zH?H_o7uS@5i9TI|(EO(Yp5IxZK|lABqx!W%)AhhYWSWzDx~O6X^})UfKl$t2(s^AD-c)(U zR;{c;6tYVgdRrXd8u7nyfNhjFb(P*c~|C5_pd+8WZ*@V=&eL>CMHSvpH$hD|V z_q7$EGmlJ{%gHXri|+}&!Fk>LFiYI+@hr5{VY}>ubo`>(NYLbkpbc0<>yQb5^4aH~ z0{a>Cg=PAwC&y}9xQx1$I#E+Qci_}WJ_>@J)&C21T^HX%sPr)Rqrw@1-_drdSKSXn{ z1A~0}lZyH_JZ@2f{nz$hg!86s;G^_5h;Yy-cs1mF@v!;S8)4+!DH~v#9~uS?)M9H; zZQ+7C(&MGMtr5N>gB0I@fKv!}Lc+cj^Z;o2gr zr!bQ^7lW#hd%eFuhKAetiLEfx%JsX6V!?zB^e4c(*e+Koh~sA}jP_2cGK#{%HQ2Z#-~K1lbS67tw`AtfI!2TesO}7UL`UG3c~(*C@qzOuP&;JOQaq zPilYwePR7E9cT}n)pM(%!AqE7YM9WUWe)3JR@9r`10Q4bsiv6NuK7~)9r(X7 ziAum%V>E7p)Mf0R(G-^^=66Ok(C9-Le-2proC(LRv|kB8m|czg$Z29ElhuD&X=F7+ z#^N1yi>s{(Z~qZ6flKcP0JH4`8)$fWnoOKm(Ta=tgWV~N%t=a;pimaql0i5 z5mAS-&V1VdvVHrpDQ{{N=AH)*R1_$Th&1a1tJe$j2f)BB1`BY{2oJtpczXH30R@C# z2i*k@tq|c5eWc2pBM=0qzHPIh`J{+`5b|=EkjfgI#iFef1}+{O$u1L+2TzioxnWY_ zdu=!_AJv%S`5It$akoNBrd!S3KCD0dz$5-)GFl|*JV@V)kO=?hc9Zd|5^U4TW3kN< z20dUd;0IIH`_}x`_vPgf6TK>DdYR4tA0*&PI{2mx1BW6G%1?WN5Qz=MkERaY#DZ;$ z9!Vr17GDD4SGu%>>+u(j5}rr;tFB_&CB=!}8_N#*cqRrB}GIMD&4Or2&p{wk2ZB?lt{9c3U1+D>nSahsg?>7HG>BCiJ zAM0*j>P!uRd`K~mVaIvtvV&go7Z>v+m>iF%8<`Me=8k6A3q){sh(3VhfzuT9SO#}5 z-L1-LtN|kA24zV+65;egCtKVdL#pI-(Jl255_3G|<68&~j8VC|BUr#R-!6T)8G+8u zmssB9Vw>*Nrr>-=3au4xmm*zL%IZ+_GjOk?%xB~es!-qAWwra|$R1M}->fyD!bZl$ z6VC5PiB6%A4u^%Yrr{Ttr>WZ@_`lHV-2tJF_?9-cbG8EU!49Ss-xfBJp%^MNsYG#` ze(1DO(q_RErmFO*#@vJKV38`8XSiJmgziZgh{UH$0`!ZdzUsVyj$!V4p`k1lRbvLg zk@*~Lu>>*lb~8R%7>v&JKIE_YCkFYL<}Bi+WGLG#b~#v}7Pw3RWRmG49rFyak*$-Ot&}feoc#NcyK74Mx*;o`ny(L&F45~0j2%^mDLnOey%kL zIQjHhi&yAqg1!3YGPwTM6;f+R1L;bTAs<=Btq716>;V?&G4%@)1D|a6kjMr>An707 zLslegGXrK_7!q+GKNgMZTsTnpx<`Q-B)V5pTU1aiKu5A2-YvVOFe7EiVDxcrDN+}s z9E}jHE7bABGW6==#6?1p)_bnYh-pYuq$|_K$gnAyGW$lfTtV-nVoj{zR6?c%7n=;5{7lp2 zdb@1s=;Ly#4BMNx$TIzBDr3(0X~!fYnS(V-;*Loq3yw4gC^}@qW!_Fn=i4uX5)e+3 zk6`ph&*`ABCd>9m%QS}N(+P*G14zAFC%ksSy_a(sAL*_)^mxv?r(!HG%0=h}a%pUn zQXxp)-kbp};XseciF6$~<-PPkIhQvL^zq4LGw%h&PjfW9ShaA~_JG_yHcgE4Q|a82 zuU5kLTv%ebe{(pLyToxcWJEzzGIAM;0+d*afgyTaRMej21E7q2TJto#Iv=o~=;M`r z2FtoqT*0UU#KvZVpubqCtWAv?@rzBwL+_@@lwfcOBhYf&MNceEu(2$t799=zOg~7R zPUV#?4iUQor$tPejEfWbjr1fOz!9m+LU=-_VYrquq1MAM9yPk&7YU72-DId&L)D_=ZmxfL7qXbGUB!74gKnJo zo-(BBL@@kKIP8AzgH4;!!Zn<6WIXoxRKxev_>r|hYwCC7YR zv=OX<9}VgHB*Jz_VC@C9ciKuWMJk8H^dzFRA+@#b;auFy_rk{Qk=;8y} zz)Ap}&)o|(erKk=aig}1J{X0L?AzmC_3cDJd#5br-`U?C8-IS-Bxt&mX5hkXZIP=y zJl%7;5TPMibRFtyeucySyW1s~mU}(0f)JlY zM4jP7K?vUQ-_kxlc!vvt*#t0PE+P<7x0_frPDDJK z@TD?LZ5}mDpmeeC3BjUjy4hMqs|96!7HL~uYuMNzhfAEXD(baX=18ZZf^UR=D-feVPx6Ry^(X>Ca$1DDyCY^w!n-c8RerO)pA}vVB$P+%>#qsW8#HxSTAoH zY^y=4v#dW+^$(XFVSLKvU4Z^WHZov=*JS>-e3e-b&b8o9{%N%+luy%&!x@cCSBr?T z#c7)qy*$EAzH`v#^jl;H551D5YvCndX=)#_?XuFLk?g5e!S2)rdzfLBpTVG6gdP`j zd`zWH{|t96_eC{)M%oK@=@7OxzCBzML_48DH4Vg}`m;i0pJdbI2tCV9Ido5W2Lm!| z^4ja`6_m_Nxm=Nivd3EFXcHp964h=lVKViXF|K3U*X6{yMy=M5P-1`!CZ-$W(jG@m zO6}p>QoYDHxlBsS8OA6^C4UR7p6eg_vO2fLU-?^A?vFAe|6r_WCy=A(P?9F~Qo+1O zVem5vDF@GS?MV4LIH44C=^%SFQT6%#+i0OR;=?b6;{EA-;iM(538xmQ)N!!X6x_nY zFvQvzfeCqZJm>A>3tG@sjqh&!Q`KioRWT@ml!@L~8_?qKRqUHRM<36x$1v}XHfQ5z|3RWVq4|C}iPRxVNzuS(b{=ty5{10IhHb8MP) zufc5O?m(#G~Pi8C>VuJjnRZ~gj zSgTm|!n`dUL5==e>e?%9SnuaP)JR9&(e&_!i6eD1%-nu(SWBEiAUP}llG)}n3s8#Y zBb&7rAP%0nb%}q0#C$zuT?ec@>s_UtmawFL+f z2(u66R72I~kzil?^?O)np5=mKIOy}vHr@u~@QhKTmpxVzQOn@A{nwkR!N&!Fa5fKCn3r3gBvs$^SD-$(GZp@K zvoawY`{Ux(CQl=-(ZmiP9^pNQlU^x{+#ui=)ao)z*DjH`;HK7X*EtY0kH8h=O*o z4iG9+%4H3g`>Lfuhrdmtw70Du<^(eA?GdR$NdP`NDcBF5G0G6i4?KAKPM-?~P zQc7p6SUKX7BbzT;={l*WbgNls5k)sJ=(Z8eZjT=h*7ZY0;#Z+TBcgBmepv<)V<;;? zY8HIFX164W$I59ZWUu@1iVvSQhZdWDHmfcf2Hy6(^?7`)Hz;88+(||^DT8l;jhCO|D;K!;BlHGAxaqeoz#w1fGux~4NhF@Dug{EH*FNZHDzTHp_}pve3Z^Y_^r9i zxl(F%)5Kg2gHD%wy3SSO4Q7=&8S&Vr=g{|`7HbGWU)=3~Dvpm-js4G@Npfc&1OA75W&!2Z=%&jFyVEI}`?% zAqP^F3KjyWp-L)6fazKEzRiWf)X-UIWSci7$MoSNafI3v+LKOXbDwPhzr>*D-00Vm z)#Xg6bwe}jOmB~9ht`>NjcN-DbUo8iaK|a~N_WX&Bay|pWg*Erl0%@7{+43lWurQ8nBHysHrcaXRAY<2GwHJcEJ{=;zVt*c% zsl{3ohl>-tq4Ch9<(W3BNg=qu13pc=7xjv58(@|QY0fA>UHgpn!J2TmIM~sRX=MNx z0Pq{IRZd{v+m&9cv!)AD|K`t8-ai-XXJklMhFytSeKFimiZ54YEu9$1jf==ZZwOWX zd+oT~tt(jmO@eFs+}+8i3AVh^5TU&1F}tTzj(oFQtY3JR$*@uB87;g7@`ygwAK|7= zb+UJ6(JEpT)6_2->tf-s(w_-`6j}w)XlD3afkflS^w8F|7l2knV09Mc7GBYscW*8x z@pe^R{abZkTlVGOhpoDyzG1s7^9$&CP3$U5{S)6uo$d2~@%2u@xo}~WW=?ow+qP}n zwr$(CZQFLf6Wg|JJDI<`r>DAVrsne9*ZXSWS%Y=c;RXz{BaHri@v3^exuN=judO;e z!=lC)w&hnvYdji(2A|wR~0H(?XQajc=0ff zyWHDyQ7M9*>~>Hl@DyAgRD@5j$p#e6sB9x6ry4CZWi?Ai!o%3w))$0+ZY#=9rho_% zNR_nS(mp6z=ecL?sY>%UNygoUfZA=#p)WIecEHB4tGDTE2t=CC9<-%uGwx7{@$k7e zJDyquGC8Ai|EZSIYrkMC{aeBmhT3+!%Ud)#u?WA2&U&Ao>q?8_0yEPY89`oBM(%6L zfnVtfd#xr2*hN}JI@#3OR9mZgM$_43Yg{~I ztQ#iZ^6;^tKHbv{V`S#|pesdXdwTgK%J00)5`OXdS53l~md%-w5^zoF30wR6ZUDwS znSidph`MERHf)9GCBWx;K$}OvCg#loS6DD~KP0}92L1x8-%0<1C`%NZkg%98wQhNc zT>e2HNtpRk(4~ck>g$*N#{0k{Y+x%&2!CAIi|QGgR?@C%71v87)@1{~@}&a#Bum(B&=vsg#sR3^_aku%Di5SklooL{yQI-CFen1nYfYNjS_eClQA zP1v<$bwuh`rKNH#{DqdJnRC0WD&E$ZZ$LLS3(J-EZYk7ycO33(Q@Py(O+*bRo7cXS z9gyqRwkT!mi)!cc6DVz!7Mb8yQyj548)xT|9-wiFkXD#eFPqqBNkn`((X5AV7fNmQ z)FR3JD^#!gS)=ry+s-DBBly$xL0+<3p(Jg^LURX~gA^h)*$f;1zhe40pAECTM$HXc z7j@P8c1#_tx(amhX-jrQnh7B?O3yD5Yf3fF(!iaBu9(NxCmrt&2!b9<3{B8(- zfW7%$SqJq|nZ#5*({YuIWw}Rt~QN29+FMDGp~Et5JK(sO7+}RC6cK zNdiZeJrZMo+lRNL(T<6lM7{-?W=r!eYcR>?cm4j#VQo&f13*>B`c@ho2BmR&!vl3w z8{QG`%>G(-4r?JZiAw1|Sc&>{Le6RH5JS{9|Ix#!n-JcVN7lTKRwoVVu*|1tHFHiL zOKFV%k*p|ud@!`R%N@tof>(P5NPryH%vD!u&R}@4JtxJWOJkyJe=?(CC0)GEE1!EB zP-Y=uA83k68V#%B?k(5ZCya6Mmla1HSw3Inah=^;Dvkc>#9q;JuBA@8SYXKb%}@Ik zthwx_y;xh8!JrIHS-6KNKhL~i*qPvR^P7_4A9BSo=m_Vh(e9|kGA9oeuSlrqF|PSW zZNe`2Hq}o+ tUalKRzebAb&M3~sg1N@69tiNYEcv#SJuSx{(h5XK)D<|Vx&_L; zMn?TzZ}8@12S+ufac8+BuRp4|ylVaT%#r5kccRFzhX?Rkp}WQES(M*}IK6p9*Ej2> zJY!uxuP-_B2LSweynKC~tIkqwSoNS=Tp@a!h;mU$+!)!jJcairvjoPAweJ1G*c3gU zf2faqdHd~JG{`U3Lw>pDGUED!=*3WB&bpVJVm8`n@;$bRlxo;PI}qf5r#y7-G~S#+ zgXk{AxfAhDVw39TU5H@IIo-Aer8+veA~Mr|F{(ok))(ng^*Zqhl_lXO)|ImZlA4vO zh~}Rp%Fr&Ho;DCj*eauT@P3;1GTB6rOF zNAsAFFD{Jm9y#P`y)y_{9iQ{a#9jAx@WYK@+89`ppw&U~^WRYVAYE>yZYjZ+Bh9pd?3~$7*%KcaUyZdsme~A^L(F^{R*NjdvFW2Y=+V0Cu^uC!kYA z{WgS6bO{eUZ4`l`1qDlT)4*&@z?w73$Bfi~5T?X-C>Bt7^p&n~*;5}g?SEHTHMH!r ziV0?tmIOSfo^*e&F+*SOzuG;CB+R<+JVmW5^O$v>IJ%7!Fb@ib8n|t(6wsuvFa3f> zl4qz{Ugj)QfWT9UBmXNlO3*$wOFM}kp=mZ|x`bPJPJVz66o9kgDVc9Q&qobEcWV*^ zrMZDkFzNIV5;%7<_}3JvU&^I7G5B>n0ZHA7MPAAhhca?d_J`JHC`8P<)DwdJDWjWk zItjSFd)=oSrpeBpbG?eX^Awy}T|)s%u**^HhB9(cBb?QeVRgDMq*p*R92nP3FCj1+ z_(aN#y-0PV&MG2y6G1$G)yLDjDz|l4gH;bj98ONh?AENlW2WXwta6dq&23I4I)V8m zOPobl3AUR;v2qvW`6|sw7umESb&QT#LBRN9%hnGho?o-M4IUhLGMxwMZWT0NbQZ*%`X%&MyiUlU6%kJq7H;WoYL37!a1n2#NDc$gNxs>yA#btu$ZPR7IZ6xkgz9WzT z=SS8=$4c8}7V#>u4(A45(n7py`j>Xr)=SdWX2_CzcK#L9t$EOC2P6HwiZL+&S4zS) zb77iPU^x<@VD?JzdmxLA$V(!i0vtG@%|UQKun50OxL(U?QQxcHJc>s z4Z~%^wu9bz0g+Vn`sd8g1~x{d~q z51sxA3wiXA{}XxWz9^8?w~@ivd#ocue4#rcjPT(g$Ij6>>3hSBpsaxQ2hs@;NY+22 z0Vd$0Rp(9;bVrbig06qi4vqN~%gc<0V|&x-oA9^yF}zfO>x12bv3Ze_K){jL6!sys zQ!d}Uj*4IgE*IO&isZ{bKsT@z1^=^_Z0 zzQ?1832ViRFqntSIQKOHjpK^%6YmGy`Zv#RMgEAs(@1;5cRTi|?9so-peE!0BhvLh zvs(Wv)5Xfk@V_%%jQ;L9fG5#+|*Z)7bs+HH;9)~??7xs+*?+7qEh(@kmQ+~F5 zT=CY)-WuQLI>f;zfo4-KulB=)+RN8%{BRXfwZsdIxTC?pg(nwOP56~)(F=X?*SfeH zS=~i^`Doj&eUCgWZanuk%#p+F$zpGRZZ~?L*M|z;Fn@OY_#59xVfQUpS?hTHKF*7; z!Kc!l`QmD zsim86^H$*UpU8|8<0B;5b45cFZnl-Xu@^ZeIF5mT*~!m|S&(QByDpRWlB+?nL7YAF6D-fd z#^~%2vtwW*sm$Le5Y9a$R4kkaI80e<$n4DB@1rZzo?AT|U664zU7WKHz_a;w@@B7J zo!&g1t;aaP3f=FMXg(Y92I=Y3&;gEYDbuXHen-2UqF+yh=vJp`S3Jy^b}?8)zzTAI zJsJ^pR;e=}cnZ%&7W`hEJ@3gguFrDlJ&m;5$#uU}oW|iq@lUJ;U|(n1fkNNA0-K(X zB5py9UaeAjFr^%X#?M%gX}%TIszA`y7y_j@`0;Ji%H68Iy-R8Ma$Bs3cRHiB~e-0~GJ|LEa{aA{(=`X%z-53B zZK+ts&u5q$zl}XCaK}2bd&2Y)^osbr0-pinJK#}HtfKR5U$kqg! z+~~iIH5z`;(P`*50UyiYldmFKF*+*chJx9pj|(rCx&QQ+?pkaEYkFtwbhg;{P-sP3 zRdsN6L-w2SNq)`SMBIR{g{|rpk^P*rpgePa9h|}9HiXC^6sdW82k`U%;H7+aio18} zZr$eZO(XV!#O>Jhdi_RGE?fW1JSO7lG0Xk=Hh;B=IVdb=`2fLt0p{QJ8jFA1=Oy}f zh1d-$4n(n6#NgoQ@FOmqV zODu}NdO0K_*ew&&VJ9Uy19KQSu1Sarh7eSlg_FUpi-&#?m`%|nB zwRY1*()_pgWiF3lY*oxys}%$RZ)-Mu9}tp;*dXA~DHC;x)$_q*{P7|~=RpW#$1b35 z#1mkR4`Gg22BP!H!7&?|=c{#p71Hd?*9J!|$Y`{`Nh#<2gO2MO(S=7A$K}sR0>)Rx z#;pXLkLF~dFsOkZ!2J;tO%JhG3~hJq@YlYuhx68uj_7)00w*&7_&}dS>EZ#5m%H;G zXoOZ(n;G~|Qq0{K;Xmd@i=cSGi#xFZedfp(cKUz%y2DvOrtBHr$y{iWl(Zv`-rdA>c zQ|2!r>8FfWCF)~`@L%f_M8Nb^u~!W)4J7%Qa7z-}SQ*V}?-QV1vOu+hUOOTNUfbc1 z#cI)IIA-6m==>5PSw;j0eWF03XAXQW6NuIF{xHG2fj|mnGde2NJoD zSW|f7Q4;;CxCkX8L;ZQ!>H7gzBn06it8^Wp@Qt)b_bCWg5QO425Fo?iiyEqxkbiLABrJS8>|*q$v-n z-m^W`(pKbVqdJ}t&|#{T_p60`i*nGDa@B$LGR=K&;ukio|A15Y%8t6#Y)Rb_C@8C$ z9;iG|p6?YAWrY?A8ks;??h4mz3o|jvC*GS2rnT8Vb|^qfl0I_b0*(xyE)X4Ey79zs z2_Sb%?u8u*();K{Eb9?1lu@}Ax$cO2Rp0y;m!W@`wf#~Lq}afQfTuhEy;57grzF)y z+-4E3TN$uup7m;c?a*3jno=MJXv|6}>cOug?&qFND8vL5{Vb%JwY*Cl=RVn`X-1|! z?Ho&mj7_bgrBkbTgdLhz>Qps{7Qk4_(n4DIX4-7YR*&PEYEsZoGEO4YDv{}ONFQPp zIXDc|!^Hy`Ji%F-O9)9&KgSz@?&$oIsmu?OMKb`~?`Z8!>6rvI(muthq(ZTf{{(3D zLwe~Nsx4~$fmN#d;~c^w%}jxw%nRufkvP{2c zL@m_{N*XH4EEw!pCQ|nB?96)Df};?z{jVOv)d|slIS%8`IHX^qYpgaNdssqSK6Q>@ zx4?vWv!;)?Sm-<%1!pdc|4d9gtMQiVp1~vYix(&^H*}%essGqFVXJ!D1xELaU`iGA z6uy=?QS#<04boPj1`FD1;G&jy+SAt@=_YwuJpBrInh1{)S_Gb}FAMXL{+yY~+cj>+@PN$?o65 zTsc19+LUC!JbW z4y7<;zj>aosUUnG!g!UMY7Kb=!`jJmSqCh_{fen03{l0JVI)C+6o`y#>JE@AgdA;d z{B4AC+rkrL3Wme5=k#Tt^nZ=%%_dT2JF(*h)({zF_Zk4}9EirU?YR$_)AXYvLa&ZlGR<)N6Ce_15 zBAjx^{PMl-cUw=JmyL9f>2bY2O)e50)9aTT` z0uJeY(32H*?6*lJu? zQJqGt`c&f&TwUs8&~4t&G;z}9Z!bAY*4St|Lp9)tc2|WsCXL0Agh#k|rfGX`NXi7K%V9)q)g;vlxF-3T znX8bNjX_jQ7+BF{7)*?+AAHo+UYkNadY6Y<^IWglD9tPMg&5M{@{)ova*lPb!xyqK*G*fg|!SUw0rR$O{yCF(;HL9+7ce`knn;O39LFJXBSH**itw?g$de{#Gtra_1b3Z+2s1{U#jv{17ZuATW-Tfn>A z9bhnvIsYbXXn9m0;KoP-Oa((xB}l~ac3$-eO&Et}FT#XM_7KvU<`DI4U#YpRDPAN+P4L_uk2JVOvK;jiP&WN7 z@>~BN@t5XKh`W!NPG&D=of@KUY;9HgZzqx8N44RsJZ)W{GlW z{G)r^dQ|64 z#g#F{{eUvcI(PzYfWjxh4)XAGE&=W=hs9HFbP7#WBfZXDSyviX@hm5zfh1R1Po+@54#*`7MdW0%;0=mq@1Ioqs!Xirohm2EsPP#kPhFtuxM z|C_O>NOxs*5Cj2PuY)-Z1y{;1jn`vx zs1Y-(f~(cNg&~DfLrqxKwI0quOIBBN+dlLfu$VjoA z=XZ5hwAL4QQza)WVA{aZdeCatWp_G!djlwUdoZs#H)N?&Ms*bbkLb|;l88PJE27!9 z;Ew*X@>$>!kjMT%aa(<18P{^ZUKUkRlkUN70?#Q3I19ni=AU8E6~(X>`Qc*2rIqSOg%-P|RuqJ86{ zmqPUgx0q1XMwPZ`A`F~|Ej}?is+-i3xN%C|^fgANm6Zdx;+5Hm)cL%HLK;cNXr-!5 zGGn3NVU@Z2QQ?*~k99jKt@kI$%Y5uZdtcSi?U%j3<>zj`y2r7FM=8cZr_xlR7b@&t zrl*Z%eRTr;22Kqv&%sp^_^zoW^tILIr3X5LuISq>zT+mS^g4>#2HXkZX~K$h58f7~ zekD%=cTqrvD7YS4=Ma!&OfJkOb#q)0@RR8wtShdYj43IqYm_*v&IA@ytl>(60zolb z#ln%OX|%?5O7`FjDo4$ETAgkuT;?+hNS+%+`S4)gQV`LZ0ieMrIf9dCm*^rP(cKps zA_hrOE|YTFRx}ltmtKCzn3gR@%KK0GRg0zK-cjs51X=aYzVMFXdgAIl$R_FQj=c{S z&^>)au}2`mP{zEq4x~Lw(y*1#0b&QN_RW-U2QQp zC`X?sR%?4-qY8=A0r}75%a_onZWsq~;}?wi?{mg{#b>q9e22Ca;-cxvDftI&dn7Yg zVPy%6)JK^+?P{gBa~2O8w2TwGLC!qifLhD!mdA5rjrcdU#tfYLvk7CIZP#jdT+CMj-<}JC>58|bLN^^BQBrdwhX95`LP z)U6Zssb|r1g%?3RbM~OxmQx}AXk(0fhpL`XQUOS`sKt{-{EX`-JKV5$u66}aYZ&0j z^SUu2JG%o@i}iI=RWLbLk6)$R#cGiWcPCA0bU2*7v6>DnqBd1SKRi267&a;nCf(2& zb4IRfe}>mO9*FuEPfx7aC9zDP1z}b}&6^H^`-Aw7$5Erl0o2QZe4-7{&&n~$A+qjpZuziJ43-&a z#P)L+G*n_tk;2a)m-5AF@^}IqVs7P2wd`33h9r^7i>w;0@dOtgo84#jpVFs1t)8Y+ zbfh1 zAIfN-Kd2!%iPRMy`!%jI`S3DcIWw}wGw;zwOYq6cb&}EVQKtPv#|c}O2xW8xe>W)E zG}PmPL-4#?i)X5ni##Mh+pzHFK5kN0=t^ZSY zURUavFr>IKMTERyk1@xSy{*+#S z*}}Hf(j97Z%xvN7Ef!wdx!Ead0%{hpgKVN_A{S%oVxua&?^VO)Hhl5zP^s1*rBTg{ z3zqKYG%Il!Ly^goAS9wY>acfG=@9E*CGGR2Zn+l9OykQAT^`b=)ZFa`*!=dDYUHeJ zMc4T&g^C{K=%vL*YB76p-Styr^$xS`5&{NlQG_q0{Y$1t)VA+1148)1Q$%fRV^gE! z&=zl=hVw&1C-u6I3l1IcR%y9r3|u~CDII$Z#-W&(Be|PiMTV!GQVwsbZKjygjigf4 z&Mh)_fMF#|_0zkgb?Dq(SJ&Vs`dwR+7ko;HYB(Ftej7`-Kze*lAQXS(UOGe5A4I(Z z*e^ErfR;=jZx={2INhq z63rJiT9GD+da3+HiQ;+pT3r_Kbk>%*cV7yp9NqFw1Yq2=VRF=$$vLUcf1p_p@3JXt zHVGO{jNUdSkjqeBhsjt|m6|y)Pc^)*xC*!S#p@|Q^g$KN-(P@+#e+mPs~hgrl-R3e z4a!ea2e(|b+=(-GW8S0@Z0;klNi=p zC6oMRJYW2(ui{iknP1Vd8$jUpH0+WqU=`L~L=~3Q3*l!y^?!ORellnJ#ZNbKHT?f_ z8vciY@IRdfHbz#~|HoxqZ2loHjDF0sTD7 zR%XG%IPD^9WF%80CM#nU{F~`KLzLEI-}m|p`0ehyoH*!Zew6V)v2;$*4M7xgs{os? zAmQb&ew}LdB37UyE}^~3$47Il7*~o+@aCG6ny{LBKBNXX1U^9jl?2dWZw^Vp(WDX{ zZ3ZPs=qc)JJ|>-?FoXb~5|KDp*W@V}5?7-WqCj5z4inR!JP@~)dj3VV3%xfI114NQ zA=Revhc(SlWR*Si=09JHR6q<)u<~-%&3sSpQwSED4tu!5dVKQ&3;jmOssSa^wytXw z;aj%nPcfX9(_dX>Wg}esD$LIgf|w!x|EQ&A14M& zDZ$znOdBhk7N*5Etz!@A&QJxZS=1GLB-6jy1X3bjmay)TI+~Z1zlxjfaWagt7=P{y|Q?AUc(?3CXP`Y zvt=F8Oq7E{OiWaKSbP|c@z_o4X5iP+JfE1qYnM=3NCl{BV#}DWqJ@TqX9B-N_SB~C zs9f{8)Ok+}Yg9E&6JxTZez}=Jr4e$WZW9+sSFXh!5J{KQ9#TU4^P4~lvB-HnE&W^e73^?5eg?|^kDO_IG*LZF^1?QD4at?VNr zi-(3UP?uS;y_)U9+N;38aq{v}Ic0i~4~sqkKFHG?g;Qkt z`x92Fk5TSt6@w%#Xe3GmIT8byH+X7Hi}fg*94jmP2x(~OY8v^NYy9^rw&!i3sS8Wa zjfWM(jajJ(0~wmwNM7j42sy%GJhf5LipU%*^x7150pS&X-?X5svfvdaL@lSp>w~FX zywwGzWz|9~;?0B(f<+L9Dx^6aVA8i|<e+x5!3&DP%V(!*jfc-JmZH~;nTh|=%;8a?b_qmR3>WOpLI zM;iB6B69h;9^Sr_kKS%2PdYtM5cd{VXJ_^_nAY!`?1sbO=G}U)n?L8x=1o03$c*Gx zyY;r&9^AdJ>ot~=eYaWH_c}AK03P|VWrG92uk;ZB=Z>Xai4V%F_J!ecT`Uh`)-4iY zGN>Mx``v)|+io#Zd|?rDSr-@lds1RJg5ak#2*^%Z(!~0ymAb*(%YR=ECnlG3m#nv- z%X8}SmCY<{7Tjzoe?KgT zX-q0_khXn3@`lUSMc@%;WzRFV?Y@7dJu9!Pa+|?x(|;d&AJ$gyH2NwZ-{$!*UcRjd z^2^Dtr?(S&Q0I9Vf3JYe<66_9#Us_8Gky#t9*c9!rEW2O6KH1tJT7f*#0Ijz%&LCq zYrd6wTu=R>CVx((ioqjKtrq{iH{ORci?$rL`;~^yZ6ntmtDpQ~@LKNca*F4j42FMx zGaQ&@MYiYEW$9^oOhyvB|2jE%HCIobW5J3CaG(1RGhaS`87`mi_sHHY&uxE<6HCKdwbQX) z@@;Y7i8$MwrJKyGhwI?A0Z%)#sQ09;RC(@tYVz64d#*ft42L@H?c}^&zwt*ae-2v} zx~lh=!)3v89d)y;n0VCpuoSe7$GCuT=v6E1CYbGy0piRCX zEeE&#C3B^z%Dd_HM9-R!#QUaMyDBg&^&~=_T*)@stgq|m*>k7=a5oXKqL|Klb&zDTH9CQkB&6xnxYOXGg>;q}5_?q{EUIE8*UzsK+@qsn;p_0~3KVy|vnb19ManADi67!27loekve0y8Zwl~wD-|Nh!Ec`Ccj zIT8R?(SFeuJHlOC=O-krdOSw90-yH^gxG#U!Mth5UYc|&0g@xc!t2Iw1Kdtk(`yNP&n7=Jglke#A zy^0K)wg3A1l6eiaE>pkqG=3UV`qqpuaenc*FFhWO4^gSn;aq4qkP*5=-1H3%`)|=C zfqaw}e&+xm@b0wIvIM<&4PRS>XR))x<*6$<*3rjbx2B!f;S}KAu{3Hpora$W=hV4& zxXu)wB$Q|xD{iw>!>{*cO8H#&GDr-<{4!<9ndH!EUtd3RAw^)SZRrZr!6}J4bMG4pKoOj`4 zt~>bq`)K{m&NQPLYMO2nNB8!OnSMrny>`0jSfwAHDpI3q`zY6RcD@cRPolH5-NEJ| zdDqw4yG!?dd_!K2gdA=YNm+4mS1HNqXm!ase^ft!{-jY{gYQ})yuDj`akkBDiLN5N z_QRhlx6!%$d|jZio1jj6x#aA7J<0Z^xaTMBeo%8*@40EcNJR3gmHYeE*QAyB`MH1T zX^;D}-*HceO_zP$Nb`^O)EM6C@HwsiyjR$N^LcqQxL&JiXM%bSkp80XPRHdf+vOnj z$!u>E4f|tv;GR9Ii_wjii<#f>!5Fuqg4*R%w9mQW8Z3X`)lw z(X;YZkot@}8GHxVeQUgrk3arrUEQP0UV$HZKL1=7x0ldgu0G8V$Mr}MZ2#Z;wZ`V| z6MB96PFnzg)&6+4)*er-ukrnCd44f}Viga|p&MtG^W;hKQo;l)-%lBL^;S;vX0_cL z=Znv6^_?k_&oPFw>eas3{i*AG_3ZpxuBzJn=BFnW-;Sf$bCK0FrsHIUN%tdSiCSE~ zhQfR^UUXYG-_LQuF23PK_S8??{f9HxSKQEJHqcSo4ejS{`?v_QZ}aCbjB@Evth}7> z!*JrR>^Z)+u!y%5h zAIucpFE`D}Kxwz>85nMUn*<=8r1T^x#$73H`GMP{AVMFsg{SoAlC*El_~&pIG! zlM=%7vh*BG>h8Pe`l6S%d>fmh9eY^$JmswW#;0Lzv&qfEr|XWXyxZ&UefH}?XnUB6 z-JaR!ZDsWO`d(HG|C5CszFqtK52pih0Jp4)|NSM=wW;NO9%eM$3_Z`0pVfN!WSZE| z%Twpf`Yi113>JdDgh4AS>TI%GO}A9u%8(-f)o_0VG) z$SEv0*N)n)zw>t`yZBV~@ADD*rj|9SzLpNW-H-2yb<>i0J$9SA?3OFd*>D?FeJr=R zq&R=ErG2#KKIKM15AV+H%+5wE^l)NmcNj#~RcvjM1cRy8PR#gpuNoj2BP8KCksRe$TV}*} z6CEEF6IIwwx)A|ekTDA-R`!?n6XD_=Ui{+QH|d=;y=iYh<>%GWeln`f{#^a?t;X#(O0TXj;dS{oUt~zR z`NATG#g;0^DzBmbp?!U2YHkJavYv*ZKdKtZ(yz<6)@xh;bKEk>lPMXR_7>a;Iegt2L zJD?4J?bzp8jOC4`R%KJNFeziW?Y25bW34ScT>h1fZbKgOeVS@+IS=N!QqWb@a>@68 z59V>>_oY25t+kOuqvVTU{W>p+4&&x-b{xeLli%pFncg&DTaK3VntK|(1Z<7h!m*dL z`ZfJ58axXOyDXie&yQO~nP{r}#p0X1L_Mi2w1WOFmc7YzZF5$~`MFv(`sFz*6-GBVszGTvG?8(A^UXPSMU=ri$a}zK> zDLnO)!e+XRPCue$kKXzFbMr|a{_@UeG@yEm8Eq^40)z2!VqG>cV2hvAhv0VgbezT7 zh&-U3iEO~OTfo33xBUtj;ovjayX7Cz<9;rhFPtp=ICOxdJ;)nCW~avKje%>w{yD-) z^8=V5+nHbKU0N*d-j0O?@8k`z112uLNlc?=P>|C)0ISHh0Iitk?XI=3bS&wWkrt6a zc=lo|6|kM2KRcRB(94BdOCeZ<{C_nAHvYN@87p!?iHe~#&deP=rYCK)6!z6M_3Q9E z4GcDtEJn?jxn|mfieagO=(6d9_v`hw z^@^%}n_FR;?kEVftU~Xzx*-nxupKdUqpZP#PJ?JkH;G)=g~d!^IC8@>OR%) z+egW6ylwEmZZ&MI6wUYcXWRYL>*gze3v#JNNMSYXev_Zh(SxcFzCcQ}mHJB?&w~F* zu&hRNj4luutEp|`a!%*T_UhjlEO^&tC9?mL(;g2G4<8R79}$HIywaY%SBZHHwQ8!D zXn*r#{Jg+C?(0wI@xn;7w?IyN0DH{@(EJ0Tgd0AKwU^rHINow{tGC@?r&G`VFk({A z-#cc1Gcpc9vtjnpc{eHjuC@1bXEpWne3{9*#-C+qSv$I>_<5U^1#{+OL#^2=<00GR zeOo$Zck63@7I|)wOx9=X``*ZL-k5TCf6C?hR$2_Ahk~6%m&I)z?)jjOx5Raapu%Mn zeT|TOwU_t4^vym+-ihuqguy)B-?@DA?pj2R6l-5fmA~#N`Mq!Av|g`S@dk8#X+546 zbi73Og|hDU;@UM+-AnZ2o`=i#E~nvpls}wjTxsgJ;}@yxPguI#SNMo>o!{;E4)Q%l zxG2|dJS?u4-+o~(o%4@v~y42+UiQ-Va#VJV5@BdjOx9ypeT z9Qav_`{|1(;~Ym0rQqBH#s<&&(Zg0y(u?N+e)qhVUGU#9z5zQ^LyNNuljoFA$xq5M z@LmMl0_Y3NPo^JGzNtT0ivoztWE+q69GR; z%zy&0l+ZW@u4#b{3kGT-p#=w(IC1|AOCh8Mkynyk;pKVdlad!vUl65DeCiskw~;>& z5Pbh|2bB6D*H+Bv0r?#c5B%(C^qo`>JpS_}Rgb2ZfG0j+f%80&Z(2EBcew4HWMgE`s0c8hR`$6R!&`$j3{p6F77f5gFjvT+N zd=dJg`FZP;l^1TGpk#)MNjy|WpA3B&d$Q!M$wLNCS-^Pt3FG%2<`-XbG^z*LcKnQ4 zQ^wDev7D2bq+M2yQA2#qsn6!2zF@JBz~XOW@>OVt4C8$1FDSZSFLg*jEiLs8JZ z?ofn&C|j~%oXEdt%7($=j^qU;dqwh!dW*2Mg|?O~x03I3mo7{>cRJpDJ#oNfjKM^P z*@@*WW*(qPY9-Otm{-$&pQZ~b9IZM%SOHTGSP&0e~)uQ1``57#X zkyIwQS)zILDQt%BU{}Kp&Ezy5{nQT0)XfsBcb{D%L-)jHtM!Xh2Cic>vD75An|YV& z5H~Lu-JrLkxkWi%Vcbi&>Yk9LI^6^JduRc47WA%eM&w+3JHWOZ0mAaKT^@Kjx8;rP zbCYk^iP#_eqxL78d)Mc4I@I}*gEuRtkoFmSS&(@MXU?q!`Feyh9h;x)8u+e^`Fweb z!Hh$BMup+|FXOWeGIL($manKxazfp05zp)us*`x;DxSsW4?xe~k}G?$5B)6H1^1hU zv{3z!`ALEdS`Cn<6j1V1^jl)Tk1d1On~^62w&1__dQL@_0ck>X=11^oG>1)T4tCWK z=Mg}92aL-E#Z>~%{9^%>90W!1LAap;f~6dh4`$sT(2Ec}oDj^$9n@>U8O?}e z1Kx;%XTTgG*BUTvVJhQ6rV$G=WVeUxL3h@KBb^AFM#yaw&7u*C(}2Zk2yqm_I)-YU zi0vl6vj%bANdM3eeiZ$U5Z#-|KO_2w10L+a2PFhr;V)j4&^-f6I)pk)VS>4Df1biA;p2hm0B=%Hi zd9e>qum&Lu3cbLv2O(Biz7X-JF8>dR7dZCpM!t#M|1sovg z;@*%291w+dhsXklFD}2AYyoA}U#>{)2QNE(dw?ntXq$kvSs3VnMm0D&rtt>vqu!v{ zZ&2TJ$LfP@6BMDO6qmwpD%`2KV^AnmNkA2%CCMuvs$5-(L6s*}^q~M!p*A5Qs*tFH zf+{<#)Md zi6tFdJfe(TDY=Bal)S`Z#l;$&B{^MmqVQPpzNEYaY(>}_p(RCIo>!PxTBa0T*}1g1 z1ZBnjjP%Udn)wmn6}usPUHYO3QK??hy!6M4{TbXf$t!R}!nR1Sq)lnF0(VKSDt1Hk zx_qNDy;69|@Zzs)3YS=~94^G>C)*mpy+V1(@T$0aqw|e%}QJS9WyH(S;{hfP6vH1)eLDZJyWCd?Qq@RMiCv zSIT=qk45@(&d&u)0}Y-lD6W*RaIsST9Oy!pD``WhT9MfgHg>qa`2G!+1rjj*UUWZ% z95_nIR|(UzOLXVme$M@*`+>JD=pJM`0wY2V6AUmDiOEQ0P!by%!^9p*Q)F<9;Vm{% ziOHIu`#firK`=HE%5We{iZm0-#2|}_G&0KMAPc}8LSYKdBx-OY&M2HhXz(81<4ryv zm+{9D;lYm^T>mSn7OboH5TJ+$gtZZ&wP#MI6_8dyd6((08 z|0C=3sPE+}gRo4X{QW=<(tRX>i52?cMJN6;X&INBThAu~qSL@NyvVQuBlTZyT}m^c z=ei2~Qgt%bs;~}ehq{0TSSwYKItj2_1-A@>_0NvIxbaSTb{ps&sSA7N+IF=bqVIgvUZLPk)2U|dGDR%a&bA;r>yE9*}=8}zi8^N*>eoVp!dR`|&v zCx0l~kEvfjNU7-EBa0TyLjww}@Z@|m0s3s=DSi>(;JkX#GJ?GQ!A061Q`mIk*7^eW zdA=5qYmrY*y|h289&sA)O8xf@cpeOxZXC6nQJz1smj^2-YuxLbI)>$kfjb+uqZ)zn zCC4llV9=`bJZ{$+{Mp+$?K5lb7;;0jKhFAKh>c^=C zg4YGR52z+-!+Y|zhfTVd*WXxmr%~Gr&=o4=h^@$hU-W1`8&=(665Y`tJ8(8WE<5M3q z%*Fj(I>d>k2ZZT`Gg%I&?}*q3hH^#j2$s)zpTSb}PWA#|OPS9=o(MlcsR>^BJ`i_q z3z^Gyj)}w2;jy_&DjW<1{q$}Ee!iVP%wESQuC}R(d1+hADM>rUm5hXZbZlf?G%O?< z0R5}tx7Wu91xg##Hb+dAA~ZyRR>6ME4?R+w?81^*#xrJSVF^up@SslY|4uNadWg-I zMp7N-m;N*|3(b24Y2@97rDY`Qb&?bmq$#tr^|r-xuQpuxaoUitAQxZ6O}Eg=QwPtH zf2b%5bLRyR+51dPxweC(He%ZKjl`#BDJ6p*-8M&-A1u*4BpBC8n*uA~PPRWEAG&M& zn9i6J{KSUnTMeit8*CfwgE~8G{}*Xr8C=)0tLbfKX540GW@ct)W@cul*p8i;nJH$B z8RD3knHge??Qzb%_qaT$# zvlFV!4LV@bMDnZ2Tap+X%G5gWzVwB}tdyauxX$V9awW|*YT358rysfRm9fZ#1)55> zH#VhyBkt|-zsP0$9qQ8@&ykw?Ii9S1nME@s)kHvn171ycPfTn{T>H&avxkA@n}rzzaLD8;=V$5nRb3F1@zU0XPm zvf1HcM}gLPj#Si2>5CfOP`K%VbzNKXxnIFCWVje=q!ifLqv^wtH&);+ zP;`>kz;=a#@8!qH)Y*=|elDNKIDTCGuJuVnD`libe#M@S9JzgAVDdIyc2_qA0-_G* z^PK~npOI2>osej zOlN!|?WE!M@Kf)vzMv=wgb?{y1nmQF=MyTWaRa0EyRM%;8l(4LZ5=M{sIxo9%)aX8 zDzmTz$K_AbSxsQJpoqO$ds zS~L69bfj&j8Hmbg`9?_0cFNH6QAw!lii9M7godQr*7944l!aHCbAf6y*bYY(N>{VR z{aB&SDQTRc%46mmADAA2LmV|HtHb_j52>q=VCgbF(nc;W)|P~ZPyV~#UMn|lh06bi zK`z>Ub#bZgnq=o|X(^n4 z(ReSDj3{Q0Z6sx!Ne6BBeWV4c@l;+3bZ^6+-rV9FB3oV3UD~5X8bN=(Q|QMkHz78mWRQi%W{A)83m42TwvF|K|} z%C!!zp7b(75)Ho)aRcWagBio5jWS6VO<&b1hoo*!PUn;7-Ay^^Sp%BQdRW zO0o@?5o;EIS)tmq|E7eE{FdA)Po*rKTw7EYWyq)bm7Fc8EzO>zjzpAG1C}6&S1C<= z0rcIXS4Dc()GTAoBej$W>2o;US3GIZd3)GRI#%q!?(Yancg_nFDkh|MVay4)YB0-f z^jF#U^j4RC%7Vg+=NPC}loP?w6f=b2y%OTCL==q(2(U1p1?1G7_S#&FV}?Dqp2*eR zio-@Mf)<5HTC>?_hO`NwgdVO6&H_QFuFy8RQ5k7tlaE4dKnf(9X^Vwe*x0M$QihKYSu$>6A9i`RHPFW2jQ4{OSH`)ju9YP-1~;%}ZiDjw@b z90i^!)}qvTFrc7#Wk{TnPrF3Rtpr8o%*@1CFbK@2d{>q6>1il9z9ht564udKE6P8~YYvvymm$-s_>BGzJ$nEnFL zH~v%oG?lu7O0aw$W5t4;tAr7B~g7ed@`X^6_2Zyn)%-{8l<%rF_+yXwKmyXRG%?ulaK5d}9 z%*`Vj*0SewMAP3(OMf-{=r(=4Pt3Cd%1BEq4-ZF%V_;Qg?W!lKi__GKm5~JR3J(ge z!9hSg@o-0Te}0+fSxH#%#e-+A&p2#o5K}zOu%Om>_VIqQF_T;GiY>HileoOtwoNSd z;w*Ifb!!H;ewHEq$QMu@nX-_OPu|Ruwd5>PlEh5HTaDJRI;0>otKypp@j#JW+Hx>q z8&^GoMpo&T$SVU6nscVSgD+KkUVk_<=8LZ9;@--^J~!C@Lcj|_ncDUTFP!U5`uBIUwKC$aMirECDf=Q1l-J=qqQ*Qvj&{50sjQ(jD&J^5IU=R@ zvU7aU-;EHAdWKCG7Zb(_c6kd5yCoh@izC1LezRB*X7U|hrSKydL)QO5D>C5~`6)6* z%YGxWD@RDpQ{^0-ZJSzW9}jk>T^NC2t7p{mRa6bUtP1brNN6ypUd7hTCXC}6_(m&1 zftnO#XZ^Z;dZqnvgnj{Nstb8>EEdtVbZdQv)fa<9`zQ_ZL9r8~!%tLO5eDMey>$4E z*DECnl@kEK#FFQ2v3lD}!AbMPTAS_7LWGyi{sAxEZRhU{4Z+%8JcjDB70#|neRY>H zW|xvWRv(r#I_&uM{R7IZvfMfwLF4&=zKYi{^_M19niRPbV|F^ajcNi}`4~(v0h=C6 z_$4Fcj^_RV^tOPcGt}D`0GtY637{EcD7yL6rUtm@1d>B6uT}O*J{|v;WZI&K&q)L- z7%JgvWFakx%p3F&&gN!Gmy*WiA`^ESw(}|hEheg-k zo*N}_Mw)VnX zrcFT$=Q9v>%+gR!ilDKFHx%Vyrw2Rd!0_t(ow8x}i@I33XqD5l=?b%l?sO_L5|mD6 z-Vp}=FoJE7I=uv|o?!IDw+Y^CYqB#qm=}@0?xZ@#53&nhh3b;erw8S5B+WYurq5Vd zzu?d}aJqAbdq<=^bRw-v`Jl|zW1d@Ty{Oqtx>@DG)pml$aJi0#Gu0cJ`)14;{qrsr z-LSG&LSY@gq|vPbS;M5O-LP;7$adZA!oFJywlRBWm{}p-eG zuN6B>QY68G`MNfxY8xCr8dNYmS^hbNxwMNvOED8}c7NYqJ_Ccpd7x@=G>zAD*y_rU zXz?VpSfHkeXdAxH=pW{yV4{#hv(F|sLk|zjQanS}t88gZaM3nzey_BwcS*8OLJ$=j z3Da;nO?B`AIyR0>AaB+Bh`Ih{3sCn4Xxq^PNg$gD+D+t=I@#JkshX84Pmo#}n(ptN zp6!h|If@sa(bLz8C)48n#Qxkma>a#`W4(J|?o?gBXk&LtWV4@LjM^4v(c>4AqCYLZ ziGE~ydQjWNo3XKnb7Vt0>&11G1;JP$!ao(qA8>z<2+I0_FC>Mb=M&E~D{NE(HY}&; zZDj>+Y!MdA?;RR}BBT2$lmewF8r6Gfe^m7R6n^)}XyP*F5?d?dfiYIk#`e(G%;UexOUXrJHIy};jczdSGd_Gzc?ZS`5T zHe?dw)SQ<19WKA>7S>g|NEEkDCPm%>F$@Y(EDt{_))~k!)EjQ8S|mM0Li+HqlmqI@ z4veXXu^D}o>5z=sf&lTNaR%c#Y_JICs?)l_Ir$x?;!V?I;-E!+BU2G{b*Pp-09 zfqaZzlQSPgKqJsJcXP_}^fZ?M#R&UGu0JEK|FwL-^5O!Q*=zRFR&#BG+hl6Uuw{-g zXR+4kE&oSE;jIfSX17Qu&C*tj(EFM)2=4bWNjf{RKcg&5ONqO_4uu&7V3`JGocJ*! zXEcIeeCm`ArxnD{Bxp80=r&0)SNk~Z@3{_EJXj|?gQ$oar=BCnS!T!EW*ol^b+H9R z%N4qkYmiSN@IoG_&EFv`rE|4%d5yci()d12$^M*Nq;L=OIEKJ)8sIix3hRB96klHN z*x&4czvi{DGa6>5BH*{bQH!WBDXu%w`WCC@fK_j%S^sgWU^^8FJR=V~seq&^C`-mD z{_g>+)v(I121Do_*aed*H^CnS_Ttty5t6+9`zp=rG+9#19)ZhTShh8YB{d+7Twx-I z&Dj`L2`xSaErI0`2Y%tIU*c?Q_qfEh&UlDBf((m{L+1;`b`(Wtsji2qprHRrofikq zz-Ioa!iqDae~_)r-fZUVm`YdAh?Fpt&|rTdWa-hR|H7b{lLLtk3TGKZwWawxI8;Yo zQNT6eU*g1Y{Rze}IKH+Om zbW*RPa99^j%7k_bU*u-!LMh@SoZFx4cr0wFfIW;5*bYf9)_8~JCf3R?blBud2pPT;ZlXXUA|ZSeSc)%#ZcDK zL*90-SCJYjq9D`6(!>g_)y#>N8h>$j_luEA1cl~wiG}BgQNA4z>j9&TLweD_%6N<-NQ&0>9F%W>&Igw^S$UqUk8b3Rz z!9Y%3=k6;)=4sPF=GU6`4u8{PgM>gusz(YzXk(DzO2Xa_G6@SMHg`~DK7Uk9SzwOJ z=mmaWV~zR@j^Yoa;d z-e3x6WyQqB9! zg@vqXoefcf4BY8@l0YYwWwN9g;vVMD0)X@q?vAx+H#q0@MG-zvYepCbLbM)3e;tuQxf&PKj*XIUl4CF2mTB@A|$aqoFxx`q4p8;3-4 zZD6zux{0IRaEEWMB;$YDPeO{is| z3sRAfd=A4tRj;85udIz+VY61ejUz=vOLN#@@W91t%1xgz^fVgYvJMv(5cVk_3YAh} zzA}gKM}^3zYV1eH#!Nv~{Q!W9^0U%H{bB3YOXdYl(T6Gr+F(SUOtG|H?SCxH2(G;M z+@3h1h)!CUg3>yaX5X5sNgENBp@8*U1Fj(||6@zRhvE$JpUH|6rRU0=ot#tgE-PN( zkHvIsdV4Xy&_r1hC56LfYt^0(Q4K>aOLIRDIwdNR-N6bj`gZX9&L4jL(a>i{&SCPk zfSiLlbSUG*z)ngEx1rf??%Ss%`MWS@{s?kk(TttaF+xGAx#@9blfw!Pt229hJ$<%O zv{gzDf~>E}8;^SVCGOT%hO%_^oZZPy~i zY3*p47By4kLZ-e7&bJ6*N0G(n2W#wBu3CpFkC!WI79@r+51mqfE>e+BJ(TvhkSFr5 zNTk=o@r`fDma-sqjs7W5l~%UKCUCZ%8!b$d2yP|0Ah}!e2^}eyol3~qv2yz&l$OUa zb|MHLK}hgRqfK$VQzj>sy`8h6Al8jRZlo{259uC(YfI*?;_q>kxU|wzwCH|5(#H-E zPueX8@GS5j!GTba8ERaXLN|q2b^%M03_Fomxm2Lk^Qb5)!j4c*m{5uj_q2&yl52Ha==UkKsNCX^pr#g^>Ad*tsae^t{>N z=aIb47{wx}*d=WV;X)}rGNarsCdOw(xBEtn)_3YsO$cDee3yF*WM0cUS61MUO19-4 z>NtN9T9bxhh}4n~zBJYcc+~&;bxC6XtS7Q7i{OrDYr2Ei!YP8=A)3io5vZZwu8_%6 z5qMDMh8bw+>tx|^lG=rkbRX>IqG4<8Hy5>#B~X3vShii=>88pE>PVuzyzy*hSBJGX zZm?9|r9OHNA>2TDQz=1#pan`&5M_tg7X0)1tC_Gr{C$GmXH!EmXgowx!fm`tJ9o|N zVQFMa9+MMs8M+jiY<@p{{rG8^=ScFw7E6)NNRh)`2KO7aQ8SiuQLD`*U;D%# z{f!xJg1$O5>0@VH{)lH>k$BUKQn7m-_F3!6H-)o)LA1$No(Ed;i=syo_1O(J2~zpa z^JQ848DETdcXkg>cI_IbXld96e(6W+$;@t**O!Qo(F~f9%UXDq+#>10u`U4*^~rwn zwdaPVu;8}3;Kpq*vt(zmTI4Y)v~tjKQ>W&YcxqWe2EC+~ClFb+9jWg{6?LSNpkrb> zxM6;#G=`CxeX_;gdFI44vnuGU|lyOouJ@ z0s5M?U`gB6Fh%KkE1*@<9uR(kM#?TzYN{}8#WnEa2QMb^8=IURGrB^rToX!>2&Evv ztlv^*osJ1DQ#@2oY2Z&&oq>X4FWrhk&-xrvs8Xj0t6*I^BZt_0anX!ccwJ_dMG%ix z;H<=!5E1j5hfGHoV}A1k~^4CyiIgM;2Ca#*b$6RYlgS5Ud2Q zmFR4Cml*NFh#E)7{~SV2LDS}QH3B(bV6{~8nlB*fM?B0RF7NhdQCV}N?pKxTPvO6c z2)3m#dwM9(dFi|QU0r#oPBD5m&jITjpS>ba-K4tw%YK>V=f>=yzy?bxnXy>K$3=Xy z{O*$KQOt`X0&a9jUN0(GSS~u3aV123QF=m zCx<|ck?cq&P{H9<+sA2SUnp$v;F$96+qk%29WrFSWwD~(?7^OIDzs&+@tyz5$=Q2~ z1$#I+-l9(2T^T?LygUka-Dyn#O?Hd({UQVQ0nI_^GV*}*dPE3CtPV>}R8P3y7pHb} zio%UUIu9LMqJx!fqwiKxcceyQL(>-hIC(@^kmOq}|-)lK0W+r^Fmn`dCKmGinTv9K<%{`kV!0A&l&lGPV3%|J-QZ3G`Zpn5x#B4+u zMAX%rhJpL|g=)uQ1>4FdsUppbIb;BiFKP=hwqQYUR7dcto5yB_&MIpincolKNep zh}%Tfphcqg*GXxiv1kX_st zhx0py@b}pWN0UF^x`#+UIlTDYWDPxIpS)G0GZf|>tvgu#PJV^U9d*0?0{^O^CBHfs z&8Pv6Q@Q$q!n$HniXiiY84-WJf3%_W1EIkPDG&>X-E;Y}<7a5g?|P48BE9zYPM5PD ztwq4CVR^uF_Gj?i#%%=F9=~&tCVf&DiToqql*B~J`|BQo3$5Bg0f(hw3_QKMUK}W= zPR$0H0{uEw2;&wM(mow@-~b)~R1^%H5)a6PJ|h?%1(gJ)>yg7yloE^J-J%TR15RD4 zNh6%tKAi}Q6cqGp%Cs7`lI_GJ>ziaQR-WB3>f4jI*pIGRGURQ8QfVp&|AJmxu!|U} znDF7#1xZ|*Xf3-fk{c~U;saIZ#dda+HW3%cjDZCSy3f=_OBWo`?bh}2@K7wxHdsw? zm6-2jO)1ec><%)~V#g)Q9pz?srDJ<>eY4v81&tU)#P9xJgW<-r!&#j8d(I)Z?r(v! zqgLh8D9E9qe9l2o99|}>9rFlZ>d=x+C?{^XP&l}Qu`d$u!imrsuXx_fPo&NIS%)Dr z%)ixBp2fvlE_)$&PrW89>`eKY`|;klxIkA8U_gKJHU)*;b6aGr;39NRlqNJ%sG`6* zgSa#S4@UP~Mud4_I`U5bY2d-QGBIr+GInl%311VV*&&G(bz(dL8ySo5MVLHCUT@{L za|JP&uh3<=kX=Gje9uuJVB;AtS8(U%a^>csVf0itxGNhP;)2@Q_1aZzqbTW1S)5&% zxIyl-G!VBZ4d=;`l~&%?T8e7dXR>8Tj7bod^jJ2UU1tZ4m=3Di7rhhd>IX;Z2j^H? zAb%6^6cO;M2b^I|E|q|^G68a0qA4LztSHF(*hnkVFRG5Yqzf9DHT69CNAYFtxyir zym@b_#}kB|uFVynNOw?Cv*s}L6qxWK##6hYu5yz6py- z<%}LN)G03Lr;rz-LPXyNfrOgknhHX2$x=uNB9}};w5h1GDH|Se!Y9hXFu+iN3O7}n zH%ftDUal`ARQB^4jMVm(&PbEGLusc#73|@Ev{x8lj_yLGMYYZq%UV)^_;S|gw|(ys zYEI7l9pa#)(e#*MG|!=z1Ixk{=^-Xuinq_^*=r({fmvigUOSCiW9{_|#_iTCd&I_` z(a-G0Vgafa%eqi_ztFj%?~(>Z-Uh}@7+sA;KGMmC17%paF1gqiH>&4%3iQ&)+;r3H z><&^k_kJh)A?LOS@p6sI74rrT3JxA5zD@r3sq+1uanTsJw^00?&6+|A<7@6+IvyH$ z{m+U;-5gjdR`5+GN@U(Yfz#&0GkNG7K$-)~^yImIH3E*rh0b zk23|mubOxZmSr=pzF%#^v04mW1i*ZUN_Cfd_at8M$RRO`$UB$gVG+bk&%a>ti8vP1 z0ewbYK^#GzF#!DmLJFb^@$B(T-l%UD8zBIHzz_$8`~_K-*@}12?LK&pXvRy3%LpV- z&DKC~=u2?qQkKe^IqVRl2(devaSP1ke_QxCj^DXjw z$PaAC3^*W7xF7MJ_g)J6{i1FVX-{#bAIh?4 zAkR$&Cz4ErN4wL078oqsV^##+YueD|v_)S)1bc*p2#w&U)IqQ$Vi%N0jlO;2J)EU9 zvIF_W9;rPiP8^7^aL=qmiP`_C=xGdL#Ft(RVkeIAj>&i%hCl`B@M=n1S#G`G5~R_)W+c=V$VQ{h9T{X$CEy815eJ zwPg35Gx{r2YnMO_hMd}=tenmvy&vXyk0q}yaZ{ulbPxm^2rM8?NE4tjB{>a0gf>1T z=pI0q7qI&*(H1>Eh<{K~FuWka0U6}}4$`#d1(7sJbY z%0)gW-54TyNH1k;P4HtM;8JPLit}^ zCW)wpGXnXKMaP8?79^je7eMEl2cM1^~ z&Uz#2*0MBBM+oDZCALh0Y6ye8(+eP5IE`sx0P6VRUBM7>${f8oN!!5dIZ;>-K7-3!jmZy?yx^^VW=W{`$s&MZl$}4k$7?IdNT{5daMq#RZ!u3I#9c~Jxuo&E z(6fC}xiln!_=jMGf!gVpe8wPWF$EJ?YcX{z@L9ay8Q-@m`vAcYuQ*ty$b!2udjpFw z&CB6$Al|G5LQty+-&#YW_x!9Xjz}9t<^cNwQVcX8E4D%2z*RUSdqhWFqFD#HKH#iiY+CFJf>bC0ELsi>5#uwHs2lE@Oz2bGXLqP6hiT90dWP&uVO9{da*8EYG+YsR$xx8-RG700m?M8Byu6#* zm0qn%z%Ixx!1N0T+t*{jb&oz9>=YQ0Me0KzyMrWAm$Cj?-%aWrsnor zE96RbFqeGfx1wYt+KUkX?;tESAJ-_Tu!ZS z$m+ezndP*|@9W|!sE$coL636v5O&T0+#g)|0(q{qfH43i*HV5qDsPsN{Qm2dj5Ge) zI!)5|t2^>v!b<(`tW)8MP+kd8AX!hotuL3v2ETJfQJ=k}EJ?|He_bbCKGybHock}m zy*=b{z2){h+zLKIy}uj1bBp}Id&ikm4n+DI7Ii!*bD}*S~;C<^mTFt4qRqfkkUm*zbOb(otVagie`lYWoNP1of6Rv-$~ z6A|+fIhpV(09~bk$t*ao4e`r4b}~Z74mI!Qj2&n zi6U`rUJiyitT(S3{Zsqt`>UAL3#@k>*$lNvPRMWgQ%+DI*0CS)B*-fSF{4QH%!hgS zJ1`N0kesA$n!Vx?<OkqA&zLj zRRAfeU$Z^(O^@Yjg9zcH-Ai^7l)&o7A3=D_2T2?EA*~ug|KJCK#7KV4A2x$0J$IwHD`mF& zr;C9u+oY{a`X50sR(te%? zFEhT@a+sw5X(9hToc%7m+kAwGDxL~NC(V`ic>EW617A*L7#O>f;Y4-tS$?vvF=={( zlRXS0O^^=QlMNd{W*2;-Va<{|U8MVKX0`B=F!ykxj6*7q@f<}${{wf=W%|!iS&-ym zI)^|EA!gTH^)=vCRdAu2Yo!C~y)qt6xKvyR zjR3iClO+zcK-L9U-}->h?32a;=Vm25TOecpF|Opp;WQVnnWKlsobD+Ql?vBz-n*966`Mmp*K%qD0e-f)0(i4q-6(L|-A!&nFx!-99Z3JL|D~ zTFaz4t^AJLtJ20U?6&3njY}KOA!bMkTgchV@Q8-H>MmoUAQ8ne&sWD-37+07^KYu zRu$c5OTI1wqv3wm#76oT=RV5N#NV;rPb}8DkbVvajm@2>@ITs~eI^(bkA@z697>x& z51;Dk)_9YPA|K>WyrX|b8UV7gtAqWu+s%%q)#n9RZZ;36U#F`zLNV@gT0+f{jy`~` zzdL#p>1mp9A|_>D`EFMy&3kaTX*aqkl-hEybG+{>cnf3_ZIz4H?IP*A_NkM2kLyjk zC-C(heQe8`og(#W#=dwKI*!@zS%XiR3$0nbliYQ%4eA;8@hc%`-17j>gMN zu68U7#YlnZKboI+-(5;}VzX11?`o@x-Ua2R*1~Z!uB@~%X4ulURww6V5>!qx_d|25 z!L^5J%1JjQ)itfj?)l8#e|>XGaaPq7XNvc8PpQIab!u9#pJOq_+Gs!~k4-~9>_FbV zF2CMP*1{vJEk7bRmZ{aQs11N=VGaF?xA_}OV?j+>b9Ii2jr<9gmCk|9T2pNiUN)KKU5vpP=a~8!W>`(-BJ67HV(fD4eC!(R66^}>0xC6l4R{rJHFza- zs%P3~>KhDy41aX*n2i{Nm|65v8Xp=TDh1^|ns(ZD>UJ6hjjSRrzf8 zLxdqn)vbxI>{t4zaUH)?x0AGEJE$4Mh+#-2py^lgsCFH_V>&1qgM>juwV~Nr%2mdd z=cRd_uwy?MFsK{DiQ!0PpxIgCrG6c=V?HPwgN4CJbx)n6$ye&7aUHi~J*XN(iJ?eE zsL5C2rFI>)V>~Dt(-p%X1BHP^KwV_ zF=!tXwWBdeACrl(iq1*hOyi)ome*?FoNW@jqcg}JQ;DHTU8AO#->T>QWk+R@JSG+c zi<&`AFOSQx{^K9N^~&|a&N(}JgWNF<7^fJP)Dvn|s#a&r@%$zA!)*5%Lxi(SrntUx zris@7qfjG%>bL3FK)KsQ>o?|c!IGzsw+R^sM6>^&!vCzh!Yt2QVm-`uo>4+D+i3dL zLvA*~dZqq1!F12uS<}(Jk;T1ESRVVD&Uw=jVBX0VqiMz#1xnr37NRLjM}q#>w`U>Q z&MH4E=B6mvTP=(hnsV3+y(9Bq;h0MMbACB2iC<;MuUTG18_Kok*T>GFq^Xpurj(-^a7OE*mBY+=Rb=2w#upDMF{q2hmq;j+mZQu$*>bMYnGIGkJbY6~s0$xEd|JkNrx1~hqI%imwzI@l~)U@2r;82Oa zjE*MdN8VT8@krrgwXchQT&Xg}PL@$J2NM=*sx;BVsO3OU3Z-i`{KP>OW;HZITR8$z z_L~_=A%w2GWF;_~p6mbzoc+r5dF8;lT$Asvr<^C6Cs>3pUvveP1yux5pS1>9sK1#J`ET(HB`!VJ+z!Fouix^=G!NA@E@s0YW+9_M(Cb2jHqzTkIu~$4pL0XevXN)-pfW5{>s@Y|r&+GqdTV|{ej-%@$LX}IrO-LBwYJRm-1fxw^p!!@%k72rIsG{Wo5=JT zyqnHcm?@8n&+RGgq3zl2@i9s*KGa&Z=a?J&7B+Z^>tgoB4n+=mHKjF$%}R?m7K>L5 znyQ-DOKEc$AKy@!cW$XT=!@vf=?|D<-7sJ&9o{Zk*q}8fuLxxivrg_WaL+Bz`JB+5 z$T6zHR^N)K=CPJF8CdZ&M(CV}>y-_`88bJl8%!x?FpOKvimGBy!u4P)2P3Z25 z^d7a%&o^*^vVvBmE`szO&49B*Zh=$*Yi;O}HGui`@M$vS*?Y7y&yTSU^5m4AKImD= zTg|Z|eG&cr)uGh+RE@D5`$YQJ)u#f-c-1mJMr)9{by-{}_uEfHqWa!vW+!Bf<@|0W zlV>~R;@|5h3{>ux&&1sK_6Z&_R#dq=mtoX+H>&98BW&cGZax(R%6t^5_vEhEq^Wm< z-NsQwdEV26xqT$V0arE6eR2^OQ^Q~5`s8YB(Cp|-I~k^iaG$+-P5%xlYG zHh)TW=L>?j1=t0=Qos)?Lj!%M7_|MwEw#f3qc693&ze_ok2o&@eceR8NL#*6;4k07 zHg}ddmjvJugKK*=m)^-AL5Br~?=81fuV5azj3aK9`{WKquK->|oss@f+hAMzSBTA< z5f7m)J(*kakK7Zd*ZNtDTbjFvJhcNY9tMz%`G#?m&ITYaJ-1wM`1kyHf|K5muWZjB z=ftlYvMF~gxf6#c-3ViIxA|ghiF#iNA(4VR+q)h+q4=N)qjZnX5-Oc85-Z&i0)=)Zrw()y}yXx9Cp+)N-ufaM1I798XDC$12 z30+D3z*-3x^`IQ1vv>7kyCMDATVeglFWez6+_^8@aqjhD830(Ju|45ipn9GH7cJZt z84c7Htqsf;5e>u^m97RqIV|<_(p)8gi`uqr6Syry`UK_9nr-tJKct%QbnWZsapuG4 z$0|wZUn*}SIAXN78C=sPKex%Q4_8p-YYweCf!C=Q|!a(p@(7>;{dZD4Cc-D2IWzj(w3xqj}iFq6d33q7g0IFO} zH@^}{U(y+`Bzqy z71teP{KbpB8~${ao0M_aXlOeQvO8`it_vr)r1wCpTPICBQ9x6$AF zt+UbN94@5%MFpvdP{w|Wj^*WoGHF1z@A>24)6wgAza z1R<(0vbhQKh4I*EX1hqpN^z%KERe~n*GPXV7i-|S7o4(}=v6Hpc|`VTrVEIDIq*`L zd$I#Y?R~w3)@7R6iXsltt3|nRd7nT)csdz-o^6dToA*v!br~Itr$#xx0D(=;*LBdDj-Ny7pJwE@j-RLvy`X z$J1@BO-kYWkGtn{cRY^AZ_k(u7V(6K5Y2X@C%SrCx@hN}ozFF~%}Ax_hpB22w5~1{ zGFRnA-)KtTi0rhv+SAb1ab8Qm!LClfhn=>(Ka2l*e+w-YPNBV4{&m=0@%~iseo1ui z`8_D`ZPHYb`R7@r_jA%-Kw_TZW= zGbdCo6gR-fmEuzvOOZf`g3!4x8K7@Zu z_zGkR;R5O**teI#38@ut4Z*vh^XfNVPT>D6tOhkgV5$N{u=mtKVlRO7;~Hs!!P^EI z|Nja9Ui=L2!SUuk48b+rHE3L`TE>)&qjD7iSAxtp512&kGGJE%HZxB-KzTh0=gZV!|+ zcQAJ`c5`(3*Q0;w0p+YsT#Q}*W%qA8|L>7{89V*=k$yb*h?MDHk$x~df5qhJqUPvm zCm?Ta>f-47CtA&qIDqs(IdM^XB^7acCMGs6Zh8$41}0ztP+VP382Irw0*cD3N~;1@ zoy<*v#tvpcF;yj?93SKVZuBFFzeVO^ANdntVPa;YXJ(;i;!tB|qT=56%DgKf?LnmizCv?_aWye)U&2{_c5y zxWD_Rxx+`J@%*bRevqziA9=C=yD|T#U;p>u?SJ)WMH3rUH~SB4cbAXt$;HH|0AyzV z8`hnTo#nrJwO7`-=BmRQ2l8vk8`vhCW~VA>90WdZCVKQL8^=nc1mT|kipJI%ByF4g zTeoFI5gD)ToUq{y6L05FoQZhS8dMeR{GzIGs9OW@{4|#WObKuDR8$Ghq`E$>b8wG1 z*CwT#f%Uow8Y zyGL)UxQtNCdRC(-U*kff1fDfIT0CDXz%#?!U-}f6npq`M+`V025JFRMfM6YgQ*~zb zEcyrGLL0P<2&1LJ)ms72WyGr1m4L5hiIfwuelZBEgZNAA$=St?s2&1&i3<(uC-|o@ zZ@#fny$FWEoL#M*Wivkp4E<8K28L_}2J-4m@n19nPnI3J51V!$D01HKfC$-qa69(O zc8gEO{N#DYF5&vKte!IBf-VcD_i35K9!Fmky0qv5qB4Ko-}EE3ULG0>44%mQ61<#v z`L^JMl^eL9zJbz<#k9-`XK0&TewScq$qfF)HMQsGiRJw({hqX0?N`+~sqF9j-$zf& zu|$chs~0Yd>XV$6=k2R{nt^Vah4P#6x8^OUk-M25k=^QD4!2soP@}(`W(}(h2}Q%G#E zkLO>6USryBlD4ECv7)9c^QfEj+3vzrfY=TNY%mQiWaw5EzAVHK1n4wyt@a>(`|^0C z2=@Kh&&@TqA%l|)ju3s)c~y97cZQ2idgC~WTL7#X1+qO(+7&L7I$Au5gZt2^?(Y7jR(Yfssburw~ww5tu5dD>MA7473PzRih!$ z5y)|G77%F`CM}gZcf^EA9=g*#b};^=S%kf#I36sR?=YS!r))M&H$&I2c
  • x#e1h{baLP@AcAEbh($8fkN8HUQ;0!C|bj-I? zC3xCvDY2pY6K-#iix|4&WDlAW_cl$v;i`yLk&4OBOGEeDv-(0OzCASLaHO54{V;o^ zthF@f|61vhBCD5N6O1S4sl6{^dh7Az=!_-oQ(|;y&b??e*(!a1$Pwp99_Le^g-+9c zym8ag)duUk+MoVelHG9NjqTzWQ$M|47x4Z)*Ov9@~|3kA2U z#Yg|$S0(-X?cF@lYKD*R;^rQGxTval)0%USpDWI7o2#mH-fLQihgCr%yNTJt{o>!O zH!S?gmvbQe%|$WWr#;K>%$K*hHf{UcQvbixS>{dbWEU%c>~K-udu@TVtd6bpqvQ8K zZe3R=*AOk6yDoq6gsX+WU#7lUm(Qj(`PGW}iN_g2N(_4WKb%VX;LWuE^q~sbkoC#l z_ZhaZGW_57tc_oHnN_a+^3G4C!E?)M`8VF=y1DaB-r{3lZrk|BFSg~o9RBk_#uocs z7k6A+S0VFCy;A4yndGILjx)Uf9I?`%GH2~9n`;J7_8s3+bpGI%uIVQ)#siCyJmKHf zLg`n#-~QZYbu$0YtGn~-Ie$)G(sfwhZFBj*{mRcTV!PkN$O3VbM{s6Us)CUvwi`Xb zl|n>NYMQ=hUP@|3v;k0EtbTa3p@NZuVJxg>ur${X%FizWiWw*b0ad2uD;PqUF3~p0 zMyAQ8rpbn;X~}6xiK(du1}TXarY5Gz2IgsLsmVrmHl~*5i6+U(KygchB(o#~qtrA5 z!?e^?qZC5}6Z14vyIACEN3>@zuLFaG%l)6rCrwbuYGu_?+_qtktjeNIje;g#+&}g` zdU`Lmkb%*5(U&Px7CtQF@43)nvM1wSO}D9h#@ai=%2%xx)qa}isGE^8FFXFt&aL+( re}uiLx$yNPvx6y58kUYuaS5JcjE;B$L(NY literal 0 HcmV?d00001 diff --git a/platforms/lpc17xx/CMSISv2p00_LPC17xx/inc/LPC17xx.h b/platforms/lpc17xx/CMSISv2p00_LPC17xx/inc/LPC17xx.h new file mode 100644 index 0000000..377fdf2 --- /dev/null +++ b/platforms/lpc17xx/CMSISv2p00_LPC17xx/inc/LPC17xx.h @@ -0,0 +1,1035 @@ +/**************************************************************************//** + * @file LPC17xx.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for + * NXP LPC17xx Device Series + * @version: V1.09 + * @date: 17. March 2010 + + * + * @note + * Copyright (C) 2009 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + + +#ifndef __LPC17xx_H__ +#define __LPC17xx_H__ + +/* + * ========================================================================== + * ---------- Interrupt Number Definition ----------------------------------- + * ========================================================================== + */ + +typedef enum IRQn +{ +/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ + +/****** LPC17xx Specific Interrupt Numbers *******************************************************/ + WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */ + TIMER0_IRQn = 1, /*!< Timer0 Interrupt */ + TIMER1_IRQn = 2, /*!< Timer1 Interrupt */ + TIMER2_IRQn = 3, /*!< Timer2 Interrupt */ + TIMER3_IRQn = 4, /*!< Timer3 Interrupt */ + UART0_IRQn = 5, /*!< UART0 Interrupt */ + UART1_IRQn = 6, /*!< UART1 Interrupt */ + UART2_IRQn = 7, /*!< UART2 Interrupt */ + UART3_IRQn = 8, /*!< UART3 Interrupt */ + PWM1_IRQn = 9, /*!< PWM1 Interrupt */ + I2C0_IRQn = 10, /*!< I2C0 Interrupt */ + I2C1_IRQn = 11, /*!< I2C1 Interrupt */ + I2C2_IRQn = 12, /*!< I2C2 Interrupt */ + SPI_IRQn = 13, /*!< SPI Interrupt */ + SSP0_IRQn = 14, /*!< SSP0 Interrupt */ + SSP1_IRQn = 15, /*!< SSP1 Interrupt */ + PLL0_IRQn = 16, /*!< PLL0 Lock (Main PLL) Interrupt */ + RTC_IRQn = 17, /*!< Real Time Clock Interrupt */ + EINT0_IRQn = 18, /*!< External Interrupt 0 Interrupt */ + EINT1_IRQn = 19, /*!< External Interrupt 1 Interrupt */ + EINT2_IRQn = 20, /*!< External Interrupt 2 Interrupt */ + EINT3_IRQn = 21, /*!< External Interrupt 3 Interrupt */ + ADC_IRQn = 22, /*!< A/D Converter Interrupt */ + BOD_IRQn = 23, /*!< Brown-Out Detect Interrupt */ + USB_IRQn = 24, /*!< USB Interrupt */ + CAN_IRQn = 25, /*!< CAN Interrupt */ + DMA_IRQn = 26, /*!< General Purpose DMA Interrupt */ + I2S_IRQn = 27, /*!< I2S Interrupt */ + ENET_IRQn = 28, /*!< Ethernet Interrupt */ + RIT_IRQn = 29, /*!< Repetitive Interrupt Timer Interrupt */ + MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */ + QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */ + PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */ + USBActivity_IRQn = 33, /* USB Activity interrupt */ + CANActivity_IRQn = 34, /* CAN Activity interrupt */ +} IRQn_Type; + + +/* + * ========================================================================== + * ----------- Processor and Core Peripheral Section ------------------------ + * ========================================================================== + */ + +/* Configuration of the Cortex-M3 Processor and Core Peripherals */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + + +#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */ +#include "system_LPC17xx.h" /* System Header */ + + +/******************************************************************************/ +/* Device Specific Peripheral registers structures */ +/******************************************************************************/ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/*------------- System Control (SC) ------------------------------------------*/ +typedef struct +{ + __IO uint32_t FLASHCFG; /* Flash Accelerator Module */ + uint32_t RESERVED0[31]; + __IO uint32_t PLL0CON; /* Clocking and Power Control */ + __IO uint32_t PLL0CFG; + __I uint32_t PLL0STAT; + __O uint32_t PLL0FEED; + uint32_t RESERVED1[4]; + __IO uint32_t PLL1CON; + __IO uint32_t PLL1CFG; + __I uint32_t PLL1STAT; + __O uint32_t PLL1FEED; + uint32_t RESERVED2[4]; + __IO uint32_t PCON; + __IO uint32_t PCONP; + uint32_t RESERVED3[15]; + __IO uint32_t CCLKCFG; + __IO uint32_t USBCLKCFG; + __IO uint32_t CLKSRCSEL; + __IO uint32_t CANSLEEPCLR; + __IO uint32_t CANWAKEFLAGS; + uint32_t RESERVED4[10]; + __IO uint32_t EXTINT; /* External Interrupts */ + uint32_t RESERVED5; + __IO uint32_t EXTMODE; + __IO uint32_t EXTPOLAR; + uint32_t RESERVED6[12]; + __IO uint32_t RSID; /* Reset */ + uint32_t RESERVED7[7]; + __IO uint32_t SCS; /* Syscon Miscellaneous Registers */ + __IO uint32_t IRCTRIM; /* Clock Dividers */ + __IO uint32_t PCLKSEL0; + __IO uint32_t PCLKSEL1; + uint32_t RESERVED8[4]; + __IO uint32_t USBIntSt; /* USB Device/OTG Interrupt Register */ + __IO uint32_t DMAREQSEL; + __IO uint32_t CLKOUTCFG; /* Clock Output Configuration */ + } LPC_SC_TypeDef; + +/*------------- Pin Connect Block (PINCON) -----------------------------------*/ +typedef struct +{ + __IO uint32_t PINSEL0; + __IO uint32_t PINSEL1; + __IO uint32_t PINSEL2; + __IO uint32_t PINSEL3; + __IO uint32_t PINSEL4; + __IO uint32_t PINSEL5; + __IO uint32_t PINSEL6; + __IO uint32_t PINSEL7; + __IO uint32_t PINSEL8; + __IO uint32_t PINSEL9; + __IO uint32_t PINSEL10; + uint32_t RESERVED0[5]; + __IO uint32_t PINMODE0; + __IO uint32_t PINMODE1; + __IO uint32_t PINMODE2; + __IO uint32_t PINMODE3; + __IO uint32_t PINMODE4; + __IO uint32_t PINMODE5; + __IO uint32_t PINMODE6; + __IO uint32_t PINMODE7; + __IO uint32_t PINMODE8; + __IO uint32_t PINMODE9; + __IO uint32_t PINMODE_OD0; + __IO uint32_t PINMODE_OD1; + __IO uint32_t PINMODE_OD2; + __IO uint32_t PINMODE_OD3; + __IO uint32_t PINMODE_OD4; + __IO uint32_t I2CPADCFG; +} LPC_PINCON_TypeDef; + +/*------------- General Purpose Input/Output (GPIO) --------------------------*/ +typedef struct +{ + union { + __IO uint32_t FIODIR; + struct { + __IO uint16_t FIODIRL; + __IO uint16_t FIODIRH; + }; + struct { + __IO uint8_t FIODIR0; + __IO uint8_t FIODIR1; + __IO uint8_t FIODIR2; + __IO uint8_t FIODIR3; + }; + }; + uint32_t RESERVED0[3]; + union { + __IO uint32_t FIOMASK; + struct { + __IO uint16_t FIOMASKL; + __IO uint16_t FIOMASKH; + }; + struct { + __IO uint8_t FIOMASK0; + __IO uint8_t FIOMASK1; + __IO uint8_t FIOMASK2; + __IO uint8_t FIOMASK3; + }; + }; + union { + __IO uint32_t FIOPIN; + struct { + __IO uint16_t FIOPINL; + __IO uint16_t FIOPINH; + }; + struct { + __IO uint8_t FIOPIN0; + __IO uint8_t FIOPIN1; + __IO uint8_t FIOPIN2; + __IO uint8_t FIOPIN3; + }; + }; + union { + __IO uint32_t FIOSET; + struct { + __IO uint16_t FIOSETL; + __IO uint16_t FIOSETH; + }; + struct { + __IO uint8_t FIOSET0; + __IO uint8_t FIOSET1; + __IO uint8_t FIOSET2; + __IO uint8_t FIOSET3; + }; + }; + union { + __O uint32_t FIOCLR; + struct { + __O uint16_t FIOCLRL; + __O uint16_t FIOCLRH; + }; + struct { + __O uint8_t FIOCLR0; + __O uint8_t FIOCLR1; + __O uint8_t FIOCLR2; + __O uint8_t FIOCLR3; + }; + }; +} LPC_GPIO_TypeDef; + +typedef struct +{ + __I uint32_t IntStatus; + __I uint32_t IO0IntStatR; + __I uint32_t IO0IntStatF; + __O uint32_t IO0IntClr; + __IO uint32_t IO0IntEnR; + __IO uint32_t IO0IntEnF; + uint32_t RESERVED0[3]; + __I uint32_t IO2IntStatR; + __I uint32_t IO2IntStatF; + __O uint32_t IO2IntClr; + __IO uint32_t IO2IntEnR; + __IO uint32_t IO2IntEnF; +} LPC_GPIOINT_TypeDef; + +/*------------- Timer (TIM) --------------------------------------------------*/ +typedef struct +{ + __IO uint32_t IR; + __IO uint32_t TCR; + __IO uint32_t TC; + __IO uint32_t PR; + __IO uint32_t PC; + __IO uint32_t MCR; + __IO uint32_t MR0; + __IO uint32_t MR1; + __IO uint32_t MR2; + __IO uint32_t MR3; + __IO uint32_t CCR; + __I uint32_t CR0; + __I uint32_t CR1; + uint32_t RESERVED0[2]; + __IO uint32_t EMR; + uint32_t RESERVED1[12]; + __IO uint32_t CTCR; +} LPC_TIM_TypeDef; + +/*------------- Pulse-Width Modulation (PWM) ---------------------------------*/ +typedef struct +{ + __IO uint32_t IR; + __IO uint32_t TCR; + __IO uint32_t TC; + __IO uint32_t PR; + __IO uint32_t PC; + __IO uint32_t MCR; + __IO uint32_t MR0; + __IO uint32_t MR1; + __IO uint32_t MR2; + __IO uint32_t MR3; + __IO uint32_t CCR; + __I uint32_t CR0; + __I uint32_t CR1; + __I uint32_t CR2; + __I uint32_t CR3; + uint32_t RESERVED0; + __IO uint32_t MR4; + __IO uint32_t MR5; + __IO uint32_t MR6; + __IO uint32_t PCR; + __IO uint32_t LER; + uint32_t RESERVED1[7]; + __IO uint32_t CTCR; +} LPC_PWM_TypeDef; + +/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/ +typedef struct +{ + union { + __I uint8_t RBR; + __O uint8_t THR; + __IO uint8_t DLL; + uint32_t RESERVED0; + }; + union { + __IO uint8_t DLM; + __IO uint32_t IER; + }; + union { + __I uint32_t IIR; + __O uint8_t FCR; + }; + __IO uint8_t LCR; + uint8_t RESERVED1[7]; + __I uint8_t LSR; + uint8_t RESERVED2[7]; + __IO uint8_t SCR; + uint8_t RESERVED3[3]; + __IO uint32_t ACR; + __IO uint8_t ICR; + uint8_t RESERVED4[3]; + __IO uint8_t FDR; + uint8_t RESERVED5[7]; + __IO uint8_t TER; + uint8_t RESERVED6[39]; + __IO uint32_t FIFOLVL; +} LPC_UART_TypeDef; + +typedef struct +{ + union { + __I uint8_t RBR; + __O uint8_t THR; + __IO uint8_t DLL; + uint32_t RESERVED0; + }; + union { + __IO uint8_t DLM; + __IO uint32_t IER; + }; + union { + __I uint32_t IIR; + __O uint8_t FCR; + }; + __IO uint8_t LCR; + uint8_t RESERVED1[7]; + __I uint8_t LSR; + uint8_t RESERVED2[7]; + __IO uint8_t SCR; + uint8_t RESERVED3[3]; + __IO uint32_t ACR; + __IO uint8_t ICR; + uint8_t RESERVED4[3]; + __IO uint8_t FDR; + uint8_t RESERVED5[7]; + __IO uint8_t TER; + uint8_t RESERVED6[39]; + __IO uint32_t FIFOLVL; +} LPC_UART0_TypeDef; + +typedef struct +{ + union { + __I uint8_t RBR; + __O uint8_t THR; + __IO uint8_t DLL; + uint32_t RESERVED0; + }; + union { + __IO uint8_t DLM; + __IO uint32_t IER; + }; + union { + __I uint32_t IIR; + __O uint8_t FCR; + }; + __IO uint8_t LCR; + uint8_t RESERVED1[3]; + __IO uint8_t MCR; + uint8_t RESERVED2[3]; + __I uint8_t LSR; + uint8_t RESERVED3[3]; + __I uint8_t MSR; + uint8_t RESERVED4[3]; + __IO uint8_t SCR; + uint8_t RESERVED5[3]; + __IO uint32_t ACR; + uint32_t RESERVED6; + __IO uint32_t FDR; + uint32_t RESERVED7; + __IO uint8_t TER; + uint8_t RESERVED8[27]; + __IO uint8_t RS485CTRL; + uint8_t RESERVED9[3]; + __IO uint8_t ADRMATCH; + uint8_t RESERVED10[3]; + __IO uint8_t RS485DLY; + uint8_t RESERVED11[3]; + __IO uint32_t FIFOLVL; +} LPC_UART1_TypeDef; + +/*------------- Serial Peripheral Interface (SPI) ----------------------------*/ +typedef struct +{ + __IO uint32_t SPCR; + __I uint32_t SPSR; + __IO uint32_t SPDR; + __IO uint32_t SPCCR; + uint32_t RESERVED0[3]; + __IO uint32_t SPINT; +} LPC_SPI_TypeDef; + +/*------------- Synchronous Serial Communication (SSP) -----------------------*/ +typedef struct +{ + __IO uint32_t CR0; + __IO uint32_t CR1; + __IO uint32_t DR; + __I uint32_t SR; + __IO uint32_t CPSR; + __IO uint32_t IMSC; + __IO uint32_t RIS; + __IO uint32_t MIS; + __IO uint32_t ICR; + __IO uint32_t DMACR; +} LPC_SSP_TypeDef; + +/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/ +typedef struct +{ + __IO uint32_t I2CONSET; + __I uint32_t I2STAT; + __IO uint32_t I2DAT; + __IO uint32_t I2ADR0; + __IO uint32_t I2SCLH; + __IO uint32_t I2SCLL; + __O uint32_t I2CONCLR; + __IO uint32_t MMCTRL; + __IO uint32_t I2ADR1; + __IO uint32_t I2ADR2; + __IO uint32_t I2ADR3; + __I uint32_t I2DATA_BUFFER; + __IO uint32_t I2MASK0; + __IO uint32_t I2MASK1; + __IO uint32_t I2MASK2; + __IO uint32_t I2MASK3; +} LPC_I2C_TypeDef; + +/*------------- Inter IC Sound (I2S) -----------------------------------------*/ +typedef struct +{ + __IO uint32_t I2SDAO; + __IO uint32_t I2SDAI; + __O uint32_t I2STXFIFO; + __I uint32_t I2SRXFIFO; + __I uint32_t I2SSTATE; + __IO uint32_t I2SDMA1; + __IO uint32_t I2SDMA2; + __IO uint32_t I2SIRQ; + __IO uint32_t I2STXRATE; + __IO uint32_t I2SRXRATE; + __IO uint32_t I2STXBITRATE; + __IO uint32_t I2SRXBITRATE; + __IO uint32_t I2STXMODE; + __IO uint32_t I2SRXMODE; +} LPC_I2S_TypeDef; + +/*------------- Repetitive Interrupt Timer (RIT) -----------------------------*/ +typedef struct +{ + __IO uint32_t RICOMPVAL; + __IO uint32_t RIMASK; + __IO uint8_t RICTRL; + uint8_t RESERVED0[3]; + __IO uint32_t RICOUNTER; +} LPC_RIT_TypeDef; + +/*------------- Real-Time Clock (RTC) ----------------------------------------*/ +typedef struct +{ + __IO uint8_t ILR; + uint8_t RESERVED0[7]; + __IO uint8_t CCR; + uint8_t RESERVED1[3]; + __IO uint8_t CIIR; + uint8_t RESERVED2[3]; + __IO uint8_t AMR; + uint8_t RESERVED3[3]; + __I uint32_t CTIME0; + __I uint32_t CTIME1; + __I uint32_t CTIME2; + __IO uint8_t SEC; + uint8_t RESERVED4[3]; + __IO uint8_t MIN; + uint8_t RESERVED5[3]; + __IO uint8_t HOUR; + uint8_t RESERVED6[3]; + __IO uint8_t DOM; + uint8_t RESERVED7[3]; + __IO uint8_t DOW; + uint8_t RESERVED8[3]; + __IO uint16_t DOY; + uint16_t RESERVED9; + __IO uint8_t MONTH; + uint8_t RESERVED10[3]; + __IO uint16_t YEAR; + uint16_t RESERVED11; + __IO uint32_t CALIBRATION; + __IO uint32_t GPREG0; + __IO uint32_t GPREG1; + __IO uint32_t GPREG2; + __IO uint32_t GPREG3; + __IO uint32_t GPREG4; + __IO uint8_t RTC_AUXEN; + uint8_t RESERVED12[3]; + __IO uint8_t RTC_AUX; + uint8_t RESERVED13[3]; + __IO uint8_t ALSEC; + uint8_t RESERVED14[3]; + __IO uint8_t ALMIN; + uint8_t RESERVED15[3]; + __IO uint8_t ALHOUR; + uint8_t RESERVED16[3]; + __IO uint8_t ALDOM; + uint8_t RESERVED17[3]; + __IO uint8_t ALDOW; + uint8_t RESERVED18[3]; + __IO uint16_t ALDOY; + uint16_t RESERVED19; + __IO uint8_t ALMON; + uint8_t RESERVED20[3]; + __IO uint16_t ALYEAR; + uint16_t RESERVED21; +} LPC_RTC_TypeDef; + +/*------------- Watchdog Timer (WDT) -----------------------------------------*/ +typedef struct +{ + __IO uint8_t WDMOD; + uint8_t RESERVED0[3]; + __IO uint32_t WDTC; + __O uint8_t WDFEED; + uint8_t RESERVED1[3]; + __I uint32_t WDTV; + __IO uint32_t WDCLKSEL; +} LPC_WDT_TypeDef; + +/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/ +typedef struct +{ + __IO uint32_t ADCR; + __IO uint32_t ADGDR; + uint32_t RESERVED0; + __IO uint32_t ADINTEN; + __I uint32_t ADDR0; + __I uint32_t ADDR1; + __I uint32_t ADDR2; + __I uint32_t ADDR3; + __I uint32_t ADDR4; + __I uint32_t ADDR5; + __I uint32_t ADDR6; + __I uint32_t ADDR7; + __I uint32_t ADSTAT; + __IO uint32_t ADTRM; +} LPC_ADC_TypeDef; + +/*------------- Digital-to-Analog Converter (DAC) ----------------------------*/ +typedef struct +{ + __IO uint32_t DACR; + __IO uint32_t DACCTRL; + __IO uint16_t DACCNTVAL; +} LPC_DAC_TypeDef; + +/*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/ +typedef struct +{ + __I uint32_t MCCON; + __O uint32_t MCCON_SET; + __O uint32_t MCCON_CLR; + __I uint32_t MCCAPCON; + __O uint32_t MCCAPCON_SET; + __O uint32_t MCCAPCON_CLR; + __IO uint32_t MCTIM0; + __IO uint32_t MCTIM1; + __IO uint32_t MCTIM2; + __IO uint32_t MCPER0; + __IO uint32_t MCPER1; + __IO uint32_t MCPER2; + __IO uint32_t MCPW0; + __IO uint32_t MCPW1; + __IO uint32_t MCPW2; + __IO uint32_t MCDEADTIME; + __IO uint32_t MCCCP; + __IO uint32_t MCCR0; + __IO uint32_t MCCR1; + __IO uint32_t MCCR2; + __I uint32_t MCINTEN; + __O uint32_t MCINTEN_SET; + __O uint32_t MCINTEN_CLR; + __I uint32_t MCCNTCON; + __O uint32_t MCCNTCON_SET; + __O uint32_t MCCNTCON_CLR; + __I uint32_t MCINTFLAG; + __O uint32_t MCINTFLAG_SET; + __O uint32_t MCINTFLAG_CLR; + __O uint32_t MCCAP_CLR; +} LPC_MCPWM_TypeDef; + +/*------------- Quadrature Encoder Interface (QEI) ---------------------------*/ +typedef struct +{ + __O uint32_t QEICON; + __I uint32_t QEISTAT; + __IO uint32_t QEICONF; + __I uint32_t QEIPOS; + __IO uint32_t QEIMAXPOS; + __IO uint32_t CMPOS0; + __IO uint32_t CMPOS1; + __IO uint32_t CMPOS2; + __I uint32_t INXCNT; + __IO uint32_t INXCMP; + __IO uint32_t QEILOAD; + __I uint32_t QEITIME; + __I uint32_t QEIVEL; + __I uint32_t QEICAP; + __IO uint32_t VELCOMP; + __IO uint32_t FILTER; + uint32_t RESERVED0[998]; + __O uint32_t QEIIEC; + __O uint32_t QEIIES; + __I uint32_t QEIINTSTAT; + __I uint32_t QEIIE; + __O uint32_t QEICLR; + __O uint32_t QEISET; +} LPC_QEI_TypeDef; + +/*------------- Controller Area Network (CAN) --------------------------------*/ +typedef struct +{ + __IO uint32_t mask[512]; /* ID Masks */ +} LPC_CANAF_RAM_TypeDef; + +typedef struct /* Acceptance Filter Registers */ +{ + __IO uint32_t AFMR; + __IO uint32_t SFF_sa; + __IO uint32_t SFF_GRP_sa; + __IO uint32_t EFF_sa; + __IO uint32_t EFF_GRP_sa; + __IO uint32_t ENDofTable; + __I uint32_t LUTerrAd; + __I uint32_t LUTerr; + __IO uint32_t FCANIE; + __IO uint32_t FCANIC0; + __IO uint32_t FCANIC1; +} LPC_CANAF_TypeDef; + +typedef struct /* Central Registers */ +{ + __I uint32_t CANTxSR; + __I uint32_t CANRxSR; + __I uint32_t CANMSR; +} LPC_CANCR_TypeDef; + +typedef struct /* Controller Registers */ +{ + __IO uint32_t MOD; + __O uint32_t CMR; + __IO uint32_t GSR; + __I uint32_t ICR; + __IO uint32_t IER; + __IO uint32_t BTR; + __IO uint32_t EWL; + __I uint32_t SR; + __IO uint32_t RFS; + __IO uint32_t RID; + __IO uint32_t RDA; + __IO uint32_t RDB; + __IO uint32_t TFI1; + __IO uint32_t TID1; + __IO uint32_t TDA1; + __IO uint32_t TDB1; + __IO uint32_t TFI2; + __IO uint32_t TID2; + __IO uint32_t TDA2; + __IO uint32_t TDB2; + __IO uint32_t TFI3; + __IO uint32_t TID3; + __IO uint32_t TDA3; + __IO uint32_t TDB3; +} LPC_CAN_TypeDef; + +/*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/ +typedef struct /* Common Registers */ +{ + __I uint32_t DMACIntStat; + __I uint32_t DMACIntTCStat; + __O uint32_t DMACIntTCClear; + __I uint32_t DMACIntErrStat; + __O uint32_t DMACIntErrClr; + __I uint32_t DMACRawIntTCStat; + __I uint32_t DMACRawIntErrStat; + __I uint32_t DMACEnbldChns; + __IO uint32_t DMACSoftBReq; + __IO uint32_t DMACSoftSReq; + __IO uint32_t DMACSoftLBReq; + __IO uint32_t DMACSoftLSReq; + __IO uint32_t DMACConfig; + __IO uint32_t DMACSync; +} LPC_GPDMA_TypeDef; + +typedef struct /* Channel Registers */ +{ + __IO uint32_t DMACCSrcAddr; + __IO uint32_t DMACCDestAddr; + __IO uint32_t DMACCLLI; + __IO uint32_t DMACCControl; + __IO uint32_t DMACCConfig; +} LPC_GPDMACH_TypeDef; + +/*------------- Universal Serial Bus (USB) -----------------------------------*/ +typedef struct +{ + __I uint32_t HcRevision; /* USB Host Registers */ + __IO uint32_t HcControl; + __IO uint32_t HcCommandStatus; + __IO uint32_t HcInterruptStatus; + __IO uint32_t HcInterruptEnable; + __IO uint32_t HcInterruptDisable; + __IO uint32_t HcHCCA; + __I uint32_t HcPeriodCurrentED; + __IO uint32_t HcControlHeadED; + __IO uint32_t HcControlCurrentED; + __IO uint32_t HcBulkHeadED; + __IO uint32_t HcBulkCurrentED; + __I uint32_t HcDoneHead; + __IO uint32_t HcFmInterval; + __I uint32_t HcFmRemaining; + __I uint32_t HcFmNumber; + __IO uint32_t HcPeriodicStart; + __IO uint32_t HcLSTreshold; + __IO uint32_t HcRhDescriptorA; + __IO uint32_t HcRhDescriptorB; + __IO uint32_t HcRhStatus; + __IO uint32_t HcRhPortStatus1; + __IO uint32_t HcRhPortStatus2; + uint32_t RESERVED0[40]; + __I uint32_t Module_ID; + + __I uint32_t OTGIntSt; /* USB On-The-Go Registers */ + __IO uint32_t OTGIntEn; + __O uint32_t OTGIntSet; + __O uint32_t OTGIntClr; + __IO uint32_t OTGStCtrl; + __IO uint32_t OTGTmr; + uint32_t RESERVED1[58]; + + __I uint32_t USBDevIntSt; /* USB Device Interrupt Registers */ + __IO uint32_t USBDevIntEn; + __O uint32_t USBDevIntClr; + __O uint32_t USBDevIntSet; + + __O uint32_t USBCmdCode; /* USB Device SIE Command Registers */ + __I uint32_t USBCmdData; + + __I uint32_t USBRxData; /* USB Device Transfer Registers */ + __O uint32_t USBTxData; + __I uint32_t USBRxPLen; + __O uint32_t USBTxPLen; + __IO uint32_t USBCtrl; + __O uint32_t USBDevIntPri; + + __I uint32_t USBEpIntSt; /* USB Device Endpoint Interrupt Regs */ + __IO uint32_t USBEpIntEn; + __O uint32_t USBEpIntClr; + __O uint32_t USBEpIntSet; + __O uint32_t USBEpIntPri; + + __IO uint32_t USBReEp; /* USB Device Endpoint Realization Reg*/ + __O uint32_t USBEpInd; + __IO uint32_t USBMaxPSize; + + __I uint32_t USBDMARSt; /* USB Device DMA Registers */ + __O uint32_t USBDMARClr; + __O uint32_t USBDMARSet; + uint32_t RESERVED2[9]; + __IO uint32_t USBUDCAH; + __I uint32_t USBEpDMASt; + __O uint32_t USBEpDMAEn; + __O uint32_t USBEpDMADis; + __I uint32_t USBDMAIntSt; + __IO uint32_t USBDMAIntEn; + uint32_t RESERVED3[2]; + __I uint32_t USBEoTIntSt; + __O uint32_t USBEoTIntClr; + __O uint32_t USBEoTIntSet; + __I uint32_t USBNDDRIntSt; + __O uint32_t USBNDDRIntClr; + __O uint32_t USBNDDRIntSet; + __I uint32_t USBSysErrIntSt; + __O uint32_t USBSysErrIntClr; + __O uint32_t USBSysErrIntSet; + uint32_t RESERVED4[15]; + + union { + __I uint32_t I2C_RX; /* USB OTG I2C Registers */ + __O uint32_t I2C_TX; + }; + __I uint32_t I2C_STS; + __IO uint32_t I2C_CTL; + __IO uint32_t I2C_CLKHI; + __O uint32_t I2C_CLKLO; + uint32_t RESERVED5[824]; + + union { + __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */ + __IO uint32_t OTGClkCtrl; + }; + union { + __I uint32_t USBClkSt; + __I uint32_t OTGClkSt; + }; +} LPC_USB_TypeDef; + +/*------------- Ethernet Media Access Controller (EMAC) ----------------------*/ +typedef struct +{ + __IO uint32_t MAC1; /* MAC Registers */ + __IO uint32_t MAC2; + __IO uint32_t IPGT; + __IO uint32_t IPGR; + __IO uint32_t CLRT; + __IO uint32_t MAXF; + __IO uint32_t SUPP; + __IO uint32_t TEST; + __IO uint32_t MCFG; + __IO uint32_t MCMD; + __IO uint32_t MADR; + __O uint32_t MWTD; + __I uint32_t MRDD; + __I uint32_t MIND; + uint32_t RESERVED0[2]; + __IO uint32_t SA0; + __IO uint32_t SA1; + __IO uint32_t SA2; + uint32_t RESERVED1[45]; + __IO uint32_t Command; /* Control Registers */ + __I uint32_t Status; + __IO uint32_t RxDescriptor; + __IO uint32_t RxStatus; + __IO uint32_t RxDescriptorNumber; + __I uint32_t RxProduceIndex; + __IO uint32_t RxConsumeIndex; + __IO uint32_t TxDescriptor; + __IO uint32_t TxStatus; + __IO uint32_t TxDescriptorNumber; + __IO uint32_t TxProduceIndex; + __I uint32_t TxConsumeIndex; + uint32_t RESERVED2[10]; + __I uint32_t TSV0; + __I uint32_t TSV1; + __I uint32_t RSV; + uint32_t RESERVED3[3]; + __IO uint32_t FlowControlCounter; + __I uint32_t FlowControlStatus; + uint32_t RESERVED4[34]; + __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */ + __IO uint32_t RxFilterWoLStatus; + __IO uint32_t RxFilterWoLClear; + uint32_t RESERVED5; + __IO uint32_t HashFilterL; + __IO uint32_t HashFilterH; + uint32_t RESERVED6[882]; + __I uint32_t IntStatus; /* Module Control Registers */ + __IO uint32_t IntEnable; + __O uint32_t IntClear; + __O uint32_t IntSet; + uint32_t RESERVED7; + __IO uint32_t PowerDown; + uint32_t RESERVED8; + __IO uint32_t Module_ID; +} LPC_EMAC_TypeDef; + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + + +/******************************************************************************/ +/* Peripheral memory map */ +/******************************************************************************/ +/* Base addresses */ +#define LPC_FLASH_BASE (0x00000000UL) +#define LPC_RAM_BASE (0x10000000UL) +#define LPC_GPIO_BASE (0x2009C000UL) +#define LPC_APB0_BASE (0x40000000UL) +#define LPC_APB1_BASE (0x40080000UL) +#define LPC_AHB_BASE (0x50000000UL) +#define LPC_CM3_BASE (0xE0000000UL) + +/* APB0 peripherals */ +#define LPC_WDT_BASE (LPC_APB0_BASE + 0x00000) +#define LPC_TIM0_BASE (LPC_APB0_BASE + 0x04000) +#define LPC_TIM1_BASE (LPC_APB0_BASE + 0x08000) +#define LPC_UART0_BASE (LPC_APB0_BASE + 0x0C000) +#define LPC_UART1_BASE (LPC_APB0_BASE + 0x10000) +#define LPC_PWM1_BASE (LPC_APB0_BASE + 0x18000) +#define LPC_I2C0_BASE (LPC_APB0_BASE + 0x1C000) +#define LPC_SPI_BASE (LPC_APB0_BASE + 0x20000) +#define LPC_RTC_BASE (LPC_APB0_BASE + 0x24000) +#define LPC_GPIOINT_BASE (LPC_APB0_BASE + 0x28080) +#define LPC_PINCON_BASE (LPC_APB0_BASE + 0x2C000) +#define LPC_SSP1_BASE (LPC_APB0_BASE + 0x30000) +#define LPC_ADC_BASE (LPC_APB0_BASE + 0x34000) +#define LPC_CANAF_RAM_BASE (LPC_APB0_BASE + 0x38000) +#define LPC_CANAF_BASE (LPC_APB0_BASE + 0x3C000) +#define LPC_CANCR_BASE (LPC_APB0_BASE + 0x40000) +#define LPC_CAN1_BASE (LPC_APB0_BASE + 0x44000) +#define LPC_CAN2_BASE (LPC_APB0_BASE + 0x48000) +#define LPC_I2C1_BASE (LPC_APB0_BASE + 0x5C000) + +/* APB1 peripherals */ +#define LPC_SSP0_BASE (LPC_APB1_BASE + 0x08000) +#define LPC_DAC_BASE (LPC_APB1_BASE + 0x0C000) +#define LPC_TIM2_BASE (LPC_APB1_BASE + 0x10000) +#define LPC_TIM3_BASE (LPC_APB1_BASE + 0x14000) +#define LPC_UART2_BASE (LPC_APB1_BASE + 0x18000) +#define LPC_UART3_BASE (LPC_APB1_BASE + 0x1C000) +#define LPC_I2C2_BASE (LPC_APB1_BASE + 0x20000) +#define LPC_I2S_BASE (LPC_APB1_BASE + 0x28000) +#define LPC_RIT_BASE (LPC_APB1_BASE + 0x30000) +#define LPC_MCPWM_BASE (LPC_APB1_BASE + 0x38000) +#define LPC_QEI_BASE (LPC_APB1_BASE + 0x3C000) +#define LPC_SC_BASE (LPC_APB1_BASE + 0x7C000) + +/* AHB peripherals */ +#define LPC_EMAC_BASE (LPC_AHB_BASE + 0x00000) +#define LPC_GPDMA_BASE (LPC_AHB_BASE + 0x04000) +#define LPC_GPDMACH0_BASE (LPC_AHB_BASE + 0x04100) +#define LPC_GPDMACH1_BASE (LPC_AHB_BASE + 0x04120) +#define LPC_GPDMACH2_BASE (LPC_AHB_BASE + 0x04140) +#define LPC_GPDMACH3_BASE (LPC_AHB_BASE + 0x04160) +#define LPC_GPDMACH4_BASE (LPC_AHB_BASE + 0x04180) +#define LPC_GPDMACH5_BASE (LPC_AHB_BASE + 0x041A0) +#define LPC_GPDMACH6_BASE (LPC_AHB_BASE + 0x041C0) +#define LPC_GPDMACH7_BASE (LPC_AHB_BASE + 0x041E0) +#define LPC_USB_BASE (LPC_AHB_BASE + 0x0C000) + +/* GPIOs */ +#define LPC_GPIO0_BASE (LPC_GPIO_BASE + 0x00000) +#define LPC_GPIO1_BASE (LPC_GPIO_BASE + 0x00020) +#define LPC_GPIO2_BASE (LPC_GPIO_BASE + 0x00040) +#define LPC_GPIO3_BASE (LPC_GPIO_BASE + 0x00060) +#define LPC_GPIO4_BASE (LPC_GPIO_BASE + 0x00080) + + +/******************************************************************************/ +/* Peripheral declaration */ +/******************************************************************************/ +#define LPC_SC ((LPC_SC_TypeDef *) LPC_SC_BASE ) +#define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE ) +#define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE ) +#define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE ) +#define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE ) +#define LPC_GPIO4 ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE ) +#define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE ) +#define LPC_TIM0 ((LPC_TIM_TypeDef *) LPC_TIM0_BASE ) +#define LPC_TIM1 ((LPC_TIM_TypeDef *) LPC_TIM1_BASE ) +#define LPC_TIM2 ((LPC_TIM_TypeDef *) LPC_TIM2_BASE ) +#define LPC_TIM3 ((LPC_TIM_TypeDef *) LPC_TIM3_BASE ) +#define LPC_RIT ((LPC_RIT_TypeDef *) LPC_RIT_BASE ) +#define LPC_UART0 ((LPC_UART0_TypeDef *) LPC_UART0_BASE ) +#define LPC_UART1 ((LPC_UART1_TypeDef *) LPC_UART1_BASE ) +#define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE ) +#define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE ) +#define LPC_PWM1 ((LPC_PWM_TypeDef *) LPC_PWM1_BASE ) +#define LPC_I2C0 ((LPC_I2C_TypeDef *) LPC_I2C0_BASE ) +#define LPC_I2C1 ((LPC_I2C_TypeDef *) LPC_I2C1_BASE ) +#define LPC_I2C2 ((LPC_I2C_TypeDef *) LPC_I2C2_BASE ) +#define LPC_I2S ((LPC_I2S_TypeDef *) LPC_I2S_BASE ) +#define LPC_SPI ((LPC_SPI_TypeDef *) LPC_SPI_BASE ) +#define LPC_RTC ((LPC_RTC_TypeDef *) LPC_RTC_BASE ) +#define LPC_GPIOINT ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE ) +#define LPC_PINCON ((LPC_PINCON_TypeDef *) LPC_PINCON_BASE ) +#define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE ) +#define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE ) +#define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE ) +#define LPC_DAC ((LPC_DAC_TypeDef *) LPC_DAC_BASE ) +#define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE) +#define LPC_CANAF ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE ) +#define LPC_CANCR ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE ) +#define LPC_CAN1 ((LPC_CAN_TypeDef *) LPC_CAN1_BASE ) +#define LPC_CAN2 ((LPC_CAN_TypeDef *) LPC_CAN2_BASE ) +#define LPC_MCPWM ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE ) +#define LPC_QEI ((LPC_QEI_TypeDef *) LPC_QEI_BASE ) +#define LPC_EMAC ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE ) +#define LPC_GPDMA ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE ) +#define LPC_GPDMACH0 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE ) +#define LPC_GPDMACH1 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE ) +#define LPC_GPDMACH2 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE ) +#define LPC_GPDMACH3 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE ) +#define LPC_GPDMACH4 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE ) +#define LPC_GPDMACH5 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE ) +#define LPC_GPDMACH6 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE ) +#define LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE ) +#define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE ) + +#endif // __LPC17xx_H__ diff --git a/platforms/lpc17xx/CMSISv2p00_LPC17xx/inc/core_cm3.h b/platforms/lpc17xx/CMSISv2p00_LPC17xx/inc/core_cm3.h new file mode 100644 index 0000000..a2b29ee --- /dev/null +++ b/platforms/lpc17xx/CMSISv2p00_LPC17xx/inc/core_cm3.h @@ -0,0 +1,1236 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V2.01 + * @date 06. December 2010 + * + * @note + * Copyright (C) 2009-2010 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + + +/** \mainpage CMSIS Cortex-M3 + + This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer. + It consists of: + + - Cortex-M Core Register Definitions + - Cortex-M functions + - Cortex-M instructions + + The CMSIS Cortex-M3 Core Peripheral Access Layer contains C and assembly functions that ease + access to the Cortex-M Core + */ + +/** \defgroup CMSIS_LintCinfiguration CMSIS Lint Configuration + List of Lint messages which will be suppressed and not shown: + - not yet checked + . + Note: To re-enable a Message, insert a space before 'lint' * + + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \defgroup CMSIS_core_definitions CMSIS Core Definitions + This file defines all structures and symbols for CMSIS core: + - CMSIS version number + - Cortex-M core + - Cortex-M core Revision Number + @{ + */ + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (0x02) /*!< [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x03) /*!< Cortex core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + +#endif + +#include /*!< standard types definitions */ +#include "core_cmInstr.h" /*!< Core Instruction Access */ +#include "core_cmFunc.h" /*!< Core Function Access */ + +#endif /* __CORE_CM3_H_GENERIC */ + + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +/* IO definitions (access restrictions to peripheral registers) */ +#ifdef __cplusplus + #define __I volatile /*!< defines 'read only' permissions */ +#else + #define __I volatile const /*!< defines 'read only' permissions */ +#endif +#define __O volatile /*!< defines 'write only' permissions */ +#define __IO volatile /*!< defines 'read / write' permissions */ + +/*@} end of group CMSIS_core_definitions */ + + + +/******************************************************************************* + * Register Abstraction + ******************************************************************************/ +/** \defgroup CMSIS_core_register CMSIS Core Register + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE CMSIS Core + Type definitions for the Cortex-M Core Registers + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC CMSIS NVIC + Type definitions for the Cortex-M NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB CMSIS SCB + Type definitions for the Cortex-M System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPU ID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt / Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) Hard Fault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) Mem Manage Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) Bus Fault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) ISA Feature Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick CMSIS SysTick + Type definitions for the Cortex-M System Timer Registers + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_ITM CMSIS ITM + Type definitions for the Cortex-M Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __IO uint32_t IWR; /*!< Offset: (R/W) ITM Integration Write Register */ + __IO uint32_t IRR; /*!< Offset: (R/W) ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __IO uint32_t LAR; /*!< Offset: (R/W) ITM Lock Access Register */ + __IO uint32_t LSR; /*!< Offset: (R/W) ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: (R/ ) ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: (R/ ) ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: (R/ ) ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: (R/ ) ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: (R/ ) ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: (R/ ) ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: (R/ ) ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: (R/ ) ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: (R/ ) ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: (R/ ) ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: (R/ ) ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_ATBID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_ATBID_Msk (0x7FUL << ITM_TCR_ATBID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_InterruptType CMSIS Interrupt Type + Type definitions for the Cortex-M Interrupt Type Register + @{ + */ + +/** \brief Structure type to access the Interrupt Type Register. + */ +typedef struct +{ + uint32_t RESERVED0; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Control Type Register */ +#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1; +#endif +} InterruptType_Type; + +/* Interrupt Controller Type Register Definitions */ +#define IntType_ICTR_INTLINESNUM_Pos 0 /*!< InterruptType ICTR: INTLINESNUM Position */ +#define IntType_ICTR_INTLINESNUM_Msk (0x1FUL << IntType_ICTR_INTLINESNUM_Pos) /*!< InterruptType ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define IntType_ACTLR_DISFOLD_Pos 2 /*!< InterruptType ACTLR: DISFOLD Position */ +#define IntType_ACTLR_DISFOLD_Msk (1UL << IntType_ACTLR_DISFOLD_Pos) /*!< InterruptType ACTLR: DISFOLD Mask */ + +#define IntType_ACTLR_DISDEFWBUF_Pos 1 /*!< InterruptType ACTLR: DISDEFWBUF Position */ +#define IntType_ACTLR_DISDEFWBUF_Msk (1UL << IntType_ACTLR_DISDEFWBUF_Pos) /*!< InterruptType ACTLR: DISDEFWBUF Mask */ + +#define IntType_ACTLR_DISMCYCINT_Pos 0 /*!< InterruptType ACTLR: DISMCYCINT Position */ +#define IntType_ACTLR_DISMCYCINT_Msk (1UL << IntType_ACTLR_DISMCYCINT_Pos) /*!< InterruptType ACTLR: DISMCYCINT Mask */ + +/*@}*/ /* end of group CMSIS_InterruptType */ + + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU CMSIS MPU + Type definitions for the Cortex-M Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: AP Position */ +#define MPU_RASR_AP_Msk (7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: TEX Position */ +#define MPU_RASR_TEX_Msk (7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: Shareable bit Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: Shareable bit Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: Cacheable bit Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: Cacheable bit Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: Bufferable bit Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: Bufferable bit Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENA_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENA_Msk (0x1UL << MPU_RASR_ENA_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug CMSIS Core Debug + Type definitions for the Cortex-M Core Debug Registers + @{ + */ + +/** \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + @{ + */ + +/* Memory mapping of Cortex-M3 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */ +#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions + @{ + */ + +/** \brief Set Priority Grouping + + This function sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + + \param [in] PriorityGroup Priority grouping field + */ +static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + (0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** \brief Get Priority Grouping + + This function gets the priority grouping from NVIC Interrupt Controller. + Priority grouping is SCB->AIRCR [10:8] PRIGROUP field. + + \return Priority grouping field + */ +static __INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + + +/** \brief Enable External Interrupt + + This function enables a device specific interupt in the NVIC interrupt controller. + The interrupt number cannot be a negative value. + + \param [in] IRQn Number of the external interrupt to enable + */ +static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ +} + + +/** \brief Disable External Interrupt + + This function disables a device specific interupt in the NVIC interrupt controller. + The interrupt number cannot be a negative value. + + \param [in] IRQn Number of the external interrupt to disable + */ +static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + + +/** \brief Get Pending Interrupt + + This function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Number of the interrupt for get pending + \return 0 Interrupt status is not pending + \return 1 Interrupt status is pending + */ +static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ +} + + +/** \brief Set Pending Interrupt + + This function sets the pending bit for the specified interrupt. + The interrupt number cannot be a negative value. + + \param [in] IRQn Number of the interrupt for set pending + */ +static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + + +/** \brief Clear Pending Interrupt + + This function clears the pending bit for the specified interrupt. + The interrupt number cannot be a negative value. + + \param [in] IRQn Number of the interrupt for clear pending + */ +static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Get Active Interrupt + + This function reads the active register in NVIC and returns the active bit. + \param [in] IRQn Number of the interrupt for get active + \return 0 Interrupt status is not active + \return 1 Interrupt status is active + */ +static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ +} + + +/** \brief Set Interrupt Priority + + This function sets the priority for the specified interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + Note: The priority cannot be set for every core interrupt. + + \param [in] IRQn Number of the interrupt for set priority + \param [in] priority Priority to set + */ +static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ +} + + +/** \brief Get Interrupt Priority + + This function reads the priority for the specified interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + The returned priority value is automatically aligned to the implemented + priority bits of the microcontroller. + + \param [in] IRQn Number of the interrupt for get priority + \return Interrupt Priority + */ +static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief Encode Priority + + This function encodes the priority for an interrupt with the given priority group, + preemptive priority value and sub priority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + + The returned priority value can be used for NVIC_SetPriority(...) function + + \param [in] PriorityGroup Used priority group + \param [in] PreemptPriority Preemptive priority value (starting from 0) + \param [in] SubPriority Sub priority value (starting from 0) + \return Encoded priority for the interrupt + */ +static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** \brief Decode Priority + + This function decodes an interrupt priority value with the given priority group to + preemptive priority value and sub priority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + + The priority value can be retrieved with NVIC_GetPriority(...) function + + \param [in] Priority Priority value + \param [in] PriorityGroup Used priority group + \param [out] pPreemptPriority Preemptive priority value (starting from 0) + \param [out] pSubPriority Sub priority value (starting from 0) + */ +static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + +/** \brief System Reset + + This function initiate a system reset request to reset the MCU. + */ +static __INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + This function initialises the system tick timer and its interrupt and start the system tick timer. + Counter is in free running mode to generate periodical interrupts. + + \param [in] ticks Number of ticks between two interrupts + \return 0 Function succeeded + \return 1 Function failed + */ +static __INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions CMSIS Core Debug Functions + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< external variable to receive characters */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */ + + +/** \brief ITM Send Character + + This function transmits a character via the ITM channel 0. + It just returns when no debugger is connected that has booked the output. + It is blocking when a debugger is connected, but the previous character send is not transmitted. + + \param [in] ch Character to transmit + \return Character to transmit + */ +static __INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */ + (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** \brief ITM Receive Character + + This function inputs a character via external variable ITM_RxBuffer. + It just returns when no debugger is connected that has booked the output. + It is blocking when a debugger is connected, but the previous character send is not transmitted. + + \return Received character + \return -1 No character received + */ +static __INLINE int32_t ITM_ReceiveChar (void) { + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** \brief ITM Check Character + + This function checks external variable ITM_RxBuffer whether a character is available or not. + It returns '1' if a character is available and '0' if no character is available. + + \return 0 No character available + \return 1 Character available + */ +static __INLINE int32_t ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ + +#ifdef __cplusplus +} +#endif + +/*lint -restore */ diff --git a/platforms/lpc17xx/CMSISv2p00_LPC17xx/inc/core_cmFunc.h b/platforms/lpc17xx/CMSISv2p00_LPC17xx/inc/core_cmFunc.h new file mode 100644 index 0000000..e3d0edb --- /dev/null +++ b/platforms/lpc17xx/CMSISv2p00_LPC17xx/inc/core_cmFunc.h @@ -0,0 +1,844 @@ +/**************************************************************************//** + * @file core_cmFunc.h + * @brief CMSIS Cortex-M Core Function Access Header File + * @version V2.01 + * @date 06. December 2010 + * + * @note + * Copyright (C) 2009-2010 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#ifndef __CORE_CMFUNC_H__ +#define __CORE_CMFUNC_H__ + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/ +/* ARM armcc specific functions */ + +/* intrinsic void __enable_irq(); */ +/* intrinsic void __disable_irq(); */ + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +#if (__ARMCC_VERSION < 400000) +extern uint32_t __get_CONTROL(void); +#else /* (__ARMCC_VERSION >= 400000) */ +static __INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} +#endif /* __ARMCC_VERSION */ + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +#if (__ARMCC_VERSION < 400000) +extern void __set_CONTROL(uint32_t control); +#else /* (__ARMCC_VERSION >= 400000) */ +static __INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} +#endif /* __ARMCC_VERSION */ + + +/** \brief Get ISPR Register + + This function returns the content of the ISPR Register. + + \return ISPR Register value + */ +#if (__ARMCC_VERSION < 400000) +extern uint32_t __get_IPSR(void); +#else /* (__ARMCC_VERSION >= 400000) */ +static __INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} +#endif /* __ARMCC_VERSION */ + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +#if (__ARMCC_VERSION < 400000) +extern uint32_t __get_APSR(void); +#else /* (__ARMCC_VERSION >= 400000) */ +static __INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} +#endif /* __ARMCC_VERSION */ + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +#if (__ARMCC_VERSION < 400000) +extern uint32_t __get_xPSR(void); +#else /* (__ARMCC_VERSION >= 400000) */ +static __INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} +#endif /* __ARMCC_VERSION */ + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +#if (__ARMCC_VERSION < 400000) +extern uint32_t __get_PSP(void); +#else /* (__ARMCC_VERSION >= 400000) */ +static __INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} +#endif /* __ARMCC_VERSION */ + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +#if (__ARMCC_VERSION < 400000) +extern void __set_PSP(uint32_t topOfProcStack); +#else /* (__ARMCC_VERSION >= 400000) */ +static __INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} +#endif /* __ARMCC_VERSION */ + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +#if (__ARMCC_VERSION < 400000) +extern uint32_t __get_MSP(void); +#else /* (__ARMCC_VERSION >= 400000) */ +static __INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} +#endif /* __ARMCC_VERSION */ + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +#if (__ARMCC_VERSION < 400000) +extern void __set_MSP(uint32_t topOfMainStack); +#else /* (__ARMCC_VERSION >= 400000) */ +static __INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} +#endif /* __ARMCC_VERSION */ + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +#if (__ARMCC_VERSION < 400000) +extern uint32_t __get_PRIMASK(void); +#else /* (__ARMCC_VERSION >= 400000) */ +static __INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} +#endif /* __ARMCC_VERSION */ + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +#if (__ARMCC_VERSION < 400000) +extern void __set_PRIMASK(uint32_t priMask); +#else /* (__ARMCC_VERSION >= 400000) */ +static __INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} +#endif /* __ARMCC_VERSION */ + + +#if (__CORTEX_M >= 0x03) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +#if (__ARMCC_VERSION < 400000) +extern uint32_t __get_BASEPRI(void); +#else /* (__ARMCC_VERSION >= 400000) */ +static __INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} +#endif /* __ARMCC_VERSION */ + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +#if (__ARMCC_VERSION < 400000) +extern void __set_BASEPRI(uint32_t basePri); +#else /* (__ARMCC_VERSION >= 400000) */ +static __INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xff); +} +#endif /* __ARMCC_VERSION */ + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +#if (__ARMCC_VERSION < 400000) +extern uint32_t __get_FAULTMASK(void); +#else /* (__ARMCC_VERSION >= 400000) */ +static __INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} +#endif /* __ARMCC_VERSION */ + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +#if (__ARMCC_VERSION < 400000) +extern void __set_FAULTMASK(uint32_t faultMask); +#else /* (__ARMCC_VERSION >= 400000) */ +static __INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & 1); +} +#endif /* __ARMCC_VERSION */ + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +static __INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +static __INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#endif +} + +#endif /* (__CORTEX_M == 0x04) */ + + + #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/ +/* IAR iccarm specific functions */ + +#if defined (__ICCARM__) + #include /* IAR Intrinsics */ +#endif + +#pragma diag_suppress=Pe940 + +/** \brief Enable IRQ Interrupts + + This function enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_irq __enable_interrupt + + +/** \brief Disable IRQ Interrupts + + This function disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_irq __disable_interrupt + + +/* intrinsic unsigned long __get_CONTROL( void ); (see intrinsic.h) */ +/* intrinsic void __set_CONTROL( unsigned long ); (see intrinsic.h) */ + + +/** \brief Get ISPR Register + + This function returns the content of the ISPR Register. + + \return ISPR Register value + */ +static uint32_t __get_IPSR(void) +{ + __ASM("mrs r0, ipsr"); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +static uint32_t __get_APSR(void) +{ + __ASM("mrs r0, apsr"); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +static uint32_t __get_xPSR(void) +{ + __ASM("mrs r0, psr"); // assembler does not know "xpsr" +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +static uint32_t __get_PSP(void) +{ + __ASM("mrs r0, psp"); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +static void __set_PSP(uint32_t topOfProcStack) +{ + __ASM("msr psp, r0"); +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +static uint32_t __get_MSP(void) +{ + __ASM("mrs r0, msp"); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +static void __set_MSP(uint32_t topOfMainStack) +{ + __ASM("msr msp, r0"); +} + + +/* intrinsic unsigned long __get_PRIMASK( void ); (see intrinsic.h) */ +/* intrinsic void __set_PRIMASK( unsigned long ); (see intrinsic.h) */ + + +#if (__CORTEX_M >= 0x03) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +static __INLINE void __enable_fault_irq(void) +{ + __ASM ("cpsie f"); +} + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +static __INLINE void __disable_fault_irq(void) +{ + __ASM ("cpsid f"); +} + + +/* intrinsic unsigned long __get_BASEPRI( void ); (see intrinsic.h) */ +/* intrinsic void __set_BASEPRI( unsigned long ); (see intrinsic.h) */ +/* intrinsic unsigned long __get_FAULTMASK( void ); (see intrinsic.h) */ +/* intrinsic void __set_FAULTMASK(unsigned long); (see intrinsic.h) */ + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +static uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) + __ASM("vmrs r0, fpscr"); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +static void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) + __ASM("vmsr fpscr, r0"); +#endif +} + +#endif /* (__CORTEX_M == 0x04) */ + +#pragma diag_default=Pe940 + + +#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/** \brief Enable IRQ Interrupts + + This function enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) static __INLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i"); +} + + +/** \brief Disable IRQ Interrupts + + This function disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) static __INLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i"); +} + + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +__attribute__( ( always_inline ) ) static __INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) ); +} + + +/** \brief Get ISPR Register + + This function returns the content of the ISPR Register. + + \return ISPR Register value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) static __INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) ); +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) static __INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) ); +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +__attribute__( ( always_inline ) ) static __INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) ); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) static __INLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f"); +} + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) static __INLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f"); +} + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); + return(result); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +__attribute__( ( always_inline ) ) static __INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) ); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +__attribute__( ( always_inline ) ) static __INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) ); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) + uint32_t result; + + __ASM volatile ("MRS %0, fpscr" : "=r" (result) ); + return(result); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__( ( always_inline ) ) static __INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) + __ASM volatile ("MSR fpscr, %0" : : "r" (fpscr) ); +#endif +} + +#endif /* (__CORTEX_M == 0x04) */ + + +#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all instrinsics, + * Including the CMSIS ones. + */ + +#endif + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +#endif /* __CORE_CMFUNC_H__ */ diff --git a/platforms/lpc17xx/CMSISv2p00_LPC17xx/inc/core_cmInstr.h b/platforms/lpc17xx/CMSISv2p00_LPC17xx/inc/core_cmInstr.h new file mode 100644 index 0000000..fb3c092 --- /dev/null +++ b/platforms/lpc17xx/CMSISv2p00_LPC17xx/inc/core_cmInstr.h @@ -0,0 +1,775 @@ +/**************************************************************************//** + * @file core_cmInstr.h + * @brief CMSIS Cortex-M Core Instruction Access Header File + * @version V2.01 + * @date 06. December 2010 + * + * @note + * Copyright (C) 2009-2010 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#ifndef __CORE_CMINSTR_H__ +#define __CORE_CMINSTR_H__ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/ +/* ARM armcc specific functions */ + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +#if (__ARMCC_VERSION < 400677) +extern uint32_t __REV16(uint32_t value); +#else /* (__ARMCC_VERSION >= 400677) */ +static __INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif /* __ARMCC_VERSION */ + + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +#if (__ARMCC_VERSION < 400677) +extern int32_t __REVSH(int32_t value); +#else /* (__ARMCC_VERSION >= 400677) */ +static __INLINE __ASM int32_t __REVSH(int32_t value) +{ + revsh r0, r0 + bx lr +} +#endif /* __ARMCC_VERSION */ + + +#if (__CORTEX_M >= 0x03) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __rbit + + +/** \brief LDR Exclusive (8 bit) + + This function performs a exclusive LDR command for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) + + +/** \brief LDR Exclusive (16 bit) + + This function performs a exclusive LDR command for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) + + +/** \brief LDR Exclusive (32 bit) + + This function performs a exclusive LDR command for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) + + +/** \brief STR Exclusive (8 bit) + + This function performs a exclusive STR command for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (16 bit) + + This function performs a exclusive STR command for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (32 bit) + + This function performs a exclusive STR command for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW(value, ptr) __strex(value, ptr) + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +#if (__ARMCC_VERSION < 400000) +extern void __CLREX(void); +#else /* (__ARMCC_VERSION >= 400000) */ +#define __CLREX __clrex +#endif /* __ARMCC_VERSION */ + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + +#endif /* (__CORTEX_M >= 0x03) */ + + + +#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/ +/* IAR iccarm specific functions */ + +#include /* IAR Intrinsics */ + +#pragma diag_suppress=Pe940 + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __no_operation + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +static __INLINE void __WFI(void) +{ + __ASM ("wfi"); +} + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +static __INLINE void __WFE(void) +{ + __ASM ("wfe"); +} + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +static __INLINE void __SEV(void) +{ + __ASM ("sev"); +} + + +/* intrinsic void __ISB(void) (see intrinsics.h) */ +/* intrinsic void __DSB(void) (see intrinsics.h) */ +/* intrinsic void __DMB(void) (see intrinsics.h) */ +/* intrinsic uint32_t __REV(uint32_t value) (see intrinsics.h) */ +/* intrinsic __SSAT (see intrinsics.h) */ +/* intrinsic __USAT (see intrinsics.h) */ + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +static uint32_t __REV16(uint32_t value) +{ + __ASM("rev16 r0, r0"); +} + + +/* intrinsic uint32_t __REVSH(uint32_t value) (see intrinsics.h */ + + +#if (__CORTEX_M >= 0x03) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +static uint32_t __RBIT(uint32_t value) +{ + __ASM("rbit r0, r0"); +} + + +/** \brief LDR Exclusive (8 bit) + + This function performs a exclusive LDR command for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +static uint8_t __LDREXB(volatile uint8_t *addr) +{ + __ASM("ldrexb r0, [r0]"); +} + + +/** \brief LDR Exclusive (16 bit) + + This function performs a exclusive LDR command for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +static uint16_t __LDREXH(volatile uint16_t *addr) +{ + __ASM("ldrexh r0, [r0]"); +} + + +/** \brief LDR Exclusive (32 bit) + + This function performs a exclusive LDR command for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +/* intrinsic unsigned long __LDREX(unsigned long *) (see intrinsics.h) */ +static uint32_t __LDREXW(volatile uint32_t *addr) +{ + __ASM("ldrex r0, [r0]"); +} + + +/** \brief STR Exclusive (8 bit) + + This function performs a exclusive STR command for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +static uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + __ASM("strexb r0, r0, [r1]"); +} + + +/** \brief STR Exclusive (16 bit) + + This function performs a exclusive STR command for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +static uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + __ASM("strexh r0, r0, [r1]"); +} + + +/** \brief STR Exclusive (32 bit) + + This function performs a exclusive STR command for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +/* intrinsic unsigned long __STREX(unsigned long, unsigned long) (see intrinsics.h )*/ +static uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + __ASM("strex r0, r0, [r1]"); +} + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +static __INLINE void __CLREX(void) +{ + __ASM ("clrex"); +} + +/* intrinsic unsigned char __CLZ( unsigned long ) (see intrinsics.h) */ + +#endif /* (__CORTEX_M >= 0x03) */ + +#pragma diag_default=Pe940 + + + +#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +__attribute__( ( always_inline ) ) static __INLINE void __NOP(void) +{ + __ASM volatile ("nop"); +} + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +__attribute__( ( always_inline ) ) static __INLINE void __WFI(void) +{ + __ASM volatile ("wfi"); +} + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +__attribute__( ( always_inline ) ) static __INLINE void __WFE(void) +{ + __ASM volatile ("wfe"); +} + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +__attribute__( ( always_inline ) ) static __INLINE void __SEV(void) +{ + __ASM volatile ("sev"); +} + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +__attribute__( ( always_inline ) ) static __INLINE void __ISB(void) +{ + __ASM volatile ("isb"); +} + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__attribute__( ( always_inline ) ) static __INLINE void __DSB(void) +{ + __ASM volatile ("dsb"); +} + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__attribute__( ( always_inline ) ) static __INLINE void __DMB(void) +{ + __ASM volatile ("dmb"); +} + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) static __INLINE int32_t __REVSH(int32_t value) +{ + uint32_t result; + + __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +/** \brief LDR Exclusive (8 bit) + + This function performs a exclusive LDR command for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__( ( always_inline ) ) static __INLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint8_t result; + + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + + +/** \brief LDR Exclusive (16 bit) + + This function performs a exclusive LDR command for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__( ( always_inline ) ) static __INLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint16_t result; + + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + + +/** \brief LDR Exclusive (32 bit) + + This function performs a exclusive LDR command for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + + +/** \brief STR Exclusive (8 bit) + + This function performs a exclusive STR command for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); + return(result); +} + + +/** \brief STR Exclusive (16 bit) + + This function performs a exclusive STR command for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); + return(result); +} + + +/** \brief STR Exclusive (32 bit) + + This function performs a exclusive STR command for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); + return(result); +} + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +__attribute__( ( always_inline ) ) static __INLINE void __CLREX(void) +{ + __ASM volatile ("clrex"); +} + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__attribute__( ( always_inline ) ) static __INLINE uint8_t __CLZ(uint32_t value) +{ + uint8_t result; + + __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + + + +#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all instrinsics, + * Including the CMSIS ones. + */ + +#endif + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + +#endif /* __CORE_CMINSTR_H__ */ diff --git a/platforms/lpc17xx/CMSISv2p00_LPC17xx/inc/system_LPC17xx.h b/platforms/lpc17xx/CMSISv2p00_LPC17xx/inc/system_LPC17xx.h new file mode 100644 index 0000000..d72cb50 --- /dev/null +++ b/platforms/lpc17xx/CMSISv2p00_LPC17xx/inc/system_LPC17xx.h @@ -0,0 +1,64 @@ +/**************************************************************************//** + * @file system_LPC17xx.h + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File + * for the NXP LPC17xx Device Series + * @version V1.02 + * @date 08. September 2009 + * + * @note + * Copyright (C) 2009 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + + +#ifndef __SYSTEM_LPC17xx_H +#define __SYSTEM_LPC17xx_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit (void); + +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + +#ifdef __cplusplus +} +#endif + +#endif /* __SYSTEM_LPC17xx_H */ diff --git a/platforms/lpc17xx/CMSISv2p00_LPC17xx/src/core_cm3.c b/platforms/lpc17xx/CMSISv2p00_LPC17xx/src/core_cm3.c new file mode 100644 index 0000000..6e13f4c --- /dev/null +++ b/platforms/lpc17xx/CMSISv2p00_LPC17xx/src/core_cm3.c @@ -0,0 +1,339 @@ +/**************************************************************************//** + * @file core_cm3.c + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File + * @version V2.00 + * @date 13. September 2010 + * + * @note + * Copyright (C) 2009-2010 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#include + +/* define compiler specific symbols */ +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + +#endif + + +/* ########################## Core Instruction Access ######################### */ + +#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/ + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +#if (__ARMCC_VERSION < 400677) +__ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif /* __ARMCC_VERSION */ + + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +#if (__ARMCC_VERSION < 400677) +__ASM int32_t __REVSH(int32_t value) +{ + revsh r0, r0 + bx lr +} +#endif /* __ARMCC_VERSION */ + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +#if (__ARMCC_VERSION < 400000) +__ASM void __CLREX(void) +{ + clrex +} +#endif /* __ARMCC_VERSION */ + + +#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/ +/* obsolete */ +#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ +/* obsolete */ +#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/ +/* obsolete */ +#endif + + +/* ########################### Core Function Access ########################### */ + +#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/ + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +#if (__ARMCC_VERSION < 400000) +__ASM uint32_t __get_CONTROL(void) +{ + mrs r0, control + bx lr +} +#endif /* __ARMCC_VERSION */ + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +#if (__ARMCC_VERSION < 400000) +__ASM void __set_CONTROL(uint32_t control) +{ + msr control, r0 + bx lr +} +#endif /* __ARMCC_VERSION */ + + +/** \brief Get ISPR Register + + This function returns the content of the ISPR Register. + + \return ISPR Register value + */ +#if (__ARMCC_VERSION < 400000) +__ASM uint32_t __get_IPSR(void) +{ + mrs r0, ipsr + bx lr +} +#endif /* __ARMCC_VERSION */ + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +#if (__ARMCC_VERSION < 400000) +__ASM uint32_t __get_APSR(void) +{ + mrs r0, apsr + bx lr +} +#endif /* __ARMCC_VERSION */ + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +#if (__ARMCC_VERSION < 400000) +__ASM uint32_t __get_xPSR(void) +{ + mrs r0, xpsr + bx lr +} +#endif /* __ARMCC_VERSION */ + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +#if (__ARMCC_VERSION < 400000) +__ASM uint32_t __get_PSP(void) +{ + mrs r0, psp + bx lr +} +#endif /* __ARMCC_VERSION */ + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +#if (__ARMCC_VERSION < 400000) +__ASM void __set_PSP(uint32_t topOfProcStack) +{ + msr psp, r0 + bx lr +} +#endif /* __ARMCC_VERSION */ + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +#if (__ARMCC_VERSION < 400000) +__ASM uint32_t __get_MSP(void) +{ + mrs r0, msp + bx lr +} +#endif /* __ARMCC_VERSION */ + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +#if (__ARMCC_VERSION < 400000) +__ASM void __set_MSP(uint32_t mainStackPointer) +{ + msr msp, r0 + bx lr +} +#endif /* __ARMCC_VERSION */ + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +#if (__ARMCC_VERSION < 400000) +__ASM uint32_t __get_BASEPRI(void) +{ + mrs r0, basepri + bx lr +} +#endif /* __ARMCC_VERSION */ + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +#if (__ARMCC_VERSION < 400000) +__ASM void __set_BASEPRI(uint32_t basePri) +{ + msr basepri, r0 + bx lr +} +#endif /* __ARMCC_VERSION */ + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +#if (__ARMCC_VERSION < 400000) +__ASM uint32_t __get_PRIMASK(void) +{ + mrs r0, primask + bx lr +} +#endif /* __ARMCC_VERSION */ + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +#if (__ARMCC_VERSION < 400000) +__ASM void __set_PRIMASK(uint32_t priMask) +{ + msr primask, r0 + bx lr +} +#endif /* __ARMCC_VERSION */ + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask Register. + + \return Fault Mask value + */ +#if (__ARMCC_VERSION < 400000) +__ASM uint32_t __get_FAULTMASK(void) +{ + mrs r0, faultmask + bx lr +} +#endif /* __ARMCC_VERSION */ + + +/** \brief Set the Fault Mask + + This function assigns the given value to the Fault Mask Register. + + \param [in] faultMask Fault Mask value value to set + */ +#if (__ARMCC_VERSION < 400000) +__ASM void __set_FAULTMASK(uint32_t faultMask) +{ + msr faultmask, r0 + bx lr +} +#endif /* __ARMCC_VERSION */ + + + +#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/ +/* obsolete */ +#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ +/* obsolete */ +#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/ +/* obsolete */ +#endif diff --git a/platforms/lpc17xx/CMSISv2p00_LPC17xx/src/system_LPC17xx.c b/platforms/lpc17xx/CMSISv2p00_LPC17xx/src/system_LPC17xx.c new file mode 100644 index 0000000..11aa44f --- /dev/null +++ b/platforms/lpc17xx/CMSISv2p00_LPC17xx/src/system_LPC17xx.c @@ -0,0 +1,532 @@ +/**************************************************************************//** + * @file system_LPC17xx.c + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Source File + * for the NXP LPC17xx Device Series + * @version V1.08 + * @date 12. May 2010 + * + * @note + * Copyright (C) 2009 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + + +#include +#include "LPC17xx.h" + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + +/*--------------------- Clock Configuration ---------------------------------- +// +// Clock Configuration +// System Controls and Status Register (SCS) +// OSCRANGE: Main Oscillator Range Select +// <0=> 1 MHz to 20 MHz +// <1=> 15 MHz to 24 MHz +// OSCEN: Main Oscillator Enable +// +// +// +// Clock Source Select Register (CLKSRCSEL) +// CLKSRC: PLL Clock Source Selection +// <0=> Internal RC oscillator +// <1=> Main oscillator +// <2=> RTC oscillator +// +// +// PLL0 Configuration (Main PLL) +// PLL0 Configuration Register (PLL0CFG) +// F_cco0 = (2 * M * F_in) / N +// F_in must be in the range of 32 kHz to 50 MHz +// F_cco0 must be in the range of 275 MHz to 550 MHz +// MSEL: PLL Multiplier Selection +// <6-32768><#-1> +// M Value +// NSEL: PLL Divider Selection +// <1-256><#-1> +// N Value +// +// +// +// PLL1 Configuration (USB PLL) +// PLL1 Configuration Register (PLL1CFG) +// F_usb = M * F_osc or F_usb = F_cco1 / (2 * P) +// F_cco1 = F_osc * M * 2 * P +// F_cco1 must be in the range of 156 MHz to 320 MHz +// MSEL: PLL Multiplier Selection +// <1-32><#-1> +// M Value (for USB maximum value is 4) +// PSEL: PLL Divider Selection +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// P Value +// +// +// +// CPU Clock Configuration Register (CCLKCFG) +// CCLKSEL: Divide Value for CPU Clock from PLL0 +// <1-256><#-1> +// +// +// USB Clock Configuration Register (USBCLKCFG) +// USBSEL: Divide Value for USB Clock from PLL0 +// <0-15> +// Divide is USBSEL + 1 +// +// +// Peripheral Clock Selection Register 0 (PCLKSEL0) +// PCLK_WDT: Peripheral Clock Selection for WDT +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_TIMER0: Peripheral Clock Selection for TIMER0 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_TIMER1: Peripheral Clock Selection for TIMER1 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_UART0: Peripheral Clock Selection for UART0 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_UART1: Peripheral Clock Selection for UART1 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_PWM1: Peripheral Clock Selection for PWM1 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_I2C0: Peripheral Clock Selection for I2C0 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_SPI: Peripheral Clock Selection for SPI +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_SSP1: Peripheral Clock Selection for SSP1 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_DAC: Peripheral Clock Selection for DAC +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_ADC: Peripheral Clock Selection for ADC +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_CAN1: Peripheral Clock Selection for CAN1 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 6 +// PCLK_CAN2: Peripheral Clock Selection for CAN2 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 6 +// PCLK_ACF: Peripheral Clock Selection for ACF +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 6 +// +// +// Peripheral Clock Selection Register 1 (PCLKSEL1) +// PCLK_QEI: Peripheral Clock Selection for the Quadrature Encoder Interface +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_GPIO: Peripheral Clock Selection for GPIOs +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_PCB: Peripheral Clock Selection for the Pin Connect Block +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_I2C1: Peripheral Clock Selection for I2C1 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_SSP0: Peripheral Clock Selection for SSP0 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_TIMER2: Peripheral Clock Selection for TIMER2 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_TIMER3: Peripheral Clock Selection for TIMER3 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_UART2: Peripheral Clock Selection for UART2 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_UART3: Peripheral Clock Selection for UART3 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_I2C2: Peripheral Clock Selection for I2C2 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_I2S: Peripheral Clock Selection for I2S +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_RIT: Peripheral Clock Selection for the Repetitive Interrupt Timer +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_SYSCON: Peripheral Clock Selection for the System Control Block +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_MC: Peripheral Clock Selection for the Motor Control PWM +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// +// +// Power Control for Peripherals Register (PCONP) +// PCTIM0: Timer/Counter 0 power/clock enable +// PCTIM1: Timer/Counter 1 power/clock enable +// PCUART0: UART 0 power/clock enable +// PCUART1: UART 1 power/clock enable +// PCPWM1: PWM 1 power/clock enable +// PCI2C0: I2C interface 0 power/clock enable +// PCSPI: SPI interface power/clock enable +// PCRTC: RTC power/clock enable +// PCSSP1: SSP interface 1 power/clock enable +// PCAD: A/D converter power/clock enable +// PCCAN1: CAN controller 1 power/clock enable +// PCCAN2: CAN controller 2 power/clock enable +// PCGPIO: GPIOs power/clock enable +// PCRIT: Repetitive interrupt timer power/clock enable +// PCMC: Motor control PWM power/clock enable +// PCQEI: Quadrature encoder interface power/clock enable +// PCI2C1: I2C interface 1 power/clock enable +// PCSSP0: SSP interface 0 power/clock enable +// PCTIM2: Timer 2 power/clock enable +// PCTIM3: Timer 3 power/clock enable +// PCUART2: UART 2 power/clock enable +// PCUART3: UART 3 power/clock enable +// PCI2C2: I2C interface 2 power/clock enable +// PCI2S: I2S interface power/clock enable +// PCGPDMA: GP DMA function power/clock enable +// PCENET: Ethernet block power/clock enable +// PCUSB: USB interface power/clock enable +// +// +// Clock Output Configuration Register (CLKOUTCFG) +// CLKOUTSEL: Selects clock source for CLKOUT +// <0=> CPU clock +// <1=> Main oscillator +// <2=> Internal RC oscillator +// <3=> USB clock +// <4=> RTC oscillator +// CLKOUTDIV: Selects clock divider for CLKOUT +// <1-16><#-1> +// CLKOUT_EN: CLKOUT enable control +// +// +// +*/ +#define CLOCK_SETUP 1 +#define SCS_Val 0x00000020 +#define CLKSRCSEL_Val 0x00000001 +#define PLL0_SETUP 1 +#define PLL0CFG_Val 0x00050063 +#define PLL1_SETUP 1 +#define PLL1CFG_Val 0x00000023 +#define CCLKCFG_Val 0x00000003 +#define USBCLKCFG_Val 0x00000000 +#define PCLKSEL0_Val 0x00000000 +#define PCLKSEL1_Val 0x00000000 +#define PCONP_Val 0x042887DE +#define CLKOUTCFG_Val 0x00000000 + + +/*--------------------- Flash Accelerator Configuration ---------------------- +// +// Flash Accelerator Configuration +// FLASHTIM: Flash Access Time +// <0=> 1 CPU clock (for CPU clock up to 20 MHz) +// <1=> 2 CPU clocks (for CPU clock up to 40 MHz) +// <2=> 3 CPU clocks (for CPU clock up to 60 MHz) +// <3=> 4 CPU clocks (for CPU clock up to 80 MHz) +// <4=> 5 CPU clocks (for CPU clock up to 100 MHz) +// <5=> 6 CPU clocks (for any CPU clock) +// +*/ +#define FLASH_SETUP 0 +#define FLASHCFG_Val 0x00004000 + +/* +//-------- <<< end of configuration section >>> ------------------------------ +*/ + +/*---------------------------------------------------------------------------- + Check the register settings + *----------------------------------------------------------------------------*/ +#define CHECK_RANGE(val, min, max) ((val < min) || (val > max)) +#define CHECK_RSVD(val, mask) (val & mask) + +/* Clock Configuration -------------------------------------------------------*/ +#if (CHECK_RSVD((SCS_Val), ~0x00000030)) + #error "SCS: Invalid values of reserved bits!" +#endif + +#if (CHECK_RANGE((CLKSRCSEL_Val), 0, 2)) + #error "CLKSRCSEL: Value out of range!" +#endif + +#if (CHECK_RSVD((PLL0CFG_Val), ~0x00FF7FFF)) + #error "PLL0CFG: Invalid values of reserved bits!" +#endif + +#if (CHECK_RSVD((PLL1CFG_Val), ~0x0000007F)) + #error "PLL1CFG: Invalid values of reserved bits!" +#endif + +#if (PLL0_SETUP) /* if PLL0 is used */ + #if (CCLKCFG_Val < 2) /* CCLKSEL must be greater then 1 */ + #error "CCLKCFG: CCLKSEL must be greater then 1 if PLL0 is used!" + #endif +#endif + +#if (CHECK_RANGE((CCLKCFG_Val), 2, 255)) + #error "CCLKCFG: Value out of range!" +#endif + +#if (CHECK_RSVD((USBCLKCFG_Val), ~0x0000000F)) + #error "USBCLKCFG: Invalid values of reserved bits!" +#endif + +#if (CHECK_RSVD((PCLKSEL0_Val), 0x000C0C00)) + #error "PCLKSEL0: Invalid values of reserved bits!" +#endif + +#if (CHECK_RSVD((PCLKSEL1_Val), 0x03000300)) + #error "PCLKSEL1: Invalid values of reserved bits!" +#endif + +#if (CHECK_RSVD((PCONP_Val), 0x10100821)) + #error "PCONP: Invalid values of reserved bits!" +#endif + +#if (CHECK_RSVD((CLKOUTCFG_Val), ~0x000001FF)) + #error "CLKOUTCFG: Invalid values of reserved bits!" +#endif + +/* Flash Accelerator Configuration -------------------------------------------*/ +#if (CHECK_RSVD((FLASHCFG_Val), ~0x0000F000)) + #error "FLASHCFG: Invalid values of reserved bits!" +#endif + + +/*---------------------------------------------------------------------------- + DEFINES + *----------------------------------------------------------------------------*/ + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (12000000UL) /* Oscillator frequency */ +#define OSC_CLK ( XTAL) /* Main oscillator frequency */ +#define RTC_CLK ( 32000UL) /* RTC oscillator frequency */ +#define IRC_OSC ( 4000000UL) /* Internal RC oscillator frequency */ + + +/* F_cco0 = (2 * M * F_in) / N */ +#define __M (((PLL0CFG_Val ) & 0x7FFF) + 1) +#define __N (((PLL0CFG_Val >> 16) & 0x00FF) + 1) +#define __FCCO(__F_IN) ((2/*ULL*/ * __M * __F_IN) / __N) +#define __CCLK_DIV (((CCLKCFG_Val ) & 0x00FF) + 1) + +/* Determine core clock frequency according to settings */ + #if (PLL0_SETUP) + #if ((CLKSRCSEL_Val & 0x03) == 1) + #define __CORE_CLK (__FCCO(OSC_CLK) / __CCLK_DIV) + #elif ((CLKSRCSEL_Val & 0x03) == 2) + #define __CORE_CLK (__FCCO(RTC_CLK) / __CCLK_DIV) + #else + #define __CORE_CLK (__FCCO(IRC_OSC) / __CCLK_DIV) + #endif + #else + #if ((CLKSRCSEL_Val & 0x03) == 1) + #define __CORE_CLK (OSC_CLK / __CCLK_DIV) + #elif ((CLKSRCSEL_Val & 0x03) == 2) + #define __CORE_CLK (RTC_CLK / __CCLK_DIV) + #else + #define __CORE_CLK (IRC_OSC / __CCLK_DIV) + #endif + #endif + + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = __CORE_CLK;/*!< System Clock Frequency (Core Clock)*/ + + +/*---------------------------------------------------------------------------- + Clock functions + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ +{ + /* Determine clock frequency according to clock register values */ + if (((LPC_SC->PLL0STAT >> 24) & 3) == 3) { /* If PLL0 enabled and connected */ + switch (LPC_SC->CLKSRCSEL & 0x03) { + case 0: /* Int. RC oscillator => PLL0 */ + case 3: /* Reserved, default to Int. RC */ + SystemCoreClock = (IRC_OSC * + ((2/*ULL*/ * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) / + (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) / + ((LPC_SC->CCLKCFG & 0xFF)+ 1)); + break; + case 1: /* Main oscillator => PLL0 */ + SystemCoreClock = (OSC_CLK * + ((2/*ULL*/ * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) / + (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) / + ((LPC_SC->CCLKCFG & 0xFF)+ 1)); + break; + case 2: /* RTC oscillator => PLL0 */ + SystemCoreClock = (RTC_CLK * + ((2/*ULL*/ * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) / + (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) / + ((LPC_SC->CCLKCFG & 0xFF)+ 1)); + break; + } + } else { + switch (LPC_SC->CLKSRCSEL & 0x03) { + case 0: /* Int. RC oscillator => PLL0 */ + case 3: /* Reserved, default to Int. RC */ + SystemCoreClock = IRC_OSC / ((LPC_SC->CCLKCFG & 0xFF)+ 1); + break; + case 1: /* Main oscillator => PLL0 */ + SystemCoreClock = OSC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1); + break; + case 2: /* RTC oscillator => PLL0 */ + SystemCoreClock = RTC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1); + break; + } + } + +} + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System. + */ +void SystemInit (void) +{ +#if (CLOCK_SETUP) /* Clock Setup */ + LPC_SC->SCS = SCS_Val; + if (SCS_Val & (1 << 5)) { /* If Main Oscillator is enabled */ + while ((LPC_SC->SCS & (1<<6)) == 0);/* Wait for Oscillator to be ready */ + } + + LPC_SC->CCLKCFG = CCLKCFG_Val; /* Setup Clock Divider */ + + LPC_SC->PCLKSEL0 = PCLKSEL0_Val; /* Peripheral Clock Selection */ + LPC_SC->PCLKSEL1 = PCLKSEL1_Val; + + LPC_SC->CLKSRCSEL = CLKSRCSEL_Val; /* Select Clock Source for PLL0 */ + +#if (PLL0_SETUP) + LPC_SC->PLL0CFG = PLL0CFG_Val; /* configure PLL0 */ + LPC_SC->PLL0FEED = 0xAA; + LPC_SC->PLL0FEED = 0x55; + + LPC_SC->PLL0CON = 0x01; /* PLL0 Enable */ + LPC_SC->PLL0FEED = 0xAA; + LPC_SC->PLL0FEED = 0x55; + while (!(LPC_SC->PLL0STAT & (1<<26)));/* Wait for PLOCK0 */ + + LPC_SC->PLL0CON = 0x03; /* PLL0 Enable & Connect */ + LPC_SC->PLL0FEED = 0xAA; + LPC_SC->PLL0FEED = 0x55; + while (!(LPC_SC->PLL0STAT & ((1<<25) | (1<<24))));/* Wait for PLLC0_STAT & PLLE0_STAT */ +#endif + +#if (PLL1_SETUP) + LPC_SC->PLL1CFG = PLL1CFG_Val; + LPC_SC->PLL1FEED = 0xAA; + LPC_SC->PLL1FEED = 0x55; + + LPC_SC->PLL1CON = 0x01; /* PLL1 Enable */ + LPC_SC->PLL1FEED = 0xAA; + LPC_SC->PLL1FEED = 0x55; + while (!(LPC_SC->PLL1STAT & (1<<10)));/* Wait for PLOCK1 */ + + LPC_SC->PLL1CON = 0x03; /* PLL1 Enable & Connect */ + LPC_SC->PLL1FEED = 0xAA; + LPC_SC->PLL1FEED = 0x55; + while (!(LPC_SC->PLL1STAT & ((1<< 9) | (1<< 8))));/* Wait for PLLC1_STAT & PLLE1_STAT */ +#else + LPC_SC->USBCLKCFG = USBCLKCFG_Val; /* Setup USB Clock Divider */ +#endif + + LPC_SC->PCONP = PCONP_Val; /* Power Control for Peripherals */ + + LPC_SC->CLKOUTCFG = CLKOUTCFG_Val; /* Clock Output Configuration */ +#endif + +#if (FLASH_SETUP == 1) /* Flash Accelerator Setup */ + LPC_SC->FLASHCFG = (LPC_SC->FLASHCFG & ~0x0000F000) | FLASHCFG_Val; +#endif +} diff --git a/platforms/lpc17xx/Makefile b/platforms/lpc17xx/Makefile new file mode 100644 index 0000000..172df5a --- /dev/null +++ b/platforms/lpc17xx/Makefile @@ -0,0 +1,95 @@ +ifeq ($(TARGET_NAME),) +TARGET_NAME=boot +endif +ifeq ($(ATOMTHREADS),) +ATOMTHREADS = $(shell pwd)/../../ +endif +ifeq ($(TEST_NAME),) +TEST_NAME = kern1 +endif + + + +CC = arm-none-eabi-gcc +LN = arm-none-eabi-gcc +AS = arm-none-eabi-gcc + +CFLAGS := $(CFLAGS) -O3 -Os -g3 -Wall -c -mcpu=cortex-m3 -mthumb +AFLAGS := $(AFLAGS) -O3 -Os -g3 -Wall -c -fmessage-length=0 -fno-builtin -ffunction-sections -fdata-sections -mcpu=cortex-m3 -mthumb +LFLAGS := $(LFLAGS) -O3 -Os -Wall -mcpu=cortex-m3 -mthumb -Wl,-Map=system.map -Tsystem.ld + +CDEFS := $(CDEFS) -DATOMTHREADS_TEST='"$(TEST_NAME)"' +ADEFS := $(ADEFS) -D__thumb2__ -DARM_RDI_MONITOR + +LLIBS := $(LLIBS) + + +SRCS := $(SRCS) \ + ./CMSISv2p00_LPC17xx/src/core_cm3.c \ + ./CMSISv2p00_LPC17xx/src/system_LPC17xx.c \ + ./drivers/lpc17xx_uart.c \ + startup.c \ + modules.c \ + $(ATOMTHREADS)/tests/$(TEST_NAME).c \ + main.c \ + + + +ASMS := $(ASMS) \ + + +INCLUDES := $(INCLUDES) \ + -I./CMSISv2p00_LPC17xx/inc \ + -I$(ATOMTHREADS) + +include $(ATOMTHREADS)/ports/cortex_m/Makefile + +OBJS = $(SRCS:.c=.o) $(ASMS:.S=.o) + +include ../rules.mk + +run_test: clean all + cp boot.bin bin/$(TEST_NAME).bin + +all_tests: + echo "Starting atomthreads test suite" + make run_test "TEST_NAME=mutex1" + make run_test "TEST_NAME=mutex2" + make run_test "TEST_NAME=mutex3" + make run_test "TEST_NAME=mutex4" + make run_test "TEST_NAME=mutex5" + make run_test "TEST_NAME=mutex6" + make run_test "TEST_NAME=mutex7" + make run_test "TEST_NAME=mutex8" + make run_test "TEST_NAME=mutex9" + make run_test "TEST_NAME=kern1" + make run_test "TEST_NAME=kern2" + make run_test "TEST_NAME=kern3" + make run_test "TEST_NAME=kern4" + make run_test "TEST_NAME=timer1" + make run_test "TEST_NAME=timer2" + make run_test "TEST_NAME=timer3" + make run_test "TEST_NAME=timer4" + make run_test "TEST_NAME=timer5" + make run_test "TEST_NAME=timer6" + make run_test "TEST_NAME=timer7" + make run_test "TEST_NAME=queue1" + make run_test "TEST_NAME=queue2" + make run_test "TEST_NAME=queue3" + make run_test "TEST_NAME=queue4" + make run_test "TEST_NAME=queue5" + make run_test "TEST_NAME=queue6" + make run_test "TEST_NAME=queue7" + make run_test "TEST_NAME=queue8" + make run_test "TEST_NAME=queue9" + make run_test "TEST_NAME=sem1" + make run_test "TEST_NAME=sem2" + make run_test "TEST_NAME=sem3" + make run_test "TEST_NAME=sem4" + make run_test "TEST_NAME=sem5" + make run_test "TEST_NAME=sem6" + make run_test "TEST_NAME=sem7" + make run_test "TEST_NAME=sem8" + make run_test "TEST_NAME=sem9" + + \ No newline at end of file diff --git a/platforms/lpc17xx/atomthreads_test.out b/platforms/lpc17xx/atomthreads_test.out new file mode 100644 index 0000000..510711a --- /dev/null +++ b/platforms/lpc17xx/atomthreads_test.out @@ -0,0 +1,153 @@ + +LPC17xx SystemCoreClock = 100000000 +Atomthreads starting mutex1... +mutex1 PASS + +LPC17xx SystemCoreClock = 100000000 +Atomthreads starting mutex2... +mutex2 PASS + +LPC17xx SystemCoreClock = 100000000 +Atomthreads starting mutex3... +mutex3 PASS + +LPC17xx SystemCoreClock = 100000000 +Atomthreads starting mutex5... +mutex5 PASS + +LPC17xx SystemCoreClock = 100000000 +Atomthreads starting mutex6... +mutex6 PASS + +LPC17xx SystemCoreClock = 100000000 +Atomthreads starting mutex7... +mutex7 PASS + +LPC17xx SystemCoreClock = 100000000 +Atomthreads starting mutex8... +mutex8 PASS + +LPC17xx SystemCoreClock = 100000000 +Atomthreads starting mutex9... +mutex9 PASS + +LPC17xx SystemCoreClock = 100000000 +Atomthreads starting kern1... +kern1 PASS + +LPC17xx SystemCoreClock = 100000000 +Atomthreads starting kern2... +kern2 PASS + +LPC17xx SystemCoreClock = 100000000 +Atomthreads starting kern3... +kern3 PASS + +LPC17xx SystemCoreClock = 100000000 +Atomthreads starting kern4... +kern4 PASS + +LPC17xx SystemCoreClock = 100000000 +Atomthreads starting timer1... +timer1 PASS + +LPC17xx SystemCoreClock = 100000000 +Atomthreads starting timer2... +timer2 PASS + +LPC17xx SystemCoreClock = 100000000 +Atomthreads starting timer3... +timer3 PASS + +LPC17xx SystemCoreClock = 100000000 +Atomthreads starting timer5... +timer5 PASS + +LPC17xx SystemCoreClock = 100000000 +Atomthreads starting timer6... +timer6 PASS + +LPC17xx SystemCoreClock = 100000000 +Atomthreads starting timer7... +timer7 PASS + +LPC17xx SystemCoreClock = 100000000 +Atomthreads starting queue1... +queue1 PASS + +LPC17xx SystemCoreClock = 100000000 +Atomthreads starting queue2... +queue2 PASS + +LPC17xx SystemCoreClock = 100000000 +Atomthreads starting queue3... +queue3 PASS + +LPC17xx SystemCoreClock = 100000000 +Atomthreads starting queue4... +queue4 PASS + +LPC17xx SystemCoreClock = 100000000 +Atomthreads starting queue5... +queue5 PASS + +LPC17xx SystemCoreClock = 100000000 +Atomthreads starting queue6... +queue6 PASS + +LPC17xx SystemCoreClock = 100000000 +Atomthreads starting queue7... +queue7 PASS + +LPC17xx SystemCoreClock = 100000000 +Atomthreads starting queue8... +queue8 PASS + +LPC17xx SystemCoreClock = 100000000 +Atomthreads starting queue9... +queue9 PASS + +LPC17xx SystemCoreClock = 100000000 +Atomthreads starting sem1... +sem1 PASS + +LPC17xx SystemCoreClock = 100000000 +Atomthreads starting sem2... +sem2 PASS + +LPC17xx SystemCoreClock = 100000000 +Atomthreads starting sem3... +sem3 PASS + +LPC17xx SystemCoreClock = 100000000 +Atomthreads starting sem5... +sem5 PASS + +LPC17xx SystemCoreClock = 100000000 +Atomthreads starting sem6... +sem6 PASS + +LPC17xx SystemCoreClock = 100000000 +Atomthreads starting sem7... +sem7 PASS + +LPC17xx SystemCoreClock = 100000000 +Atomthreads starting sem8... +sem8 PASS + +LPC17xx SystemCoreClock = 100000000 +Atomthreads starting sem9... +sem9 PASS + +LPC17xx SystemCoreClock = 100000000 +Atomthreads starting mutex4... +mutex4 PASS + +LPC17xx SystemCoreClock = 100000000 +Atomthreads starting sem4... +sem4 PASS + +LPC17xx SystemCoreClock = 100000000 +Atomthreads starting timer4... +timer4 PASS + diff --git a/platforms/lpc17xx/drivers/lpc17xx.h b/platforms/lpc17xx/drivers/lpc17xx.h new file mode 100644 index 0000000..377fdf2 --- /dev/null +++ b/platforms/lpc17xx/drivers/lpc17xx.h @@ -0,0 +1,1035 @@ +/**************************************************************************//** + * @file LPC17xx.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for + * NXP LPC17xx Device Series + * @version: V1.09 + * @date: 17. March 2010 + + * + * @note + * Copyright (C) 2009 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + + +#ifndef __LPC17xx_H__ +#define __LPC17xx_H__ + +/* + * ========================================================================== + * ---------- Interrupt Number Definition ----------------------------------- + * ========================================================================== + */ + +typedef enum IRQn +{ +/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ + +/****** LPC17xx Specific Interrupt Numbers *******************************************************/ + WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */ + TIMER0_IRQn = 1, /*!< Timer0 Interrupt */ + TIMER1_IRQn = 2, /*!< Timer1 Interrupt */ + TIMER2_IRQn = 3, /*!< Timer2 Interrupt */ + TIMER3_IRQn = 4, /*!< Timer3 Interrupt */ + UART0_IRQn = 5, /*!< UART0 Interrupt */ + UART1_IRQn = 6, /*!< UART1 Interrupt */ + UART2_IRQn = 7, /*!< UART2 Interrupt */ + UART3_IRQn = 8, /*!< UART3 Interrupt */ + PWM1_IRQn = 9, /*!< PWM1 Interrupt */ + I2C0_IRQn = 10, /*!< I2C0 Interrupt */ + I2C1_IRQn = 11, /*!< I2C1 Interrupt */ + I2C2_IRQn = 12, /*!< I2C2 Interrupt */ + SPI_IRQn = 13, /*!< SPI Interrupt */ + SSP0_IRQn = 14, /*!< SSP0 Interrupt */ + SSP1_IRQn = 15, /*!< SSP1 Interrupt */ + PLL0_IRQn = 16, /*!< PLL0 Lock (Main PLL) Interrupt */ + RTC_IRQn = 17, /*!< Real Time Clock Interrupt */ + EINT0_IRQn = 18, /*!< External Interrupt 0 Interrupt */ + EINT1_IRQn = 19, /*!< External Interrupt 1 Interrupt */ + EINT2_IRQn = 20, /*!< External Interrupt 2 Interrupt */ + EINT3_IRQn = 21, /*!< External Interrupt 3 Interrupt */ + ADC_IRQn = 22, /*!< A/D Converter Interrupt */ + BOD_IRQn = 23, /*!< Brown-Out Detect Interrupt */ + USB_IRQn = 24, /*!< USB Interrupt */ + CAN_IRQn = 25, /*!< CAN Interrupt */ + DMA_IRQn = 26, /*!< General Purpose DMA Interrupt */ + I2S_IRQn = 27, /*!< I2S Interrupt */ + ENET_IRQn = 28, /*!< Ethernet Interrupt */ + RIT_IRQn = 29, /*!< Repetitive Interrupt Timer Interrupt */ + MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */ + QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */ + PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */ + USBActivity_IRQn = 33, /* USB Activity interrupt */ + CANActivity_IRQn = 34, /* CAN Activity interrupt */ +} IRQn_Type; + + +/* + * ========================================================================== + * ----------- Processor and Core Peripheral Section ------------------------ + * ========================================================================== + */ + +/* Configuration of the Cortex-M3 Processor and Core Peripherals */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + + +#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */ +#include "system_LPC17xx.h" /* System Header */ + + +/******************************************************************************/ +/* Device Specific Peripheral registers structures */ +/******************************************************************************/ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/*------------- System Control (SC) ------------------------------------------*/ +typedef struct +{ + __IO uint32_t FLASHCFG; /* Flash Accelerator Module */ + uint32_t RESERVED0[31]; + __IO uint32_t PLL0CON; /* Clocking and Power Control */ + __IO uint32_t PLL0CFG; + __I uint32_t PLL0STAT; + __O uint32_t PLL0FEED; + uint32_t RESERVED1[4]; + __IO uint32_t PLL1CON; + __IO uint32_t PLL1CFG; + __I uint32_t PLL1STAT; + __O uint32_t PLL1FEED; + uint32_t RESERVED2[4]; + __IO uint32_t PCON; + __IO uint32_t PCONP; + uint32_t RESERVED3[15]; + __IO uint32_t CCLKCFG; + __IO uint32_t USBCLKCFG; + __IO uint32_t CLKSRCSEL; + __IO uint32_t CANSLEEPCLR; + __IO uint32_t CANWAKEFLAGS; + uint32_t RESERVED4[10]; + __IO uint32_t EXTINT; /* External Interrupts */ + uint32_t RESERVED5; + __IO uint32_t EXTMODE; + __IO uint32_t EXTPOLAR; + uint32_t RESERVED6[12]; + __IO uint32_t RSID; /* Reset */ + uint32_t RESERVED7[7]; + __IO uint32_t SCS; /* Syscon Miscellaneous Registers */ + __IO uint32_t IRCTRIM; /* Clock Dividers */ + __IO uint32_t PCLKSEL0; + __IO uint32_t PCLKSEL1; + uint32_t RESERVED8[4]; + __IO uint32_t USBIntSt; /* USB Device/OTG Interrupt Register */ + __IO uint32_t DMAREQSEL; + __IO uint32_t CLKOUTCFG; /* Clock Output Configuration */ + } LPC_SC_TypeDef; + +/*------------- Pin Connect Block (PINCON) -----------------------------------*/ +typedef struct +{ + __IO uint32_t PINSEL0; + __IO uint32_t PINSEL1; + __IO uint32_t PINSEL2; + __IO uint32_t PINSEL3; + __IO uint32_t PINSEL4; + __IO uint32_t PINSEL5; + __IO uint32_t PINSEL6; + __IO uint32_t PINSEL7; + __IO uint32_t PINSEL8; + __IO uint32_t PINSEL9; + __IO uint32_t PINSEL10; + uint32_t RESERVED0[5]; + __IO uint32_t PINMODE0; + __IO uint32_t PINMODE1; + __IO uint32_t PINMODE2; + __IO uint32_t PINMODE3; + __IO uint32_t PINMODE4; + __IO uint32_t PINMODE5; + __IO uint32_t PINMODE6; + __IO uint32_t PINMODE7; + __IO uint32_t PINMODE8; + __IO uint32_t PINMODE9; + __IO uint32_t PINMODE_OD0; + __IO uint32_t PINMODE_OD1; + __IO uint32_t PINMODE_OD2; + __IO uint32_t PINMODE_OD3; + __IO uint32_t PINMODE_OD4; + __IO uint32_t I2CPADCFG; +} LPC_PINCON_TypeDef; + +/*------------- General Purpose Input/Output (GPIO) --------------------------*/ +typedef struct +{ + union { + __IO uint32_t FIODIR; + struct { + __IO uint16_t FIODIRL; + __IO uint16_t FIODIRH; + }; + struct { + __IO uint8_t FIODIR0; + __IO uint8_t FIODIR1; + __IO uint8_t FIODIR2; + __IO uint8_t FIODIR3; + }; + }; + uint32_t RESERVED0[3]; + union { + __IO uint32_t FIOMASK; + struct { + __IO uint16_t FIOMASKL; + __IO uint16_t FIOMASKH; + }; + struct { + __IO uint8_t FIOMASK0; + __IO uint8_t FIOMASK1; + __IO uint8_t FIOMASK2; + __IO uint8_t FIOMASK3; + }; + }; + union { + __IO uint32_t FIOPIN; + struct { + __IO uint16_t FIOPINL; + __IO uint16_t FIOPINH; + }; + struct { + __IO uint8_t FIOPIN0; + __IO uint8_t FIOPIN1; + __IO uint8_t FIOPIN2; + __IO uint8_t FIOPIN3; + }; + }; + union { + __IO uint32_t FIOSET; + struct { + __IO uint16_t FIOSETL; + __IO uint16_t FIOSETH; + }; + struct { + __IO uint8_t FIOSET0; + __IO uint8_t FIOSET1; + __IO uint8_t FIOSET2; + __IO uint8_t FIOSET3; + }; + }; + union { + __O uint32_t FIOCLR; + struct { + __O uint16_t FIOCLRL; + __O uint16_t FIOCLRH; + }; + struct { + __O uint8_t FIOCLR0; + __O uint8_t FIOCLR1; + __O uint8_t FIOCLR2; + __O uint8_t FIOCLR3; + }; + }; +} LPC_GPIO_TypeDef; + +typedef struct +{ + __I uint32_t IntStatus; + __I uint32_t IO0IntStatR; + __I uint32_t IO0IntStatF; + __O uint32_t IO0IntClr; + __IO uint32_t IO0IntEnR; + __IO uint32_t IO0IntEnF; + uint32_t RESERVED0[3]; + __I uint32_t IO2IntStatR; + __I uint32_t IO2IntStatF; + __O uint32_t IO2IntClr; + __IO uint32_t IO2IntEnR; + __IO uint32_t IO2IntEnF; +} LPC_GPIOINT_TypeDef; + +/*------------- Timer (TIM) --------------------------------------------------*/ +typedef struct +{ + __IO uint32_t IR; + __IO uint32_t TCR; + __IO uint32_t TC; + __IO uint32_t PR; + __IO uint32_t PC; + __IO uint32_t MCR; + __IO uint32_t MR0; + __IO uint32_t MR1; + __IO uint32_t MR2; + __IO uint32_t MR3; + __IO uint32_t CCR; + __I uint32_t CR0; + __I uint32_t CR1; + uint32_t RESERVED0[2]; + __IO uint32_t EMR; + uint32_t RESERVED1[12]; + __IO uint32_t CTCR; +} LPC_TIM_TypeDef; + +/*------------- Pulse-Width Modulation (PWM) ---------------------------------*/ +typedef struct +{ + __IO uint32_t IR; + __IO uint32_t TCR; + __IO uint32_t TC; + __IO uint32_t PR; + __IO uint32_t PC; + __IO uint32_t MCR; + __IO uint32_t MR0; + __IO uint32_t MR1; + __IO uint32_t MR2; + __IO uint32_t MR3; + __IO uint32_t CCR; + __I uint32_t CR0; + __I uint32_t CR1; + __I uint32_t CR2; + __I uint32_t CR3; + uint32_t RESERVED0; + __IO uint32_t MR4; + __IO uint32_t MR5; + __IO uint32_t MR6; + __IO uint32_t PCR; + __IO uint32_t LER; + uint32_t RESERVED1[7]; + __IO uint32_t CTCR; +} LPC_PWM_TypeDef; + +/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/ +typedef struct +{ + union { + __I uint8_t RBR; + __O uint8_t THR; + __IO uint8_t DLL; + uint32_t RESERVED0; + }; + union { + __IO uint8_t DLM; + __IO uint32_t IER; + }; + union { + __I uint32_t IIR; + __O uint8_t FCR; + }; + __IO uint8_t LCR; + uint8_t RESERVED1[7]; + __I uint8_t LSR; + uint8_t RESERVED2[7]; + __IO uint8_t SCR; + uint8_t RESERVED3[3]; + __IO uint32_t ACR; + __IO uint8_t ICR; + uint8_t RESERVED4[3]; + __IO uint8_t FDR; + uint8_t RESERVED5[7]; + __IO uint8_t TER; + uint8_t RESERVED6[39]; + __IO uint32_t FIFOLVL; +} LPC_UART_TypeDef; + +typedef struct +{ + union { + __I uint8_t RBR; + __O uint8_t THR; + __IO uint8_t DLL; + uint32_t RESERVED0; + }; + union { + __IO uint8_t DLM; + __IO uint32_t IER; + }; + union { + __I uint32_t IIR; + __O uint8_t FCR; + }; + __IO uint8_t LCR; + uint8_t RESERVED1[7]; + __I uint8_t LSR; + uint8_t RESERVED2[7]; + __IO uint8_t SCR; + uint8_t RESERVED3[3]; + __IO uint32_t ACR; + __IO uint8_t ICR; + uint8_t RESERVED4[3]; + __IO uint8_t FDR; + uint8_t RESERVED5[7]; + __IO uint8_t TER; + uint8_t RESERVED6[39]; + __IO uint32_t FIFOLVL; +} LPC_UART0_TypeDef; + +typedef struct +{ + union { + __I uint8_t RBR; + __O uint8_t THR; + __IO uint8_t DLL; + uint32_t RESERVED0; + }; + union { + __IO uint8_t DLM; + __IO uint32_t IER; + }; + union { + __I uint32_t IIR; + __O uint8_t FCR; + }; + __IO uint8_t LCR; + uint8_t RESERVED1[3]; + __IO uint8_t MCR; + uint8_t RESERVED2[3]; + __I uint8_t LSR; + uint8_t RESERVED3[3]; + __I uint8_t MSR; + uint8_t RESERVED4[3]; + __IO uint8_t SCR; + uint8_t RESERVED5[3]; + __IO uint32_t ACR; + uint32_t RESERVED6; + __IO uint32_t FDR; + uint32_t RESERVED7; + __IO uint8_t TER; + uint8_t RESERVED8[27]; + __IO uint8_t RS485CTRL; + uint8_t RESERVED9[3]; + __IO uint8_t ADRMATCH; + uint8_t RESERVED10[3]; + __IO uint8_t RS485DLY; + uint8_t RESERVED11[3]; + __IO uint32_t FIFOLVL; +} LPC_UART1_TypeDef; + +/*------------- Serial Peripheral Interface (SPI) ----------------------------*/ +typedef struct +{ + __IO uint32_t SPCR; + __I uint32_t SPSR; + __IO uint32_t SPDR; + __IO uint32_t SPCCR; + uint32_t RESERVED0[3]; + __IO uint32_t SPINT; +} LPC_SPI_TypeDef; + +/*------------- Synchronous Serial Communication (SSP) -----------------------*/ +typedef struct +{ + __IO uint32_t CR0; + __IO uint32_t CR1; + __IO uint32_t DR; + __I uint32_t SR; + __IO uint32_t CPSR; + __IO uint32_t IMSC; + __IO uint32_t RIS; + __IO uint32_t MIS; + __IO uint32_t ICR; + __IO uint32_t DMACR; +} LPC_SSP_TypeDef; + +/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/ +typedef struct +{ + __IO uint32_t I2CONSET; + __I uint32_t I2STAT; + __IO uint32_t I2DAT; + __IO uint32_t I2ADR0; + __IO uint32_t I2SCLH; + __IO uint32_t I2SCLL; + __O uint32_t I2CONCLR; + __IO uint32_t MMCTRL; + __IO uint32_t I2ADR1; + __IO uint32_t I2ADR2; + __IO uint32_t I2ADR3; + __I uint32_t I2DATA_BUFFER; + __IO uint32_t I2MASK0; + __IO uint32_t I2MASK1; + __IO uint32_t I2MASK2; + __IO uint32_t I2MASK3; +} LPC_I2C_TypeDef; + +/*------------- Inter IC Sound (I2S) -----------------------------------------*/ +typedef struct +{ + __IO uint32_t I2SDAO; + __IO uint32_t I2SDAI; + __O uint32_t I2STXFIFO; + __I uint32_t I2SRXFIFO; + __I uint32_t I2SSTATE; + __IO uint32_t I2SDMA1; + __IO uint32_t I2SDMA2; + __IO uint32_t I2SIRQ; + __IO uint32_t I2STXRATE; + __IO uint32_t I2SRXRATE; + __IO uint32_t I2STXBITRATE; + __IO uint32_t I2SRXBITRATE; + __IO uint32_t I2STXMODE; + __IO uint32_t I2SRXMODE; +} LPC_I2S_TypeDef; + +/*------------- Repetitive Interrupt Timer (RIT) -----------------------------*/ +typedef struct +{ + __IO uint32_t RICOMPVAL; + __IO uint32_t RIMASK; + __IO uint8_t RICTRL; + uint8_t RESERVED0[3]; + __IO uint32_t RICOUNTER; +} LPC_RIT_TypeDef; + +/*------------- Real-Time Clock (RTC) ----------------------------------------*/ +typedef struct +{ + __IO uint8_t ILR; + uint8_t RESERVED0[7]; + __IO uint8_t CCR; + uint8_t RESERVED1[3]; + __IO uint8_t CIIR; + uint8_t RESERVED2[3]; + __IO uint8_t AMR; + uint8_t RESERVED3[3]; + __I uint32_t CTIME0; + __I uint32_t CTIME1; + __I uint32_t CTIME2; + __IO uint8_t SEC; + uint8_t RESERVED4[3]; + __IO uint8_t MIN; + uint8_t RESERVED5[3]; + __IO uint8_t HOUR; + uint8_t RESERVED6[3]; + __IO uint8_t DOM; + uint8_t RESERVED7[3]; + __IO uint8_t DOW; + uint8_t RESERVED8[3]; + __IO uint16_t DOY; + uint16_t RESERVED9; + __IO uint8_t MONTH; + uint8_t RESERVED10[3]; + __IO uint16_t YEAR; + uint16_t RESERVED11; + __IO uint32_t CALIBRATION; + __IO uint32_t GPREG0; + __IO uint32_t GPREG1; + __IO uint32_t GPREG2; + __IO uint32_t GPREG3; + __IO uint32_t GPREG4; + __IO uint8_t RTC_AUXEN; + uint8_t RESERVED12[3]; + __IO uint8_t RTC_AUX; + uint8_t RESERVED13[3]; + __IO uint8_t ALSEC; + uint8_t RESERVED14[3]; + __IO uint8_t ALMIN; + uint8_t RESERVED15[3]; + __IO uint8_t ALHOUR; + uint8_t RESERVED16[3]; + __IO uint8_t ALDOM; + uint8_t RESERVED17[3]; + __IO uint8_t ALDOW; + uint8_t RESERVED18[3]; + __IO uint16_t ALDOY; + uint16_t RESERVED19; + __IO uint8_t ALMON; + uint8_t RESERVED20[3]; + __IO uint16_t ALYEAR; + uint16_t RESERVED21; +} LPC_RTC_TypeDef; + +/*------------- Watchdog Timer (WDT) -----------------------------------------*/ +typedef struct +{ + __IO uint8_t WDMOD; + uint8_t RESERVED0[3]; + __IO uint32_t WDTC; + __O uint8_t WDFEED; + uint8_t RESERVED1[3]; + __I uint32_t WDTV; + __IO uint32_t WDCLKSEL; +} LPC_WDT_TypeDef; + +/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/ +typedef struct +{ + __IO uint32_t ADCR; + __IO uint32_t ADGDR; + uint32_t RESERVED0; + __IO uint32_t ADINTEN; + __I uint32_t ADDR0; + __I uint32_t ADDR1; + __I uint32_t ADDR2; + __I uint32_t ADDR3; + __I uint32_t ADDR4; + __I uint32_t ADDR5; + __I uint32_t ADDR6; + __I uint32_t ADDR7; + __I uint32_t ADSTAT; + __IO uint32_t ADTRM; +} LPC_ADC_TypeDef; + +/*------------- Digital-to-Analog Converter (DAC) ----------------------------*/ +typedef struct +{ + __IO uint32_t DACR; + __IO uint32_t DACCTRL; + __IO uint16_t DACCNTVAL; +} LPC_DAC_TypeDef; + +/*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/ +typedef struct +{ + __I uint32_t MCCON; + __O uint32_t MCCON_SET; + __O uint32_t MCCON_CLR; + __I uint32_t MCCAPCON; + __O uint32_t MCCAPCON_SET; + __O uint32_t MCCAPCON_CLR; + __IO uint32_t MCTIM0; + __IO uint32_t MCTIM1; + __IO uint32_t MCTIM2; + __IO uint32_t MCPER0; + __IO uint32_t MCPER1; + __IO uint32_t MCPER2; + __IO uint32_t MCPW0; + __IO uint32_t MCPW1; + __IO uint32_t MCPW2; + __IO uint32_t MCDEADTIME; + __IO uint32_t MCCCP; + __IO uint32_t MCCR0; + __IO uint32_t MCCR1; + __IO uint32_t MCCR2; + __I uint32_t MCINTEN; + __O uint32_t MCINTEN_SET; + __O uint32_t MCINTEN_CLR; + __I uint32_t MCCNTCON; + __O uint32_t MCCNTCON_SET; + __O uint32_t MCCNTCON_CLR; + __I uint32_t MCINTFLAG; + __O uint32_t MCINTFLAG_SET; + __O uint32_t MCINTFLAG_CLR; + __O uint32_t MCCAP_CLR; +} LPC_MCPWM_TypeDef; + +/*------------- Quadrature Encoder Interface (QEI) ---------------------------*/ +typedef struct +{ + __O uint32_t QEICON; + __I uint32_t QEISTAT; + __IO uint32_t QEICONF; + __I uint32_t QEIPOS; + __IO uint32_t QEIMAXPOS; + __IO uint32_t CMPOS0; + __IO uint32_t CMPOS1; + __IO uint32_t CMPOS2; + __I uint32_t INXCNT; + __IO uint32_t INXCMP; + __IO uint32_t QEILOAD; + __I uint32_t QEITIME; + __I uint32_t QEIVEL; + __I uint32_t QEICAP; + __IO uint32_t VELCOMP; + __IO uint32_t FILTER; + uint32_t RESERVED0[998]; + __O uint32_t QEIIEC; + __O uint32_t QEIIES; + __I uint32_t QEIINTSTAT; + __I uint32_t QEIIE; + __O uint32_t QEICLR; + __O uint32_t QEISET; +} LPC_QEI_TypeDef; + +/*------------- Controller Area Network (CAN) --------------------------------*/ +typedef struct +{ + __IO uint32_t mask[512]; /* ID Masks */ +} LPC_CANAF_RAM_TypeDef; + +typedef struct /* Acceptance Filter Registers */ +{ + __IO uint32_t AFMR; + __IO uint32_t SFF_sa; + __IO uint32_t SFF_GRP_sa; + __IO uint32_t EFF_sa; + __IO uint32_t EFF_GRP_sa; + __IO uint32_t ENDofTable; + __I uint32_t LUTerrAd; + __I uint32_t LUTerr; + __IO uint32_t FCANIE; + __IO uint32_t FCANIC0; + __IO uint32_t FCANIC1; +} LPC_CANAF_TypeDef; + +typedef struct /* Central Registers */ +{ + __I uint32_t CANTxSR; + __I uint32_t CANRxSR; + __I uint32_t CANMSR; +} LPC_CANCR_TypeDef; + +typedef struct /* Controller Registers */ +{ + __IO uint32_t MOD; + __O uint32_t CMR; + __IO uint32_t GSR; + __I uint32_t ICR; + __IO uint32_t IER; + __IO uint32_t BTR; + __IO uint32_t EWL; + __I uint32_t SR; + __IO uint32_t RFS; + __IO uint32_t RID; + __IO uint32_t RDA; + __IO uint32_t RDB; + __IO uint32_t TFI1; + __IO uint32_t TID1; + __IO uint32_t TDA1; + __IO uint32_t TDB1; + __IO uint32_t TFI2; + __IO uint32_t TID2; + __IO uint32_t TDA2; + __IO uint32_t TDB2; + __IO uint32_t TFI3; + __IO uint32_t TID3; + __IO uint32_t TDA3; + __IO uint32_t TDB3; +} LPC_CAN_TypeDef; + +/*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/ +typedef struct /* Common Registers */ +{ + __I uint32_t DMACIntStat; + __I uint32_t DMACIntTCStat; + __O uint32_t DMACIntTCClear; + __I uint32_t DMACIntErrStat; + __O uint32_t DMACIntErrClr; + __I uint32_t DMACRawIntTCStat; + __I uint32_t DMACRawIntErrStat; + __I uint32_t DMACEnbldChns; + __IO uint32_t DMACSoftBReq; + __IO uint32_t DMACSoftSReq; + __IO uint32_t DMACSoftLBReq; + __IO uint32_t DMACSoftLSReq; + __IO uint32_t DMACConfig; + __IO uint32_t DMACSync; +} LPC_GPDMA_TypeDef; + +typedef struct /* Channel Registers */ +{ + __IO uint32_t DMACCSrcAddr; + __IO uint32_t DMACCDestAddr; + __IO uint32_t DMACCLLI; + __IO uint32_t DMACCControl; + __IO uint32_t DMACCConfig; +} LPC_GPDMACH_TypeDef; + +/*------------- Universal Serial Bus (USB) -----------------------------------*/ +typedef struct +{ + __I uint32_t HcRevision; /* USB Host Registers */ + __IO uint32_t HcControl; + __IO uint32_t HcCommandStatus; + __IO uint32_t HcInterruptStatus; + __IO uint32_t HcInterruptEnable; + __IO uint32_t HcInterruptDisable; + __IO uint32_t HcHCCA; + __I uint32_t HcPeriodCurrentED; + __IO uint32_t HcControlHeadED; + __IO uint32_t HcControlCurrentED; + __IO uint32_t HcBulkHeadED; + __IO uint32_t HcBulkCurrentED; + __I uint32_t HcDoneHead; + __IO uint32_t HcFmInterval; + __I uint32_t HcFmRemaining; + __I uint32_t HcFmNumber; + __IO uint32_t HcPeriodicStart; + __IO uint32_t HcLSTreshold; + __IO uint32_t HcRhDescriptorA; + __IO uint32_t HcRhDescriptorB; + __IO uint32_t HcRhStatus; + __IO uint32_t HcRhPortStatus1; + __IO uint32_t HcRhPortStatus2; + uint32_t RESERVED0[40]; + __I uint32_t Module_ID; + + __I uint32_t OTGIntSt; /* USB On-The-Go Registers */ + __IO uint32_t OTGIntEn; + __O uint32_t OTGIntSet; + __O uint32_t OTGIntClr; + __IO uint32_t OTGStCtrl; + __IO uint32_t OTGTmr; + uint32_t RESERVED1[58]; + + __I uint32_t USBDevIntSt; /* USB Device Interrupt Registers */ + __IO uint32_t USBDevIntEn; + __O uint32_t USBDevIntClr; + __O uint32_t USBDevIntSet; + + __O uint32_t USBCmdCode; /* USB Device SIE Command Registers */ + __I uint32_t USBCmdData; + + __I uint32_t USBRxData; /* USB Device Transfer Registers */ + __O uint32_t USBTxData; + __I uint32_t USBRxPLen; + __O uint32_t USBTxPLen; + __IO uint32_t USBCtrl; + __O uint32_t USBDevIntPri; + + __I uint32_t USBEpIntSt; /* USB Device Endpoint Interrupt Regs */ + __IO uint32_t USBEpIntEn; + __O uint32_t USBEpIntClr; + __O uint32_t USBEpIntSet; + __O uint32_t USBEpIntPri; + + __IO uint32_t USBReEp; /* USB Device Endpoint Realization Reg*/ + __O uint32_t USBEpInd; + __IO uint32_t USBMaxPSize; + + __I uint32_t USBDMARSt; /* USB Device DMA Registers */ + __O uint32_t USBDMARClr; + __O uint32_t USBDMARSet; + uint32_t RESERVED2[9]; + __IO uint32_t USBUDCAH; + __I uint32_t USBEpDMASt; + __O uint32_t USBEpDMAEn; + __O uint32_t USBEpDMADis; + __I uint32_t USBDMAIntSt; + __IO uint32_t USBDMAIntEn; + uint32_t RESERVED3[2]; + __I uint32_t USBEoTIntSt; + __O uint32_t USBEoTIntClr; + __O uint32_t USBEoTIntSet; + __I uint32_t USBNDDRIntSt; + __O uint32_t USBNDDRIntClr; + __O uint32_t USBNDDRIntSet; + __I uint32_t USBSysErrIntSt; + __O uint32_t USBSysErrIntClr; + __O uint32_t USBSysErrIntSet; + uint32_t RESERVED4[15]; + + union { + __I uint32_t I2C_RX; /* USB OTG I2C Registers */ + __O uint32_t I2C_TX; + }; + __I uint32_t I2C_STS; + __IO uint32_t I2C_CTL; + __IO uint32_t I2C_CLKHI; + __O uint32_t I2C_CLKLO; + uint32_t RESERVED5[824]; + + union { + __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */ + __IO uint32_t OTGClkCtrl; + }; + union { + __I uint32_t USBClkSt; + __I uint32_t OTGClkSt; + }; +} LPC_USB_TypeDef; + +/*------------- Ethernet Media Access Controller (EMAC) ----------------------*/ +typedef struct +{ + __IO uint32_t MAC1; /* MAC Registers */ + __IO uint32_t MAC2; + __IO uint32_t IPGT; + __IO uint32_t IPGR; + __IO uint32_t CLRT; + __IO uint32_t MAXF; + __IO uint32_t SUPP; + __IO uint32_t TEST; + __IO uint32_t MCFG; + __IO uint32_t MCMD; + __IO uint32_t MADR; + __O uint32_t MWTD; + __I uint32_t MRDD; + __I uint32_t MIND; + uint32_t RESERVED0[2]; + __IO uint32_t SA0; + __IO uint32_t SA1; + __IO uint32_t SA2; + uint32_t RESERVED1[45]; + __IO uint32_t Command; /* Control Registers */ + __I uint32_t Status; + __IO uint32_t RxDescriptor; + __IO uint32_t RxStatus; + __IO uint32_t RxDescriptorNumber; + __I uint32_t RxProduceIndex; + __IO uint32_t RxConsumeIndex; + __IO uint32_t TxDescriptor; + __IO uint32_t TxStatus; + __IO uint32_t TxDescriptorNumber; + __IO uint32_t TxProduceIndex; + __I uint32_t TxConsumeIndex; + uint32_t RESERVED2[10]; + __I uint32_t TSV0; + __I uint32_t TSV1; + __I uint32_t RSV; + uint32_t RESERVED3[3]; + __IO uint32_t FlowControlCounter; + __I uint32_t FlowControlStatus; + uint32_t RESERVED4[34]; + __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */ + __IO uint32_t RxFilterWoLStatus; + __IO uint32_t RxFilterWoLClear; + uint32_t RESERVED5; + __IO uint32_t HashFilterL; + __IO uint32_t HashFilterH; + uint32_t RESERVED6[882]; + __I uint32_t IntStatus; /* Module Control Registers */ + __IO uint32_t IntEnable; + __O uint32_t IntClear; + __O uint32_t IntSet; + uint32_t RESERVED7; + __IO uint32_t PowerDown; + uint32_t RESERVED8; + __IO uint32_t Module_ID; +} LPC_EMAC_TypeDef; + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + + +/******************************************************************************/ +/* Peripheral memory map */ +/******************************************************************************/ +/* Base addresses */ +#define LPC_FLASH_BASE (0x00000000UL) +#define LPC_RAM_BASE (0x10000000UL) +#define LPC_GPIO_BASE (0x2009C000UL) +#define LPC_APB0_BASE (0x40000000UL) +#define LPC_APB1_BASE (0x40080000UL) +#define LPC_AHB_BASE (0x50000000UL) +#define LPC_CM3_BASE (0xE0000000UL) + +/* APB0 peripherals */ +#define LPC_WDT_BASE (LPC_APB0_BASE + 0x00000) +#define LPC_TIM0_BASE (LPC_APB0_BASE + 0x04000) +#define LPC_TIM1_BASE (LPC_APB0_BASE + 0x08000) +#define LPC_UART0_BASE (LPC_APB0_BASE + 0x0C000) +#define LPC_UART1_BASE (LPC_APB0_BASE + 0x10000) +#define LPC_PWM1_BASE (LPC_APB0_BASE + 0x18000) +#define LPC_I2C0_BASE (LPC_APB0_BASE + 0x1C000) +#define LPC_SPI_BASE (LPC_APB0_BASE + 0x20000) +#define LPC_RTC_BASE (LPC_APB0_BASE + 0x24000) +#define LPC_GPIOINT_BASE (LPC_APB0_BASE + 0x28080) +#define LPC_PINCON_BASE (LPC_APB0_BASE + 0x2C000) +#define LPC_SSP1_BASE (LPC_APB0_BASE + 0x30000) +#define LPC_ADC_BASE (LPC_APB0_BASE + 0x34000) +#define LPC_CANAF_RAM_BASE (LPC_APB0_BASE + 0x38000) +#define LPC_CANAF_BASE (LPC_APB0_BASE + 0x3C000) +#define LPC_CANCR_BASE (LPC_APB0_BASE + 0x40000) +#define LPC_CAN1_BASE (LPC_APB0_BASE + 0x44000) +#define LPC_CAN2_BASE (LPC_APB0_BASE + 0x48000) +#define LPC_I2C1_BASE (LPC_APB0_BASE + 0x5C000) + +/* APB1 peripherals */ +#define LPC_SSP0_BASE (LPC_APB1_BASE + 0x08000) +#define LPC_DAC_BASE (LPC_APB1_BASE + 0x0C000) +#define LPC_TIM2_BASE (LPC_APB1_BASE + 0x10000) +#define LPC_TIM3_BASE (LPC_APB1_BASE + 0x14000) +#define LPC_UART2_BASE (LPC_APB1_BASE + 0x18000) +#define LPC_UART3_BASE (LPC_APB1_BASE + 0x1C000) +#define LPC_I2C2_BASE (LPC_APB1_BASE + 0x20000) +#define LPC_I2S_BASE (LPC_APB1_BASE + 0x28000) +#define LPC_RIT_BASE (LPC_APB1_BASE + 0x30000) +#define LPC_MCPWM_BASE (LPC_APB1_BASE + 0x38000) +#define LPC_QEI_BASE (LPC_APB1_BASE + 0x3C000) +#define LPC_SC_BASE (LPC_APB1_BASE + 0x7C000) + +/* AHB peripherals */ +#define LPC_EMAC_BASE (LPC_AHB_BASE + 0x00000) +#define LPC_GPDMA_BASE (LPC_AHB_BASE + 0x04000) +#define LPC_GPDMACH0_BASE (LPC_AHB_BASE + 0x04100) +#define LPC_GPDMACH1_BASE (LPC_AHB_BASE + 0x04120) +#define LPC_GPDMACH2_BASE (LPC_AHB_BASE + 0x04140) +#define LPC_GPDMACH3_BASE (LPC_AHB_BASE + 0x04160) +#define LPC_GPDMACH4_BASE (LPC_AHB_BASE + 0x04180) +#define LPC_GPDMACH5_BASE (LPC_AHB_BASE + 0x041A0) +#define LPC_GPDMACH6_BASE (LPC_AHB_BASE + 0x041C0) +#define LPC_GPDMACH7_BASE (LPC_AHB_BASE + 0x041E0) +#define LPC_USB_BASE (LPC_AHB_BASE + 0x0C000) + +/* GPIOs */ +#define LPC_GPIO0_BASE (LPC_GPIO_BASE + 0x00000) +#define LPC_GPIO1_BASE (LPC_GPIO_BASE + 0x00020) +#define LPC_GPIO2_BASE (LPC_GPIO_BASE + 0x00040) +#define LPC_GPIO3_BASE (LPC_GPIO_BASE + 0x00060) +#define LPC_GPIO4_BASE (LPC_GPIO_BASE + 0x00080) + + +/******************************************************************************/ +/* Peripheral declaration */ +/******************************************************************************/ +#define LPC_SC ((LPC_SC_TypeDef *) LPC_SC_BASE ) +#define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE ) +#define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE ) +#define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE ) +#define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE ) +#define LPC_GPIO4 ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE ) +#define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE ) +#define LPC_TIM0 ((LPC_TIM_TypeDef *) LPC_TIM0_BASE ) +#define LPC_TIM1 ((LPC_TIM_TypeDef *) LPC_TIM1_BASE ) +#define LPC_TIM2 ((LPC_TIM_TypeDef *) LPC_TIM2_BASE ) +#define LPC_TIM3 ((LPC_TIM_TypeDef *) LPC_TIM3_BASE ) +#define LPC_RIT ((LPC_RIT_TypeDef *) LPC_RIT_BASE ) +#define LPC_UART0 ((LPC_UART0_TypeDef *) LPC_UART0_BASE ) +#define LPC_UART1 ((LPC_UART1_TypeDef *) LPC_UART1_BASE ) +#define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE ) +#define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE ) +#define LPC_PWM1 ((LPC_PWM_TypeDef *) LPC_PWM1_BASE ) +#define LPC_I2C0 ((LPC_I2C_TypeDef *) LPC_I2C0_BASE ) +#define LPC_I2C1 ((LPC_I2C_TypeDef *) LPC_I2C1_BASE ) +#define LPC_I2C2 ((LPC_I2C_TypeDef *) LPC_I2C2_BASE ) +#define LPC_I2S ((LPC_I2S_TypeDef *) LPC_I2S_BASE ) +#define LPC_SPI ((LPC_SPI_TypeDef *) LPC_SPI_BASE ) +#define LPC_RTC ((LPC_RTC_TypeDef *) LPC_RTC_BASE ) +#define LPC_GPIOINT ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE ) +#define LPC_PINCON ((LPC_PINCON_TypeDef *) LPC_PINCON_BASE ) +#define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE ) +#define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE ) +#define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE ) +#define LPC_DAC ((LPC_DAC_TypeDef *) LPC_DAC_BASE ) +#define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE) +#define LPC_CANAF ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE ) +#define LPC_CANCR ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE ) +#define LPC_CAN1 ((LPC_CAN_TypeDef *) LPC_CAN1_BASE ) +#define LPC_CAN2 ((LPC_CAN_TypeDef *) LPC_CAN2_BASE ) +#define LPC_MCPWM ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE ) +#define LPC_QEI ((LPC_QEI_TypeDef *) LPC_QEI_BASE ) +#define LPC_EMAC ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE ) +#define LPC_GPDMA ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE ) +#define LPC_GPDMACH0 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE ) +#define LPC_GPDMACH1 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE ) +#define LPC_GPDMACH2 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE ) +#define LPC_GPDMACH3 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE ) +#define LPC_GPDMACH4 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE ) +#define LPC_GPDMACH5 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE ) +#define LPC_GPDMACH6 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE ) +#define LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE ) +#define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE ) + +#endif // __LPC17xx_H__ diff --git a/platforms/lpc17xx/drivers/lpc17xx_uart.c b/platforms/lpc17xx/drivers/lpc17xx_uart.c new file mode 100644 index 0000000..3a0202f --- /dev/null +++ b/platforms/lpc17xx/drivers/lpc17xx_uart.c @@ -0,0 +1,166 @@ +/**************************************************************************//** + * @file lpc17xx_uart.c + * @brief Drivers for UART peripheral in lpc17xx. + * @version 1.0 + * @date 18. Nov. 2010 + * + * @note + * Copyright (C) 2010 NXP Semiconductors(NXP). All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * products. This software is supplied "AS IS" without any warranties. + * NXP Semiconductors assumes no responsibility or liability for the + * use of the software, conveys no license or title under any patent, + * copyright, or mask work right to the product. NXP Semiconductors + * reserves the right to make changes in the software without + * notification. NXP Semiconductors also make no representation or + * warranty that such application will be suitable for the specified + * use without further testing or modification. + ******************************************************************************/ + +#include +#include +#include "lpc17xx_uart.h" +#include "lpc17xx.h" + + +/** + * @brief Initializes the UART0. + * + * @param baudrate: Specifies the baud rate + * @retval None + */ +void LPC17xx_UART_Init(uint32_t baudrate) +{ + uint32_t Fdiv; + uint32_t pclkdiv, pclk; + + /***/ + LPC_PINCON->PINSEL0 &= ~0x000000F0; + + LPC_PINCON->PINSEL0 |= 0x00000050; /* RxD0 and TxD0 */ + + /* PCLK_UART0=CCLK/2 */ + //**LPC_SC->PCLKSEL1 &= ~(3<<6); /* PCLK_UART0 = CCLK/4 (18MHz) */ + //**LPC_SC->PCLKSEL1 |= (2<<6); /* PCLK_UART0 = CCLK/2 (36MHz) */ + //**pclk = SystemCoreClock/2; + + /* By default, the PCLKSELx value is zero, thus, the PCLK for + all the peripherals is 1/4 of the SystemFrequency. */ + /* Bit 6~7 is for UART0 */ + pclkdiv = (LPC_SC->PCLKSEL0 >> 6) & 0x03; + switch ( pclkdiv ) + { + case 0x00: + default: + pclk = SystemCoreClock/4; + break; + case 0x01: + pclk = SystemCoreClock; + break; + case 0x02: + pclk = SystemCoreClock/2; + break; + case 0x03: + pclk = SystemCoreClock/8; + break; + } + + LPC_UART0->LCR = 0x83; /* 8 bits, no Parity, 1 Stop bit */ + Fdiv = ( pclk / 16 ) / baudrate ; /*baud rate */ + LPC_UART0->DLM = Fdiv / 256; + LPC_UART0->DLL = Fdiv % 256; + LPC_UART0->LCR = 0x03; /* DLAB = 0 */ + LPC_UART0->FCR = 0x07; /* Enable and reset TX and RX FIFO. */ +} + +/** + * @brief Write one character to UART0. + * + * @param ch: Character to be written + * @retval None + */ +void LPC17xx_UART_PutChar (uint8_t ch) +{ + while (!(LPC_UART0->LSR & 0x20)); + + LPC_UART0->THR = ch; +} + +/** + * @brief Read one character from UART0 (blocking read). + * + * @param None + * @retval Received character + */ +uint8_t LPC17xx_UART_GetChar (void) +{ + while (!(LPC_UART0->LSR & 0x01)); + return (LPC_UART0->RBR); +} + +/** + * @brief Read one character from UART0 (non blocking read). + * + * @param None + * @retval Received character + */ +uint8_t LPC17xx_UART_GetChar_nb (void) +{ + if (LPC_UART0->LSR & 0x01) + return (LPC_UART0->RBR); + else + return 0; +} + +/** + * @brief Write a string to UART0. + * + * @param str: NULL-terminated char string to be written + * @retval None + */ +void LPC17xx_UART_PutString (uint8_t *str) +{ +/* usage: LPC1700_UART_Printf("xxx\n\r");*/ +#if 1 + while (*str != 0) + { + LPC17xx_UART_PutChar(*str++); + } + +#else +/* usage: LPC1700_UART_Printf("xxx\n");*/ + while ((*str) != 0) { + if (*str == '\n') { + LPC17xx_UART_PutChar(*str++); + LPC17xx_UART_PutChar('\r'); + } else { + LPC17xx_UART_PutChar(*str++); + } + } +#endif +} + +/** + * @brief Print formatted string. This function takes variable length arguments. + * + * @param format + * @param ... + * @retval None + * + * Note: using library functions "vsprintf" will increase the RO size by about 6KB + */ +//void LPC17xx_UART_Printf (const uint8_t *format, ...) +//{ +// static uint8_t buffer[40 + 1]; +// va_list vArgs; +// +// va_start(vArgs, format); +// vsprintf((char *)buffer, (char const *)format, vArgs); +// va_end(vArgs); +// LPC17xx_UART_PutString((uint8_t *) buffer); +//} + +/* --------------------------------- End Of File ------------------------------ */ diff --git a/platforms/lpc17xx/drivers/lpc17xx_uart.h b/platforms/lpc17xx/drivers/lpc17xx_uart.h new file mode 100644 index 0000000..9e7f045 --- /dev/null +++ b/platforms/lpc17xx/drivers/lpc17xx_uart.h @@ -0,0 +1,37 @@ +/**************************************************************************//** + * @file lpc17xx_uart.h + * @brief Header file for lpc17xx_uart.c. + * @version 1.0 + * @date 18. Nov. 2010 + * + * @note + * Copyright (C) 2010 NXP Semiconductors(NXP). All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * products. This software is supplied "AS IS" without any warranties. + * NXP Semiconductors assumes no responsibility or liability for the + * use of the software, conveys no license or title under any patent, + * copyright, or mask work right to the product. NXP Semiconductors + * reserves the right to make changes in the software without + * notification. NXP Semiconductors also make no representation or + * warranty that such application will be suitable for the specified + * use without further testing or modification. + ******************************************************************************/ + +#ifndef __LPC17xx_UART_H_ +#define __LPC17xx_UART_H_ + +#include + +/* external functions */ +void LPC17xx_UART_PutChar (uint8_t); +uint8_t LPC17xx_UART_GetChar (void); +void LPC17xx_UART_Init(uint32_t baudrate); +//void LPC17xx_UART_Printf (const uint8_t *format, ...); +void LPC17xx_UART_PutString (uint8_t *str) ; + +#endif // __LPC17xx_UART_H_ + +/* --------------------------------- End Of File ------------------------------ */ diff --git a/platforms/lpc17xx/main.c b/platforms/lpc17xx/main.c new file mode 100644 index 0000000..755f965 --- /dev/null +++ b/platforms/lpc17xx/main.c @@ -0,0 +1,116 @@ +/* + * Copyright (c) 2012, Natie van Rooyen. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. No personal names or organizations' names associated with the + * Atomthreads project may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + + +#include "LPC17xx.h" +#include "drivers/lpc17xx_uart.h" +#include +#include "modules.h" +#include "atom.h" +#include "tests/atomtests.h" + +// for mbed board +#define LED1_GPIO (1 << 18) +#define LED2_GPIO (1 << 20) +#define LED3_GPIO (1 << 21) +#define LED4_GPIO (1 << 23) + +#define LED_GET(led) (LPC_GPIO1->FIOSET & led) +#define LED_SET(led, on) { if (on) LPC_GPIO1->FIOSET = led ; else LPC_GPIO1->FIOCLR = led ; } +#define LED_TOGGLE(led) LED_SET(led, !LED_GET(led)) + + +#ifndef ATOMTHREADS_TEST +#define ATOMTHREADS_TEST "kern1" +#endif + +#define TEST_STACK_BYTE_SIZE 1024 +#define IDLE_STACK_BYTE_SIZE 512 + +static unsigned char test_stack[TEST_STACK_BYTE_SIZE] ; +static unsigned char idle_stack[IDLE_STACK_BYTE_SIZE] ; +ATOM_TCB test_tcb ; + + +/** + * \b test_thread + * + * Function calling the test function of the Atomthreads test suite. + * + */ +void +test_thread (uint32_t param) +{ + uint32_t failures ; + static volatile unsigned int i ; + CRITICAL_STORE ; + + failures = test_start () ; + + atomTimerDelay (10) ; + CRITICAL_START() ; + dbg_format_msg ("%s %s\r\n", ATOMTHREADS_TEST, failures ? "FAIL" : "PASS") ; + CRITICAL_END() ; + + while(1) { + LED_TOGGLE(LED1_GPIO) ; + for (i=0; i<1000000; i++) ; + } + +} + +int main(void) { + + static volatile unsigned int i ; + + // mbed board + LPC_GPIO1->FIODIR |= LED1_GPIO | LED2_GPIO | LED3_GPIO | LED4_GPIO ; + + dbg_format_msg ("\r\nLPC17xx SystemCoreClock = %d\r\n",SystemCoreClock) ; + + //atomthreads_stress_test (36) ; + + dbg_format_msg ("Atomthreads starting %s... \r\n", ATOMTHREADS_TEST) ; + + atomOSInit(&idle_stack[0], IDLE_STACK_BYTE_SIZE, TRUE) ; + atomThreadCreate ((ATOM_TCB *)&test_tcb, TEST_THREAD_PRIO, test_thread, 0, &test_stack[0], TEST_STACK_BYTE_SIZE, TRUE); + atomOSStart() ; + + + + while(1) { + + LED_TOGGLE(LED1_GPIO) ; + for (i=0; i<1000000; i++) ; + + + } + return 0 ; +} + diff --git a/platforms/lpc17xx/modules.c b/platforms/lpc17xx/modules.c new file mode 100644 index 0000000..7901bcd --- /dev/null +++ b/platforms/lpc17xx/modules.c @@ -0,0 +1,178 @@ +/* + * Copyright (c) 2012, Natie van Rooyen. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. No personal names or organizations' names associated with the + * Atomthreads project may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include "modules.h" +#include +#include +#include "atomport_private.h" +#include "atom.h" +#include "atomport.h" + + + +/** + * \b dbg_format_msg + * + * Same as printf. + * + */ +void +dbg_format_msg (char *format, ...) +{ + va_list args; + static char msg[256] ; + //CRITICAL_STORE ; + + va_start (args, format) ; + //CRITICAL_START() ; + vsnprintf ((char*)msg, 256, (char*)format, args) ; + LPC17xx_UART_PutString (msg) ; + //CRITICAL_END() ; + +} + + +/** + * \b low_level_init + * + * Initializes the PIC and start the system timer tick intrerupt. + * + */ +int +low_level_init (void) +{ + SystemInit () ; + SystemCoreClockUpdate (); + //contextInit () ; + NVIC_SetPriority (PendSV_IRQn, 0xFF) ; + LPC17xx_UART_Init (115200) ; + SysTick_Config (1000000) ; + + return 0 ; +} + + + +/** + * \b __context_preempt_handler + * + * System timer tic interupt handler. + * + */ +void +__context_tick_handler (void) +{ + + /* Call the interrupt enter routine */ + atomIntEnter(); + + /* Call the OS system tick handler */ + atomTimerTick(); + + /* Call the interrupt exit routine */ + atomIntExit(TRUE); + +} + +/** + * \b dbg_mem_dump_40 + * + * Dumps size bytes of memory from data. + * + */ +void dbg_mem_dump_40 (unsigned int* data, int size) +{ + int j ; + + dbg_format_msg ("Dump %d bytes at %.8X:\r\n",size * 4, (unsigned int)data) ; + data = (unsigned int*)((unsigned int)data & ~0x3) ; + for (j=0; jSHCSR); + + dbg_mem_dump_40 (hardfault_args, 0x40) ; + + while (1); + +} + diff --git a/platforms/lpc17xx/modules.h b/platforms/lpc17xx/modules.h new file mode 100644 index 0000000..e947d38 --- /dev/null +++ b/platforms/lpc17xx/modules.h @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2012, Natie van Rooyen. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. No personal names or organizations' names associated with the + * Atomthreads project may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __MODULES_H__ +#define __MODULES_H__ + +/* + * Module definitions to use with the Stellaris LM3S6965 Microcontroller + */ + + +#include "LPC17xx.h" +#include "drivers/lpc17xx_uart.h" + + +/* Function prototypes */ +extern int low_level_init (void) ; +extern void dbg_format_msg (char *format, ...) ; +extern void dbg_fault_handler (unsigned int * hardfault_args) ; + +#endif /* __MODULES_H__ */ diff --git a/platforms/lpc17xx/startup.c b/platforms/lpc17xx/startup.c new file mode 100644 index 0000000..87a90a5 --- /dev/null +++ b/platforms/lpc17xx/startup.c @@ -0,0 +1,295 @@ +/**************************************************************************//** + * @file startup.c + * @brief + * @version + * @date + * + * @note + * Copyright (C) 2010 NXP Semiconductors(NXP). All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * products. This software is supplied "AS IS" without any warranties. + * NXP Semiconductors assumes no responsibility or liability for the + * use of the software, conveys no license or title under any patent, + * copyright, or mask work right to the product. NXP Semiconductors + * reserves the right to make changes in the software without + * notification. NXP Semiconductors also make no representation or + * warranty that such application will be suitable for the specified + * use without further testing or modification. + ******************************************************************************/ +#define WEAK __attribute__ ((weak)) +#define ALIAS(f) __attribute__ ((weak, alias (#f))) + + +#include "system_LPC17xx.h" +#include "atomport_private.h" + + + + + void ResetISR(void); +WEAK void NMI_Handler(void); +WEAK void HardFault_Handler(void); +WEAK void MemManage_Handler(void); +WEAK void BusFault_Handler(void); +WEAK void UsageFault_Handler(void); +WEAK void SVC_Handler(void); +WEAK void DebugMon_Handler(void); +WEAK void PendSV_Handler(void); +WEAK void SysTick_Handler(void); +WEAK void IntDefault_Handler(void); + + +//***************************************************************************** +// +// The entry point for the application. +// __main() is the entry point for Redlib based applications +// main() is the entry point for Newlib based applications +// +//***************************************************************************** + +extern int main(void); +//***************************************************************************** +// +// External declaration for the pointer to the stack top from the Linker Script +// +//***************************************************************************** +extern void _vStackTop(void); + + +//***************************************************************************** +// +// The vector table. +// This relies on the linker script to place at correct location in memory. +// +//***************************************************************************** +extern void (* const g_pfnVectors[])(void); +__attribute__ ((section(".isr_vector"))) +void (* const g_pfnVectors[])(void) = { + // Core Level - CM3 + &_vStackTop, // The initial stack pointer + ResetISR, // The reset handler + NMI_Handler, // The NMI handler + HardFault_Handler, // The hard fault handler + MemManage_Handler, // The MPU fault handler + BusFault_Handler, // The bus fault handler + UsageFault_Handler, // The usage fault handler + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + SVC_Handler, // SVCall handler + DebugMon_Handler, // Debug monitor handler + 0, // Reserved + archPendSVHandler, // The PendSV handler + archTickHandler /*SysTick_Handler*/, // The SysTick handler + + // Chip Level - LPC17 + IntDefault_Handler, // 16, 0x40 - WDT + IntDefault_Handler, // 17, 0x44 - TIMER0 + IntDefault_Handler, // 18, 0x48 - TIMER1 + IntDefault_Handler, // 19, 0x4c - TIMER2 + IntDefault_Handler, // 20, 0x50 - TIMER3 + IntDefault_Handler, // 21, 0x54 - UART0 + IntDefault_Handler, // 22, 0x58 - UART1 + IntDefault_Handler, // 23, 0x5c - UART2 + IntDefault_Handler, // 24, 0x60 - UART3 + IntDefault_Handler, // 25, 0x64 - PWM1 + IntDefault_Handler, // 26, 0x68 - I2C0 + IntDefault_Handler, // 27, 0x6c - I2C1 + IntDefault_Handler, // 28, 0x70 - I2C2 + IntDefault_Handler, // 29, 0x74 - SPI + IntDefault_Handler, // 30, 0x78 - SSP0 + IntDefault_Handler, // 31, 0x7c - SSP1 + IntDefault_Handler, // 32, 0x80 - PLL0 (Main PLL) + IntDefault_Handler, // 33, 0x84 - RTC + IntDefault_Handler, // 34, 0x88 - EINT0 + IntDefault_Handler, // 35, 0x8c - EINT1 + IntDefault_Handler, // 36, 0x90 - EINT2 + IntDefault_Handler, // 37, 0x94 - EINT3 + IntDefault_Handler, // 38, 0x98 - ADC + IntDefault_Handler, // 39, 0x9c - BOD + IntDefault_Handler, // 40, 0xA0 - USB + IntDefault_Handler, // 41, 0xa4 - CAN + IntDefault_Handler, // 42, 0xa8 - GP DMA + IntDefault_Handler, // 43, 0xac - I2S + IntDefault_Handler, // 44, 0xb0 - Ethernet + IntDefault_Handler, // 45, 0xb4 - RITINT + IntDefault_Handler, // 46, 0xb8 - Motor Control PWM + IntDefault_Handler, // 47, 0xbc - Quadrature Encoder + IntDefault_Handler, // 48, 0xc0 - PLL1 (USB PLL) + IntDefault_Handler, // 49, 0xc4 - USB Activity interrupt to wakeup + IntDefault_Handler, // 50, 0xc8 - CAN Activity interrupt to wakeup +}; + +//***************************************************************************** +// Functions to carry out the initialization of RW and BSS data sections. These +// are written as separate functions rather than being inlined within the +// ResetISR() function in order to cope with MCUs with multiple banks of +// memory. +//***************************************************************************** +__attribute__ ((section(".after_vectors"))) +void data_init(unsigned int romstart, unsigned int start, unsigned int len) { + unsigned int *pulDest = (unsigned int*) start; + unsigned int *pulSrc = (unsigned int*) romstart; + unsigned int loop; + for (loop = 0; loop < len; loop = loop + 4) + *pulDest++ = *pulSrc++; +} + +__attribute__ ((section(".after_vectors"))) +void bss_init(unsigned int start, unsigned int len) { + unsigned int *pulDest = (unsigned int*) start; + unsigned int loop; + for (loop = 0; loop < len; loop = loop + 4) + *pulDest++ = 0; +} + + +//***************************************************************************** +// The following symbols are constructs generated by the linker, indicating +// the location of various points in the "Global Section Table". This table is +// created by the linker via the Code Red managed linker script mechanism. It +// contains the load address, execution address and length of each RW data +// section and the execution and length of each BSS (zero initialized) section. +//***************************************************************************** +extern unsigned int __data_section_table; +extern unsigned int __data_section_table_end; +extern unsigned int __bss_section_table; +extern unsigned int __bss_section_table_end; + + +//***************************************************************************** +// Reset entry point for your code. +// Sets up a simple runtime environment and initializes the C/C++ +// library. +//***************************************************************************** +__attribute__ ((section(".after_vectors"))) +void +ResetISR(void) { + + // + // Copy the data sections from flash to SRAM. + // + unsigned int LoadAddr, ExeAddr, SectionLen; + unsigned int *SectionTableAddr; + + // Load base address of Global Section Table + SectionTableAddr = &__data_section_table; + + // Copy the data sections from flash to SRAM. + while (SectionTableAddr < &__data_section_table_end) { + LoadAddr = *SectionTableAddr++; + ExeAddr = *SectionTableAddr++; + SectionLen = *SectionTableAddr++; + data_init(LoadAddr, ExeAddr, SectionLen); + } + // At this point, SectionTableAddr = &__bss_section_table; + // Zero fill the bss segment + while (SectionTableAddr < &__bss_section_table_end) { + ExeAddr = *SectionTableAddr++; + SectionLen = *SectionTableAddr++; + bss_init(ExeAddr, SectionLen); + } + + + + low_level_init(); + + + + + main(); + + + // + // main() shouldn't return, but if it does, we'll just enter an infinite loop + // + while (1) ; +} + +//***************************************************************************** +// Default exception handlers. Override the ones here by defining your own +// handler routines in your application code. +//***************************************************************************** +__attribute__ ((section(".after_vectors"))) __attribute__( ( naked ) ) +void NMI_Handler(void) +{ + while(1) ; + +} + +__attribute__ ((section(".after_vectors"))) __attribute__( ( naked ) ) +void HardFault_Handler(void) +{ + + __asm volatile + ( + " tst lr, #4 \n" + " ite eq \n" + " mrseq r0, msp \n" + " mrsne r0, psp \n" + " b dbg_fault_handler \n" + ); + + while(1) ; + +} + +__attribute__ ((section(".after_vectors"))) __attribute__( ( naked ) ) +void MemManage_Handler(void) +{ + while(1) ; + +} + +__attribute__ ((section(".after_vectors"))) __attribute__( ( naked ) ) +void BusFault_Handler(void) +{ + while(1) ; + +} + +__attribute__ ((section(".after_vectors"))) __attribute__( ( naked ) ) +void UsageFault_Handler(void) +{ + while(1) ; + +} + +__attribute__ ((section(".after_vectors"))) __attribute__( ( naked ) ) +void SVC_Handler(void) +{ + while(1) ; + +} + +__attribute__ ((section(".after_vectors"))) __attribute__( ( naked ) ) +void DebugMon_Handler(void) +{ + while(1) ; + +} + +__attribute__ ((section(".after_vectors"))) __attribute__( ( naked ) ) +void PendSV_Handler(void) +{ + while(1) ; + +} + +__attribute__ ((section(".after_vectors"))) __attribute__( ( naked ) ) +void SysTick_Handler(void) +{ + while(1) ; + +} + +__attribute__ ((section(".after_vectors"))) __attribute__( ( naked ) ) +void IntDefault_Handler(void) +{ + while(1) ; + +} diff --git a/platforms/lpc17xx/system.ld b/platforms/lpc17xx/system.ld new file mode 100644 index 0000000..0112192 --- /dev/null +++ b/platforms/lpc17xx/system.ld @@ -0,0 +1,148 @@ +/**************************************************************************//** + * @file system.ld + * @brief + * @version + * @date + * + * @note + * Copyright (C) 2010 NXP Semiconductors(NXP). All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * products. This software is supplied "AS IS" without any warranties. + * NXP Semiconductors assumes no responsibility or liability for the + * use of the software, conveys no license or title under any patent, + * copyright, or mask work right to the product. NXP Semiconductors + * reserves the right to make changes in the software without + * notification. NXP Semiconductors also make no representation or + * warranty that such application will be suitable for the specified + * use without further testing or modification. + ******************************************************************************/ + +MEMORY +{ + /* Define each memory region */ + MFlash512 (rx) : ORIGIN = 0x0, LENGTH = 0x80000 /* 512k */ + RamLoc32 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x8000 /* 32k */ + RamAHB32 (rwx) : ORIGIN = 0x2007c000, LENGTH = 0x8000 /* 32k */ + +} + /* Define a symbol for the top of each memory region */ + __top_MFlash512 = 0x0 + 0x80000; + __top_RamLoc32 = 0x10000000 + 0x8000; + __top_RamAHB32 = 0x2007c000 + 0x8000; + + + +ENTRY(ResetISR) + +SECTIONS +{ + + /* MAIN TEXT SECTION */ + .text : ALIGN(4) + { + FILL(0xff) + KEEP(*(.isr_vector)) + + /* Global Section Table */ + . = ALIGN(4) ; + __section_table_start = .; + __data_section_table = .; + LONG(LOADADDR(.data)); + LONG( ADDR(.data)) ; + LONG( SIZEOF(.data)); + LONG(LOADADDR(.data_RAM2)); + LONG( ADDR(.data_RAM2)) ; + LONG( SIZEOF(.data_RAM2)); + __data_section_table_end = .; + __bss_section_table = .; + LONG( ADDR(.bss)); + LONG( SIZEOF(.bss)); + LONG( ADDR(.bss_RAM2)); + LONG( SIZEOF(.bss_RAM2)); + __bss_section_table_end = .; + __section_table_end = . ; + /* End of Global Section Table */ + + + *(.after_vectors*) + + *(.text*) + *(.rodata .rodata.*) + . = ALIGN(4); + + } > MFlash512 + + /* + * for exception handling/unwind - some Newlib functions (in common + * with C++ and STDC++) use this. + * Use KEEP so not discarded with --gc-sections + */ + .ARM.extab : ALIGN(4) + { + KEEP(*(.ARM.extab* .gnu.linkonce.armextab.*)) + } > MFlash512 + __exidx_start = .; + + .ARM.exidx : ALIGN(4) + { + KEEP(*(.ARM.exidx* .gnu.linkonce.armexidx.*)) + } > MFlash512 + __exidx_end = .; + + _etext = .; + + + .data_RAM2 : ALIGN(4) + { + FILL(0xff) + *(.data.$RAM2*) + *(.data.$RamAHB32*) + . = ALIGN(4) ; + } > RamAHB32 AT>MFlash512 + + /* MAIN DATA SECTION */ + + .uninit_RESERVED : ALIGN(4) + { + KEEP(*(.bss.$RESERVED*)) + . = ALIGN(4) ; + _end_uninit_RESERVED = .; + } > RamLoc32 + + .data : ALIGN(4) + { + FILL(0xff) + _data = .; + *(vtable) + *(.data*) + . = ALIGN(4) ; + _edata = .; + } > RamLoc32 AT>MFlash512 + + + .bss_RAM2 : ALIGN(4) + { + *(.bss.$RAM2*) + *(.bss.$RamAHB32*) + . = ALIGN(4) ; + } > RamAHB32 + + /* MAIN BSS SECTION */ + .bss : ALIGN(4) + { + __bss_start__ = . ; + _bss = .; + *(.bss*) + *(COMMON) + . = ALIGN(4) ; + __bss_end__ = . ; + _ebss = .; + PROVIDE(end = .); + } > RamLoc32 + + PROVIDE(_pvHeapStart = .); + PROVIDE(_vStackTop = __top_RamLoc32 - 0); +}