From 9ebb4d14b4b362b1c2b7be19483ce97e99b4c511 Mon Sep 17 00:00:00 2001 From: Natie van Rooyen Date: Thu, 27 Sep 2012 21:46:59 +0200 Subject: [PATCH] white space --- platforms/qemu_integratorcp/README | 1 + platforms/qemu_integratorcp/modules.c | 8 +- platforms/qemu_integratorcp/modules.h | 38 ++++----- platforms/qemu_integratorcp/startup.s | 4 - platforms/qemu_lm3s/modules.c | 84 +++++++++--------- platforms/qemu_lm3s/modules.h | 118 +++++++++++++------------- 6 files changed, 128 insertions(+), 125 deletions(-) diff --git a/platforms/qemu_integratorcp/README b/platforms/qemu_integratorcp/README index 0177f81..d8b53c9 100644 --- a/platforms/qemu_integratorcp/README +++ b/platforms/qemu_integratorcp/README @@ -10,5 +10,6 @@ QEMU ARM Integrator/CP (ARM926EJ-S) Platform The "qemu_integratorcp" platform contains sources for building a sample Atomthreads application for the ARM Integrator/CP (ARM926EJ-S) platform. + BUGS: kern4 testcase fails (sometimes). \ No newline at end of file diff --git a/platforms/qemu_integratorcp/modules.c b/platforms/qemu_integratorcp/modules.c index c611d68..a6ee156 100644 --- a/platforms/qemu_integratorcp/modules.c +++ b/platforms/qemu_integratorcp/modules.c @@ -46,16 +46,16 @@ ICP_PIC_T * const board_pic = (ICP_PI void dbg_format_msg (char *format, ...) { - va_list args; - static char msg[256] ; + va_list args; + static char msg[256] ; CRITICAL_STORE ; va_start (args, format) ; CRITICAL_START() ; - vsnprintf ((char*)msg, 256, (char*)format, args) ; + vsnprintf ((char*)msg, 256, (char*)format, args) ; + printf (msg) ; CRITICAL_END() ; - printf (msg) ; } /** diff --git a/platforms/qemu_integratorcp/modules.h b/platforms/qemu_integratorcp/modules.h index 58a48ed..a94140a 100644 --- a/platforms/qemu_integratorcp/modules.h +++ b/platforms/qemu_integratorcp/modules.h @@ -59,21 +59,21 @@ typedef struct ICP_TIMER_S { // -------- ICP_TIMER_LOAD : (LOAD Offset: 0x00) Load value for Timer -------- // -------- ICP_TIMER_VALUE : (LOAD Offset: 0x04) The current value for Timer -------- // -------- ICP_TIMER_CONTROL : (CONTROL Offset: 0x04) Timer control register -------- -#define ICP_TIMER_CONTROL_MASK ((unsigned int)0x0F << 0) // Timer control mask - #define ICP_TIMER_CONTROL_ENABLE ((unsigned int)0x01 << 7) // Timer enable: 0 = disabled 1 = enabled. - #define ICP_TIMER_CONTROL_MODE ((unsigned int)0x01 << 6) // Timer mode: 0 = free running, counts once and then wraps to 0xFFFF 1 = periodic, reloads from load register at the end of each count.. - #define ICP_TIMER_CONTROL_IE ((unsigned int)0x01 << 5) // Interrupt enable. - #define ICP_TIMER_CONTROL_R ((unsigned int)0x01 << 4) // Unused, always write as 0s. - #define ICP_TIMER_CONTROL_PRESCALE_MASK ((unsigned int)0x03 << 2) // Prescale divisor - #define ICP_TIMER_CONTROL_PRESCALE_NONE ((unsigned int)0x00 << 2) // - #define ICP_TIMER_CONTROL_PRESCALE_16 ((unsigned int)0x01 << 2) // - #define ICP_TIMER_CONTROL_PRESCALE_256 ((unsigned int)0x02 << 2) // -#define ICP_TIMER_CONTROL_TIMER_SIZE ((unsigned int)0x01 << 1) // Selects 16/32 bit counter operation: 0 = 16-bit counter (default) 1 = 32-bit counter For 16-bit mode, write the high 16 bits of the 32-bit value as 0. -#define ICP_TIMER_CONTROL_ONE_SHOT ((unsigned int)0x01 << 0) // Selects one-shot or wrapping counter mode: 0 = wrapping mode (default) 1 = one-shot mode +#define ICP_TIMER_CONTROL_MASK ((unsigned int)0x0F << 0) // Timer control mask + #define ICP_TIMER_CONTROL_ENABLE ((unsigned int)0x01 << 7) // Timer enable: 0 = disabled 1 = enabled. + #define ICP_TIMER_CONTROL_MODE ((unsigned int)0x01 << 6) // Timer mode: 0 = free running, counts once and then wraps to 0xFFFF 1 = periodic, reloads from load register at the end of each count.. + #define ICP_TIMER_CONTROL_IE ((unsigned int)0x01 << 5) // Interrupt enable. + #define ICP_TIMER_CONTROL_R ((unsigned int)0x01 << 4) // Unused, always write as 0s. + #define ICP_TIMER_CONTROL_PRESCALE_MASK ((unsigned int)0x03 << 2) // Prescale divisor + #define ICP_TIMER_CONTROL_PRESCALE_NONE ((unsigned int)0x00 << 2) // + #define ICP_TIMER_CONTROL_PRESCALE_16 ((unsigned int)0x01 << 2) // + #define ICP_TIMER_CONTROL_PRESCALE_256 ((unsigned int)0x02 << 2) // +#define ICP_TIMER_CONTROL_TIMER_SIZE ((unsigned int)0x01 << 1) // Selects 16/32 bit counter operation: 0 = 16-bit counter (default) 1 = 32-bit counter For 16-bit mode, write the high 16 bits of the 32-bit value as 0. +#define ICP_TIMER_CONTROL_ONE_SHOT ((unsigned int)0x01 << 0) // Selects one-shot or wrapping counter mode: 0 = wrapping mode (default) 1 = one-shot mode // -------- ICP_TIMER_INTCLR : (INTCLR Offset: 0x0C) Timer interrupt clear -------- // -------- ICP_TIMER_RIS : (RIS Offset: 0x10) Timer raw interrupt status -------- // -------- ICP_TIMER_MIS : (MIS Offset: 0x14) Timer masked interrupt status -------- -#define ICP_TIMER_INT ((unsigned int)0x01 << 0) // Interrupt +#define ICP_TIMER_INT ((unsigned int)0x01 << 0) // Interrupt // -------- ICP_TIMER_BGLOAD : (BGLOAD Offset: 0x18) Timer masked interrupt status -------- @@ -100,19 +100,19 @@ typedef struct ICP_PIC_S { // -------- ICP_PIC_IRQ_RAWSTAT : (IRQ_RAWSTAT Offset: 0x04) IRQ raw interrupt status -------- // -------- ICP_PIC_IRQ_ENABLESET : (IRQ_ENABLESET Offset: 0x08) IRQ enable set -------- // -------- ICP_PIC_IRQ_ENABLECLR : (IRQ_ENABLECLR Offset: 0x0C) IRQ enable clear -------- -#define ICP_PIC_IRQ_MASK ((unsigned int)0x3FFFFF << 0) // IRQ mask - #define ICP_PIC_IRQ_TIMERINT2 ((unsigned int)0x01 << 7) // TIMERINT2 Counter-timer 2 interrupt - #define ICP_PIC_IRQ_TIMERINT1 ((unsigned int)0x01 << 6) // TIMERINT1 Counter-timer 1 interrupt - #define ICP_PIC_IRQ_TIMERINT0 ((unsigned int)0x01 << 5) // TIMERINT0 Counter-timer 0 interrupt - #define ICP_PIC_IRQ_SOFTINT ((unsigned int)0x01 << 0) // OFTINT Software interrupt +#define ICP_PIC_IRQ_MASK ((unsigned int)0x3FFFFF << 0) // IRQ mask + #define ICP_PIC_IRQ_TIMERINT2 ((unsigned int)0x01 << 7) // TIMERINT2 Counter-timer 2 interrupt + #define ICP_PIC_IRQ_TIMERINT1 ((unsigned int)0x01 << 6) // TIMERINT1 Counter-timer 1 interrupt + #define ICP_PIC_IRQ_TIMERINT0 ((unsigned int)0x01 << 5) // TIMERINT0 Counter-timer 0 interrupt + #define ICP_PIC_IRQ_SOFTINT ((unsigned int)0x01 << 0) // OFTINT Software interrupt // -------- ICP_PIC_INT_SOFTSET : (INT_SOFTSET Offset: 0x10) Software interrupt set -------- // -------- ICP_PIC_INT_SOFTCLR : (INT_SOFTCLR Offset: 0x14) Software interrupt clear -------- /* module definitions */ -#define BOARD_BASE_ADDRESS_TIMER_0 0x13000000 -#define BOARD_BASE_ADDRESS_PIC 0x14000000 +#define BOARD_BASE_ADDRESS_TIMER_0 0x13000000 +#define BOARD_BASE_ADDRESS_PIC 0x14000000 extern ICP_TIMER_T* const board_timer_0 ; extern ICP_PIC_T* const board_pic ; diff --git a/platforms/qemu_integratorcp/startup.s b/platforms/qemu_integratorcp/startup.s index 0c3675d..a19ea76 100644 --- a/platforms/qemu_integratorcp/startup.s +++ b/platforms/qemu_integratorcp/startup.s @@ -5,10 +5,6 @@ .extern __fiq_stack_top__ .extern __svc_stack_top__ -.global bsp_ints_enable -.global bsp_ints_disable -.global bsp_ints_restore - .equ USR_MODE, 0x10 .equ FIQ_MODE, 0x11 diff --git a/platforms/qemu_lm3s/modules.c b/platforms/qemu_lm3s/modules.c index c375e4e..10c0058 100644 --- a/platforms/qemu_lm3s/modules.c +++ b/platforms/qemu_lm3s/modules.c @@ -49,13 +49,13 @@ GPTM_TIMER_T * const board_gptm0 = (GPTM_TIMER_T*) void dbg_format_msg (char *format, ...) { - va_list args; - static char msg[256] ; + va_list args; + static char msg[256] ; CRITICAL_STORE ; va_start (args, format) ; CRITICAL_START() ; - vsnprintf ((char*)msg, 256, (char*)format, args) ; + vsnprintf ((char*)msg, 256, (char*)format, args) ; printf (msg) ; CRITICAL_END() ; @@ -92,7 +92,7 @@ low_level_init (void) /** - * \b __context_preempt_handler + * \b __context_tick_handler * * System timer tic interupt handler. * @@ -113,44 +113,50 @@ __context_tick_handler (void) } +/** + * \b dbg_hard_fault_handler_c + * + * Dumps the registers pushed on the stack after a fault. + * + */ void dbg_hard_fault_handler_c (unsigned int * hardfault_args) { - unsigned int stacked_r0; - unsigned int stacked_r1; - unsigned int stacked_r2; - unsigned int stacked_r3; - unsigned int stacked_r12; - unsigned int stacked_lr; - unsigned int stacked_pc; - unsigned int stacked_psr; - - stacked_r0 = ((unsigned long) hardfault_args[0]); - stacked_r1 = ((unsigned long) hardfault_args[1]); - stacked_r2 = ((unsigned long) hardfault_args[2]); - stacked_r3 = ((unsigned long) hardfault_args[3]); - - stacked_r12 = ((unsigned long) hardfault_args[4]); - stacked_lr = ((unsigned long) hardfault_args[5]); - stacked_pc = ((unsigned long) hardfault_args[6]); - stacked_psr = ((unsigned long) hardfault_args[7]); - - printf ("\r\n\r\n[Hard fault handler - all numbers in hex]\r\n"); - printf ("SP = 0x%x\r\n", hardfault_args); - printf ("R0 = 0x%x\r\n", stacked_r0); - printf ("R1 = 0x%x\r\n", stacked_r1); - printf ("R2 = 0x%x\r\n", stacked_r2); - printf ("R3 = 0x%x\r\n", stacked_r3); - printf ("R12 = 0x%x\r\n", stacked_r12); - printf ("LR [R14] = 0x%x subroutine call return address\r\n", stacked_lr); - printf ("PC [R15] = 0x%x program counter\r\n", stacked_pc); - printf ("PSR = 0x%x\r\n", stacked_psr); - //printf ("BFAR = 0x%x\r\n", (*((volatile unsigned long *)(0xE000ED38)))); - //printf ("CFSR = 0x%x\r\n", (*((volatile unsigned long *)(0xE000ED28)))); - //printf ("HFSR = 0x%x\r\n", (*((volatile unsigned long *)(0xE000ED2C)))); - //printf ("DFSR = 0x%x\r\n", (*((volatile unsigned long *)(0xE000ED30)))); - //printf ("AFSR = 0x%x\r\n", (*((volatile unsigned long *)(0xE000ED3C)))); - // printf ("SCB_SHCSR = %x\n", SCB->SHCSR); + unsigned int stacked_r0; + unsigned int stacked_r1; + unsigned int stacked_r2; + unsigned int stacked_r3; + unsigned int stacked_r12; + unsigned int stacked_lr; + unsigned int stacked_pc; + unsigned int stacked_psr; + + stacked_r0 = ((unsigned long) hardfault_args[0]); + stacked_r1 = ((unsigned long) hardfault_args[1]); + stacked_r2 = ((unsigned long) hardfault_args[2]); + stacked_r3 = ((unsigned long) hardfault_args[3]); + + stacked_r12 = ((unsigned long) hardfault_args[4]); + stacked_lr = ((unsigned long) hardfault_args[5]); + stacked_pc = ((unsigned long) hardfault_args[6]); + stacked_psr = ((unsigned long) hardfault_args[7]); + + printf ("\r\n\r\n[Hard fault handler - all numbers in hex]\r\n"); + printf ("SP = 0x%x\r\n", hardfault_args); + printf ("R0 = 0x%x\r\n", stacked_r0); + printf ("R1 = 0x%x\r\n", stacked_r1); + printf ("R2 = 0x%x\r\n", stacked_r2); + printf ("R3 = 0x%x\r\n", stacked_r3); + printf ("R12 = 0x%x\r\n", stacked_r12); + printf ("LR [R14] = 0x%x subroutine call return address\r\n", stacked_lr); + printf ("PC [R15] = 0x%x program counter\r\n", stacked_pc); + printf ("PSR = 0x%x\r\n", stacked_psr); + //printf ("BFAR = 0x%x\r\n", (*((volatile unsigned long *)(0xE000ED38)))); + //printf ("CFSR = 0x%x\r\n", (*((volatile unsigned long *)(0xE000ED28)))); + //printf ("HFSR = 0x%x\r\n", (*((volatile unsigned long *)(0xE000ED2C)))); + //printf ("DFSR = 0x%x\r\n", (*((volatile unsigned long *)(0xE000ED30)))); + //printf ("AFSR = 0x%x\r\n", (*((volatile unsigned long *)(0xE000ED3C)))); + // printf ("SCB_SHCSR = %x\n", SCB->SHCSR); while (1); diff --git a/platforms/qemu_lm3s/modules.h b/platforms/qemu_lm3s/modules.h index 8d3bb4c..5a074b4 100644 --- a/platforms/qemu_lm3s/modules.h +++ b/platforms/qemu_lm3s/modules.h @@ -46,26 +46,26 @@ typedef volatile unsigned char REG_BYTE ; // ***************************************************************************** typedef struct GPTM_TIMER_S { - // offset read/write reset Description - REG_DWORD CFG ; // 0x000 R/W 0x00000000 GPTM Configuration 345 - REG_DWORD TAMR ; // 0x004 R/W 0x00000000 GPTM TimerA Mode 346 - REG_DWORD TBMR ; // 0x008 R/W 0x00000000 GPTM TimerB Mode 348 - REG_DWORD CTL ; // 0x00C R/W 0x00000000 GPTM Control 350 - REG_DWORD Reserved[2] ; // 0x010 - REG_DWORD IMR ; // 0x018 R/W 0x00000000 GPTM Interrupt Mask 353 - REG_DWORD RIS ; // 0x01C RO 0x00000000 GPTM Raw Interrupt Status 355 - REG_DWORD MIS ; // 0x020 RO 0x00000000 GPTM Masked Interrupt Status 356 - REG_DWORD ICR ; // 0x024 W1C 0x00000000 GPTM Interrupt Clear 357 - REG_DWORD TAILR ; // 0x028 R/W 0xFFFFFFFF GPTM TimerA Interval Load 359 - REG_DWORD TBILR ; // 0x02C R/W 0x0000FFFF GPTM TimerB Interval Load 360 - REG_DWORD TAMATCHR ; // 0x030 R/W 0xFFFFFFFF GPTM TimerA Match 361 - REG_DWORD TBMATCHR ; // 0x034 R/W 0x0000FFFF GPTM TimerB Match 362 - REG_DWORD TAPR ; // 0x038 R/W 0x00000000 GPTM TimerA Prescale 363 - REG_DWORD TBPR ; // 0x03C R/W 0x00000000 GPTM TimerB Prescale 364 - REG_DWORD TAPMR ; // 0x040 R/W 0x00000000 GPTM TimerA Prescale Match 365 - REG_DWORD TBPMR ; // 0x044 R/W 0x00000000 GPTM TimerB Prescale Match 366 - REG_DWORD TAR ; // 0x048 RO 0xFFFFFFFF GPTM TimerA 367 - REG_DWORD TBR ; // 0x04C RO 0x0000FFFF GPTM TimerB 368 + // offset read/write reset Description + REG_DWORD CFG ; // 0x000 R/W 0x00000000 GPTM Configuration 345 + REG_DWORD TAMR ; // 0x004 R/W 0x00000000 GPTM TimerA Mode 346 + REG_DWORD TBMR ; // 0x008 R/W 0x00000000 GPTM TimerB Mode 348 + REG_DWORD CTL ; // 0x00C R/W 0x00000000 GPTM Control 350 + REG_DWORD Reserved[2] ; // 0x010 + REG_DWORD IMR ; // 0x018 R/W 0x00000000 GPTM Interrupt Mask 353 + REG_DWORD RIS ; // 0x01C RO 0x00000000 GPTM Raw Interrupt Status 355 + REG_DWORD MIS ; // 0x020 RO 0x00000000 GPTM Masked Interrupt Status 356 + REG_DWORD ICR ; // 0x024 W1C 0x00000000 GPTM Interrupt Clear 357 + REG_DWORD TAILR ; // 0x028 R/W 0xFFFFFFFF GPTM TimerA Interval Load 359 + REG_DWORD TBILR ; // 0x02C R/W 0x0000FFFF GPTM TimerB Interval Load 360 + REG_DWORD TAMATCHR ; // 0x030 R/W 0xFFFFFFFF GPTM TimerA Match 361 + REG_DWORD TBMATCHR ; // 0x034 R/W 0x0000FFFF GPTM TimerB Match 362 + REG_DWORD TAPR ; // 0x038 R/W 0x00000000 GPTM TimerA Prescale 363 + REG_DWORD TBPR ; // 0x03C R/W 0x00000000 GPTM TimerB Prescale 364 + REG_DWORD TAPMR ; // 0x040 R/W 0x00000000 GPTM TimerA Prescale Match 365 + REG_DWORD TBPMR ; // 0x044 R/W 0x00000000 GPTM TimerB Prescale Match 366 + REG_DWORD TAR ; // 0x048 RO 0xFFFFFFFF GPTM TimerA 367 + REG_DWORD TBR ; // 0x04C RO 0x0000FFFF GPTM TimerB 368 } GPTM_TIMER_T, *PGPTM_TIMER_T ; @@ -81,36 +81,36 @@ typedef struct GPTM_TIMER_S { #define GPTM_TIMER_TMR_TMR_PERIODIC ((unsigned int)0x02 << 0) // Periodic Timer mode #define GPTM_TIMER_TMR_TMR_CAPTURE ((unsigned int)0x03 << 0) // Capture mode // -------- GPTM_TIMER_CTL : (CTL Offset: 0x0C) This register is used alongside the GPTMCFG and GMTMTnMR registers to fine-tune the timer configuration -------- -#define GPTM_TIMER_CTL_TBPWML ((unsigned int)0x01 << 14) // GPTM TimerB PWM Output Level. 0 Output is unaffected. 1 Output is inverted. -#define GPTM_TIMER_CTL_TBOTE ((unsigned int)0x01 << 13) // GPTM TimerB Output Trigger Enable. 0 The output TimerB ADC trigger is disabled. 1 The output TimerB ADC trigger is enabled. -#define GPTM_TIMER_CTL_TBEVENT_MASK ((unsigned int)0x03 << 10) // GPTM TimerB Event Mode - #define GPTM_TIMER_CTL_TBEVENT_PE ((unsigned int)0x00 << 10) // Positive edge - #define GPTM_TIMER_CTL_TBEVENT_NE ((unsigned int)0x01 << 10) // Negative edge - #define GPTM_TIMER_CTL_TBEVENT ((unsigned int)0x03 << 10) // Both edges -#define GPTM_TIMER_CTL_TBSTALL ((unsigned int)0x01 << 9) // GPTM Timer B Stall Enable. 0 Timer B continues counting while the processor is halted by the debugger -#define GPTM_TIMER_CTL_TBEN ((unsigned int)0x01 << 8) // GPTM TimerB Enable -// -------- -#define GPTM_TIMER_CTL_TAPWML ((unsigned int)0x01 << 6) // GPTM TimerA PWM Output Level. 0 Output is unaffected. 1 Output is inverted. -#define GPTM_TIMER_CTL_TAOTE ((unsigned int)0x01 << 5) // GPTM TimerA Output Trigger Enable. 0 The output TimerB ADC trigger is disabled. 1 The output TimerB ADC trigger is enabled. -#define GPTM_TIMER_CTL_RTCEN ((unsigned int)0x01 << 4) // GPTM RTC Enable -#define GPTM_TIMER_CTL_TAEVENT_MASK ((unsigned int)0x03 << 2) // GPTM TimerA Event Mode - #define GPTM_TIMER_CTL_TAEVENT_PE ((unsigned int)0x00 << 2) // Positive edge - #define GPTM_TIMER_CTL_TAEVENT_NE ((unsigned int)0x01 << 2) // Negative edge - #define GPTM_TIMER_CTL_TAEVENT ((unsigned int)0x03 << 2) // Both edges -#define GPTM_TIMER_CTL_TASTALL ((unsigned int)0x01 << 1) // GPTM Timer A Stall Enable. 0 Timer B continues counting while the processor is halted by the debugger -#define GPTM_TIMER_CTL_TAEN ((unsigned int)0x01 << 0) // GPTM TimerA Enable +#define GPTM_TIMER_CTL_TBPWML ((unsigned int)0x01 << 14) // GPTM TimerB PWM Output Level. 0 Output is unaffected. 1 Output is inverted. +#define GPTM_TIMER_CTL_TBOTE ((unsigned int)0x01 << 13) // GPTM TimerB Output Trigger Enable. 0 The output TimerB ADC trigger is disabled. 1 The output TimerB ADC trigger is enabled. +#define GPTM_TIMER_CTL_TBEVENT_MASK ((unsigned int)0x03 << 10) // GPTM TimerB Event Mode + #define GPTM_TIMER_CTL_TBEVENT_PE ((unsigned int)0x00 << 10) // Positive edge + #define GPTM_TIMER_CTL_TBEVENT_NE ((unsigned int)0x01 << 10) // Negative edge + #define GPTM_TIMER_CTL_TBEVENT ((unsigned int)0x03 << 10) // Both edges +#define GPTM_TIMER_CTL_TBSTALL ((unsigned int)0x01 << 9) // GPTM Timer B Stall Enable. 0 Timer B continues counting while the processor is halted by the debugger +#define GPTM_TIMER_CTL_TBEN ((unsigned int)0x01 << 8) // GPTM TimerB Enable +// -------- // +#define GPTM_TIMER_CTL_TAPWML ((unsigned int)0x01 << 6) // GPTM TimerA PWM Output Level. 0 Output is unaffected. 1 Output is inverted. +#define GPTM_TIMER_CTL_TAOTE ((unsigned int)0x01 << 5) // GPTM TimerA Output Trigger Enable. 0 The output TimerB ADC trigger is disabled. 1 The output TimerB ADC trigger is enabled. +#define GPTM_TIMER_CTL_RTCEN ((unsigned int)0x01 << 4) // GPTM RTC Enable +#define GPTM_TIMER_CTL_TAEVENT_MASK ((unsigned int)0x03 << 2) // GPTM TimerA Event Mode + #define GPTM_TIMER_CTL_TAEVENT_PE ((unsigned int)0x00 << 2) // Positive edge + #define GPTM_TIMER_CTL_TAEVENT_NE ((unsigned int)0x01 << 2) // Negative edge + #define GPTM_TIMER_CTL_TAEVENT ((unsigned int)0x03 << 2) // Both edges +#define GPTM_TIMER_CTL_TASTALL ((unsigned int)0x01 << 1) // GPTM Timer A Stall Enable. 0 Timer B continues counting while the processor is halted by the debugger +#define GPTM_TIMER_CTL_TAEN ((unsigned int)0x01 << 0) // GPTM TimerA Enable // -------- GPTM_TIMER_IMR : (IMR Offset: 0x18) This register allows software to enable/disable GPTM controller-level interrupts. -------- // -------- GPTM_TIMER_RIS : (RIS Offset: 0x1C) This register shows the state of the GPTM's internal interrupt signal. -------- // -------- GPTM_TIMER_MIS : (MIS Offset: 0x20) This register show the state of the GPTM's controller-level interrupt. -------- // -------- GPTM_TIMER_ICR : (ICR Offset: 0x24) This register is used to clear the status bits in the GPTMRIS and GPTMMIS registers. -------- -#define GPTM_TIMER_INT_CBEIM ((unsigned int)0x01 << 10) // GPTM CaptureB Event Interrupt Mask -#define GPTM_TIMER_INT_CBMIM ((unsigned int)0x01 << 9) // GPTM CaptureB Match Interrupt Mask -#define GPTM_TIMER_INT_TBTOIM ((unsigned int)0x01 << 8) // GPTM TimerB Time-Out Interrupt Mask -// -------- -#define GPTM_TIMER_INT_RTCIM ((unsigned int)0x01 << 3) // GPTM RTC Interrupt Mask -#define GPTM_TIMER_INT_CAEIM ((unsigned int)0x01 << 2) // GPTM CaptureA Event Interrupt Mask -#define GPTM_TIMER_INT_CAMIM ((unsigned int)0x01 << 1) // GPTM CaptureA Match Interrupt Mask -#define GPTM_TIMER_INT_TATOIM ((unsigned int)0x01 << 0) // GPTM TimerA Time-Out Interrupt Mask +#define GPTM_TIMER_INT_CBEIM ((unsigned int)0x01 << 10) // GPTM CaptureB Event Interrupt Mask +#define GPTM_TIMER_INT_CBMIM ((unsigned int)0x01 << 9) // GPTM CaptureB Match Interrupt Mask +#define GPTM_TIMER_INT_TBTOIM ((unsigned int)0x01 << 8) // GPTM TimerB Time-Out Interrupt Mask +// -------- // +#define GPTM_TIMER_INT_RTCIM ((unsigned int)0x01 << 3) // GPTM RTC Interrupt Mask +#define GPTM_TIMER_INT_CAEIM ((unsigned int)0x01 << 2) // GPTM CaptureA Event Interrupt Mask +#define GPTM_TIMER_INT_CAMIM ((unsigned int)0x01 << 1) // GPTM CaptureA Match Interrupt Mask +#define GPTM_TIMER_INT_TATOIM ((unsigned int)0x01 << 0) // GPTM TimerA Time-Out Interrupt Mask @@ -131,10 +131,10 @@ typedef struct SYSTICK_S { } SYSTICK_T, *PSYSTICK_T ; // -------- SYSTICK_STCTRL : (STCTRL Offset: 0xE000E010) SysTick Control and Status Register -------- -#define SYSTICK_STCTRL_COUNT ((unsigned int)0x1 << 16) // 0 - The SysTick timer has not counted to 0 since the last time this bit was read. -#define SYSTICK_STCTRL_CLK ((unsigned int)0x1 << 2) // 1 - System clock -#define SYSTICK_STCTRL_INTEN ((unsigned int)0x1 << 1) // 1 - An interrupt is generated to the NVIC when SysTick counts to 0. -#define SYSTICK_STCTRL_ENABLE ((unsigned int)0x1 << 1) // Enables SysTick to operate in a multi-shot way. +#define SYSTICK_STCTRL_COUNT ((unsigned int)0x1 << 16) // 0 - The SysTick timer has not counted to 0 since the last time this bit was read. +#define SYSTICK_STCTRL_CLK ((unsigned int)0x1 << 2) // 1 - System clock +#define SYSTICK_STCTRL_INTEN ((unsigned int)0x1 << 1) // 1 - An interrupt is generated to the NVIC when SysTick counts to 0. +#define SYSTICK_STCTRL_ENABLE ((unsigned int)0x1 << 1) // Enables SysTick to operate in a multi-shot way. // -------- SYSTICK_STRELOAD : (STRELOAD Offset: 0xE000E014) Reload Value -------- #define SYSTICK_STRELOAD_MASK ((unsigned int)0xFFFFFF << 0) // IRQ mask // -------- SYSTICK_STCURRENT : (STCURRENT Offset: 0xE000E018) SysTick Current Value Register -------- @@ -155,7 +155,7 @@ typedef struct NVIC_S { REG_DWORD Res6[30] ; // 0xE000E2A0 REG_DWORD IABR[2] ; // 0xE000E300 REG_DWORD Res7[64] ; // 0xE000E320 - REG_DWORD IPR[2] ; // 0xE000E400 + REG_DWORD IPR[2] ; // 0xE000E400 // REG_DWORD Res7[515] ; // 0xE000E4F4 } NVIC_T, *PNVIC_T ; @@ -192,15 +192,15 @@ typedef struct SCB_S { /* module definitions */ -#define BOARD_BASE_ADDRESS_SYSTICK 0xE000E000 -#define BOARD_BASE_ADDRESS_NVIC 0xE000E100 -#define BOARD_BASE_ADDRESS_SCB 0xE000ED00 -#define BOARD_BASE_ADDRESS_GPTIMER0 0x40030000 +#define BOARD_BASE_ADDRESS_SYSTICK 0xE000E000 +#define BOARD_BASE_ADDRESS_NVIC 0xE000E100 +#define BOARD_BASE_ADDRESS_SCB 0xE000ED00 +#define BOARD_BASE_ADDRESS_GPTIMER0 0x40030000 -extern SYSTICK_T* const board_systick ; -extern NVIC_T* const board_nvic ; -extern SCB_T* const board_scb ; -extern GPTM_TIMER_T* const board_gptm0 ; +extern SYSTICK_T* const board_systick ; +extern NVIC_T* const board_nvic ; +extern SCB_T* const board_scb ; +extern GPTM_TIMER_T* const board_gptm0 ; /* Function prototypes */