From 3ac858b8e038b2435f47a8ad03422d196b15c3b9 Mon Sep 17 00:00:00 2001 From: kelvinlawson Date: Thu, 14 Jan 2010 13:59:49 -0700 Subject: [PATCH 01/28] github generated gh-pages branch --- index.html | 82 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 82 insertions(+) create mode 100644 index.html diff --git a/index.html b/index.html new file mode 100644 index 0000000..7fdf81a --- /dev/null +++ b/index.html @@ -0,0 +1,82 @@ + + + + + + + kelvinlawson/atomthreads @ GitHub + + + + + + + Fork me on GitHub + +
+ +
+ + + + +
+ +

atomthreads + by kelvinlawson

+ +
+ Lightweight, Portable RTOS Scheduler +
+ +

License

+

BSD

+

Authors

+

Kelvin Lawson (kelvinl@users.sf.net)

+

Contact

+

Kelvin Lawson (kelvinl@users.sf.net)

+ + +

Download

+

+ You can download this project in either + zip or + tar formats. +

+

You can also clone the project with Git + by running: + 

$ git clone git://github.com/kelvinlawson/atomthreads
+

+ +
+ get the source code on GitHub : kelvinlawson/atomthreads +
+ +
+ + + + From b9e7e9cc63a69180539219c8044cdf2078151593 Mon Sep 17 00:00:00 2001 From: Natie van Rooyen Date: Fri, 3 Sep 2010 22:23:47 +0200 Subject: [PATCH 02/28] New, atomvm! Added ATOM_TLS for TLS or other thread specific storage. --- kernel/atom.h | 4 + ports/atomvm/README.txt | 39 +++ ports/atomvm/atomport-tests.h | 58 ++++ ports/atomvm/atomport.c | 172 ++++++++++ ports/atomvm/atomport.h | 74 ++++ ports/atomvm/atomuser.h | 63 ++++ ports/atomvm/atomvm.c | 626 ++++++++++++++++++++++++++++++++++ ports/atomvm/atomvm.h | 72 ++++ ports/atomvm/test/main.c | 249 ++++++++++++++ 9 files changed, 1357 insertions(+) create mode 100644 ports/atomvm/README.txt create mode 100644 ports/atomvm/atomport-tests.h create mode 100644 ports/atomvm/atomport.c create mode 100644 ports/atomvm/atomport.h create mode 100644 ports/atomvm/atomuser.h create mode 100644 ports/atomvm/atomvm.c create mode 100644 ports/atomvm/atomvm.h create mode 100644 ports/atomvm/test/main.c diff --git a/kernel/atom.h b/kernel/atom.h index 43c3734..b725c66 100755 --- a/kernel/atom.h +++ b/kernel/atom.h @@ -66,6 +66,10 @@ typedef struct atom_tcb uint32_t stack_size; /* Size of stack allocation in bytes */ #endif +#ifdef ATOM_TLS + ATOM_TLS +#endif + } ATOM_TCB; diff --git a/ports/atomvm/README.txt b/ports/atomvm/README.txt new file mode 100644 index 0000000..0fa9099 --- /dev/null +++ b/ports/atomvm/README.txt @@ -0,0 +1,39 @@ +--------------------------------------------------------------------------- + +Library: Atomvn +Author: Natie van Rooyen +License: BSD Revised + +--------------------------------------------------------------------------- + +Atomvm is a tiny virtual machine that can run on Windows inside an IDE with a +debugger like Microsoft Visual C++ Express. The primary purpose of this VM is +for the evaluation of Real Time Operating Systems (like atomthreads) and +the development and testing of modules for this Real Time Operating System +in a user friendly environment. + +--------------------------------------------------------------------------- + +BUILDING THE SOURCE + +To test this project, just add all the files from the “atomthreads/kernel” +directory and the “atomthreads/ports/atomvm” directory as well as the test +program “atomthreads/ports/atomvm/test/main.c” to your project. Add both the +before mentioned directories to the include paths of your project and compile. + +Atomvm was designed for multi core systems but also runs well on single core +systems. + +--------------------------------------------------------------------------- + +RUNNING THE TESTS + +The test, main.c, was designed to stress the vm as opposed to testing the RTOS. +However, the test can also run the unit tests if desired by using the +precompiled directive UNIT_TESTS and linking in the desired unit test. + +--------------------------------------------------------------------------- + +FINALLY + +Good luck, but most of all, have fun! diff --git a/ports/atomvm/atomport-tests.h b/ports/atomvm/atomport-tests.h new file mode 100644 index 0000000..9f5320d --- /dev/null +++ b/ports/atomvm/atomport-tests.h @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2010, Kelvin Lawson. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. No personal names or organizations' names associated with the + * Atomthreads project may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __ATOM_PORT_TESTS_H +#define __ATOM_PORT_TESTS_H + +/* Include Atomthreads kernel API */ +#include "atom.h" + +/* Prerequisite include for ATOMLOG() macro (via printf) */ +#include + +/* Logger macro for viewing test results */ +#define ATOMLOG printf + +/* + * String location macro: for platforms which need to place strings in + * alternative locations, e.g. on avr-gcc strings can be placed in + * program space, saving SRAM. On most platforms this can expand to + * empty. + */ +#define _STR(x) x + +/* Default thread stack size (in bytes) */ +#define TEST_THREAD_STACK_SIZE 0x4000 + +/* Uncomment to enable logging of stack usage to UART */ +/* #define TESTS_LOG_STACK_USAGE */ + + +#endif /* __ATOM_PORT_TESTS_H */ + diff --git a/ports/atomvm/atomport.c b/ports/atomvm/atomport.c new file mode 100644 index 0000000..a832e03 --- /dev/null +++ b/ports/atomvm/atomport.c @@ -0,0 +1,172 @@ +/* + * Copyright (c) 2010, Kelvin Lawson. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. No personal names or organizations' names associated with the + * Atomthreads project may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include "atom.h" +#include "atomport.h" +#include "atomvm.h" + + +/** Forward declarations */ +static void thread_shell (void); +DWORD WINAPI cntrl_thread_proc (LPVOID lpParameter) ; + +/* Global data */ +HATOMVM the_atomvm ; + +/* Local data */ +static HANDLE cntrl_thread ; + + +/** + * \b atomvmRun + * + * Starts the atom vm. atomvmRun creates a thread from where the atomvmCtrlRun function + * will be called. atomvmCtrlRun never returns and this thread becomes the controll + * thread of the vm. + * + */ +void +atomvmRun () +{ + atomvmCtrlInit (&the_atomvm) ; + cntrl_thread = CreateThread (NULL, 0, cntrl_thread_proc, 0, CREATE_SUSPENDED, NULL) ; + ResumeThread (cntrl_thread) ; +} + +DWORD WINAPI +cntrl_thread_proc (LPVOID lpParameter) + { + atomvmCtrlRun (the_atomvm, 0) ; + return 0 ; + } + + +/** + * \b thread_shell + * + * Documented in atomThreads. + * + */ +void +thread_shell (void) +{ + ATOM_TCB *curr_tcb; + + /* Get the TCB of the thread being started */ + curr_tcb = atomCurrentContext(); + + /** + * Enable interrupts - these will not be enabled when a thread + * is first restored. + */ + // sei(); + atomvmExitCritical (the_atomvm) ; + + /* Call the thread entry point */ + if (curr_tcb && curr_tcb->entry_point) + { + curr_tcb->entry_point(curr_tcb->entry_param); + } + + /* Not reached - threads should never return from the entry point */ +} + + +/** + * \b archThreadContextInit + * + * Documented in atomThreads. + * + */ +void +archThreadContextInit (ATOM_TCB *tcb_ptr, void *stack_top, void (*entry_point)(uint32_t), uint32_t entry_param) +{ + tcb_ptr->sp_save_ptr = stack_top; + tcb_ptr->entry_param = entry_param ; + tcb_ptr->entry_point = entry_point ; + + atomvmContextCreate (the_atomvm, &tcb_ptr->context, (unsigned int )stack_top, (unsigned int )thread_shell) ; +} + + +/** + * \b archFirstThreadRestore + * + * Documented in atomThreads. + * + */ +void +archFirstThreadRestore(ATOM_TCB * p_sp_new) +{ + atomvmContextSwitch (the_atomvm, p_sp_new->context) ; +} + + +/** + * \b archContextSwitch + * + * Documented in atomThreads. + * + */ +void +archContextSwitch (ATOM_TCB * p_sp_old, ATOM_TCB * p_sp_new) +{ + atomvmContextSwitch (the_atomvm, p_sp_new->context) ; +} + + +/** + * \b archTimerTickIrqHandler + * + * System timer tick interrupt handler. + * + */ +void archTimerTickIrqHandler () +{ + atomIntEnter(); + + /* Call the OS system tick handler */ + atomTimerTick(); + + /* Call the interrupt exit routine */ + atomIntExit(TRUE); +} + + +unsigned int +__enter_critical () +{ + return atomvmEnterCritical (the_atomvm) ; +} + + +void +__exit_critical (unsigned int isr) +{ + atomvmExitCritical (the_atomvm) ; +} diff --git a/ports/atomvm/atomport.h b/ports/atomvm/atomport.h new file mode 100644 index 0000000..1022e3e --- /dev/null +++ b/ports/atomvm/atomport.h @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2010, Kelvin Lawson. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. No personal names or organizations' names associated with the + * Atomthreads project may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __ATOM_PORT_H__ +#define __ATOM_PORT_H__ + +#include "atomvm.h" + +#define SYSTEM_MEMALIGN sizeof (unsigned int) +#define SYSTEM_TICKS_PER_SEC 100 + + +typedef unsigned int uintptr_t ; +typedef int intptr_t ; +typedef unsigned int uint32_t ; +typedef unsigned short uint16_t ; +typedef unsigned char uint8_t ; +typedef int int32_t ; +typedef short int16_t ; +typedef char int8_t ; + + +/** + * Architecture-specific types. + * Most of these are available from stdint.h on this platform, which is + * included above. + */ +#define POINTER void * + + +/* Critical region protection */ +extern unsigned int __enter_critical() ; +extern void __exit_critical(unsigned int) ; + +#define CRITICAL_STORE unsigned int __atom +#define CRITICAL_START() __atom = __enter_critical() +#define CRITICAL_END() __exit_critical(__atom) + +#define ATOM_TLS HATOMVM_CONTEXT context ; + +/* Function prototypes */ +extern void atomvmRun () ; +extern void archTimerTickIrqHandler () ; + +/* The instance of the atomvm for this port */ +extern HATOMVM the_atomvm ; + +#endif /* __ATOM_PORT_H */ diff --git a/ports/atomvm/atomuser.h b/ports/atomvm/atomuser.h new file mode 100644 index 0000000..c12374d --- /dev/null +++ b/ports/atomvm/atomuser.h @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2010,Kelvin Lawson. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. No personal names or organizations' names associated with the + * Atomthreads project may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#if 1 +#ifndef __ATOM_USER_H__ +#define __ATOM_USER_H__ + + +/* Portable uint8_t and friends not available from stdint.h on this platform */ +#include + + +#define SYSTEM_MEMALIGN sizeof (unsigned int) + + +typedef unsigned int uintptr_t ; +typedef int intptr_t ; +typedef unsigned int uint32_t ; +typedef unsigned short uint16_t ; +typedef unsigned char uint8_t ; +typedef int int32_t ; +typedef short int16_t ; +typedef char int8_t ; + + +/** + * Architecture-specific types. + * Most of these are available from stdint.h on this platform, which is + * included above. + */ +#define POINTER void * + + +#define ATOM_TLS HATOMVM_CONTEXT context ; + + +#endif /* __ATOM_USER_H__ */ +#endif diff --git a/ports/atomvm/atomvm.c b/ports/atomvm/atomvm.c new file mode 100644 index 0000000..fe8ca3e --- /dev/null +++ b/ports/atomvm/atomvm.c @@ -0,0 +1,626 @@ +/* +* Copyright (c) 2010, Natie van Rooyen. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* 1. Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* 2. Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* 3. No personal names or organizations' names associated with the +* Atomthreads project may be used to endorse or promote products +* derived from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +*/ + +#include "atomvm.h" +#include + +#define CONTEXT_VM (CONTEXT_INTEGER | CONTEXT_CONTROL | CONTEXT_SEGMENTS) + +#define ATOMVM_ATOMVM_PERF_COUNTER(patomvm, counter) (InterlockedIncrement(&patomvm->perf_counters.counter)) + +/* Data types */ + +/* Forward declarations */ +typedef struct ATOMVM_S * PATOMVM ; +typedef struct ATOMVM_CALLBACK_S * PATOMVM_CALLBACK ; +typedef struct ATOMVM_CONTEXT_S * PATOMVM_CONTEXT ; + +typedef uint32_t (*ATOMVM_CALLBACK_F) (PATOMVM, PATOMVM_CALLBACK) ; + +typedef struct ATOMVM_CALLBACK_S { + + /* Address of callback function */ + volatile ATOMVM_CALLBACK_F callback ; + + /* Synchronization lock, the virtual machine will be suspended during + the callback. Regular WIN32 synchronization methods cant be used + because SuspendThread() is used on the vm thread. */ + volatile uint32_t lock ; + + /* Result of the call */ + volatile uint32_t result ; + +} ATOMVM_CALLBACK, *PATOMVM_CALLBACK ; + + +/* ATOMVM_CALLBACK_CONTEXT is the parameter for a ATOMVM_CALLBACK_F call +that take as parameter a pointer to a ATOMVM_CONTEXT to operate on */ +typedef struct ATOMVM_CALLBACK_CONTEXT_S { + + ATOMVM_CALLBACK callback ; + + /* Context the callback function will operate on */ + volatile PATOMVM_CONTEXT pcontext ; + +} ATOMVM_CALLBACK_CONTEXT, *PATOMVM_CALLBACK_CONTEXT ; + +typedef struct ATOMVM_PERF_COUNTERS_S { + + /* Number of interrupt requests */ + uint32_t int_request ; + + /* Number of service calls (context switches and + context init from atom virtual machime) */ + uint32_t service_call ; + + /* Total number of context switches */ + uint32_t context_switch ; + +} ATOMVM_PERF_COUNTERS, *PATOMVM_PERF_COUNTERS ; + +/* ATOMVM_CONTEXT saves the state of a context created by +atomvmContextCreate() and sheduled by atomvmContextSwitch(). */ +typedef struct ATOMVM_CONTEXT_S { + + /* A virtual machine thread context. These are saved and restored + during context initialization and context switches */ + CONTEXT context ; + + /* When entering a critical section the critical_count is + incremented for the context. Interrupts will only occur while + the critical_count is zero. The functions atomvmExitCritical() + and atomvmEnterCritical() will respectively decrement and + increment the critical count */ + volatile uint32_t critical_count ; + +} ATOMVM_CONTEXT, *PATOMVM_CONTEXT ; + +/* ATOMVM defines the state of an instance to an atomvm. It is created +by a call to atomvmCtrlInit(). */ +typedef struct ATOMVM_S { + + /* Thread the virtual machine will run in */ + HANDLE vm_thread ; + + /* Handles to events and mutexes used for synchronization */ + HANDLE atomvm_call ; + HANDLE atomvm_int ; + HANDLE atomvm_int_complete ; + HANDLE atomvm_close ; + + /* next ISR */ + volatile void (*isr)(void) ; + /* True if in an ISR */ + volatile uint32_t status_isr ; + + /* The current context that was scheduled by a call + to atomvmContextSwitch() */ + PATOMVM_CONTEXT current_context ; + + /* Service call address, synchronization lock, parameters + and, return value for the current service call */ + PATOMVM_CALLBACK service_call ; + + /* Context for startup, before any context was scheduled + (workaround to not check everytime if the first context + was already started) */ + ATOMVM_CONTEXT atom_init_context ; + + /* Performance counters */ + volatile ATOMVM_PERF_COUNTERS perf_counters ; + +} ATOMVM, *PATOMVM ; + + +/* Forward declaration for the atom virtual machine thread */ +static DWORD WINAPI vm_thread (LPVOID lpParameter) ; + + +/** +* \b atomvmCtrlInit +* +* This is an atomvm controll function used by a controlling thread +* and must not be called from the atom virtual machine. +* +* Initializes the virtual machine. +* +* ToDo: More Error checking. +* +* @param[out] atomvm Handle to the virtual machine created. +* +* @return Zero on failure. +*/ +uint32_t +atomvmCtrlInit (HATOMVM *atomvm) +{ + PATOMVM patomvm = (PATOMVM) malloc (sizeof(struct ATOMVM_S)) ; + + if (patomvm) { + + memset (patomvm, 0, sizeof(struct ATOMVM_S)) ; + + patomvm->atomvm_call = CreateEvent (NULL, TRUE, FALSE, 0) ; + patomvm->atomvm_int = CreateEvent (NULL, TRUE, FALSE, 0) ; + patomvm->atomvm_int_complete = CreateEvent (NULL, FALSE, TRUE, 0) ; + patomvm->atomvm_close = CreateEvent (NULL, TRUE, FALSE, 0) ; + + patomvm->vm_thread = CreateThread (NULL, 0, vm_thread, 0, CREATE_SUSPENDED, NULL) ; + + patomvm->atom_init_context.critical_count = 1 ; + patomvm->current_context = &patomvm->atom_init_context ; + + *atomvm = (HATOMVM)patomvm ; + + } + + return patomvm != 0 ; +} + + +/** +* \b atomvmCtrlRun +* +* This is an atomvm controll function used by a controlling thread +* and must not be called from the atom virtual machine. +* +* After a call to atomvmCtrlInit this function start the atom virtual machine. +* The calling thread will be used to manage interrupts and service calls in +* the virtual machine. This function will not return untill atomvmCtrlClose +* is called. +* +* @param[in] atomvm Handle to the virtual machine created by atomvmCtrlInit. +* @param[in] flags Reserved for later use. +* +* @return None +*/ +void +atomvmCtrlRun (HATOMVM atomvm, uint32_t flags) +{ + PATOMVM patomvm = (PATOMVM) atomvm ; + HANDLE wait[3] ; + uint32_t res ; + uint32_t wait_object ; + PATOMVM_CALLBACK pservice_call ; + + ResumeThread (patomvm->vm_thread) ; + + wait[0] = patomvm->atomvm_call ; + wait[1] = patomvm->atomvm_int ; + wait[2] = patomvm->atomvm_close ; + + for(;;) { + + wait_object = WaitForMultipleObjects (3, wait,FALSE,INFINITE) ; + + if (wait_object == WAIT_OBJECT_0) { + + ATOMVM_ATOMVM_PERF_COUNTER(patomvm, service_call) ; + + //InterlockedExchange ((volatile uint32_t*)&pservice_call, (uint32_t)patomvm->service_call) ; + pservice_call = patomvm->service_call ; + while (!pservice_call->lock) { + SwitchToThread () ; + } + + while ((res = SuspendThread (patomvm->vm_thread)) == (DWORD)-1) ; + ATOMVM_ASSERT(res == 0 , _T("SuspendThread failed")) ; +#if (_WIN32_WINNT >= 0x0600) + /* + This is used for multi processor machines to ensure the thread + is stopped before executing the next instruction. */ + FlushProcessWriteBuffers (); +#endif + InterlockedExchange (&pservice_call->result, pservice_call->callback (patomvm, pservice_call)) ; + InterlockedExchange (&pservice_call->lock, 0) ; + ResetEvent (patomvm->atomvm_call) ; + res = ResumeThread (patomvm->vm_thread) ; + ATOMVM_ASSERT(res == 1 , _T("ResumeThread failed")) ; + + } + + else if (wait_object == WAIT_OBJECT_0 + 1) { + + if (patomvm->current_context->critical_count == 0) { + + while ((res = SuspendThread (patomvm->vm_thread)) == (DWORD)-1) ; + ATOMVM_ASSERT(res == 0 , _T("SuspendThread failed")) ; +#if (_WIN32_WINNT >= 0x0600) + /* + This is used for multi processor machines to ensure the thread + is stopped before executing the next instruction. */ + FlushProcessWriteBuffers (); +#endif + if (patomvm->current_context->critical_count == 0) { + + ATOMVM_ATOMVM_PERF_COUNTER(patomvm, int_request) ; + + patomvm->status_isr++ ; + patomvm->isr () ; + patomvm->status_isr-- ; + + res = ResumeThread (patomvm->vm_thread) ; + ATOMVM_ASSERT(res == 1 , _T("ResumeThread failed")) ; + InterlockedExchange ((volatile uint32_t*)&patomvm->isr, 0) ; + ResetEvent (patomvm->atomvm_int) ; + SetEvent (patomvm->atomvm_int_complete) ; + + } else { + + res = ResumeThread (patomvm->vm_thread) ; + ATOMVM_ASSERT(res == 1 , _T("ResumeThread failed")) ; + SwitchToThread () ; + + } + + } else { + + SwitchToThread () ; + + } + + } else if (wait_object == WAIT_OBJECT_0 + 2) { + + break ; + + } + + } + +} + + +/** +* \b atomvmCtrlClose +* +* This is an atomvm controll function used by a controlling thread +* and must not be called from the atom virtual machine. +* +* Closes the virtual machine and release all memory and handles created +* in atomvmCtrlInit. +* +* ToDo: this function was never tested. +* +* @param[in] atomvm Handle to the virtual machine created by atomvmCtrlInit. +* +* @return None +*/ +void +atomvmCtrlClose (HATOMVM atomvm) +{ + PATOMVM patomvm = (PATOMVM) atomvm ; + DWORD code ; + + __atomvmClose () ; + + SetEvent (patomvm->atomvm_close) ; + do { + SwitchToThread () ; + GetExitCodeThread (patomvm->vm_thread, &code) ; + } while (code == STILL_ACTIVE) ; + + CloseHandle (patomvm->atomvm_call) ; + CloseHandle (patomvm->atomvm_int) ; + CloseHandle (patomvm->atomvm_int_complete) ; + CloseHandle (patomvm->atomvm_close) ; + CloseHandle (patomvm->vm_thread) ; + + free (atomvm) ; +} + + +/** +* \b invokeCallback +* +* Invokes callback functions in the context of the controll thread as +* requested from the virtual machine. In case this callback came from inside, +* an isr it is already in the conrtext of the controll thread and the callback +* routine is called directly. +* +* The atom virtual machine is suspended during the callback. +* +* @param[in] patomvm Pointer to the virtual machine created by atomvmCtrlInit. +* @param[in] callback Callback function. +* @param[in/out] context Context the function will operate on. +* +* @return Zero on failure, try to call GetLastError(). +*/ +uint32_t +invokeCallback (PATOMVM patomvm, ATOMVM_CALLBACK_F callback, PATOMVM_CALLBACK service_call) +{ + uint32_t res ; + + if (patomvm->status_isr == 0) { + + service_call->lock = 0 ; + service_call->callback = callback ; + patomvm->service_call = service_call ; + + SetEvent (patomvm->atomvm_call) ; + InterlockedIncrement (&service_call->lock) ; + while (service_call->lock != 0) ; + res = service_call->result ; + + } else { + + res = callback (patomvm, service_call) ; + + } + + return res ; +} + + +/** +* \b atomvmExitCritical +* +* This function is to be used by the atom virtual machine. +* +* This function will decrement the critical count for the current atomvm context. +* When the critical count reaches zero, interrupts will be enabled again. Calling +* this function from inside an isr has no effect. +* +* @param[in] atomvm Handle to the virtual machine created by atomvmCtrlInit. +* +* @return Critical count before this function was called. +*/ +int32_t +atomvmExitCritical (HATOMVM atomvm) +{ + PATOMVM patomvm = (PATOMVM) atomvm ; + int32_t count = 0; + + if (patomvm->status_isr == 0) { + count = InterlockedDecrement (&patomvm->current_context->critical_count) ; + } + + return count ; +} + + +/** +* \b atomvmEnterCritical +* +* This function is to be used by the atom virtual machine. +* +* This function will increment the critical count for the current atomvm +* context. Interrupts will be disabled when the critical count is not zero. +* Calling this function from inside an isr has no effect. +* +* All threads are created with a critical count of 1. +* +* @param[in] atomvm Handle to the virtual machine created by atomvmCtrlInit. +* +* @return Critical count before this function was called. +*/ +int32_t +atomvmEnterCritical (HATOMVM atomvm) +{ + PATOMVM patomvm = (PATOMVM) atomvm ; + int32_t count = 0 ; + + if (patomvm->status_isr == 0) { + count = InterlockedIncrement (&patomvm->current_context->critical_count) ; + } + + return count ; +} + + +/** +* \b atomvmCtrlIntRequest +* +* This is an atomvm controll function used by a controlling thread(s) +* and must not be called from the atom virtual machine. +* +* This function requests an interrupt service routine to be called in the +* context of the atom virtual machine. +* +* The call will block untill after the interrupt completes. +* +* @param[in] atomvm Handle to the virtual machine created by atomvmCtrlInit. +* @param[in] isr The address of the interrupt service routine. The routine must use +* the default calling convention of the compiler. +* +* @return None +*/ +void +atomvmCtrlIntRequest (HATOMVM atomvm, uint32_t isr) +{ + PATOMVM patomvm = (PATOMVM) atomvm ; + + while (InterlockedCompareExchange ((volatile uint32_t *)&patomvm->isr, isr, 0) == 0) { + SwitchToThread() ; + } + SignalObjectAndWait(patomvm->atomvm_int, patomvm->atomvm_int_complete, INFINITE, FALSE) ; + +} + + +/** +* \b callbackContextCreate +* +* This function is invoked from the controll thread after a call to atomvmContextCreate. +* +* The atom virtual machine is suspended while this function is called. +* +* @param[in] patomvm Pointer to the virtual machine created by atomvmCtrlInit. +* @param[out] context Context to be initialized. +* +* @return Zero on failure, try to call GetLastError(). +*/ +uint32_t +callbackContextCreate (PATOMVM patomvm, PATOMVM_CALLBACK callback) +{ + PATOMVM_CALLBACK_CONTEXT context_switch = (PATOMVM_CALLBACK_CONTEXT)callback; + CONTEXT * pcontext = &context_switch->pcontext->context ; + + pcontext->ContextFlags = CONTEXT_VM ; + + return GetThreadContext (patomvm->vm_thread, pcontext) ; +} + + +/** +* \b atomvmContextCreate +* +* This function is to be used by the atom virtual machine. +* +* This function creates a atomvm thread context that can be scheduled +* by atomvmContextSwitch. +* +* @param[in] atomvm Handle to the virtual machine created by atomvmCtrlInit. +* @param[out] context Handle to the context of the thread that are allocated +* by the caller. +* @param[in] stack Stack top. +* @param[in] entry Entry point using the default caling convention of the compiler. +* +* @return Zero on failure, try to call GetLastError(). +*/ +uint32_t +atomvmContextCreate (HATOMVM atomvm, HATOMVM_CONTEXT* atomvm_context, uint32_t stack, uint32_t entry) +{ + uint32_t res ; + PATOMVM patomvm = (PATOMVM) atomvm ; + PATOMVM_CONTEXT new_context = (PATOMVM_CONTEXT)malloc (sizeof(ATOMVM_CONTEXT)) ; + CONTEXT* pcontext = &new_context->context ; + ATOMVM_CALLBACK_CONTEXT context_init ; + + context_init.pcontext = new_context ; + + new_context->critical_count = 1 ; + + res = invokeCallback (patomvm, callbackContextCreate, (PATOMVM_CALLBACK)&context_init) ; + + if (res) { + pcontext->Ebp = stack ; + pcontext->Esp = stack ; + pcontext->Eip = entry ; + *atomvm_context = (HATOMVM_CONTEXT)new_context ; + } + + return res ; +} + + +/** +* \b callbackContextSwitch +* +* This function is invoked from the controll thread after a call to atomvmContextSwitch. +* +* The atom virtual machine is suspended while this function is called. +* +* @param[in] patomvm Pointer to the virtual machine created by atomvmCtrlInit. +* @param[out] context Context to be scheduled. +* +* @return Zero on failure, try to call GetLastError(). +*/ +uint32_t +callbackContextSwitch (PATOMVM patomvm, PATOMVM_CALLBACK callback) +{ + uint32_t res1 ; + uint32_t res2 ; + PATOMVM_CALLBACK_CONTEXT context_switch = (PATOMVM_CALLBACK_CONTEXT)callback ; + CONTEXT* pnew_context = &context_switch->pcontext->context ; + + ATOMVM_ATOMVM_PERF_COUNTER(patomvm, context_switch) ; + + res1 = GetThreadContext (patomvm->vm_thread, &patomvm->current_context->context) ; + ATOMVM_ASSERT(res1 , _T("GetThreadContext failed")) ; + + InterlockedExchange ((volatile uint32_t*)&patomvm->current_context, (uint32_t)pnew_context) ; + res2 = SetThreadContext (patomvm->vm_thread, &patomvm->current_context->context) ; + ATOMVM_ASSERT(res2 , _T("SetThreadContext failed")) ; + + return res1 & res2 ; +} + + +/** +* \b atomvmContextSwitch +* +* This function is to be used by the atom virtual machine. +* +* This function schedules a thread for the context created by atomvmContextCreate. +* +* @param[in] atomvm Handle to the virtual machine created by atomvmCtrlInit. +* @param[in] new_context The context to schedule. +* +* @return Zero on failure, try to call GetLastError(). +*/ +uint32_t +atomvmContextSwitch (HATOMVM atomvm, HATOMVM_CONTEXT new_context) +{ + PATOMVM patomvm = (PATOMVM) atomvm ; + ATOMVM_CALLBACK_CONTEXT context_switch ; + + context_switch.pcontext = (PATOMVM_CONTEXT) new_context ; + + return invokeCallback (patomvm, callbackContextSwitch, (PATOMVM_CALLBACK)&context_switch) ; +} + +/** +* \b atomvmContextDesrtroy +* +* This function is to be used by the atom virtual machine. +* +* This functiondestroyes a atomvm context created by atomvmContextCreate. +* +* @param[in] atomvm Handle to the virtual machine created by atomvmCtrlInit. +* @param[in] context The context to destroy. +* +* @return None +*/ +void +atomvmContextDesrtroy (HATOMVM atomvm, HATOMVM_CONTEXT context) +{ + PATOMVM patomvm = (PATOMVM) atomvm ; + + ATOMVM_ASSERT(patomvm->current_context != (PATOMVM_CONTEXT)context, + _T("atomvmContextDesrtroy failed")) ; + + free((void*)context) ; +} + + +/** +* \b vm_thread +* +* Windows thread in which the atom virtual machine will execute. +* +* __atomvmReset() runs the virtual machie and should only return after +* __atomvmClose() was called. +* +* @return None. +*/ +DWORD WINAPI +vm_thread (LPVOID lpParameter) +{ + __atomvmReset () ; + return 0 ; +} diff --git a/ports/atomvm/atomvm.h b/ports/atomvm/atomvm.h new file mode 100644 index 0000000..52ab2cb --- /dev/null +++ b/ports/atomvm/atomvm.h @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2010, Natie van Rooyen. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. No personal names or organizations' names associated with the + * Atomthreads project may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __ATOMVM_H__ +#define __ATOMVM_H__ + +#include +#include "atomuser.h" + + +#ifdef _DEBUG +#define ATOMVM_ASSERT(x, msg) _ASSERT(x) +#else +#define ATOMVM_ASSERT(x, msg) +#endif + + +/* Forward declarations */ + +/* This is an opaque handle to an instance of an atomvm created + by a call to atomvmCtrlInit() */ +typedef struct ATOMVM* HATOMVM ; + +/* This is an opaque handle to an atomvm context created + by a call to atomvmContextCreate() */ +typedef struct ATOMVM_CONTEXT* HATOMVM_CONTEXT ; + + +/* Function prototypes used for controlling the atom virtual machine */ +extern uint32_t atomvmCtrlInit (HATOMVM* atomvm) ; +extern void atomvmCtrlRun (HATOMVM atomvm, uint32_t flags) ; +extern void atomvmCtrlIntRequest (HATOMVM atomvm, uintptr_t isr) ; +extern void atomvmCtrlClose (HATOMVM atomvm) ; + +/* Function prototypes for use by the atom virtual machine */ +extern int32_t atomvmExitCritical (HATOMVM atomvm) ; +extern int32_t atomvmEnterCritical (HATOMVM atomvm) ; +extern uint32_t atomvmContextCreate (HATOMVM atomvm, HATOMVM_CONTEXT* context, uint32_t stack, uint32_t entry) ; +extern uint32_t atomvmContextSwitch (HATOMVM atomvm, HATOMVM_CONTEXT new_context) ; +extern void atomvmContextDesrtroy (HATOMVM atomvm, HATOMVM_CONTEXT context) ; + +/* Function prototypes to be implemted in the atom virtual machine */ +extern void __atomvmReset (void) ; +extern void __atomvmClose (void) ; + + +#endif /* __ATOMVM_H__ */ diff --git a/ports/atomvm/test/main.c b/ports/atomvm/test/main.c new file mode 100644 index 0000000..ed05b5b --- /dev/null +++ b/ports/atomvm/test/main.c @@ -0,0 +1,249 @@ +#include +#include + +#include "atom.h" +#include "atomvm.h" +#include "atomport.h" + + +// #define UNIT_TESTS +#ifdef UNIT_TESTS +extern uint32_t test_start (void) ; +#endif + +#define TEST_THREADS 51 + +#define TEST_STACK_BYTE_SIZE 0x10000 +#define IDLE_STACK_BYTE_SIZE 0x10000 +#define MONITOR_STACK_BYTE_SIZE 0x10000 + + + +static unsigned char idle_stack[IDLE_STACK_BYTE_SIZE] ; +static unsigned char monitor_stack[MONITOR_STACK_BYTE_SIZE] ; +static unsigned char test_stack[TEST_THREADS+1][TEST_STACK_BYTE_SIZE] ; +static unsigned int test_counter[TEST_THREADS+1] = {0} ; + +static unsigned int test2_counter = 0 ; +static unsigned int test3_counter = 0 ; +static unsigned int test_isr_count = 0 ; + + +static unsigned char test2_stack[TEST_STACK_BYTE_SIZE] ; +static unsigned char test3_stack[TEST_STACK_BYTE_SIZE] ; +static unsigned char test_idle_stack[TEST_STACK_BYTE_SIZE] ; + + +static uint8_t test_prio[60] = { + 001,010,100,200,250, 200,200,200,200,200, + 150,150,150,150,150, 250,250,250,250,250, + 101,102,103,104,105, 202,204,206,208,210, + 150,150,150,150,150, 250,250,250,250,250, + 121,122,123,124,125, 061,063,065,067,061, + 150,150,150,150,150, 250,250,250,250,250 + }; + +static uint32_t test_interv[60] = { + 001,001,001,001,001, 002,003,004,005,006, + 015,015,015,015,015, 025,024,023,022,021, + 905,005,005,005,805, 050,051,052,053,054, + 015,015,015,015,015, 025,024,023,022,021, + 030,030,030,030,030, 070,071,072,073,474, + 005,006,007,007,001, 001,001,003,003,005 + }; + + +ATOM_TCB test_tcb[TEST_THREADS+1] ; +ATOM_TCB monitor_tcb ; +ATOM_TCB test2_tcb ; +ATOM_TCB test3_tcb ; +ATOM_TCB test_idle_tcb ; + +DWORD WINAPI isr_thread_proc (LPVOID lpParameter) ; +static HANDLE isr_thread_1 ; +static HANDLE isr_thread_2 ; +static HANDLE isr_thread_3 ; +static HANDLE isr_thread_4 ; + +void +monitor_thread (uint32_t parm) +{ + CRITICAL_STORE; + int i ; + int c = 0 ; + ATOM_TCB *tcb ; + + tcb = atomCurrentContext() ; + + for (;;) + { + + CRITICAL_START(); + + printf("Monitor # %04d (%08d)\n", c++, atomTimeGet()) ; + printf("-------------------------\n") ; + + for (i=0; i Date: Tue, 7 Sep 2010 19:27:15 +0200 Subject: [PATCH 03/28] Initial realease. --- ports/atomvm/README.txt | 19 +++---- ports/atomvm/atomvm.c | 115 ++++++++++++++++++++-------------------- ports/atomvm/atomvm.h | 29 +++++----- 3 files changed, 81 insertions(+), 82 deletions(-) diff --git a/ports/atomvm/README.txt b/ports/atomvm/README.txt index 0fa9099..c12310a 100644 --- a/ports/atomvm/README.txt +++ b/ports/atomvm/README.txt @@ -7,9 +7,9 @@ License: BSD Revised --------------------------------------------------------------------------- Atomvm is a tiny virtual machine that can run on Windows inside an IDE with a -debugger like Microsoft Visual C++ Express. The primary purpose of this VM is -for the evaluation of Real Time Operating Systems (like atomthreads) and -the development and testing of modules for this Real Time Operating System +debugger like Microsoft Visual C++ Express. The primary purpose of this virtual +machine is for the evaluation of Real Time Operating Systems (like atomthreads) +and the development and testing of modules for this Real Time Operating System in a user friendly environment. --------------------------------------------------------------------------- @@ -21,19 +21,20 @@ directory and the program “atomthreads/ports/atomvm/test/main.c” to your project. Add both the before mentioned directories to the include paths of your project and compile. -Atomvm was designed for multi core systems but also runs well on single core -systems. +Atomvm was designed for multi core systems but also runs fine on any single +core system. --------------------------------------------------------------------------- RUNNING THE TESTS -The test, main.c, was designed to stress the vm as opposed to testing the RTOS. -However, the test can also run the unit tests if desired by using the -precompiled directive UNIT_TESTS and linking in the desired unit test. +The test, main.c, is intentioned to stress the virtual machine as opposed to +testing the Real Time Operating System. However, this test can also run the +unit tests of atomthreads by using the preprocessor directive "UNIT_TESTS" and +linking in the desired unit test into the project. --------------------------------------------------------------------------- FINALLY -Good luck, but most of all, have fun! +Good luck, but most of all, have fun!! diff --git a/ports/atomvm/atomvm.c b/ports/atomvm/atomvm.c index fe8ca3e..34075cb 100644 --- a/ports/atomvm/atomvm.c +++ b/ports/atomvm/atomvm.c @@ -30,31 +30,31 @@ #include "atomvm.h" #include -#define CONTEXT_VM (CONTEXT_INTEGER | CONTEXT_CONTROL | CONTEXT_SEGMENTS) +#define CONTEXT_VM (CONTEXT_INTEGER | CONTEXT_CONTROL | CONTEXT_SEGMENTS) -#define ATOMVM_ATOMVM_PERF_COUNTER(patomvm, counter) (InterlockedIncrement(&patomvm->perf_counters.counter)) +#define ATOMVM_ATOMVM_PERF_COUNTER(patomvm, counter) (InterlockedIncrement(&patomvm->perf_counters.counter)) /* Data types */ /* Forward declarations */ -typedef struct ATOMVM_S * PATOMVM ; -typedef struct ATOMVM_CALLBACK_S * PATOMVM_CALLBACK ; -typedef struct ATOMVM_CONTEXT_S * PATOMVM_CONTEXT ; +typedef struct ATOMVM_S * PATOMVM ; +typedef struct ATOMVM_CALLBACK_S * PATOMVM_CALLBACK ; +typedef struct ATOMVM_CONTEXT_S * PATOMVM_CONTEXT ; typedef uint32_t (*ATOMVM_CALLBACK_F) (PATOMVM, PATOMVM_CALLBACK) ; typedef struct ATOMVM_CALLBACK_S { /* Address of callback function */ - volatile ATOMVM_CALLBACK_F callback ; + volatile ATOMVM_CALLBACK_F callback ; /* Synchronization lock, the virtual machine will be suspended during the callback. Regular WIN32 synchronization methods cant be used because SuspendThread() is used on the vm thread. */ - volatile uint32_t lock ; + volatile uint32_t lock ; /* Result of the call */ - volatile uint32_t result ; + volatile uint32_t result ; } ATOMVM_CALLBACK, *PATOMVM_CALLBACK ; @@ -63,24 +63,24 @@ typedef struct ATOMVM_CALLBACK_S { that take as parameter a pointer to a ATOMVM_CONTEXT to operate on */ typedef struct ATOMVM_CALLBACK_CONTEXT_S { - ATOMVM_CALLBACK callback ; + ATOMVM_CALLBACK callback ; /* Context the callback function will operate on */ - volatile PATOMVM_CONTEXT pcontext ; + volatile PATOMVM_CONTEXT pcontext ; } ATOMVM_CALLBACK_CONTEXT, *PATOMVM_CALLBACK_CONTEXT ; typedef struct ATOMVM_PERF_COUNTERS_S { /* Number of interrupt requests */ - uint32_t int_request ; + uint32_t int_request ; /* Number of service calls (context switches and context init from atom virtual machime) */ - uint32_t service_call ; + uint32_t service_call ; /* Total number of context switches */ - uint32_t context_switch ; + uint32_t context_switch ; } ATOMVM_PERF_COUNTERS, *PATOMVM_PERF_COUNTERS ; @@ -90,14 +90,14 @@ typedef struct ATOMVM_CONTEXT_S { /* A virtual machine thread context. These are saved and restored during context initialization and context switches */ - CONTEXT context ; + CONTEXT context ; /* When entering a critical section the critical_count is incremented for the context. Interrupts will only occur while the critical_count is zero. The functions atomvmExitCritical() and atomvmEnterCritical() will respectively decrement and increment the critical count */ - volatile uint32_t critical_count ; + volatile uint32_t critical_count ; } ATOMVM_CONTEXT, *PATOMVM_CONTEXT ; @@ -106,40 +106,40 @@ by a call to atomvmCtrlInit(). */ typedef struct ATOMVM_S { /* Thread the virtual machine will run in */ - HANDLE vm_thread ; + HANDLE vm_thread ; /* Handles to events and mutexes used for synchronization */ - HANDLE atomvm_call ; - HANDLE atomvm_int ; - HANDLE atomvm_int_complete ; - HANDLE atomvm_close ; + HANDLE atomvm_call ; + HANDLE atomvm_int ; + HANDLE atomvm_int_complete ; + HANDLE atomvm_close ; /* next ISR */ - volatile void (*isr)(void) ; + volatile void (*isr)(void) ; /* True if in an ISR */ - volatile uint32_t status_isr ; + volatile uint32_t status_isr ; /* The current context that was scheduled by a call to atomvmContextSwitch() */ - PATOMVM_CONTEXT current_context ; + PATOMVM_CONTEXT current_context ; /* Service call address, synchronization lock, parameters and, return value for the current service call */ - PATOMVM_CALLBACK service_call ; + PATOMVM_CALLBACK service_call ; /* Context for startup, before any context was scheduled (workaround to not check everytime if the first context was already started) */ - ATOMVM_CONTEXT atom_init_context ; + ATOMVM_CONTEXT atom_init_context ; /* Performance counters */ - volatile ATOMVM_PERF_COUNTERS perf_counters ; + volatile ATOMVM_PERF_COUNTERS perf_counters ; } ATOMVM, *PATOMVM ; /* Forward declaration for the atom virtual machine thread */ -static DWORD WINAPI vm_thread (LPVOID lpParameter) ; +static DWORD WINAPI vm_thread (LPVOID lpParameter) ; /** @@ -202,11 +202,11 @@ atomvmCtrlInit (HATOMVM *atomvm) void atomvmCtrlRun (HATOMVM atomvm, uint32_t flags) { - PATOMVM patomvm = (PATOMVM) atomvm ; - HANDLE wait[3] ; - uint32_t res ; - uint32_t wait_object ; - PATOMVM_CALLBACK pservice_call ; + PATOMVM patomvm = (PATOMVM) atomvm ; + HANDLE wait[3] ; + uint32_t res ; + uint32_t wait_object ; + PATOMVM_CALLBACK service_call ; ResumeThread (patomvm->vm_thread) ; @@ -222,9 +222,8 @@ atomvmCtrlRun (HATOMVM atomvm, uint32_t flags) ATOMVM_ATOMVM_PERF_COUNTER(patomvm, service_call) ; - //InterlockedExchange ((volatile uint32_t*)&pservice_call, (uint32_t)patomvm->service_call) ; - pservice_call = patomvm->service_call ; - while (!pservice_call->lock) { + service_call = patomvm->service_call ; + while (!service_call->lock) { SwitchToThread () ; } @@ -236,8 +235,8 @@ atomvmCtrlRun (HATOMVM atomvm, uint32_t flags) is stopped before executing the next instruction. */ FlushProcessWriteBuffers (); #endif - InterlockedExchange (&pservice_call->result, pservice_call->callback (patomvm, pservice_call)) ; - InterlockedExchange (&pservice_call->lock, 0) ; + InterlockedExchange (&service_call->result, service_call->callback (patomvm, service_call)) ; + InterlockedExchange (&service_call->lock, 0) ; ResetEvent (patomvm->atomvm_call) ; res = ResumeThread (patomvm->vm_thread) ; ATOMVM_ASSERT(res == 1 , _T("ResumeThread failed")) ; @@ -313,8 +312,8 @@ atomvmCtrlRun (HATOMVM atomvm, uint32_t flags) void atomvmCtrlClose (HATOMVM atomvm) { - PATOMVM patomvm = (PATOMVM) atomvm ; - DWORD code ; + PATOMVM patomvm = (PATOMVM) atomvm ; + DWORD code ; __atomvmClose () ; @@ -392,8 +391,8 @@ invokeCallback (PATOMVM patomvm, ATOMVM_CALLBACK_F callback, PATOMVM_CALLBACK se int32_t atomvmExitCritical (HATOMVM atomvm) { - PATOMVM patomvm = (PATOMVM) atomvm ; - int32_t count = 0; + PATOMVM patomvm = (PATOMVM) atomvm ; + int32_t count = 0; if (patomvm->status_isr == 0) { count = InterlockedDecrement (&patomvm->current_context->critical_count) ; @@ -421,8 +420,8 @@ atomvmExitCritical (HATOMVM atomvm) int32_t atomvmEnterCritical (HATOMVM atomvm) { - PATOMVM patomvm = (PATOMVM) atomvm ; - int32_t count = 0 ; + PATOMVM patomvm = (PATOMVM) atomvm ; + int32_t count = 0 ; if (patomvm->status_isr == 0) { count = InterlockedIncrement (&patomvm->current_context->critical_count) ; @@ -452,7 +451,7 @@ atomvmEnterCritical (HATOMVM atomvm) void atomvmCtrlIntRequest (HATOMVM atomvm, uint32_t isr) { - PATOMVM patomvm = (PATOMVM) atomvm ; + PATOMVM patomvm = (PATOMVM) atomvm ; while (InterlockedCompareExchange ((volatile uint32_t *)&patomvm->isr, isr, 0) == 0) { SwitchToThread() ; @@ -477,8 +476,8 @@ atomvmCtrlIntRequest (HATOMVM atomvm, uint32_t isr) uint32_t callbackContextCreate (PATOMVM patomvm, PATOMVM_CALLBACK callback) { - PATOMVM_CALLBACK_CONTEXT context_switch = (PATOMVM_CALLBACK_CONTEXT)callback; - CONTEXT * pcontext = &context_switch->pcontext->context ; + PATOMVM_CALLBACK_CONTEXT context_switch = (PATOMVM_CALLBACK_CONTEXT)callback; + CONTEXT * pcontext = &context_switch->pcontext->context ; pcontext->ContextFlags = CONTEXT_VM ; @@ -505,11 +504,11 @@ callbackContextCreate (PATOMVM patomvm, PATOMVM_CALLBACK callback) uint32_t atomvmContextCreate (HATOMVM atomvm, HATOMVM_CONTEXT* atomvm_context, uint32_t stack, uint32_t entry) { - uint32_t res ; - PATOMVM patomvm = (PATOMVM) atomvm ; - PATOMVM_CONTEXT new_context = (PATOMVM_CONTEXT)malloc (sizeof(ATOMVM_CONTEXT)) ; - CONTEXT* pcontext = &new_context->context ; - ATOMVM_CALLBACK_CONTEXT context_init ; + uint32_t res ; + PATOMVM patomvm = (PATOMVM) atomvm ; + PATOMVM_CONTEXT new_context = (PATOMVM_CONTEXT)malloc (sizeof(ATOMVM_CONTEXT)) ; + CONTEXT* pcontext = &new_context->context ; + ATOMVM_CALLBACK_CONTEXT context_init ; context_init.pcontext = new_context ; @@ -543,10 +542,10 @@ atomvmContextCreate (HATOMVM atomvm, HATOMVM_CONTEXT* atomvm_context, uint32_t s uint32_t callbackContextSwitch (PATOMVM patomvm, PATOMVM_CALLBACK callback) { - uint32_t res1 ; - uint32_t res2 ; - PATOMVM_CALLBACK_CONTEXT context_switch = (PATOMVM_CALLBACK_CONTEXT)callback ; - CONTEXT* pnew_context = &context_switch->pcontext->context ; + uint32_t res1 ; + uint32_t res2 ; + PATOMVM_CALLBACK_CONTEXT context_switch = (PATOMVM_CALLBACK_CONTEXT)callback ; + CONTEXT* pnew_context = &context_switch->pcontext->context ; ATOMVM_ATOMVM_PERF_COUNTER(patomvm, context_switch) ; @@ -576,8 +575,8 @@ callbackContextSwitch (PATOMVM patomvm, PATOMVM_CALLBACK callback) uint32_t atomvmContextSwitch (HATOMVM atomvm, HATOMVM_CONTEXT new_context) { - PATOMVM patomvm = (PATOMVM) atomvm ; - ATOMVM_CALLBACK_CONTEXT context_switch ; + PATOMVM patomvm = (PATOMVM) atomvm ; + ATOMVM_CALLBACK_CONTEXT context_switch ; context_switch.pcontext = (PATOMVM_CONTEXT) new_context ; @@ -599,7 +598,7 @@ atomvmContextSwitch (HATOMVM atomvm, HATOMVM_CONTEXT new_context) void atomvmContextDesrtroy (HATOMVM atomvm, HATOMVM_CONTEXT context) { - PATOMVM patomvm = (PATOMVM) atomvm ; + PATOMVM patomvm = (PATOMVM) atomvm ; ATOMVM_ASSERT(patomvm->current_context != (PATOMVM_CONTEXT)context, _T("atomvmContextDesrtroy failed")) ; diff --git a/ports/atomvm/atomvm.h b/ports/atomvm/atomvm.h index 52ab2cb..3374506 100644 --- a/ports/atomvm/atomvm.h +++ b/ports/atomvm/atomvm.h @@ -34,7 +34,7 @@ #ifdef _DEBUG -#define ATOMVM_ASSERT(x, msg) _ASSERT(x) +#define ATOMVM_ASSERT(x, msg) _ASSERT(x) #else #define ATOMVM_ASSERT(x, msg) #endif @@ -44,29 +44,28 @@ /* This is an opaque handle to an instance of an atomvm created by a call to atomvmCtrlInit() */ -typedef struct ATOMVM* HATOMVM ; +typedef struct ATOMVM* HATOMVM ; /* This is an opaque handle to an atomvm context created by a call to atomvmContextCreate() */ -typedef struct ATOMVM_CONTEXT* HATOMVM_CONTEXT ; +typedef struct ATOMVM_CONTEXT* HATOMVM_CONTEXT ; /* Function prototypes used for controlling the atom virtual machine */ -extern uint32_t atomvmCtrlInit (HATOMVM* atomvm) ; -extern void atomvmCtrlRun (HATOMVM atomvm, uint32_t flags) ; -extern void atomvmCtrlIntRequest (HATOMVM atomvm, uintptr_t isr) ; -extern void atomvmCtrlClose (HATOMVM atomvm) ; +extern uint32_t atomvmCtrlInit (HATOMVM* atomvm) ; +extern void atomvmCtrlRun (HATOMVM atomvm, uint32_t flags) ; +extern void atomvmCtrlIntRequest (HATOMVM atomvm, uintptr_t isr) ; +extern void atomvmCtrlClose (HATOMVM atomvm) ; /* Function prototypes for use by the atom virtual machine */ -extern int32_t atomvmExitCritical (HATOMVM atomvm) ; -extern int32_t atomvmEnterCritical (HATOMVM atomvm) ; -extern uint32_t atomvmContextCreate (HATOMVM atomvm, HATOMVM_CONTEXT* context, uint32_t stack, uint32_t entry) ; -extern uint32_t atomvmContextSwitch (HATOMVM atomvm, HATOMVM_CONTEXT new_context) ; -extern void atomvmContextDesrtroy (HATOMVM atomvm, HATOMVM_CONTEXT context) ; +extern int32_t atomvmExitCritical (HATOMVM atomvm) ; +extern int32_t atomvmEnterCritical (HATOMVM atomvm) ; +extern uint32_t atomvmContextCreate (HATOMVM atomvm, HATOMVM_CONTEXT* context, uint32_t stack, uint32_t entry) ; +extern uint32_t atomvmContextSwitch (HATOMVM atomvm, HATOMVM_CONTEXT new_context) ; +extern void atomvmContextDesrtroy (HATOMVM atomvm, HATOMVM_CONTEXT context) ; /* Function prototypes to be implemted in the atom virtual machine */ -extern void __atomvmReset (void) ; -extern void __atomvmClose (void) ; +extern void __atomvmReset (void) ; +extern void __atomvmClose (void) ; - #endif /* __ATOMVM_H__ */ From 8a880d27161e47ee63e707a98c4e90e19122e5de Mon Sep 17 00:00:00 2001 From: Natie van Rooyen Date: Tue, 7 Sep 2010 19:37:59 +0200 Subject: [PATCH 04/28] Added "Thread Local Storage" --- kernel/atom.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/kernel/atom.h b/kernel/atom.h index b725c66..55d469e 100755 --- a/kernel/atom.h +++ b/kernel/atom.h @@ -67,7 +67,7 @@ typedef struct atom_tcb #endif #ifdef ATOM_TLS - ATOM_TLS + ATOM_TLS /* Thread Local Storage */ #endif } ATOM_TCB; From a3dec2170717df9cbbfbd13f3f4ad006bc80de60 Mon Sep 17 00:00:00 2001 From: navaro Date: Mon, 20 Sep 2010 01:43:38 -0700 Subject: [PATCH 05/28] --- ports/atomvm/README.txt | 80 ++++++++++++++++++++--------------------- 1 file changed, 40 insertions(+), 40 deletions(-) diff --git a/ports/atomvm/README.txt b/ports/atomvm/README.txt index c12310a..77b327e 100644 --- a/ports/atomvm/README.txt +++ b/ports/atomvm/README.txt @@ -1,40 +1,40 @@ ---------------------------------------------------------------------------- - -Library: Atomvn -Author: Natie van Rooyen -License: BSD Revised - ---------------------------------------------------------------------------- - -Atomvm is a tiny virtual machine that can run on Windows inside an IDE with a -debugger like Microsoft Visual C++ Express. The primary purpose of this virtual -machine is for the evaluation of Real Time Operating Systems (like atomthreads) -and the development and testing of modules for this Real Time Operating System -in a user friendly environment. - ---------------------------------------------------------------------------- - -BUILDING THE SOURCE - -To test this project, just add all the files from the “atomthreads/kernel” -directory and the “atomthreads/ports/atomvm” directory as well as the test -program “atomthreads/ports/atomvm/test/main.c” to your project. Add both the -before mentioned directories to the include paths of your project and compile. - -Atomvm was designed for multi core systems but also runs fine on any single -core system. - ---------------------------------------------------------------------------- - -RUNNING THE TESTS - -The test, main.c, is intentioned to stress the virtual machine as opposed to -testing the Real Time Operating System. However, this test can also run the -unit tests of atomthreads by using the preprocessor directive "UNIT_TESTS" and -linking in the desired unit test into the project. - ---------------------------------------------------------------------------- - -FINALLY - -Good luck, but most of all, have fun!! +--------------------------------------------------------------------------- + +Library: Atomvn +Author: Natie van Rooyen +License: BSD Revised + +--------------------------------------------------------------------------- + +Atomvm is a tiny virtual machine that can run on Windows inside an IDE with a +debugger like Microsoft Visual C++ Express. The primary purpose of this virtual +machine is for the evaluation of Real Time Operating Systems (like atomthreads) +and the development and testing of modules for this Real Time Operating System +in a user friendly environment. + +--------------------------------------------------------------------------- + +BUILDING THE SOURCE + +To test this project, just add all the files from the "atomthreads/kernel" +directory and the "atomthreads/ports/atomvm" directory as well as the test +program "atomthreads/ports/atomvm/test/main.c" to your project. Add both the +before mentioned directories to the include paths of your project and compile. + +Atomvm was designed for multi core systems but also runs fine on any single +core system. + +--------------------------------------------------------------------------- + +RUNNING THE TESTS + +The test, main.c, is intentioned to stress the virtual machine as opposed to +testing the Real Time Operating System. However, this test can also run the +unit tests of atomthreads by using the preprocessor directive "UNIT_TESTS" and +linking in the desired unit test into the project. + +--------------------------------------------------------------------------- + +FINALLY + +Good luck, but most of all, have fun!! From 202cbcf2dffb5ea4243e84f43b4fa05131e8353c Mon Sep 17 00:00:00 2001 From: Natie van Rooyen Date: Fri, 24 Sep 2010 18:44:18 +0200 Subject: [PATCH 06/28] interrupt request updated. started multicore support. --- ports/atomvm/atomport.c | 12 +- ports/atomvm/atomvm.c | 461 +++++++++++++++++++++++++++++++++++---- ports/atomvm/atomvm.h | 74 ++++++- ports/atomvm/test/main.c | 6 +- 4 files changed, 497 insertions(+), 56 deletions(-) diff --git a/ports/atomvm/atomport.c b/ports/atomvm/atomport.c index a832e03..b930fde 100644 --- a/ports/atomvm/atomport.c +++ b/ports/atomvm/atomport.c @@ -85,7 +85,7 @@ thread_shell (void) * is first restored. */ // sei(); - atomvmExitCritical (the_atomvm) ; + atomvmExitCritical () ; /* Call the thread entry point */ if (curr_tcb && curr_tcb->entry_point) @@ -110,7 +110,7 @@ archThreadContextInit (ATOM_TCB *tcb_ptr, void *stack_top, void (*entry_point)(u tcb_ptr->entry_param = entry_param ; tcb_ptr->entry_point = entry_point ; - atomvmContextCreate (the_atomvm, &tcb_ptr->context, (unsigned int )stack_top, (unsigned int )thread_shell) ; + atomvmContextCreate (&tcb_ptr->context, (unsigned int )stack_top, (unsigned int )thread_shell) ; } @@ -123,7 +123,7 @@ archThreadContextInit (ATOM_TCB *tcb_ptr, void *stack_top, void (*entry_point)(u void archFirstThreadRestore(ATOM_TCB * p_sp_new) { - atomvmContextSwitch (the_atomvm, p_sp_new->context) ; + atomvmContextSwitch (0, p_sp_new->context) ; } @@ -136,7 +136,7 @@ archFirstThreadRestore(ATOM_TCB * p_sp_new) void archContextSwitch (ATOM_TCB * p_sp_old, ATOM_TCB * p_sp_new) { - atomvmContextSwitch (the_atomvm, p_sp_new->context) ; + atomvmContextSwitch (p_sp_old->context, p_sp_new->context) ; } @@ -161,12 +161,12 @@ void archTimerTickIrqHandler () unsigned int __enter_critical () { - return atomvmEnterCritical (the_atomvm) ; + return atomvmEnterCritical () ; } void __exit_critical (unsigned int isr) { - atomvmExitCritical (the_atomvm) ; + atomvmExitCritical () ; } diff --git a/ports/atomvm/atomvm.c b/ports/atomvm/atomvm.c index 34075cb..8367d8d 100644 --- a/ports/atomvm/atomvm.c +++ b/ports/atomvm/atomvm.c @@ -27,8 +27,43 @@ * POSSIBILITY OF SUCH DAMAGE. */ +/** + * \file + * Atom Virtual Machine. + * + * + * This module implements the virtual machine. + * + * + * \b Functions contained in this module:\n + * + * \b Function prototypes used for controlling the atom virtual machine: \n + * + * \li atomvmCtrlInit(): . + * \li atomvmCtrlRun(): . + * \li atomvmCtrlIntRequest(): . + * \li atomvmCtrlClose(): . + * + * \b Function prototypes for use by the atom virtual machine: \n + * + * \li atomvmExitCritical(): . + * \li atomvmEnterCritical(): . + * \li atomvmContextCreate(): . + * \li atomvmContextSwitch(): . + * \li atomvmContextDesrtroy(): . + * + * \b Function prototypes to be implemted in the atom virtual machine: \n + * + * \li __atomvmReset(): . + * \li __atomvmClose(): . + * + */ + #include "atomvm.h" #include +#include + + #define CONTEXT_VM (CONTEXT_INTEGER | CONTEXT_CONTROL | CONTEXT_SEGMENTS) @@ -70,6 +105,31 @@ typedef struct ATOMVM_CALLBACK_CONTEXT_S { } ATOMVM_CALLBACK_CONTEXT, *PATOMVM_CALLBACK_CONTEXT ; + +/* ATOMVM_CALLBACK_CONTEXT_SWITCH is the parameter for a ATOMVM_CALLBACK_F call +that take as parameter a pointer to a ATOMVM_CONTEXT to operate on */ +typedef struct ATOMVM_CALLBACK_CONTEXT_SWITCH_S { + + ATOMVM_CALLBACK callback ; + + /* Context the callback function will operate on */ + volatile PATOMVM_CONTEXT p_old_context ; + volatile PATOMVM_CONTEXT p_new_context ; + +} ATOMVM_CALLBACK_CONTEXT_SWITCH, *PATOMVM_CALLBACK_CONTEXT_SWITCH ; + +/* ATOMVM_CALLBACK_IPI is the parameter for a ATOMVM_CALLBACK_F call +that take as parameter a pointer to a ipi target and the isr to call */ +typedef struct ATOMVM_CALLBACK_IPI_S { + + ATOMVM_CALLBACK callback ; + + /* Parameters the callback function will operate on */ + volatile uint32_t target ; + volatile uint32_t isr ; + +} ATOMVM_CALLBACK_IPI, *PATOMVM_CALLBACK_IPI ; + typedef struct ATOMVM_PERF_COUNTERS_S { /* Number of interrupt requests */ @@ -98,6 +158,7 @@ typedef struct ATOMVM_CONTEXT_S { and atomvmEnterCritical() will respectively decrement and increment the critical count */ volatile uint32_t critical_count ; + uint32_t thread_id ; } ATOMVM_CONTEXT, *PATOMVM_CONTEXT ; @@ -105,6 +166,8 @@ typedef struct ATOMVM_CONTEXT_S { by a call to atomvmCtrlInit(). */ typedef struct ATOMVM_S { + uint32_t atomvm_id ; + /* Thread the virtual machine will run in */ HANDLE vm_thread ; @@ -138,11 +201,19 @@ typedef struct ATOMVM_S { } ATOMVM, *PATOMVM ; +/* Global declarations */ +volatile uint32_t g_atomvm_counter = 0 ; +HANDLE g_atomvm_event = 0 ; +DWORD g_atomvm_tls_idx ; +PATOMVM g_vms[ATOMVM_MAX_VM] ; + + /* Forward declaration for the atom virtual machine thread */ static DWORD WINAPI vm_thread (LPVOID lpParameter) ; /** +* \ingroup atomvm * \b atomvmCtrlInit * * This is an atomvm controll function used by a controlling thread @@ -159,24 +230,41 @@ static DWORD WINAPI vm_thread (LPVOID lpParameter) ; uint32_t atomvmCtrlInit (HATOMVM *atomvm) { - PATOMVM patomvm = (PATOMVM) malloc (sizeof(struct ATOMVM_S)) ; + PATOMVM patomvm = 0 ; + int32_t i ; - if (patomvm) { + if (g_atomvm_counter < ATOMVM_MAX_VM) { - memset (patomvm, 0, sizeof(struct ATOMVM_S)) ; + patomvm = (PATOMVM) malloc (sizeof(struct ATOMVM_S)) ; - patomvm->atomvm_call = CreateEvent (NULL, TRUE, FALSE, 0) ; - patomvm->atomvm_int = CreateEvent (NULL, TRUE, FALSE, 0) ; - patomvm->atomvm_int_complete = CreateEvent (NULL, FALSE, TRUE, 0) ; - patomvm->atomvm_close = CreateEvent (NULL, TRUE, FALSE, 0) ; + if (patomvm) { - patomvm->vm_thread = CreateThread (NULL, 0, vm_thread, 0, CREATE_SUSPENDED, NULL) ; + memset (patomvm, 0, sizeof(struct ATOMVM_S)) ; - patomvm->atom_init_context.critical_count = 1 ; - patomvm->current_context = &patomvm->atom_init_context ; + patomvm->atomvm_id = InterlockedIncrement(&g_atomvm_counter) - 1 ; - *atomvm = (HATOMVM)patomvm ; + if (patomvm->atomvm_id == 0) { + g_atomvm_event = CreateEvent (NULL, FALSE, FALSE, 0) ; + g_atomvm_tls_idx = TlsAlloc () ; + for (i=0; iatomvm_id] = patomvm ; + patomvm->atomvm_call = CreateEvent (NULL, TRUE, FALSE, 0) ; + patomvm->atomvm_int = CreateEvent (NULL, TRUE, FALSE, 0) ; + patomvm->atomvm_int_complete = CreateEvent (NULL, FALSE, TRUE, 0) ; + patomvm->atomvm_close = CreateEvent (NULL, TRUE, FALSE, 0) ; + + patomvm->vm_thread = CreateThread (NULL, 0, vm_thread, (void*)patomvm, CREATE_SUSPENDED, NULL) ; + + patomvm->atom_init_context.critical_count = 1 ; + patomvm->current_context = &patomvm->atom_init_context ; + + *atomvm = (HATOMVM)patomvm ; + + } } return patomvm != 0 ; @@ -184,6 +272,7 @@ atomvmCtrlInit (HATOMVM *atomvm) /** +* \ingroup atomvm * \b atomvmCtrlRun * * This is an atomvm controll function used by a controlling thread @@ -207,6 +296,13 @@ atomvmCtrlRun (HATOMVM atomvm, uint32_t flags) uint32_t res ; uint32_t wait_object ; PATOMVM_CALLBACK service_call ; +#if defined DEBUG || defined _DEBUG + BOOL tls_res = +#endif + TlsSetValue (g_atomvm_tls_idx, (void*) atomvm) ; + + + ATOMVM_ASSERT(tls_res, _T("TlsSetValue failed")) ; ResumeThread (patomvm->vm_thread) ; @@ -240,6 +336,7 @@ atomvmCtrlRun (HATOMVM atomvm, uint32_t flags) ResetEvent (patomvm->atomvm_call) ; res = ResumeThread (patomvm->vm_thread) ; ATOMVM_ASSERT(res == 1 , _T("ResumeThread failed")) ; + } @@ -265,9 +362,10 @@ atomvmCtrlRun (HATOMVM atomvm, uint32_t flags) res = ResumeThread (patomvm->vm_thread) ; ATOMVM_ASSERT(res == 1 , _T("ResumeThread failed")) ; + + ResetEvent (patomvm->atomvm_int) ; InterlockedExchange ((volatile uint32_t*)&patomvm->isr, 0) ; - ResetEvent (patomvm->atomvm_int) ; - SetEvent (patomvm->atomvm_int_complete) ; + SetEvent (patomvm->atomvm_int_complete) ; } else { @@ -295,6 +393,7 @@ atomvmCtrlRun (HATOMVM atomvm, uint32_t flags) /** +* \ingroup atomvm * \b atomvmCtrlClose * * This is an atomvm controll function used by a controlling thread @@ -329,6 +428,8 @@ atomvmCtrlClose (HATOMVM atomvm) CloseHandle (patomvm->atomvm_close) ; CloseHandle (patomvm->vm_thread) ; + TlsFree (g_atomvm_tls_idx) ; + free (atomvm) ; } @@ -375,7 +476,27 @@ invokeCallback (PATOMVM patomvm, ATOMVM_CALLBACK_F callback, PATOMVM_CALLBACK se } +/* +* \b getAtomvm +* +* Get the atomvm instance for the calling thredd +* +* @return atomvm instance +*/ +__inline PATOMVM +getAtomvm () +{ + PATOMVM patomvm = (PATOMVM) TlsGetValue (g_atomvm_tls_idx) ; + + ATOMVM_ASSERT(patomvm , _T("TlsGetValue failed")) ; + + return patomvm ; + +} + + /** +* \ingroup atomvm * \b atomvmExitCritical * * This function is to be used by the atom virtual machine. @@ -384,14 +505,12 @@ invokeCallback (PATOMVM patomvm, ATOMVM_CALLBACK_F callback, PATOMVM_CALLBACK se * When the critical count reaches zero, interrupts will be enabled again. Calling * this function from inside an isr has no effect. * -* @param[in] atomvm Handle to the virtual machine created by atomvmCtrlInit. -* -* @return Critical count before this function was called. +* @return Critical count before the function call. */ int32_t -atomvmExitCritical (HATOMVM atomvm) +atomvmExitCritical () { - PATOMVM patomvm = (PATOMVM) atomvm ; + PATOMVM patomvm = getAtomvm () ; int32_t count = 0; if (patomvm->status_isr == 0) { @@ -403,6 +522,7 @@ atomvmExitCritical (HATOMVM atomvm) /** +* \ingroup atomvm * \b atomvmEnterCritical * * This function is to be used by the atom virtual machine. @@ -413,14 +533,13 @@ atomvmExitCritical (HATOMVM atomvm) * * All threads are created with a critical count of 1. * -* @param[in] atomvm Handle to the virtual machine created by atomvmCtrlInit. * -* @return Critical count before this function was called. +* @return Critical count before the function call. */ int32_t -atomvmEnterCritical (HATOMVM atomvm) +atomvmEnterCritical () { - PATOMVM patomvm = (PATOMVM) atomvm ; + PATOMVM patomvm = getAtomvm () ; int32_t count = 0 ; if (patomvm->status_isr == 0) { @@ -432,6 +551,24 @@ atomvmEnterCritical (HATOMVM atomvm) /** +* \ingroup atomvm +* \b atomvmCriticalCount +* +* Rerurns the critical cont of the current context. +* +* @return the critical cont of the current context. +*/ +int32_t +atomvmCriticalCount () +{ + PATOMVM patomvm = getAtomvm () ; + + return patomvm->current_context->critical_count ; +} + + +/** +* \ingroup atomvm * \b atomvmCtrlIntRequest * * This is an atomvm controll function used by a controlling thread(s) @@ -440,7 +577,7 @@ atomvmEnterCritical (HATOMVM atomvm) * This function requests an interrupt service routine to be called in the * context of the atom virtual machine. * -* The call will block untill after the interrupt completes. +* The call will block while a previously scheduled interrupt is in progress. * * @param[in] atomvm Handle to the virtual machine created by atomvmCtrlInit. * @param[in] isr The address of the interrupt service routine. The routine must use @@ -453,10 +590,11 @@ atomvmCtrlIntRequest (HATOMVM atomvm, uint32_t isr) { PATOMVM patomvm = (PATOMVM) atomvm ; + WaitForSingleObject (patomvm->atomvm_int_complete, INFINITE) ; while (InterlockedCompareExchange ((volatile uint32_t *)&patomvm->isr, isr, 0) == 0) { SwitchToThread() ; } - SignalObjectAndWait(patomvm->atomvm_int, patomvm->atomvm_int_complete, INFINITE, FALSE) ; + SetEvent (patomvm->atomvm_int) ; } @@ -486,6 +624,7 @@ callbackContextCreate (PATOMVM patomvm, PATOMVM_CALLBACK callback) /** +* \ingroup atomvm * \b atomvmContextCreate * * This function is to be used by the atom virtual machine. @@ -493,7 +632,6 @@ callbackContextCreate (PATOMVM patomvm, PATOMVM_CALLBACK callback) * This function creates a atomvm thread context that can be scheduled * by atomvmContextSwitch. * -* @param[in] atomvm Handle to the virtual machine created by atomvmCtrlInit. * @param[out] context Handle to the context of the thread that are allocated * by the caller. * @param[in] stack Stack top. @@ -502,10 +640,10 @@ callbackContextCreate (PATOMVM patomvm, PATOMVM_CALLBACK callback) * @return Zero on failure, try to call GetLastError(). */ uint32_t -atomvmContextCreate (HATOMVM atomvm, HATOMVM_CONTEXT* atomvm_context, uint32_t stack, uint32_t entry) +atomvmContextCreate (HATOMVM_CONTEXT* atomvm_context, uint32_t stack, uint32_t entry) { uint32_t res ; - PATOMVM patomvm = (PATOMVM) atomvm ; + PATOMVM patomvm = getAtomvm () ; PATOMVM_CONTEXT new_context = (PATOMVM_CONTEXT)malloc (sizeof(ATOMVM_CONTEXT)) ; CONTEXT* pcontext = &new_context->context ; ATOMVM_CALLBACK_CONTEXT context_init ; @@ -542,17 +680,20 @@ atomvmContextCreate (HATOMVM atomvm, HATOMVM_CONTEXT* atomvm_context, uint32_t s uint32_t callbackContextSwitch (PATOMVM patomvm, PATOMVM_CALLBACK callback) { - uint32_t res1 ; + uint32_t res1 = 1 ; uint32_t res2 ; - PATOMVM_CALLBACK_CONTEXT context_switch = (PATOMVM_CALLBACK_CONTEXT)callback ; - CONTEXT* pnew_context = &context_switch->pcontext->context ; + PATOMVM_CALLBACK_CONTEXT_SWITCH context_switch = (PATOMVM_CALLBACK_CONTEXT_SWITCH)callback ; + CONTEXT* p_old_context = &context_switch->p_old_context->context ; + CONTEXT* p_new_context = &context_switch->p_new_context->context ; ATOMVM_ATOMVM_PERF_COUNTER(patomvm, context_switch) ; - res1 = GetThreadContext (patomvm->vm_thread, &patomvm->current_context->context) ; - ATOMVM_ASSERT(res1 , _T("GetThreadContext failed")) ; + if (p_old_context) { + res1 = GetThreadContext (patomvm->vm_thread, p_old_context) ; + ATOMVM_ASSERT(res1 , _T("GetThreadContext failed")) ; + } - InterlockedExchange ((volatile uint32_t*)&patomvm->current_context, (uint32_t)pnew_context) ; + InterlockedExchange ((volatile uint32_t*)&patomvm->current_context, (uint32_t)p_new_context) ; res2 = SetThreadContext (patomvm->vm_thread, &patomvm->current_context->context) ; ATOMVM_ASSERT(res2 , _T("SetThreadContext failed")) ; @@ -561,44 +702,45 @@ callbackContextSwitch (PATOMVM patomvm, PATOMVM_CALLBACK callback) /** +* \ingroup atomvm * \b atomvmContextSwitch * * This function is to be used by the atom virtual machine. * * This function schedules a thread for the context created by atomvmContextCreate. * -* @param[in] atomvm Handle to the virtual machine created by atomvmCtrlInit. * @param[in] new_context The context to schedule. * * @return Zero on failure, try to call GetLastError(). */ uint32_t -atomvmContextSwitch (HATOMVM atomvm, HATOMVM_CONTEXT new_context) +atomvmContextSwitch (HATOMVM_CONTEXT old_context, HATOMVM_CONTEXT new_context) { - PATOMVM patomvm = (PATOMVM) atomvm ; - ATOMVM_CALLBACK_CONTEXT context_switch ; + PATOMVM patomvm = getAtomvm () ; + ATOMVM_CALLBACK_CONTEXT_SWITCH context_switch ; - context_switch.pcontext = (PATOMVM_CONTEXT) new_context ; + context_switch.p_old_context = (PATOMVM_CONTEXT) old_context ; + context_switch.p_new_context = (PATOMVM_CONTEXT) new_context ; return invokeCallback (patomvm, callbackContextSwitch, (PATOMVM_CALLBACK)&context_switch) ; } /** +* \ingroup atomvm * \b atomvmContextDesrtroy * * This function is to be used by the atom virtual machine. * * This functiondestroyes a atomvm context created by atomvmContextCreate. * -* @param[in] atomvm Handle to the virtual machine created by atomvmCtrlInit. * @param[in] context The context to destroy. * * @return None */ void -atomvmContextDesrtroy (HATOMVM atomvm, HATOMVM_CONTEXT context) +atomvmContextDesrtroy (HATOMVM_CONTEXT context) { - PATOMVM patomvm = (PATOMVM) atomvm ; + PATOMVM patomvm = getAtomvm () ; ATOMVM_ASSERT(patomvm->current_context != (PATOMVM_CONTEXT)context, _T("atomvmContextDesrtroy failed")) ; @@ -606,6 +748,240 @@ atomvmContextDesrtroy (HATOMVM atomvm, HATOMVM_CONTEXT context) free((void*)context) ; } +/** +* \ingroup atomvm +* \b atomvmWriteThreadId +* +* Write a thread ID. +* +* Write a thread ID for the current context. +* +* @param[in] thread_id thread_id. +* +* @return None +*/ +void +atomvmWriteThreadId (uint32_t thread_id) +{ + PATOMVM patomvm = getAtomvm () ; + + patomvm->current_context->thread_id = thread_id ; +} + +/** +* \ingroup atomvm +* \b atomvmReadThreadId +* +* Write a thread ID. +* +* Read a thread ID for the current context. +* +* @return thread_id +*/ +uint32_t +atomvmReadThreadId () +{ + PATOMVM patomvm = getAtomvm () ; + + return patomvm->current_context->thread_id ; +} + + +/** +* \ingroup atomvm +* \b atomvmGetVmId +* +* Returns an identifier for the virtual machine. This is zero for the first +* virtual machine created with atomvmCtrlInit(), 1 for the second and so on. +* +* @return The atom vm ID +*/ +uint32_t +atomvmGetVmId () +{ + PATOMVM patomvm = getAtomvm () ; + + return patomvm->atomvm_id ; +} +/** +* \b callbackEventWait +* +* This function is invoked from the controll thread after a call to atomvmEventWait. +* +* The atom virtual machine is suspended while this function is called. +* +* @param[in] patomvm Pointer to the virtual machine created by atomvmCtrlInit. +* @param[out] context Context to be scheduled. +* +* @return Zero on failure, try to call GetLastError(). +*/ +uint32_t +callbackEventWait (PATOMVM patomvm, PATOMVM_CALLBACK callback) +{ + return WaitForSingleObject (g_atomvm_event, INFINITE) == WAIT_OBJECT_0 ; + +} + + +/** +* \ingroup atomvm +* \b atomvmEventWait +* +* This function is to be used by the atom virtual machine. +* +* This function if for synchronization between multiple +* atom vms. +* +* +* @return void. +*/ +void +atomvmEventWait () +{ + PATOMVM patomvm = getAtomvm () ; + ATOMVM_CALLBACK callback ; + + invokeCallback (patomvm, callbackEventWait, (PATOMVM_CALLBACK)&callback) ; +} + +/** +* \b callbackEventSend +* +* This function is invoked from the controll thread after a call to atomvmEventSend. +* +* The atom virtual machine is suspended while this function is called. +* +* @param[in] patomvm Pointer to the virtual machine created by atomvmCtrlInit. +* @param[out] context Context to be scheduled. +* +* @return Zero on failure, try to call GetLastError(). +*/ +uint32_t +callbackEventSend (PATOMVM patomvm, PATOMVM_CALLBACK callback) +{ + return SetEvent (g_atomvm_event) ; +} + +/** +* \ingroup atomvm +* \b atomvmEventSend +* +* This function is to be used by the atom virtual machine. +* +* This function if for synchronization between multiple +* atom vms. +* +* +* @return void. +*/ +void +atomvmEventSend () +{ + PATOMVM patomvm = getAtomvm () ; + ATOMVM_CALLBACK callback ; + + invokeCallback (patomvm, callbackEventSend, (PATOMVM_CALLBACK)&callback) ; +} + +/** +* \b callbackInterruptWait +* +* This function is invoked from the controll thread after a call to atomvmInterruptWait(). +* +* The atom virtual machine is suspended while this function is called. +* +* @param[in] patomvm Pointer to the virtual machine created by atomvmCtrlInit. +* @param[out] callback Callback parameter. +* +* @return Zero on failure, try to call GetLastError(). +*/ +uint32_t +callbackInterruptWait (PATOMVM patomvm, PATOMVM_CALLBACK callback) +{ + return WaitForSingleObject (patomvm->atomvm_int, INFINITE) == WAIT_OBJECT_0 ; +} + +/** +* \ingroup atomvm +* \b atomvmInterruptWait +* +* This function is to be used by the atom virtual machine. +* +* This function if for synchronization between multiple +* atom vms. +* +* +* @return void. +*/ +void +atomvmInterruptWait () +{ + PATOMVM patomvm = getAtomvm () ; + ATOMVM_CALLBACK callback ; + + invokeCallback (patomvm, callbackInterruptWait, (PATOMVM_CALLBACK)&callback) ; +} + +/** +* \ingroup atomvm +* \b callbackScheduleIpi +* +* This function is invoked from the controll thread after a call to atomvmScheduleIpi(). +* +* This function if for synchronization between multiple +* atom vms. +* +* @param[in] target Target atomvm ID, less than ATOMVM_MAX_VM +* @param[in] isr interrupt service routine +* +* @return Zero on failure, try to call GetLastError(). +*/ +uint32_t +callbackScheduleIpi (PATOMVM patomvm, PATOMVM_CALLBACK callback) +{ + PATOMVM_CALLBACK_IPI callback_ipi = (PATOMVM_CALLBACK_IPI)callback ; + uint32_t res = 0 ; + + if ((callback_ipi->target < ATOMVM_MAX_VM) && + (g_vms[callback_ipi->target] != patomvm) ) { + + atomvmCtrlIntRequest ((HATOMVM)g_vms[callback_ipi->target], callback_ipi->isr) ; + res = 1 ; + + } + + return res ; +} + + +/** +* \ingroup atomvm +* \b atomvmScheduleIpi +* +* This function is to be used by the atom virtual machine. +* +* This function if for synchronization between multiple +* atom vms. +* +* @param[in] target Target atomvm ID +* @param[in] isr interrupt service routine +* +* @return Zero on failure, the vm is not running. +*/ +uint32_t +atomvmScheduleIpi (uint32_t target, uintptr_t isr) +{ + PATOMVM patomvm = getAtomvm () ; + ATOMVM_CALLBACK_IPI callback ; + + callback.target = target ; + callback.isr = isr ; + + return invokeCallback (patomvm, callbackScheduleIpi, (PATOMVM_CALLBACK)&callback) ; + + +} + /** * \b vm_thread @@ -620,6 +996,9 @@ atomvmContextDesrtroy (HATOMVM atomvm, HATOMVM_CONTEXT context) DWORD WINAPI vm_thread (LPVOID lpParameter) { + BOOL res = TlsSetValue (g_atomvm_tls_idx, lpParameter) ; + + ATOMVM_ASSERT(res, _T("TlsSetValue failed")) ; __atomvmReset () ; return 0 ; } diff --git a/ports/atomvm/atomvm.h b/ports/atomvm/atomvm.h index 3374506..acc10d6 100644 --- a/ports/atomvm/atomvm.h +++ b/ports/atomvm/atomvm.h @@ -26,6 +26,36 @@ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ + + + +/** \mainpage \ref atomvm +* \defgroup atomvm Atomvm API +* +* @authors Natie van Rooyen +* +* @section intro Introduction +* Atomvm is a tiny virtual machine that can run on Windows inside an IDE with a +* debugger like Microsoft Visual C++ Express. The primary purpose of this virtual +* machine is for the evaluation of Real Time Operating Systems (like atomthreads) +* and the development and testing of modules for this Real Time Operating System +* in a user friendly environment.: +* +* @section build Building The Source +* To test this project, just add all the files from the "atomthreads/kernel" +* directory and the "atomthreads/ports/atomvm" directory as well as the test +* program main.c to your project. Add both the +* before mentioned directories to the include paths of your project and compile. \n +* Atomvm was designed for multi core systems but also runs fine on any single +* core system. +* +* @section test Running The Test +* The test, main.c, is intentioned to stress the virtual machine as opposed to +* testing the Real Time Operating System. However, this test can also run the +* unit tests of atomthreads by using the preprocessor directive "UNIT_TESTS" and +* linking in the desired unit test into the project. +* */ + #ifndef __ATOMVM_H__ #define __ATOMVM_H__ @@ -33,13 +63,15 @@ #include "atomuser.h" -#ifdef _DEBUG +#if defined _DEBUG || defined DEBUG #define ATOMVM_ASSERT(x, msg) _ASSERT(x) #else #define ATOMVM_ASSERT(x, msg) #endif +#define ATOMVM_MAX_VM 8 + /* Forward declarations */ /* This is an opaque handle to an instance of an atomvm created @@ -58,14 +90,42 @@ extern void atomvmCtrlIntRequest (HATOMVM atomvm, uintptr_t isr) ; extern void atomvmCtrlClose (HATOMVM atomvm) ; /* Function prototypes for use by the atom virtual machine */ -extern int32_t atomvmExitCritical (HATOMVM atomvm) ; -extern int32_t atomvmEnterCritical (HATOMVM atomvm) ; -extern uint32_t atomvmContextCreate (HATOMVM atomvm, HATOMVM_CONTEXT* context, uint32_t stack, uint32_t entry) ; -extern uint32_t atomvmContextSwitch (HATOMVM atomvm, HATOMVM_CONTEXT new_context) ; -extern void atomvmContextDesrtroy (HATOMVM atomvm, HATOMVM_CONTEXT context) ; +extern int32_t atomvmExitCritical () ; +extern int32_t atomvmEnterCritical () ; +extern int32_t atomvmCriticalCount () ; +extern uint32_t atomvmContextCreate (HATOMVM_CONTEXT* context, uint32_t stack, uint32_t entry) ; +extern uint32_t atomvmContextSwitch (HATOMVM_CONTEXT old_context, HATOMVM_CONTEXT new_context) ; +extern void atomvmContextDesrtroy (HATOMVM_CONTEXT context) ; +extern void atomvmWriteThreadId (uint32_t thread_id) ; +extern uint32_t atomvmReadThreadId () ; +/* Function prototypes for use by the atom virtual machine + for synchronization with other running atom virtual machines */ +extern uint32_t atomvmGetVmId () ; +extern void atomvmInterruptWait () ; +extern void atomvmEventWait () ; +extern void atomvmEventSend () ; +extern uint32_t atomvmScheduleIpi (uint32_t target, uintptr_t isr) ; -/* Function prototypes to be implemted in the atom virtual machine */ + + + +/** +* \ingroup atomvm +* \b __atomvmReset +* +* Function prototype to be implemted in the atom virtual machine +* +* @return void. +*/ extern void __atomvmReset (void) ; +/** +* \ingroup atomvm +* \b __atomvmClose +* +* Function prototype to be implemted in the atom virtual machine +* +* @return void. +*/ extern void __atomvmClose (void) ; #endif /* __ATOMVM_H__ */ diff --git a/ports/atomvm/test/main.c b/ports/atomvm/test/main.c index ed05b5b..d991614 100644 --- a/ports/atomvm/test/main.c +++ b/ports/atomvm/test/main.c @@ -91,8 +91,10 @@ monitor_thread (uint32_t parm) printf("\nIdle Threadd 1 Counter = %d\nIdle Theadrd 2 Counter = %d\nInterrupt Counter = %d",test2_counter,test3_counter,test_isr_count); printf ("\n\n") ; CRITICAL_END(); - - atomTimerDelay (300) ; + //for (i=0; i<100;i++) { + // atomvmInterruptWait () ; + //} + atomTimerDelay (150) ; } } From 10b93017a3e307a7c8a93190687b3445d3debb20 Mon Sep 17 00:00:00 2001 From: Natie van Rooyen Date: Mon, 28 Feb 2011 16:49:35 +0100 Subject: [PATCH 07/28] atomvmCtrlIntRequest bug fix (and other updates) --- ports/atomvm/atomport.c | 4 ++-- ports/atomvm/atomvm.c | 38 ++++++++++++++++++++++++-------------- ports/atomvm/atomvm.h | 2 +- ports/atomvm/test/main.c | 2 +- 4 files changed, 28 insertions(+), 18 deletions(-) diff --git a/ports/atomvm/atomport.c b/ports/atomvm/atomport.c index b930fde..7660040 100644 --- a/ports/atomvm/atomport.c +++ b/ports/atomvm/atomport.c @@ -54,14 +54,14 @@ void atomvmRun () { atomvmCtrlInit (&the_atomvm) ; - cntrl_thread = CreateThread (NULL, 0, cntrl_thread_proc, 0, CREATE_SUSPENDED, NULL) ; + cntrl_thread = CreateThread (NULL, 0, cntrl_thread_proc, (uint32_t*)the_atomvm, CREATE_SUSPENDED, NULL) ; ResumeThread (cntrl_thread) ; } DWORD WINAPI cntrl_thread_proc (LPVOID lpParameter) { - atomvmCtrlRun (the_atomvm, 0) ; + atomvmCtrlRun ((HATOMVM)lpParameter, 0) ; return 0 ; } diff --git a/ports/atomvm/atomvm.c b/ports/atomvm/atomvm.c index c01c28d..286428a 100644 --- a/ports/atomvm/atomvm.c +++ b/ports/atomvm/atomvm.c @@ -176,6 +176,7 @@ typedef struct ATOMVM_S { HANDLE atomvm_int ; HANDLE atomvm_int_complete ; HANDLE atomvm_close ; + HANDLE atomvm_event ; /* next ISR */ volatile void (*isr)(void) ; @@ -203,8 +204,7 @@ typedef struct ATOMVM_S { /* Global declarations */ volatile uint32_t g_atomvm_counter = 0 ; -HANDLE g_atomvm_event = 0 ; -DWORD g_atomvm_tls_idx ; +volatile DWORD g_atomvm_tls_idx ; PATOMVM g_vms[ATOMVM_MAX_VM] ; @@ -244,7 +244,6 @@ atomvmCtrlInit (HATOMVM *atomvm) patomvm->atomvm_id = InterlockedIncrement(&g_atomvm_counter) - 1 ; if (patomvm->atomvm_id == 0) { - g_atomvm_event = CreateEvent (NULL, FALSE, FALSE, 0) ; g_atomvm_tls_idx = TlsAlloc () ; for (i=0; iatomvm_int = CreateEvent (NULL, TRUE, FALSE, 0) ; patomvm->atomvm_int_complete = CreateEvent (NULL, FALSE, TRUE, 0) ; patomvm->atomvm_close = CreateEvent (NULL, TRUE, FALSE, 0) ; + patomvm->atomvm_event = CreateEvent (NULL, FALSE, FALSE, 0) ; patomvm->vm_thread = CreateThread (NULL, 0, vm_thread, (void*)patomvm, CREATE_SUSPENDED, NULL) ; @@ -385,6 +385,10 @@ atomvmCtrlRun (HATOMVM atomvm, uint32_t flags) break ; + } else { + + ATOMVM_ASSERT(res == 1 , _T("WaitForMultipleObjects failed")) ; + } } @@ -554,9 +558,9 @@ atomvmEnterCritical () * \ingroup atomvm * \b atomvmCriticalCount * -* Rerurns the critical count of the current context. +* Rerurns the critical cont of the current context. * -* @return the critical count of the current context. +* @return the critical cont of the current context. */ int32_t atomvmCriticalCount () @@ -591,7 +595,7 @@ atomvmCtrlIntRequest (HATOMVM atomvm, uint32_t isr) PATOMVM patomvm = (PATOMVM) atomvm ; WaitForSingleObject (patomvm->atomvm_int_complete, INFINITE) ; - while (InterlockedCompareExchange ((volatile uint32_t *)&patomvm->isr, isr, 0) == 0) { + while (InterlockedCompareExchange ((volatile uint32_t *)&patomvm->isr, isr, 0) != 0) { SwitchToThread() ; } SetEvent (patomvm->atomvm_int) ; @@ -818,7 +822,7 @@ atomvmGetVmId () uint32_t callbackEventWait (PATOMVM patomvm, PATOMVM_CALLBACK callback) { - return WaitForSingleObject (g_atomvm_event, INFINITE) == WAIT_OBJECT_0 ; + return WaitForSingleObject (patomvm->atomvm_event, INFINITE) == WAIT_OBJECT_0 ; } @@ -859,7 +863,14 @@ atomvmEventWait () uint32_t callbackEventSend (PATOMVM patomvm, PATOMVM_CALLBACK callback) { - return SetEvent (g_atomvm_event) ; + int32_t i ; + for (i=0; iatomvm_event) ; + } + } + + return 1 ; } /** @@ -898,7 +909,7 @@ atomvmEventSend () uint32_t callbackInterruptWait (PATOMVM patomvm, PATOMVM_CALLBACK callback) { - //WaitForSingleObject (patomvm->atomvm_int_complete, INFINITE) ; + WaitForSingleObject (patomvm->atomvm_int_complete, INFINITE) ; return WaitForSingleObject (patomvm->atomvm_int, INFINITE) == WAIT_OBJECT_0 ; } @@ -943,13 +954,12 @@ callbackScheduleIpi (PATOMVM patomvm, PATOMVM_CALLBACK callback) PATOMVM_CALLBACK_IPI callback_ipi = (PATOMVM_CALLBACK_IPI)callback ; uint32_t res = 0 ; - if (callback_ipi->target < ATOMVM_MAX_VM) { - if (g_vms[callback_ipi->target] != patomvm) { + if ((callback_ipi->target < ATOMVM_MAX_VM) && + (g_vms[callback_ipi->target] != patomvm) ) { - atomvmCtrlIntRequest ((HATOMVM)g_vms[callback_ipi->target], callback_ipi->isr) ; - res = 1 ; + atomvmCtrlIntRequest ((HATOMVM)g_vms[callback_ipi->target], callback_ipi->isr) ; + res = 1 ; - } } return res ; diff --git a/ports/atomvm/atomvm.h b/ports/atomvm/atomvm.h index acc10d6..0b61570 100644 --- a/ports/atomvm/atomvm.h +++ b/ports/atomvm/atomvm.h @@ -64,7 +64,7 @@ #if defined _DEBUG || defined DEBUG -#define ATOMVM_ASSERT(x, msg) _ASSERT(x) +#define ATOMVM_ASSERT(x, msg) _ASSERT((x)) #else #define ATOMVM_ASSERT(x, msg) #endif diff --git a/ports/atomvm/test/main.c b/ports/atomvm/test/main.c index 9a7eb99..4bd4efb 100644 --- a/ports/atomvm/test/main.c +++ b/ports/atomvm/test/main.c @@ -11,7 +11,7 @@ extern uint32_t test_start (void) ; #endif -#define TEST_THREADS 51 +#define TEST_THREADS 47 #define TEST_STACK_BYTE_SIZE 0x10000 #define IDLE_STACK_BYTE_SIZE 0x10000 From 4a84c4cccfb60e972eb782468c0ece20a40ebe4a Mon Sep 17 00:00:00 2001 From: unknown Date: Mon, 14 May 2012 23:57:07 +0200 Subject: [PATCH 08/28] added armv7 and cortex_m3 port --- ports/armv7/Makefile | 19 +++ ports/armv7/README | 38 +++++ ports/armv7/atomport.c | 170 ++++++++++++++++++++++ ports/armv7/atomport.h | 54 +++++++ ports/armv7/atomport_arm.asm | 213 ++++++++++++++++++++++++++++ ports/armv7/atomport_private.h | 37 +++++ ports/armv7/types.h | 63 +++++++++ ports/cortex_m3/Makefile | 19 +++ ports/cortex_m3/README | 31 +++++ ports/cortex_m3/atomport.c | 194 ++++++++++++++++++++++++++ ports/cortex_m3/atomport.h | 54 +++++++ ports/cortex_m3/atomport_arm.asm | 217 +++++++++++++++++++++++++++++ ports/cortex_m3/atomport_private.h | 38 +++++ ports/cortex_m3/types.h | 44 ++++++ 14 files changed, 1191 insertions(+) create mode 100644 ports/armv7/Makefile create mode 100644 ports/armv7/README create mode 100644 ports/armv7/atomport.c create mode 100644 ports/armv7/atomport.h create mode 100644 ports/armv7/atomport_arm.asm create mode 100644 ports/armv7/atomport_private.h create mode 100644 ports/armv7/types.h create mode 100644 ports/cortex_m3/Makefile create mode 100644 ports/cortex_m3/README create mode 100644 ports/cortex_m3/atomport.c create mode 100644 ports/cortex_m3/atomport.h create mode 100644 ports/cortex_m3/atomport_arm.asm create mode 100644 ports/cortex_m3/atomport_private.h create mode 100644 ports/cortex_m3/types.h diff --git a/ports/armv7/Makefile b/ports/armv7/Makefile new file mode 100644 index 0000000..87b9c17 --- /dev/null +++ b/ports/armv7/Makefile @@ -0,0 +1,19 @@ +ATOMTHREADS_PORT = $(COLOSSAL)/libraries/atomthreads/ports/armv7 +ATOMTHREADS_KERNEL = $(COLOSSAL)/libraries/atomthreads/kernel + +INCLUDES := $(INCLUDES) \ + -I$(ATOMTHREADS_KERNEL) \ + -I$(ATOMTHREADS_PORT) + +SRCS := $(SRCS) \ + $(ATOMTHREADS_KERNEL)/atomkernel.c \ + $(ATOMTHREADS_KERNEL)/atommutex.c \ + $(ATOMTHREADS_KERNEL)/atomqueue.c \ + $(ATOMTHREADS_KERNEL)/atomsem.c \ + $(ATOMTHREADS_KERNEL)/atomtimer.c \ + $(ATOMTHREADS_PORT)/atomport.c + +ASMS := $(ASMS) \ + $(ATOMTHREADS_PORT)/atomport_arm.asm + + diff --git a/ports/armv7/README b/ports/armv7/README new file mode 100644 index 0000000..f3bc0fa --- /dev/null +++ b/ports/armv7/README @@ -0,0 +1,38 @@ +--------------------------------------------------------------------------- + +Library: Atomthreads ARMv7 Port +Author: Natie van Rooyen +License: BSD Revised + +--------------------------------------------------------------------------- + +ARM ARMv7 PORT + +This folder contains a port of the Atomthreads real time kernel for the +ARMv7 processor architecture. This port was only tested on a ARMv7 but +should work on other versions of the ARM processor as well. + +To Use: + +1. From your platforms IRQ vector branch to the "__irq_context_handler()". + All interrupts from where calls to Atomthreads will be made should do + this. The "__irq_context_handler()" will call a platform specific + function called "__context_preempt_handler()" to dispatch the interrupt. + +2. Implement the function "__context_preempt_handler()" + from where your platforms interrupt cotroller will be serviced and the + interrupt will be dispatched to a specic interrupt service routine. In + the case of your platforms timer tick interrupt call the "archTickHandler()" + implemented in "atomport.c". + +3. Initialize your platforms timer tick hardware to generata an OS timer tick + interrupt. + +4. Add code to acknowledge your timer hardware's interrupt in the + function "archTickHandler()" implemented in "atomport.c". This must + be done here because "atomIntExit()" might switch the context. + +5. After your platforms c-runtime initialization has completed, start + Atomthreads from your runtime's "main()" function. + +6. Include the port's Maefile in your platform build flow. \ No newline at end of file diff --git a/ports/armv7/atomport.c b/ports/armv7/atomport.c new file mode 100644 index 0000000..bac9c17 --- /dev/null +++ b/ports/armv7/atomport.c @@ -0,0 +1,170 @@ +/* + * Copyright (c) 2012, Natie van Rooyen. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. No personal names or organizations' names associated with the + * Atomthreads project may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include "atom.h" +#include "atomport.h" +#include "types.h" + + +/* * + * + * Functions defined in atomport_arm.asm + * + */ +extern void contextInit (void) ; +extern void contextSwitch (SYSCONTEXT* save_context, SYSCONTEXT* new_context) ; +extern void contextStart (SYSCONTEXT* context) ; +extern uint32_t contextEnterCritical (void) ; +extern void contextExitCritical (uint32_t posture) ; +extern void contextEnableInterrupts (void) ; + +/** + * \b thread_shell + * + * Documented in atomThreads. + * + */ +void +thread_shell (void) +{ + ATOM_TCB *curr_tcb; + + /* Get the TCB of the thread being started */ + curr_tcb = atomCurrentContext(); + + /** + * Enable interrupts - these will not be enabled when a thread + * is first restored. + */ + // sei(); + contextEnableInterrupts () ; + + /* Call the thread entry point */ + if (curr_tcb && curr_tcb->entry_point) + { + curr_tcb->entry_point(curr_tcb->entry_param); + } + + /* Not reached - threads should never return from the entry point */ +} + + +/** + * \b archThreadContextInit + * + * Documented in atomThreads. + * + */ +void +archThreadContextInit (ATOM_TCB *tcb_ptr, void *stack_top, void (*entry_point)(uint32_t), uint32_t entry_param) +{ + uint32_t * stack_ptr ; + + tcb_ptr->sp_save_ptr = stack_top; + tcb_ptr->entry_param = entry_param ; + tcb_ptr->entry_point = entry_point ; + + stack_ptr = (uint32_t *)stack_top; //-- Load stack pointer + + *stack_ptr = ( uint32_t ) entry ; + stack_ptr--; + + *stack_ptr = ( uint32_t ) 0x00001111; /* R11 */ + stack_ptr--; + *stack_ptr = ( uint32_t ) 0x00001010; /* R10 */ + stack_ptr--; + *stack_ptr = ( uint32_t ) 0x00000909; /* R9 */ + stack_ptr--; + *stack_ptr = ( uint32_t ) 0x00000808; /* R8 */ + stack_ptr--; + *stack_ptr = ( uint32_t ) 0x00000707; /* R7 */ + stack_ptr--; + *stack_ptr = ( uint32_t ) 0x00000606; /* R6 */ + stack_ptr--; + *stack_ptr = ( uint32_t ) 0x00000505; /* R5 */ + stack_ptr--; + *stack_ptr = ( uint32_t ) 0x00000404; /* R4 */ + +// #ifdef CONTEXT_THREAD_ID + stack_ptr--; + *stack_ptr = context_thread_id++ ; /* thread_id */ +// #endif + + tcb_ptr->sp_save_ptr = stack_ptr ; +} + + +/** + * \b archFirstThreadRestore + * + * Documented in atomThreads. + * + */ +void +archFirstThreadRestore(ATOM_TCB * p_sp_new) +{ + contextStart (&p_sp_new->sp_save_ptr) ; +} + + +/** + * \b archContextSwitch + * + * Documented in atomThreads. + * + */ +void +archContextSwitch (ATOM_TCB * p_sp_old, ATOM_TCB * p_sp_new) +{ + contextSwitch (&p_sp_old->sp_save_ptr, &p_sp_new->sp_save_ptr) ; +} + + +/** + * \b archTimerTickIrqHandler + * + * System timer tick interrupt handler. + * + */ +void +archTickHandler (void) +{ + atomIntEnter(); + + /* Call the OS system tick handler */ + atomTimerTick(); + + /* ack the interrupt if needed */ + /* ... */ + + /* Call the interrupt exit routine */ + atomIntExit(TRUE); +} + + + diff --git a/ports/armv7/atomport.h b/ports/armv7/atomport.h new file mode 100644 index 0000000..2a6cf50 --- /dev/null +++ b/ports/armv7/atomport.h @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2012, Natie van Rooyen. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. No personal names or organizations' names associated with the + * Atomthreads project may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __ATOM_PORT_H__ +#define __ATOM_PORT_H__ + +#include "arch/context.h" +#include "types.h" + +#define SYSTEM_TICKS_PER_SEC 1000 + + +/** + * Architecture-specific types. + * Most of these are available from types.h on this platform, which is + * included above. + */ +#define POINTER void * + + +/* Critical region protection */ + +#define CRITICAL_STORE uint32_t __atom_critical +#define CRITICAL_START() __atom_critical = contextEnterCritical() +#define CRITICAL_END() contextExitCritical(__atom_critical) + + +#endif /* __ATOM_PORT_H__ */ diff --git a/ports/armv7/atomport_arm.asm b/ports/armv7/atomport_arm.asm new file mode 100644 index 0000000..9ba9664 --- /dev/null +++ b/ports/armv7/atomport_arm.asm @@ -0,0 +1,213 @@ +; +; Copyright (c) 2012, Natie van Rooyen. All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions +; are met: +; +; 1. Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the distribution. +; 3. No personal names or organizations' names associated with the +; Atomthreads project may be used to endorse or promote products +; derived from this software without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS +; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +; TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +; PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE +; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +; POSSIBILITY OF SUCH DAMAGE. +; + + + PRESERVE8 {TRUE} + AREA UTILS, CODE, READONLY +;-- + EXPORT contextInit + EXPORT contextSwitch + EXPORT contextStart + EXPORT contextEnableInterrupts + EXPORT contextEnterCritical + EXPORT contextExitCritical + EXPORT __irq_context_handler + + + EXTERN archTickHandler + +;-- +ARM_SVC_MODE EQU 0xd3 +ARM_IRQ_MODE EQU 0xD2 +ARM_FIQ_MODE EQU 0xD1 +ARM_MODE_MASK EQU 0x1F +ARM_FIQ_MODE_BITS EQU 0x11 +ARM_IRQ_MODE_BITS EQU 0x12 +ARM_SVC_MODE_BITS EQU 0x13 + +CONTEXT_SWITCH_MODE EQU ARM_SVC_MODE + + ARM + +;-- +; \b contextInit +; +; Architecture-specific one time initialization. +; +; @return None +; +contextInit + + BX lr + +;-- +; \b contextSwitch +; +; Architecture-specific context switch routine. +; +; Note that interrupts are always locked out when this routine is +; called. For cooperative switches, the scheduler will have entered +; a critical region. For preemptions (called from an ISR), the +; interrupts will have disabled in the tick_Handler. +; +; @param[in] [r0] -> Address to save old stack pointer +; @param[in] [r1] -> Address where new stack pointer is stored +; +; @return None +; +contextSwitch + STMFD sp!, {r4 - r11, lr} ;- Save registers + + ;- IF :DEF:CONTEXT_THREAD_ID + MRC p15,0,r3,c13,c0,2 + STMFD sp!, {r3} + ;- ENDIF + + STR sp, [r0] ;- Save old stack pointer + LDR r1, [r1] + MOV sp, r1 ;- Load new stack pointer + + ISB + + ;- IF :DEF:CONTEXT_THREAD_ID + LDMFD sp!, {r3} + MCR p15,0,r3,c13,c0,2 + ;- ENDIF + + LDMFD sp!, {r4 - r11, pc} ;- Load new registers + +;-- +; \b contextStart +; +; Architecture-specific context start routine. +; +; @param[in] [r0] -> Address where stack pointer is stored +; +; @return Does not return +; +contextStart + LDR r0, [r0] + MOV sp, r0 ;- Load new stack pointer + + ;- IF :DEF:CONTEXT_THREAD_ID + LDMFD sp!, {r3} + MCR p15,0,r3,c13,c0,2 + ;- ENDIF + + LDMFD sp!, {r4 - r11, pc} ;- Load new registers + +;-- +; \b contextId +; +; Returns a unique ID for the context +; +; @return ID +; +contextId + MRC p15,0,r0,c13,c0,2 + BX lr + +;-- +; \b contextEnableInterrupts +; +; Enables interrupts on the processor +; +; @return None +; +contextEnableInterrupts + MRS r0,CPSR + MOV r1, #0x80 + BIC r0,r0,r1 + MSR CPSR_c,r0 + BX lr + + +;-- +; \b contextExitCritical +; +; Exit critical section (restores interrupt posture) +; +; @param[in] r0 Interrupt Posture +; +; @return None +; +contextExitCritical + MSR CPSR_cxsf,r0 + BX lr + + +;-- +; \b contextEnterCritical +; +; Enter critical section (disables interrupts) +; +; @return Current interrupt posture +; +contextEnterCritical + MRS r0,CPSR + ORR r1,r0,#0x80 + MSR CPSR_cxsf,r1 + BX lr + +;-- +; \b __irq_context_handler +; +; IRQ entry point +; +; @return None +; +__irq_context_handler + + MSR cpsr_c, #CONTEXT_SWITCH_MODE ;- Save current process context + STMFD sp!, {r0 - r3, ip, lr} + + MSR cpsr_c, #ARM_IRQ_MODE ;- Save lr_irq and spsr_irq in process stack + SUB lr,lr,#4 + MOV r1, lr + MRS r2, spsr + MSR cpsr_c, #CONTEXT_SWITCH_MODE + STMFD sp!, {r1, r2} + + BL __context_preempt_handler ;- Dispatch the interrupt to archTickHandler for the timer tick interrupt or a simular function for other interrupts which might call atomthread functions. + + LDMFD sp!, {r1, r2} ;- Restore lr_irq and spsr_irq from process stack + MSR cpsr_c, #ARM_IRQ_MODE + STMFD sp!, {r1} + MSR spsr_cxsf, r2 + + MSR cpsr_c, #CONTEXT_SWITCH_MODE ;- Restore process regs + LDMFD sp!, {r0 - r3, ip, lr} + + MSR cpsr_c, #ARM_IRQ_MODE ;- Exit from ISR + + LDMFD sp!, {pc}^ + + +;-- + END diff --git a/ports/armv7/atomport_private.h b/ports/armv7/atomport_private.h new file mode 100644 index 0000000..c0dfc6d --- /dev/null +++ b/ports/armv7/atomport_private.h @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2012, Natie van Rooyen. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. No personal names or organizations' names associated with the + * Atomthreads project may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __ATOM_PORT_PRIVATE_H__ +#define __ATOM_PORT_PRIVATE_H__ + + +/* Function prototypes */ +extern void archTickHandler (void) ; + +#endif /* __ATOM_PORT_PRIVATE_H__ */ diff --git a/ports/armv7/types.h b/ports/armv7/types.h new file mode 100644 index 0000000..0fd6feb --- /dev/null +++ b/ports/armv7/types.h @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2012, Natie van Rooyen. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. No personal names or organizations' names associated with the + * Atomthreads project may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __TYPES_H__ +#define __TYPES_H__ + +typedef unsigned int uintptr_t ; +typedef int intptr_t ; +typedef unsigned long long uint64_t ; +typedef unsigned int uint32_t ; +typedef unsigned short uint16_t ; +typedef unsigned char uint8_t ; +typedef int int32_t ; +typedef short int16_t ; +typedef char int8_t ; + +typedef volatile unsigned int REG_DWORD ;// Hardware register definition + +#define UWORD64 unsigned long long +#define UWORD32 unsigned int +#define UWORD16 unsigned short +#define UWORD8 unsigned char +#define WORD32 int +#define WORD16 short +#define WORD8 char + +#ifndef OFFSETOF +#define OFFSETOF(TYPE, MEMBER) ((int) &((TYPE *)0)->MEMBER) +#endif + +#ifndef INLINE +#define INLINE __inline +#endif + + +#endif /* __TYPES_H__ */ + diff --git a/ports/cortex_m3/Makefile b/ports/cortex_m3/Makefile new file mode 100644 index 0000000..fcf84e7 --- /dev/null +++ b/ports/cortex_m3/Makefile @@ -0,0 +1,19 @@ +ATOMTHREADS_PORT = ..... /libraries/atomthreads/ports/cortex_m3 +ATOMTHREADS_KERNEL = ..... /libraries/atomthreads/kernel + +INCLUDES := $(INCLUDES) \ + -I$(ATOMTHREADS_KERNEL) \ + -I$(ATOMTHREADS_PORT) + +SRCS := $(SRCS) \ + $(ATOMTHREADS_KERNEL)/atomkernel.c \ + $(ATOMTHREADS_KERNEL)/atommutex.c \ + $(ATOMTHREADS_KERNEL)/atomqueue.c \ + $(ATOMTHREADS_KERNEL)/atomsem.c \ + $(ATOMTHREADS_KERNEL)/atomtimer.c \ + $(ATOMTHREADS_PORT)/atomport.c + +ASMS := $(ASMS) \ + $(ATOMTHREADS_PORT)/atomport_arm.asm + + diff --git a/ports/cortex_m3/README b/ports/cortex_m3/README new file mode 100644 index 0000000..6784187 --- /dev/null +++ b/ports/cortex_m3/README @@ -0,0 +1,31 @@ +--------------------------------------------------------------------------- + +Library: Atomthreads CortexM3 Port +Author: Natie van Rooyen +License: BSD Revised + +--------------------------------------------------------------------------- + +ARM CortexM3 PORT + +This folder contains a port of the Atomthreads real time kernel for the +ARM CortexM3 processor architecture. + +To Use: + +1. Install the "pendSV_Handler" and "tick_Handler" implemented in the file + "atomport_arm.asm" in your platforms interrupt vectors. + +2. Complete the function "archTickInit()" implemented in "atomport.c" to + initialize your platforms timer tick interrupt. If you use the build in + SysTick of the CortexM3 you also have to add code here to start it. + +3. If required, add code to acknowledge your timer hardware's interrupt in + the function "archTickHandler()" also implemented in "atomport.c". + +4. During your platform initialization call the function "archTickInit()" + exported from "atomport_private.h" to initialize the CortexM3 + "PendSV_Handler". + +5. After your platforms c-runtime initialization has completed, start + Atomthreads from your runtime's "main()" function. \ No newline at end of file diff --git a/ports/cortex_m3/atomport.c b/ports/cortex_m3/atomport.c new file mode 100644 index 0000000..1941305 --- /dev/null +++ b/ports/cortex_m3/atomport.c @@ -0,0 +1,194 @@ +/* + * Copyright (c) 2012, Natie van Rooyen. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. No personal names or organizations' names associated with the + * Atomthreads project may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include "atom.h" +#include "atomport.h" +#include "types.h" + + +/* * + * + * Functions defined in atomport_arm.asm + * + */ +extern void contextInit (void) ; +extern void contextSwitch (SYSCONTEXT* save_context, SYSCONTEXT* new_context) ; +extern void contextStart (SYSCONTEXT* context) ; +extern uint32_t contextCreate (SYSCONTEXT* context, uint32_t stack_top, uint32_t entry) ; +extern uint32_t contextEnterCritical (void) ; +extern void contextExitCritical (uint32_t posture) ; +extern void contextEnableInterrupts (void) ; + +/** + * \b thread_shell + * + * Documented in atomThreads. + * + */ +void +thread_shell (void) +{ + ATOM_TCB *curr_tcb; + + /* Get the TCB of the thread being started */ + curr_tcb = atomCurrentContext(); + + /** + * Enable interrupts - these will not be enabled when a thread + * is first restored. + */ + // sei(); + contextEnableInterrupts () ; + + /* Call the thread entry point */ + if (curr_tcb && curr_tcb->entry_point) + { + curr_tcb->entry_point(curr_tcb->entry_param); + } + + /* Not reached - threads should never return from the entry point */ +} + + +/** + * \b archThreadContextInit + * + * Documented in atomThreads. + * + */ +void +archThreadContextInit (ATOM_TCB *tcb_ptr, void *stack_top, void (*entry_point)(uint32_t), uint32_t entry_param) +{ + uint32_t * stack_ptr ; + + tcb_ptr->sp_save_ptr = stack_top; + tcb_ptr->entry_param = entry_param ; + tcb_ptr->entry_point = entry_point ; + + stack_ptr = (uint32_t *)stack_top; //-- Load stack pointer + + *stack_ptr = 0x01000000L; //-- xPSR + stack_ptr--; + *stack_ptr = ((uint32_t)entry_point) | 1; //-- Entry Point (1 for THUMB mode) + stack_ptr--; + *stack_ptr = ((uint32_t)/*exit*/0) | 1; //-- R14 (LR) (1 for THUMB mode) + stack_ptr--; + *stack_ptr = 0x00121212L; //-- R12 + stack_ptr--; + *stack_ptr = 0x00030303L; //-- R3 + stack_ptr--; + *stack_ptr = 0x00020202L; //-- R2 + stack_ptr--; + *stack_ptr = 0x00010101L; //-- R1 + stack_ptr--; + *stack_ptr = entry_param ; //-- R0 - task's function argument + stack_ptr--; + *stack_ptr = 0x00111111L; //-- R11 + stack_ptr--; + *stack_ptr = 0x00101010L; //-- R10 + stack_ptr--; + *stack_ptr = 0x00090909L; //-- R9 + stack_ptr--; + *stack_ptr = 0x00080808L; //-- R8 + stack_ptr--; + *stack_ptr = 0x00070707L; //-- R7 + stack_ptr--; + *stack_ptr = 0x00060606L; //-- R6 + stack_ptr--; + *stack_ptr = 0x00050505L; //-- R5 + stack_ptr--; + *stack_ptr = 0x00040404L; //-- R4 + + tcb_ptr->sp_save_ptr = stack_ptr ; +} + + +/** + * \b archFirstThreadRestore + * + * Documented in atomThreads. + * + */ +void +archFirstThreadRestore(ATOM_TCB * p_sp_new) +{ + contextStart (&p_sp_new->sp_save_ptr) ; +} + + +/** + * \b archContextSwitch + * + * Documented in atomThreads. + * + */ +void +archContextSwitch (ATOM_TCB * p_sp_old, ATOM_TCB * p_sp_new) +{ + contextSwitch (&p_sp_old->sp_save_ptr, &p_sp_new->sp_save_ptr) ; +} + + +/** + * \b archTimerTickIrqHandler + * + * System timer tick interrupt handler. + * + */ +void +archTickHandler (void) +{ + atomIntEnter(); + + /* Call the OS system tick handler */ + atomTimerTick(); + + /* ack the interrupt if needed */ + /* ... */ + + /* Call the interrupt exit routine */ + atomIntExit(TRUE); +} + +/** + * \b archTickInit + * + * System timer initialization. + * + */ +void +archTickInit (void) +{ + /* Initialize NVIC PendSV */ + contextInit () ; + + /* Initializa Timer Hardware */ + /* ... */ +} + + diff --git a/ports/cortex_m3/atomport.h b/ports/cortex_m3/atomport.h new file mode 100644 index 0000000..2a6cf50 --- /dev/null +++ b/ports/cortex_m3/atomport.h @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2012, Natie van Rooyen. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. No personal names or organizations' names associated with the + * Atomthreads project may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __ATOM_PORT_H__ +#define __ATOM_PORT_H__ + +#include "arch/context.h" +#include "types.h" + +#define SYSTEM_TICKS_PER_SEC 1000 + + +/** + * Architecture-specific types. + * Most of these are available from types.h on this platform, which is + * included above. + */ +#define POINTER void * + + +/* Critical region protection */ + +#define CRITICAL_STORE uint32_t __atom_critical +#define CRITICAL_START() __atom_critical = contextEnterCritical() +#define CRITICAL_END() contextExitCritical(__atom_critical) + + +#endif /* __ATOM_PORT_H__ */ diff --git a/ports/cortex_m3/atomport_arm.asm b/ports/cortex_m3/atomport_arm.asm new file mode 100644 index 0000000..2195db6 --- /dev/null +++ b/ports/cortex_m3/atomport_arm.asm @@ -0,0 +1,217 @@ +; +; Copyright (c) 2012, Natie van Rooyen. All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions +; are met: +; +; 1. Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the distribution. +; 3. No personal names or organizations' names associated with the +; Atomthreads project may be used to endorse or promote products +; derived from this software without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS +; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +; TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +; PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE +; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +; POSSIBILITY OF SUCH DAMAGE. +; + + + PRESERVE8 {TRUE} + AREA UTILS, CODE, READONLY +;-- + EXPORT contextInit + EXPORT contextSwitch + EXPORT contextStart + EXPORT contextEnableInterrupts + EXPORT contextEnterCritical + EXPORT contextExitCritical + EXPORT pendSV_Handler + EXPORT tick_Handler + + EXTERN archTickHandler + +;-- +NVIC_INT_CTRL EQU 0xE000ED04 ; Interrupt control state register +NVIC_PENDSVSET EQU 0x10000000 ; Value to trigger PendSV exception +NVIC_PR_12_15_ADDR EQU 0xE000ED20 ; System Handlers 12-15 Priority Register Address +NVIC_PENDS_VPRIORITY EQU 0x00FF0000 ; PendSV priority is minimal (0xFF) + +;-- +; \b contextInit +; +; Architecture-specific one time initialization. +; +; Configures PendSV priority to lowest. +; +; @return None +; +contextInit + LDR r1, =NVIC_PR_12_15_ADDR ;-- Load the System 12-15 Priority Register + LDR r0, [r1] + ORR r0, r0, #NVIC_PENDS_VPRIORITY ;-- set PRI_14 (PendSV) to 0xFF - minimal + STR r0, [r1] + + BX lr + +;-- +; \b contextSwitch +; +; Architecture-specific context switch routine. +; +; Note that interrupts are always locked out when this routine is +; called. For cooperative switches, the scheduler will have entered +; a critical region. For preemptions (called from an ISR), the +; interrupts will have disabled in the tick_Handler. +; +; @param[in] [r0] -> Address to save old stack pointer +; @param[in] [r1] -> Address where new stack pointer is stored +; +; @return None +; +contextSwitch + LDR r2, =context_new_stack_ptr + STR r1, [r2] + + LDR r2, =context_save_stack_ptr + LDR r1, [r2] + TEQ r1, #0 ; if contextSwitch is going to be called again before pend_sv + STREQ r0, [r2] + + LDR R0, =NVIC_INT_CTRL ; Trigger the PendSV exception (causes context switch) + LDR R1, =NVIC_PENDSVSET + STR R1, [R0] + + BX lr + +;-- +; \b contextStart +; +; Architecture-specific context start routine. +; +; @param[in] [r0] -> Address where stack pointer is stored +; +; @return Does not return +; +contextStart + LDR r1, =context_new_stack_ptr + STR r0, [r1] + LDR r1, =context_save_stack_ptr + MOV r0, #0 + STR r0, [r1] + LDR r0, =NVIC_INT_CTRL ; Trigger the PendSV exception (causes context switch) + LDR r1, =NVIC_PENDSVSET + STR r1, [r0] + + BX lr + +;-- +; \b contextEnableInterrupts +; +; Enables interrupts on the processor +; +; @return None +; +contextEnableInterrupts + CPSIE i + BX lr + + +;-- +; \b contextExitCritical +; +; Exit critical section (restores interrupt posture) +; +; @param[in] r0 Interrupt Posture +; +; @return None +; +contextExitCritical + MSR PRIMASK, r0 + BX lr + + +;-- +; \b contextEnterCritical +; +; Enter critical section (disables interrupts) +; +; @return Current interrupt posture +; +contextEnterCritical + MRS r0, PRIMASK + CPSID i + BX lr + +;-- +; \b PendSV_Handler +; +; CortexM3 PendSV_Handler. Switch context to a new stack. +; +; @return None +; +pendSV_Handler + CPSID i ; Disable core int + + LDR r1, =context_save_stack_ptr + LDR r0, [r1] ; Load old (current) stack pointer address + + LDR r2, =context_new_stack_ptr + LDR r2, [r2] ; Load new stack pointer address + TEQ r0, r2 + BEQ pendsv_handler_exit + + TEQ r0, #0 + BEQ pendsv_handler_new_stack + ; Save context + MRS r3, PSP ; Get PSP point + STMDB r3!, {R4-R11} ; Store r4-r11 + STR r3, [r0] ; Save old stack pointer + MOV r3, #0 + STR r3, [r1] + +pendsv_handler_new_stack + ; Restore context + LDR r2, [r2] ; Load new stack pointer + LDMIA r2!, {r4-r11} ; Restore context + MSR PSP, r2 ; Mov new stack point to PSP + +pendsv_handler_exit + CPSIE i ; Enable core int + + ORR lr, lr, #0x04 ; Ensure exception return uses process stack + BX lr ; Exit interrupt + + +;-- +; \b Tick_Handler +; +; System timer tick interrupt handler. +; +; @return None +; +tick_Handler + PUSH {r4-r11, lr} + cpsid I ; Disable core int + BL archTickHandler + cpsie I ; Enable core int + POP {r4-r11, pc} + + +;-- +context_new_stack_ptr DCD 0x00000000 +context_save_stack_ptr DCD 0x00000000 + +;-- + END diff --git a/ports/cortex_m3/atomport_private.h b/ports/cortex_m3/atomport_private.h new file mode 100644 index 0000000..0f4a004 --- /dev/null +++ b/ports/cortex_m3/atomport_private.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2012, Natie van Rooyen. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. No personal names or organizations' names associated with the + * Atomthreads project may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __ATOM_PORT_PRIVATE_H__ +#define __ATOM_PORT_PRIVATE_H__ + + +/* Function prototypes */ +extern void archTickHandler (void) ; +extern void archTickInit (void) ; + +#endif /* __ATOM_PORT_PRIVATE_H__ */ diff --git a/ports/cortex_m3/types.h b/ports/cortex_m3/types.h new file mode 100644 index 0000000..82317f7 --- /dev/null +++ b/ports/cortex_m3/types.h @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2012, Natie van Rooyen. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. No personal names or organizations' names associated with the + * Atomthreads project may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __TYPES_H__ +#define __TYPES_H__ + +typedef unsigned int uintptr_t ; +typedef int intptr_t ; +typedef unsigned long long uint64_t ; +typedef unsigned int uint32_t ; +typedef unsigned short uint16_t ; +typedef unsigned char uint8_t ; +typedef int int32_t ; +typedef short int16_t ; +typedef char int8_t ; + +#endif /* __TYPES_H__ */ + From 5cc1e9831da2dcafb4d03df56cff54020f0035b6 Mon Sep 17 00:00:00 2001 From: unknown Date: Tue, 15 May 2012 00:03:43 +0200 Subject: [PATCH 09/28] atomvm fix --- ports/atomvm/atomport.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ports/atomvm/atomport.c b/ports/atomvm/atomport.c index 7660040..a4de433 100644 --- a/ports/atomvm/atomport.c +++ b/ports/atomvm/atomport.c @@ -29,7 +29,7 @@ #include "atom.h" #include "atomport.h" #include "atomvm.h" - +#include "windows.h" /** Forward declarations */ static void thread_shell (void); From 37d6d553bfe114b758e59b34b8349ec696bc5238 Mon Sep 17 00:00:00 2001 From: Natie van Rooyen Date: Tue, 15 May 2012 01:23:48 +0300 Subject: [PATCH 10/28] Update ports/atomvm/README.txt --- ports/atomvm/README.txt | 4 ---- 1 file changed, 4 deletions(-) diff --git a/ports/atomvm/README.txt b/ports/atomvm/README.txt index 77b327e..7a07533 100644 --- a/ports/atomvm/README.txt +++ b/ports/atomvm/README.txt @@ -33,8 +33,4 @@ testing the Real Time Operating System. However, this test can also run the unit tests of atomthreads by using the preprocessor directive "UNIT_TESTS" and linking in the desired unit test into the project. ---------------------------------------------------------------------------- -FINALLY - -Good luck, but most of all, have fun!! From 113f0a8690362b7ef56ad3d0293e27239796be5e Mon Sep 17 00:00:00 2001 From: Natie van Rooyen Date: Thu, 17 May 2012 23:42:58 +0200 Subject: [PATCH 11/28] Please enter the commit message for your changes. Lines starting --- ports/armv7/atomport.c | 18 +++++++++- ports/armv7/atomport_arm.asm | 64 ++++++++++++++++------------------ ports/armv7/atomport_private.h | 2 ++ ports/cortex_m3/atomport.c | 2 +- 4 files changed, 51 insertions(+), 35 deletions(-) diff --git a/ports/armv7/atomport.c b/ports/armv7/atomport.c index bac9c17..8fa0b2a 100644 --- a/ports/armv7/atomport.c +++ b/ports/armv7/atomport.c @@ -83,6 +83,7 @@ thread_shell (void) void archThreadContextInit (ATOM_TCB *tcb_ptr, void *stack_top, void (*entry_point)(uint32_t), uint32_t entry_param) { + static uint32_t context_thread_id = 0 ; uint32_t * stack_ptr ; tcb_ptr->sp_save_ptr = stack_top; @@ -91,7 +92,7 @@ archThreadContextInit (ATOM_TCB *tcb_ptr, void *stack_top, void (*entry_point)(u stack_ptr = (uint32_t *)stack_top; //-- Load stack pointer - *stack_ptr = ( uint32_t ) entry ; + *stack_ptr = ( uint32_t ) thread_shell ; stack_ptr--; *stack_ptr = ( uint32_t ) 0x00001111; /* R11 */ @@ -166,5 +167,20 @@ archTickHandler (void) atomIntExit(TRUE); } +/** + * \b archTickInit + * + * System timer initialization. + * + */ +void +archTickInit (void) +{ + /* Initialize NVIC PendSV */ + contextInit () ; + + /* Initializa Timer Hardware */ + /* ... */ +} diff --git a/ports/armv7/atomport_arm.asm b/ports/armv7/atomport_arm.asm index 9ba9664..db21f89 100644 --- a/ports/armv7/atomport_arm.asm +++ b/ports/armv7/atomport_arm.asm @@ -37,10 +37,9 @@ EXPORT contextEnableInterrupts EXPORT contextEnterCritical EXPORT contextExitCritical - EXPORT __irq_context_handler + EXPORT archIRQHandler - - EXTERN archTickHandler + EXTERN __context_preempt_handler [WEAK] ;-- ARM_SVC_MODE EQU 0xd3 @@ -49,9 +48,7 @@ ARM_FIQ_MODE EQU 0xD1 ARM_MODE_MASK EQU 0x1F ARM_FIQ_MODE_BITS EQU 0x11 ARM_IRQ_MODE_BITS EQU 0x12 -ARM_SVC_MODE_BITS EQU 0x13 -CONTEXT_SWITCH_MODE EQU ARM_SVC_MODE ARM @@ -85,19 +82,19 @@ contextSwitch STMFD sp!, {r4 - r11, lr} ;- Save registers ;- IF :DEF:CONTEXT_THREAD_ID - MRC p15,0,r3,c13,c0,2 + MRC p15, 0, r3, c13, c0, 2 STMFD sp!, {r3} ;- ENDIF STR sp, [r0] ;- Save old stack pointer - LDR r1, [r1] - MOV sp, r1 ;- Load new stack pointer + LDR r1, [r1] ;- Load new stack pointer + MOV sp, r1 ISB ;- IF :DEF:CONTEXT_THREAD_ID LDMFD sp!, {r3} - MCR p15,0,r3,c13,c0,2 + MCR p15, 0, r3, c13, c0, 2 ;- ENDIF LDMFD sp!, {r4 - r11, pc} ;- Load new registers @@ -113,11 +110,11 @@ contextSwitch ; contextStart LDR r0, [r0] - MOV sp, r0 ;- Load new stack pointer + MOV sp, r0 ;- Load new stack pointer ;- IF :DEF:CONTEXT_THREAD_ID LDMFD sp!, {r3} - MCR p15,0,r3,c13,c0,2 + MCR p15, 0, r3, c13, c0, 2 ;- ENDIF LDMFD sp!, {r4 - r11, pc} ;- Load new registers @@ -130,7 +127,7 @@ contextStart ; @return ID ; contextId - MRC p15,0,r0,c13,c0,2 + MRC p15, 0, r0, c13, c0, 2 BX lr ;-- @@ -141,12 +138,11 @@ contextId ; @return None ; contextEnableInterrupts - MRS r0,CPSR + MRS r0, CPSR MOV r1, #0x80 - BIC r0,r0,r1 - MSR CPSR_c,r0 - BX lr - + BIC r0, r0, r1 + MSR CPSR_c, r0 + BX lr ;-- ; \b contextExitCritical @@ -158,9 +154,8 @@ contextEnableInterrupts ; @return None ; contextExitCritical - MSR CPSR_cxsf,r0 - BX lr - + MSR CPSR_cxsf, r0 + BX lr ;-- ; \b contextEnterCritical @@ -170,42 +165,45 @@ contextExitCritical ; @return Current interrupt posture ; contextEnterCritical - MRS r0,CPSR - ORR r1,r0,#0x80 - MSR CPSR_cxsf,r1 + MRS r0, CPSR + ORR r1, r0, #0x80 + MSR CPSR_cxsf, r1 BX lr ;-- -; \b __irq_context_handler +; \b archIRQHandler ; -; IRQ entry point +; IRQ entry point. +; +; Save the process/thread context onto its own stackm before calling __context_preempt_handler (). +; __context_preempt_handler() might switch stacks. On return the same context is poped from the +; stack and control is returned to the process. ; ; @return None ; -__irq_context_handler +archIRQHandler - MSR cpsr_c, #CONTEXT_SWITCH_MODE ;- Save current process context + MSR cpsr_c, #ARM_SVC_MODE ;- Save current process context in process stack STMFD sp!, {r0 - r3, ip, lr} MSR cpsr_c, #ARM_IRQ_MODE ;- Save lr_irq and spsr_irq in process stack - SUB lr,lr,#4 + SUB lr, lr, #4 MOV r1, lr MRS r2, spsr - MSR cpsr_c, #CONTEXT_SWITCH_MODE + MSR cpsr_c, #ARM_SVC_MODE STMFD sp!, {r1, r2} - BL __context_preempt_handler ;- Dispatch the interrupt to archTickHandler for the timer tick interrupt or a simular function for other interrupts which might call atomthread functions. + BL __context_preempt_handler ;- Dispatch the interrupt to archTickHandler for the timer tick interrupt or a simular function for other interrupts which might call atomthread functions. LDMFD sp!, {r1, r2} ;- Restore lr_irq and spsr_irq from process stack MSR cpsr_c, #ARM_IRQ_MODE STMFD sp!, {r1} MSR spsr_cxsf, r2 - MSR cpsr_c, #CONTEXT_SWITCH_MODE ;- Restore process regs + MSR cpsr_c, #ARM_SVC_MODE ;- Restore process regs LDMFD sp!, {r0 - r3, ip, lr} - MSR cpsr_c, #ARM_IRQ_MODE ;- Exit from ISR - + MSR cpsr_c, #ARM_IRQ_MODE ;- Exit from IRQ LDMFD sp!, {pc}^ diff --git a/ports/armv7/atomport_private.h b/ports/armv7/atomport_private.h index c0dfc6d..87a032f 100644 --- a/ports/armv7/atomport_private.h +++ b/ports/armv7/atomport_private.h @@ -33,5 +33,7 @@ /* Function prototypes */ extern void archTickHandler (void) ; +extern void archTickInit (void) ; +extern void archIRQHandler (void) ; #endif /* __ATOM_PORT_PRIVATE_H__ */ diff --git a/ports/cortex_m3/atomport.c b/ports/cortex_m3/atomport.c index 1941305..1f659c3 100644 --- a/ports/cortex_m3/atomport.c +++ b/ports/cortex_m3/atomport.c @@ -94,7 +94,7 @@ archThreadContextInit (ATOM_TCB *tcb_ptr, void *stack_top, void (*entry_point)(u *stack_ptr = 0x01000000L; //-- xPSR stack_ptr--; - *stack_ptr = ((uint32_t)entry_point) | 1; //-- Entry Point (1 for THUMB mode) + *stack_ptr = ((uint32_t)thread_shell) | 1; //-- Entry Point (1 for THUMB mode) stack_ptr--; *stack_ptr = ((uint32_t)/*exit*/0) | 1; //-- R14 (LR) (1 for THUMB mode) stack_ptr--; From 12dbe5ebe94be60d1672ffd5299ee488f484b146 Mon Sep 17 00:00:00 2001 From: Natie van Rooyen Date: Thu, 17 May 2012 23:52:29 +0200 Subject: [PATCH 12/28] tabs to spaces --- ports/armv7/atomport_arm.asm | 106 +++++++++++++++++------------------ 1 file changed, 53 insertions(+), 53 deletions(-) diff --git a/ports/armv7/atomport_arm.asm b/ports/armv7/atomport_arm.asm index db21f89..496e779 100644 --- a/ports/armv7/atomport_arm.asm +++ b/ports/armv7/atomport_arm.asm @@ -61,7 +61,7 @@ ARM_IRQ_MODE_BITS EQU 0x12 ; contextInit - BX lr + BX lr ;-- ; \b contextSwitch @@ -79,25 +79,25 @@ contextInit ; @return None ; contextSwitch - STMFD sp!, {r4 - r11, lr} ;- Save registers + STMFD sp!, {r4 - r11, lr} ;- Save registers - ;- IF :DEF:CONTEXT_THREAD_ID - MRC p15, 0, r3, c13, c0, 2 - STMFD sp!, {r3} - ;- ENDIF + ;- IF :DEF:CONTEXT_THREAD_ID + MRC p15, 0, r3, c13, c0, 2 + STMFD sp!, {r3} + ;- ENDIF - STR sp, [r0] ;- Save old stack pointer - LDR r1, [r1] ;- Load new stack pointer - MOV sp, r1 + STR sp, [r0] ;- Save old stack pointer + LDR r1, [r1] ;- Load new stack pointer + MOV sp, r1 - ISB + ISB - ;- IF :DEF:CONTEXT_THREAD_ID - LDMFD sp!, {r3} - MCR p15, 0, r3, c13, c0, 2 - ;- ENDIF + ;- IF :DEF:CONTEXT_THREAD_ID + LDMFD sp!, {r3} + MCR p15, 0, r3, c13, c0, 2 + ;- ENDIF - LDMFD sp!, {r4 - r11, pc} ;- Load new registers + LDMFD sp!, {r4 - r11, pc} ;- Load new registers ;-- ; \b contextStart @@ -109,15 +109,15 @@ contextSwitch ; @return Does not return ; contextStart - LDR r0, [r0] - MOV sp, r0 ;- Load new stack pointer + LDR r0, [r0] + MOV sp, r0 ;- Load new stack pointer - ;- IF :DEF:CONTEXT_THREAD_ID - LDMFD sp!, {r3} - MCR p15, 0, r3, c13, c0, 2 - ;- ENDIF + ;- IF :DEF:CONTEXT_THREAD_ID + LDMFD sp!, {r3} + MCR p15, 0, r3, c13, c0, 2 + ;- ENDIF - LDMFD sp!, {r4 - r11, pc} ;- Load new registers + LDMFD sp!, {r4 - r11, pc} ;- Load new registers ;-- ; \b contextId @@ -127,8 +127,8 @@ contextStart ; @return ID ; contextId - MRC p15, 0, r0, c13, c0, 2 - BX lr + MRC p15, 0, r0, c13, c0, 2 + BX lr ;-- ; \b contextEnableInterrupts @@ -138,11 +138,11 @@ contextId ; @return None ; contextEnableInterrupts - MRS r0, CPSR - MOV r1, #0x80 - BIC r0, r0, r1 - MSR CPSR_c, r0 - BX lr + MRS r0, CPSR + MOV r1, #0x80 + BIC r0, r0, r1 + MSR CPSR_c, r0 + BX lr ;-- ; \b contextExitCritical @@ -154,8 +154,8 @@ contextEnableInterrupts ; @return None ; contextExitCritical - MSR CPSR_cxsf, r0 - BX lr + MSR CPSR_cxsf, r0 + BX lr ;-- ; \b contextEnterCritical @@ -165,10 +165,10 @@ contextExitCritical ; @return Current interrupt posture ; contextEnterCritical - MRS r0, CPSR - ORR r1, r0, #0x80 - MSR CPSR_cxsf, r1 - BX lr + MRS r0, CPSR + ORR r1, r0, #0x80 + MSR CPSR_cxsf, r1 + BX lr ;-- ; \b archIRQHandler @@ -183,28 +183,28 @@ contextEnterCritical ; archIRQHandler - MSR cpsr_c, #ARM_SVC_MODE ;- Save current process context in process stack - STMFD sp!, {r0 - r3, ip, lr} + MSR cpsr_c, #ARM_SVC_MODE ;- Save current process context in process stack + STMFD sp!, {r0 - r3, ip, lr} - MSR cpsr_c, #ARM_IRQ_MODE ;- Save lr_irq and spsr_irq in process stack - SUB lr, lr, #4 - MOV r1, lr - MRS r2, spsr - MSR cpsr_c, #ARM_SVC_MODE - STMFD sp!, {r1, r2} - - BL __context_preempt_handler ;- Dispatch the interrupt to archTickHandler for the timer tick interrupt or a simular function for other interrupts which might call atomthread functions. + MSR cpsr_c, #ARM_IRQ_MODE ;- Save lr_irq and spsr_irq in process stack + SUB lr, lr, #4 + MOV r1, lr + MRS r2, spsr + MSR cpsr_c, #ARM_SVC_MODE + STMFD sp!, {r1, r2} + + BL __context_preempt_handler ;- Dispatch the interrupt to archTickHandler for the timer tick interrupt or a simular function for other interrupts which might call atomthread functions. - LDMFD sp!, {r1, r2} ;- Restore lr_irq and spsr_irq from process stack - MSR cpsr_c, #ARM_IRQ_MODE - STMFD sp!, {r1} - MSR spsr_cxsf, r2 + LDMFD sp!, {r1, r2} ;- Restore lr_irq and spsr_irq from process stack + MSR cpsr_c, #ARM_IRQ_MODE + STMFD sp!, {r1} + MSR spsr_cxsf, r2 - MSR cpsr_c, #ARM_SVC_MODE ;- Restore process regs - LDMFD sp!, {r0 - r3, ip, lr} + MSR cpsr_c, #ARM_SVC_MODE ;- Restore process regs + LDMFD sp!, {r0 - r3, ip, lr} - MSR cpsr_c, #ARM_IRQ_MODE ;- Exit from IRQ - LDMFD sp!, {pc}^ + MSR cpsr_c, #ARM_IRQ_MODE ;- Exit from IRQ + LDMFD sp!, {pc}^ ;-- From a2646ec6953feb7905e1996284909e0702140be2 Mon Sep 17 00:00:00 2001 From: Natie van Rooyen Date: Tue, 22 May 2012 00:22:09 +0200 Subject: [PATCH 13/28] updates --- ports/armv7/Makefile | 4 ++-- ports/armv7/README | 8 ++++---- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/ports/armv7/Makefile b/ports/armv7/Makefile index 87b9c17..3a15998 100644 --- a/ports/armv7/Makefile +++ b/ports/armv7/Makefile @@ -1,5 +1,5 @@ -ATOMTHREADS_PORT = $(COLOSSAL)/libraries/atomthreads/ports/armv7 -ATOMTHREADS_KERNEL = $(COLOSSAL)/libraries/atomthreads/kernel +ATOMTHREADS_PORT = .../libraries/atomthreads/ports/armv7 +ATOMTHREADS_KERNEL = .../libraries/atomthreads/kernel INCLUDES := $(INCLUDES) \ -I$(ATOMTHREADS_KERNEL) \ diff --git a/ports/armv7/README b/ports/armv7/README index f3bc0fa..fae939d 100644 --- a/ports/armv7/README +++ b/ports/armv7/README @@ -20,12 +20,12 @@ To Use: function called "__context_preempt_handler()" to dispatch the interrupt. 2. Implement the function "__context_preempt_handler()" - from where your platforms interrupt cotroller will be serviced and the - interrupt will be dispatched to a specic interrupt service routine. In + from where your platforms interrupt controller will be serviced and the + interrupt will be dispatched to a specific interrupt service routine. In the case of your platforms timer tick interrupt call the "archTickHandler()" implemented in "atomport.c". -3. Initialize your platforms timer tick hardware to generata an OS timer tick +3. Initialize your platforms timer tick hardware to generate an OS timer tick interrupt. 4. Add code to acknowledge your timer hardware's interrupt in the @@ -35,4 +35,4 @@ To Use: 5. After your platforms c-runtime initialization has completed, start Atomthreads from your runtime's "main()" function. -6. Include the port's Maefile in your platform build flow. \ No newline at end of file +6. Include the port's Makefile in your platform build flow. \ No newline at end of file From dfb831fa6315aa4a78e9467e98397cb60643b21c Mon Sep 17 00:00:00 2001 From: Natie van Rooyen Date: Mon, 17 Sep 2012 13:02:09 +0200 Subject: [PATCH 14/28] =?UTF-8?q?Added=20=E2=80=9Carm=E2=80=9D=20port=20.?= =?UTF-8?q?=20Added=20platforms=20directory.=20Added=20QEMU=20qemu=5Finteg?= =?UTF-8?q?ratorcp=20platform=20in=20platforms.=20Modified=20test=20cases?= =?UTF-8?q?=20to=20make=20stack=20top=20DWORD=20aligned.?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- platforms/qemu_integratorcp/Makefile | 91 +++++++ .../qemu_integratorcp/atomthreads_test.out | 75 ++++++ platforms/qemu_integratorcp/boot.elf | Bin 0 -> 419255 bytes platforms/qemu_integratorcp/main.c | 85 +++++++ platforms/qemu_integratorcp/modules.c | 115 +++++++++ platforms/qemu_integratorcp/modules.h | 124 ++++++++++ platforms/qemu_integratorcp/startup.s | 55 +++++ platforms/qemu_integratorcp/system.ld | 94 ++++++++ platforms/rules.mk | 60 +++++ ports/{armv7 => arm}/Makefile | 10 +- ports/{armv7 => arm}/README | 0 ports/arm/atomport-tests.h | 50 ++++ ports/{armv7 => arm}/atomport.c | 11 +- ports/{armv7 => arm}/atomport.h | 13 +- ports/arm/atomport.o | Bin 0 -> 5436 bytes ports/arm/atomport_asm.o | Bin 0 -> 2220 bytes ports/{armv7 => arm}/atomport_private.h | 0 ports/arm/atomport_s.S | 227 ++++++++++++++++++ ports/{armv7 => arm}/types.h | 2 +- ports/armv7/atomport_arm.asm | 211 ---------------- tests/atomtests.h | 2 +- tests/kern1.c | 6 +- tests/kern3.c | 4 +- tests/kern4.c | 8 +- tests/mutex1.c | 4 +- tests/mutex2.c | 2 +- tests/mutex3.c | 8 +- tests/mutex4.c | 8 +- tests/mutex5.c | 2 +- tests/mutex6.c | 2 +- tests/mutex7.c | 2 +- tests/mutex8.c | 6 +- tests/mutex9.c | 2 +- tests/queue2.c | 4 +- tests/queue3.c | 4 +- tests/queue5.c | 8 +- tests/queue6.c | 2 +- tests/queue7.c | 6 +- tests/queue9.c | 8 +- tests/sem1.c | 4 +- tests/sem3.c | 8 +- tests/sem4.c | 8 +- tests/sem5.c | 2 +- tests/sem6.c | 2 +- tests/sem7.c | 2 +- tests/sem8.c | 6 +- tests/sem9.c | 6 +- tests/timer2.c | 6 +- 48 files changed, 1062 insertions(+), 293 deletions(-) create mode 100644 platforms/qemu_integratorcp/Makefile create mode 100644 platforms/qemu_integratorcp/atomthreads_test.out create mode 100644 platforms/qemu_integratorcp/boot.elf create mode 100644 platforms/qemu_integratorcp/main.c create mode 100644 platforms/qemu_integratorcp/modules.c create mode 100644 platforms/qemu_integratorcp/modules.h create mode 100644 platforms/qemu_integratorcp/startup.s create mode 100644 platforms/qemu_integratorcp/system.ld create mode 100644 platforms/rules.mk rename ports/{armv7 => arm}/Makefile (68%) rename ports/{armv7 => arm}/README (100%) create mode 100644 ports/arm/atomport-tests.h rename ports/{armv7 => arm}/atomport.c (94%) rename ports/{armv7 => arm}/atomport.h (90%) create mode 100644 ports/arm/atomport.o create mode 100644 ports/arm/atomport_asm.o rename ports/{armv7 => arm}/atomport_private.h (100%) create mode 100644 ports/arm/atomport_s.S rename ports/{armv7 => arm}/types.h (96%) delete mode 100644 ports/armv7/atomport_arm.asm diff --git a/platforms/qemu_integratorcp/Makefile b/platforms/qemu_integratorcp/Makefile new file mode 100644 index 0000000..551529f --- /dev/null +++ b/platforms/qemu_integratorcp/Makefile @@ -0,0 +1,91 @@ +ifeq ($(TARGET_NAME),) +TARGET_NAME=boot +endif +ifeq ($(ATOMTHREADS),) +ATOMTHREADS = $(shell pwd)/../../ +endif +ifeq ($(TEST_NAME),) +TEST_NAME = kern1 +endif + + + +CC = arm-none-eabi-gcc +LN = arm-none-eabi-gcc +AS = arm-none-eabi-gcc + +CFLAGS := $(CFLAGS) -Wall -g -c -mcpu=arm926ej-s -ffreestanding +AFLAGS := $(CFLAGS) -Wall -g -c -mcpu=arm926ej-s -ffreestanding +LFLAGS := $(LFLAGS) -Wall -mcpu=arm926ej-s -Wl,-Map=system.map,--verbose -Tsystem.ld + +CDEFS := $(CDEFS) -DATOMTHREADS_TEST='"$(TEST_NAME)"' +ADEFS := $(ADEFS) + +LLIBS := $(LLIBS) + + +SRCS := $(SRCS) \ + modules.c \ + main.c \ + $(ATOMTHREADS)/tests/$(TEST_NAME).c + +ASMS := $(ASMS) \ + startup.S \ + +INCLUDES := $(INCLUDES) \ + -I$(ATOMTHREADS) + +include $(ATOMTHREADS)/ports/arm/Makefile + +OBJS = $(SRCS:.c=.o) $(ASMS:.S=.o) + +include ../rules.mk + + +run_test: clean all + echo "START TEST $(TEST_NAME)" + qemu-system-arm -M integratorcp -kernel boot.elf -semihosting | tee atomthreads_test.out + +all_tests: + echo "Starting atomthreads test suite" > atomthreads_test.out + make run_test "TEST_NAME=mutex1" + make run_test "TEST_NAME=mutex2" + make run_test "TEST_NAME=mutex3" + make run_test "TEST_NAME=mutex4" + make run_test "TEST_NAME=mutex5" + make run_test "TEST_NAME=mutex6" + make run_test "TEST_NAME=mutex7" + make run_test "TEST_NAME=mutex8" + make run_test "TEST_NAME=mutex9" + make run_test "TEST_NAME=kern1" + make run_test "TEST_NAME=kern2" + make run_test "TEST_NAME=kern3" + make run_test "TEST_NAME=kern4" + make run_test "TEST_NAME=timer1" + make run_test "TEST_NAME=timer2" + make run_test "TEST_NAME=timer3" + make run_test "TEST_NAME=timer5" + make run_test "TEST_NAME=timer6" + make run_test "TEST_NAME=timer7" + make run_test "TEST_NAME=queue1" + make run_test "TEST_NAME=queue2" + make run_test "TEST_NAME=queue3" + make run_test "TEST_NAME=queue4" + make run_test "TEST_NAME=queue5" + make run_test "TEST_NAME=queue6" + make run_test "TEST_NAME=queue7" + make run_test "TEST_NAME=queue8" + make run_test "TEST_NAME=queue9" + make run_test "TEST_NAME=sem1" + make run_test "TEST_NAME=sem2" + make run_test "TEST_NAME=sem3" + make run_test "TEST_NAME=sem4" + make run_test "TEST_NAME=sem5" + make run_test "TEST_NAME=sem6" + make run_test "TEST_NAME=sem7" + make run_test "TEST_NAME=sem8" + make run_test "TEST_NAME=sem9" + +run_last: + qemu-system-arm -M integratorcp -kernel boot.elf -monitor stdio -semihosting + diff --git a/platforms/qemu_integratorcp/atomthreads_test.out b/platforms/qemu_integratorcp/atomthreads_test.out new file mode 100644 index 0000000..1c4897d --- /dev/null +++ b/platforms/qemu_integratorcp/atomthreads_test.out @@ -0,0 +1,75 @@ +Starting atomthreads test suite +VNC server running on `127.0.0.1:5900' +atomthreads starting mutex1... mutex1 PASS +VNC server running on `127.0.0.1:5900' +atomthreads starting mutex2... mutex2 PASS +VNC server running on `127.0.0.1:5900' +atomthreads starting mutex3... mutex3 PASS +VNC server running on `127.0.0.1:5900' +atomthreads starting mutex4... mutex4 PASS +VNC server running on `127.0.0.1:5900' +atomthreads starting mutex5... mutex5 PASS +VNC server running on `127.0.0.1:5900' +atomthreads starting mutex6... mutex6 PASS +VNC server running on `127.0.0.1:5900' +atomthreads starting mutex7... mutex7 PASS +VNC server running on `127.0.0.1:5900' +atomthreads starting mutex8... mutex8 PASS +VNC server running on `127.0.0.1:5900' +atomthreads starting mutex9... mutex9 PASS +VNC server running on `127.0.0.1:5900' +atomthreads starting kern1... kern1 PASS +VNC server running on `127.0.0.1:5900' +atomthreads starting kern2... kern2 PASS +VNC server running on `127.0.0.1:5900' +atomthreads starting kern3... kern3 PASS +VNC server running on `127.0.0.1:5900' +atomthreads starting kern4... kern4 PASS +VNC server running on `127.0.0.1:5900' +atomthreads starting timer1... timer1 PASS +VNC server running on `127.0.0.1:5900' +atomthreads starting timer2... timer2 FAIL +VNC server running on `127.0.0.1:5900' +atomthreads starting timer3... timer3 PASS +VNC server running on `127.0.0.1:5900' +atomthreads starting timer5... timer5 PASS +VNC server running on `127.0.0.1:5900' +atomthreads starting timer6... timer6 PASS +VNC server running on `127.0.0.1:5900' +atomthreads starting timer7... timer7 PASS +VNC server running on `127.0.0.1:5900' +atomthreads starting queue1... queue1 PASS +VNC server running on `127.0.0.1:5900' +atomthreads starting queue2... queue2 PASS +VNC server running on `127.0.0.1:5900' +atomthreads starting queue3... queue3 PASS +VNC server running on `127.0.0.1:5900' +atomthreads starting queue4... queue4 PASS +VNC server running on `127.0.0.1:5900' +atomthreads starting queue5... queue5 PASS +VNC server running on `127.0.0.1:5900' +atomthreads starting queue6... queue6 PASS +VNC server running on `127.0.0.1:5900' +atomthreads starting queue7... queue7 PASS +VNC server running on `127.0.0.1:5900' +atomthreads starting queue8... queue8 PASS +VNC server running on `127.0.0.1:5900' +atomthreads starting queue9... queue9 PASS +VNC server running on `127.0.0.1:5900' +atomthreads starting sem1... sem1 PASS +VNC server running on `127.0.0.1:5900' +atomthreads starting sem2... sem2 PASS +VNC server running on `127.0.0.1:5900' +atomthreads starting sem3... sem3 PASS +VNC server running on `127.0.0.1:5900' +atomthreads starting sem4... sem4 PASS +VNC server running on `127.0.0.1:5900' +atomthreads starting sem5... sem5 PASS +VNC server running on `127.0.0.1:5900' +atomthreads starting sem6... sem6 PASS +VNC server running on `127.0.0.1:5900' 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z^CitK@{S+T6n(}q_0~U!qw&J&YK$n#CFe==DJZqZc&K#Dfi?6Y&g{3g7l!$!!;V5v zU>$+Y+v!K*!SqxnJB?p0lF>0f{zvupJ?PnZhMxRulcP{b$q9FSuEshjJ1~i_Y8HK6 z)5k&QABGygMeh%1;hQ`Rt9hq`b?OcCQ&Z{Y{W(o1{VE$)Vew{cukkojX$VKN!lid? zcI3Rzu}V`Ic=SzY&17`6zmC+@D5H#T_D}AFZYw|eUo2}6{*f)*SbW7Q@3~lqs4?TC z`uHKdHazK^D6QEfzM5AVSf{{{FbdFbj=W&~KeI!{^iK$zWue#NQ1EC>g~_WHe^S*} zd&s99xR}>XD_{-Ye&(|j_)s2KJF4o53jZbt_^K +#include "modules.h" +#include "atom.h" +#include "tests/atomtests.h" + +#ifndef ATOMTHREADS_TEST +#define ATOMTHREADS_TEST "kern1" +#endif + +#define TEST_STACK_BYTE_SIZE 1024 +#define IDLE_STACK_BYTE_SIZE 512 + +static unsigned char test_stack[TEST_STACK_BYTE_SIZE] ; +static unsigned char idle_stack[IDLE_STACK_BYTE_SIZE] ; +ATOM_TCB test_tcb ; + + +/** + * \b test_thread + * + * Function calling the test function of the Atomthreads test suite. + * + */ +void +test_thread (uint32_t param) +{ + uint32_t failures ; + CRITICAL_STORE ; + + failures = test_start () ; + + atomTimerDelay (10) ; + CRITICAL_START() ; + printf ("%s %s\r\n", ATOMTHREADS_TEST, failures ? "FAIL" : "PASS") ; + exit (failures) ; + CRITICAL_END() ; +} + +/** + * \b main + * + * Initialize atomthreads and start a test_thread to run the Atomthreads test suite. + * + */ +int +main (void) +{ + uint32_t failures ; + + printf ("atomthreads starting %s... ", ATOMTHREADS_TEST) ; + + atomOSInit(&idle_stack[IDLE_STACK_BYTE_SIZE - sizeof(unsigned int)], IDLE_STACK_BYTE_SIZE - sizeof(unsigned int)) ; + atomThreadCreate ((ATOM_TCB *)&test_tcb, TEST_THREAD_PRIO, test_thread, 0, &test_stack[(TEST_STACK_BYTE_SIZE) - sizeof(unsigned int)], TEST_STACK_BYTE_SIZE - sizeof(unsigned int)); + atomOSStart() ; + + return 0 ; +} diff --git a/platforms/qemu_integratorcp/modules.c b/platforms/qemu_integratorcp/modules.c new file mode 100644 index 0000000..c611d68 --- /dev/null +++ b/platforms/qemu_integratorcp/modules.c @@ -0,0 +1,115 @@ +/* + * Copyright (c) 2012, Natie van Rooyen. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. No personal names or organizations' names associated with the + * Atomthreads project may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include "modules.h" +#include +#include +#include "atomport_private.h" +#include "atom.h" +#include "atomport.h" +#include "types.h" + +ICP_TIMER_T* const board_timer_0 = (ICP_TIMER_T*) BOARD_BASE_ADDRESS_TIMER_0 ; +ICP_PIC_T * const board_pic = (ICP_PIC_T*) BOARD_BASE_ADDRESS_PIC ; + +/** + * \b dbg_format_msg + * + * Same as printf. + * + */ +void +dbg_format_msg (char *format, ...) +{ + va_list args; + static char msg[256] ; + CRITICAL_STORE ; + + va_start (args, format) ; + CRITICAL_START() ; + vsnprintf ((char*)msg, 256, (char*)format, args) ; + CRITICAL_END() ; + + printf (msg) ; +} + +/** + * \b low_level_init + * + * Initializes the PIC and start the system timer tick intrerupt. + * + */ +int +low_level_init (void) +{ + + board_pic->IRQ_ENABLECLR = ICP_PIC_IRQ_TIMERINT0 ; + board_timer_0->INTCLR = 1 ; + board_pic->IRQ_ENABLESET |= ICP_PIC_IRQ_TIMERINT0 ; + + board_timer_0->LOAD = 0x2000 ; + board_timer_0->BGLOAD = 0x2000 ; + board_timer_0->CONTROL = ICP_TIMER_CONTROL_ENABLE | + ICP_TIMER_CONTROL_MODE | + ICP_TIMER_CONTROL_IE | + /*ICP_TIMER_CONTROL_PRESCALE_256 |*/ + ICP_TIMER_CONTROL_TIMER_SIZE ; + + return 0 ; +} + + +/** + * \b __context_preempt_handler + * + * System timer tic interupt handler. + * + */ +void +__context_preempt_handler (void) +{ + unsigned int status = board_pic->IRQ_STATUS ; + + if (status | ICP_PIC_IRQ_TIMERINT0) { + + atomIntEnter(); + + /* Call the OS system tick handler */ + atomTimerTick(); + + /* ack the interrupt */ + board_timer_0->INTCLR = 0x1 ; + + /* Call the interrupt exit routine */ + atomIntExit(TRUE); + + } + + +} + diff --git a/platforms/qemu_integratorcp/modules.h b/platforms/qemu_integratorcp/modules.h new file mode 100644 index 0000000..38aa37f --- /dev/null +++ b/platforms/qemu_integratorcp/modules.h @@ -0,0 +1,124 @@ +/* + * Copyright (c) 2012, Natie van Rooyen. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. No personal names or organizations' names associated with the + * Atomthreads project may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __MODULES_H__ +#define __MODULES_H__ + +#include "atomport.h" + +extern void dbg_format_msg (char *format, ...) ; + +#define DBG_MESSAGE(fmt_str) { dbg_format_msg fmt_str ; } + + +typedef volatile unsigned int REG_DWORD ;// Hardware register definition +typedef volatile unsigned short REG_WORD ; +typedef volatile unsigned char REG_BYTE ; + + +// ***************************************************************************** +// INTEGRATORCP TIMER +// ***************************************************************************** +typedef struct ICP_TIMER_S { + // offset read/write word size reset Description + REG_DWORD LOAD ; // 0x0000 Read/write 32 0x00000000 Load value for Timer + REG_DWORD VALUE ; // 0x0004 Read 32 0xFFFFFFFF The current value for Timer + REG_BYTE CONTROL ; // 0x0008 Read/write 8 0x20 Timer control register + REG_DWORD INTCLR ; // 0x000C Write - - Timer interrupt clear + REG_DWORD RIS ; // 0x0010 Read 1 0x0 Timer raw interrupt status + REG_DWORD MIS ; // 0x0014 Read 1 0x0 Timer masked interrupt status + REG_DWORD BGLOAD ; // 0x0018 Read/write 32 0x00000000 Background load value for Timer + +} ICP_TIMER_T, *PICP_TIMER_T ; + +// -------- ICP_TIMER_LOAD : (LOAD Offset: 0x00) Load value for Timer -------- +// -------- ICP_TIMER_VALUE : (LOAD Offset: 0x04) The current value for Timer -------- +// -------- ICP_TIMER_CONTROL : (CONTROL Offset: 0x04) Timer control register -------- +#define ICP_TIMER_CONTROL_MASK ((unsigned int)0x0F << 0) // Timer control mask + #define ICP_TIMER_CONTROL_ENABLE ((unsigned int)0x01 << 7) // Timer enable: 0 = disabled 1 = enabled. + #define ICP_TIMER_CONTROL_MODE ((unsigned int)0x01 << 6) // Timer mode: 0 = free running, counts once and then wraps to 0xFFFF 1 = periodic, reloads from load register at the end of each count.. + #define ICP_TIMER_CONTROL_IE ((unsigned int)0x01 << 5) // Interrupt enable. + #define ICP_TIMER_CONTROL_R ((unsigned int)0x01 << 4) // Unused, always write as 0s. + #define ICP_TIMER_CONTROL_PRESCALE_MASK ((unsigned int)0x03 << 2) // Prescale divisor + #define ICP_TIMER_CONTROL_PRESCALE_NONE ((unsigned int)0x00 << 2) // + #define ICP_TIMER_CONTROL_PRESCALE_16 ((unsigned int)0x01 << 2) // + #define ICP_TIMER_CONTROL_PRESCALE_256 ((unsigned int)0x02 << 2) // +#define ICP_TIMER_CONTROL_TIMER_SIZE ((unsigned int)0x01 << 1) // Selects 16/32 bit counter operation: 0 = 16-bit counter (default) 1 = 32-bit counter For 16-bit mode, write the high 16 bits of the 32-bit value as 0. +#define ICP_TIMER_CONTROL_ONE_SHOT ((unsigned int)0x01 << 0) // Selects one-shot or wrapping counter mode: 0 = wrapping mode (default) 1 = one-shot mode +// -------- ICP_TIMER_INTCLR : (INTCLR Offset: 0x0C) Timer interrupt clear -------- +// -------- ICP_TIMER_RIS : (RIS Offset: 0x10) Timer raw interrupt status -------- +// -------- ICP_TIMER_MIS : (MIS Offset: 0x14) Timer masked interrupt status -------- +#define ICP_TIMER_INT ((unsigned int)0x01 << 0) // Interrupt +// -------- ICP_TIMER_BGLOAD : (BGLOAD Offset: 0x18) Timer masked interrupt status -------- + + +// ***************************************************************************** +// INTEGRATORCP PIC +// ***************************************************************************** +typedef struct ICP_PIC_S { + // offset read/write word size reset Description + REG_DWORD IRQ_STATUS ; // 0x0000 Read 22 IRQ gated interrupt status + REG_DWORD IRQ_RAWSTAT ; // 0x0004 Read 22 IRQ raw interrupt status + REG_DWORD IRQ_ENABLESET ; // 0x0008 Read/write 22 IRQ enable set + REG_DWORD IRQ_ENABLECLR ; // 0x000C Write 22 IRQ enable clear + REG_DWORD INT_SOFTSET ; // 0x0010 Read/write 16 Software interrupt set + REG_DWORD INT_SOFTCLR ; // 0x0014 Write 16 Software interrupt clear + REG_DWORD RESERVED[2] ; // 0x0018 + REG_DWORD FIQ_STATUS ; // 0x0020 Read 22 FIQ gated interrupt status + REG_DWORD FIQ_RAWSTAT ; // 0x0024 Read 22 FIQ raw interrupt status + REG_DWORD FIQ_ENABLESET ; // 0x0028 Read/write 22 FIQ enable set + REG_DWORD FIQ_ENABLECLR ; // 0x002C Write-only 22 FIQ enable clear + +} ICP_PIC_T, *PICP_PIC_T ; + +// -------- ICP_PIC_IRQ_STATUS : (IRQ_STATUS Offset: 0x00) IRQ gated interrupt status -------- +// -------- ICP_PIC_IRQ_RAWSTAT : (IRQ_RAWSTAT Offset: 0x04) IRQ raw interrupt status -------- +// -------- ICP_PIC_IRQ_ENABLESET : (IRQ_ENABLESET Offset: 0x08) IRQ enable set -------- +// -------- ICP_PIC_IRQ_ENABLECLR : (IRQ_ENABLECLR Offset: 0x0C) IRQ enable clear -------- +#define ICP_PIC_IRQ_MASK ((unsigned int)0x3FFFFF << 0) // IRQ mask + #define ICP_PIC_IRQ_TIMERINT2 ((unsigned int)0x01 << 7) // TIMERINT2 Counter-timer 2 interrupt + #define ICP_PIC_IRQ_TIMERINT1 ((unsigned int)0x01 << 6) // TIMERINT1 Counter-timer 1 interrupt + #define ICP_PIC_IRQ_TIMERINT0 ((unsigned int)0x01 << 5) // TIMERINT0 Counter-timer 0 interrupt + #define ICP_PIC_IRQ_SOFTINT ((unsigned int)0x01 << 0) // OFTINT Software interrupt +// -------- ICP_PIC_INT_SOFTSET : (INT_SOFTSET Offset: 0x10) Software interrupt set -------- +// -------- ICP_PIC_INT_SOFTCLR : (INT_SOFTCLR Offset: 0x14) Software interrupt clear -------- + + + + +#define BOARD_BASE_ADDRESS_TIMER_0 0x13000000 +#define BOARD_BASE_ADDRESS_PIC 0x14000000 + +extern ICP_TIMER_T* const board_timer_0 ; +extern ICP_PIC_T* const board_pic ; + + + +extern int low_level_init (void) ; + +#endif /* __MODULES_H__ */ diff --git a/platforms/qemu_integratorcp/startup.s b/platforms/qemu_integratorcp/startup.s new file mode 100644 index 0000000..dc4a167 --- /dev/null +++ b/platforms/qemu_integratorcp/startup.s @@ -0,0 +1,55 @@ +.section .vectors, "x" + +.global __interrupt_vector_table +.global __irq_stack_top__ +.global __fiq_stack_top__ +.global __svc_stack_top__ + +.global bsp_ints_enable +.global bsp_ints_disable +.global bsp_ints_restore + + +.equ USR_MODE, 0x10 +.equ FIQ_MODE, 0x11 +.equ IRQ_MODE, 0x12 +.equ SVC_MODE, 0x13 +.equ ABT_MODE, 0x17 +.equ UND_MODE, 0x1B +.equ SYS_MODE, 0x1F + +.equ I_BIT, 0x80 /* when I bit is set, IRQ is disabled */ +.equ F_BIT, 0x40 /* when F bit is set, FIQ is disabled */ + +__interrupt_vector_table: + + B Reset_Handler /* Reset */ + B . /* Undefined */ + B . /* SWI */ + B . /* Prefetch Abort */ + B . /* Data Abort */ + B . /* reserved */ + B IRQ_Handler /* IRQ */ + B . /* FIQ */ + + + +Reset_Handler: + + + MSR CPSR_c,#(IRQ_MODE | I_BIT | F_BIT) + LDR sp,=__irq_stack_top__ /* set the IRQ stack pointer */ + MSR CPSR_c,#(FIQ_MODE | I_BIT | F_BIT) + LDR sp,=__fiq_stack_top__ /* set the FIQ stack pointer */ + MSR CPSR_c,#(SVC_MODE | I_BIT | F_BIT) + LDR sp,=__svc_stack_top__ /* set the SVC stack pointer */ + + BL low_level_init + BL _mainCRTStartup + + + B . + +IRQ_Handler: + B archIRQHandler + diff --git a/platforms/qemu_integratorcp/system.ld b/platforms/qemu_integratorcp/system.ld new file mode 100644 index 0000000..4d4fc2c --- /dev/null +++ b/platforms/qemu_integratorcp/system.ld @@ -0,0 +1,94 @@ + +ENTRY(__interrupt_vector_table) + + +MEMORY +{ + flash (rx) : ORIGIN = 0x00000000, LENGTH = 0x00020000 + sram (rwx) : ORIGIN = 0x00020000, LENGTH = 0x00020000 +} + + +EXTERN(__interrupt_vector_table); + + +C_STACK_SIZE = 512; +IRQ_STACK_SIZE = 256; +FIQ_STACK_SIZE = 256; +SVC_STACK_SIZE = 512; +ABT_STACK_SIZE = 256; +UND_STACK_SIZE = 256; + +SECTIONS +{ + + + .text : + { + *(.vectors) + /* Startup assembly */ + *(.startup) + *(.init) + + /* Rest of the code (C) */ + *(.text) + *(.rodata) + *(.rodata*) + + _end_text = .; + } >flash + + .data : + { + _start_data = .; + *(.data) + _end_data = .; + } >sram + + .bss : + { + _start_bss = .; + __bss_start__ = . ; + *(.bss) + *(.eh_*) + } >sram + + . = ALIGN(4); + _end_bss = .; + __bss_end__ = . ; + + . = ALIGN(256); + + + .stack : { + __stack_start__ = . ; + . += IRQ_STACK_SIZE; + . = ALIGN (4); + __irq_stack_top__ = . ; + . += FIQ_STACK_SIZE; + . = ALIGN (4); + __fiq_stack_top__ = . ; + . += SVC_STACK_SIZE; + . = ALIGN (4); + __svc_stack_top__ = . ; + . += ABT_STACK_SIZE; + . = ALIGN (4); + __abt_stack_top__ = . ; + . += UND_STACK_SIZE; + . = ALIGN (4); + __und_stack_top__ = . ; + . += C_STACK_SIZE; + . = ALIGN (4); + __c_stack_top__ = . ; + __stack_end__ = .; + } >sram + + + /*DISCARD : + { + *(.eh_*) + }*/ +} + +_end = .; +PROVIDE(end = .); \ No newline at end of file diff --git a/platforms/rules.mk b/platforms/rules.mk new file mode 100644 index 0000000..7f0f767 --- /dev/null +++ b/platforms/rules.mk @@ -0,0 +1,60 @@ +# +# The following part of the makefile is generic; it can be used to +# build any executable just by changing the definitions above and by +# deleting dependencies appended to the file from 'make depend' +# +.SUFFIXES: .asm .elf .hex .lst .o .S .s .c .cpp +.PHONY: depend clean + +dump: + @echo "Target: " + @echo $(TARGET_NAME) + @echo "Source files: " + @echo $(SRCS) + @echo $(ASMS) + @echo "Object files: " + @echo $(OBJS) + +all: target + +target: $(OBJS) + $(LN) $(LFLAGS) $(LIBFLAGS) $(OBJS) $(LLIBS) -o $(TARGET_NAME).elf + @echo $(TARGET_NAME).elf was compiled + +clean: + rm -f $(OBJS) + + +# this is a suffix replacement rule for building .o's from .c's +# it uses automatic variables $<: the name of the prerequisite of +# the rule(a .c file) and $@: the name of the target of the rule (a .o file) +# (see the gnu make manual section about automatic variables) + +.c.o: + $(CC) $(CDEFS) $(CFLAGS) $(INCLUDES) -c $< -o $@ + +.cpp.o: + $(CC) $(CDEFS) $(CFLAGS) $(INCLUDES) -c $< -o $@ + +.S.o: + $(AS) $(ADEFS) $(AFLAGS) $(INCLUDES) -c $< -o $@ + +.s.o: + $(AS) $(ADEFS) $(AFLAGS) $(INCLUDES) -c $< -o $@ + +DEPFILE=.depends +DEPTOKEN='\# MAKEDEPENDS' +DEPFLAGS=-Y -f $(DEPFILE) -s $(DEPTOKEN) -p $(OUTDIR)/ + + +depend: + rm -f $(DEPFILE) + make $(DEPFILE) + +$(DEPFILE): + @echo $(DEPTOKEN) > $(DEPFILE) + makedepend $(DEPFLAGS) -- $(CFLAGS) -- $(SRCS) >&/dev/null + +# put this file in the last line of your Makefile +sinclude $(DEPFILE) + \ No newline at end of file diff --git a/ports/armv7/Makefile b/ports/arm/Makefile similarity index 68% rename from ports/armv7/Makefile rename to ports/arm/Makefile index 3a15998..9c33741 100644 --- a/ports/armv7/Makefile +++ b/ports/arm/Makefile @@ -1,5 +1,5 @@ -ATOMTHREADS_PORT = .../libraries/atomthreads/ports/armv7 -ATOMTHREADS_KERNEL = .../libraries/atomthreads/kernel +ATOMTHREADS_PORT = $(ATOMTHREADS)/ports/arm +ATOMTHREADS_KERNEL = $(ATOMTHREADS)/kernel INCLUDES := $(INCLUDES) \ -I$(ATOMTHREADS_KERNEL) \ @@ -14,6 +14,6 @@ SRCS := $(SRCS) \ $(ATOMTHREADS_PORT)/atomport.c ASMS := $(ASMS) \ - $(ATOMTHREADS_PORT)/atomport_arm.asm - - + $(ATOMTHREADS_PORT)/atomport_s.S + + diff --git a/ports/armv7/README b/ports/arm/README similarity index 100% rename from ports/armv7/README rename to ports/arm/README diff --git a/ports/arm/atomport-tests.h b/ports/arm/atomport-tests.h new file mode 100644 index 0000000..cfb909a --- /dev/null +++ b/ports/arm/atomport-tests.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2012, Natie van Rooyen. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. No personal names or organizations' names associated with the + * Atomthreads project may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __ATOMPORT_TEST_H__ +#define __ATOMPORT_TEST_H__ + +/* Include Atomthreads kernel API */ +#include "atom.h" + +extern void dbg_format_msg (char *format, ...) ; + + +#define TEST_THREAD_STACK_SIZE 1024 +#define ATOMLOG dbg_format_msg +#define _STR(x) x + + + + +/* API for starting each test */ +extern uint32_t test_start (void); + + +#endif /* __ATOMPORT_TEST_H__ */ diff --git a/ports/armv7/atomport.c b/ports/arm/atomport.c similarity index 94% rename from ports/armv7/atomport.c rename to ports/arm/atomport.c index 8fa0b2a..da96930 100644 --- a/ports/armv7/atomport.c +++ b/ports/arm/atomport.c @@ -33,14 +33,14 @@ /* * * - * Functions defined in atomport_arm.asm + * Functions defined in atomport_s.asm * */ +typedef void * SYSCONTEXT ; + extern void contextInit (void) ; extern void contextSwitch (SYSCONTEXT* save_context, SYSCONTEXT* new_context) ; extern void contextStart (SYSCONTEXT* context) ; -extern uint32_t contextEnterCritical (void) ; -extern void contextExitCritical (uint32_t posture) ; extern void contextEnableInterrupts (void) ; /** @@ -83,7 +83,6 @@ thread_shell (void) void archThreadContextInit (ATOM_TCB *tcb_ptr, void *stack_top, void (*entry_point)(uint32_t), uint32_t entry_param) { - static uint32_t context_thread_id = 0 ; uint32_t * stack_ptr ; tcb_ptr->sp_save_ptr = stack_top; @@ -111,10 +110,10 @@ archThreadContextInit (ATOM_TCB *tcb_ptr, void *stack_top, void (*entry_point)(u stack_ptr--; *stack_ptr = ( uint32_t ) 0x00000404; /* R4 */ -// #ifdef CONTEXT_THREAD_ID +#ifdef CONTEXT_THREAD_ID stack_ptr--; *stack_ptr = context_thread_id++ ; /* thread_id */ -// #endif +#endif tcb_ptr->sp_save_ptr = stack_ptr ; } diff --git a/ports/armv7/atomport.h b/ports/arm/atomport.h similarity index 90% rename from ports/armv7/atomport.h rename to ports/arm/atomport.h index 2a6cf50..39bd0c0 100644 --- a/ports/armv7/atomport.h +++ b/ports/arm/atomport.h @@ -30,10 +30,9 @@ #ifndef __ATOM_PORT_H__ #define __ATOM_PORT_H__ -#include "arch/context.h" #include "types.h" -#define SYSTEM_TICKS_PER_SEC 1000 +#define SYSTEM_TICKS_PER_SEC 100 /** @@ -43,12 +42,18 @@ */ #define POINTER void * +/* * + * + * Functions defined in atomport_arm.asm + * + */ +extern uint32_t contextEnterCritical (void) ; +extern void contextExitCritical (uint32_t posture) ; + /* Critical region protection */ - #define CRITICAL_STORE uint32_t __atom_critical #define CRITICAL_START() __atom_critical = contextEnterCritical() #define CRITICAL_END() contextExitCritical(__atom_critical) - #endif /* __ATOM_PORT_H__ */ diff --git a/ports/arm/atomport.o b/ports/arm/atomport.o new file mode 100644 index 0000000000000000000000000000000000000000..31708720d585be2ba9192034494e6518dee87692 GIT binary patch literal 5436 zcmbtYTa1)f9Y1HjnVs30-Ra(-up*txQcz%afu$g~!fsjE!UBaYsl;}!A3Fnc^P6v2 z*e$v$l|GnSS~Lw!Oj_Fq?>xXmwOE?e#D^x5`qXND&<7heX+c3^jrjYW@0{70mByH! zaK7LFe*XV+o3ngn$DR=>r7%s37k7&uF>~o_7sO9*|Ks1ct&!;@ zaXKefv|gRgy#Nd-oXWkO>lk@{XYg7mczI;z^326E@VS+IH93{sl>8|7vs^E}8*}gC zJC!@1{CRFVwe7mFuAoolyOY!T?_Kj-)2ZqF_UoNpy-j?FuaVz&v$aXT?PjQ1e?90l z*JF_ z3lX>rCL~(s$z^R4L@*%8ho}&uwOd-zNQCB8hTH4D8^S_F;_`tuFW9m+j=HUdR&9fI zD<7=d15Io+F6KI6Q~bb(eAVXg%O|jN|G{4v14gOd9WQX)gAl_KyIWim7g@V^C-wX}+Fz<(0o7WpK;L4HKY-`WZ2uvXA2 z+=`F2GKa5ki3tA%-qtGG`Ih*@C35lm6&DKMpyg^h`IfXH@EK74)fBEJ+4@&}V*X`0 zIEA}VreDVq;df~{unS*CT|{oJ3p3x6Q1}YDL2rz<@E^&opHjMx@N#k+Jgz6am@zkb zQ5J+psN3vu3&V%WZJAMii%>432N@K3GNFL~Jw?AwyDaCE!8y-@!O4kJ9CWq=0)dh%V;i;}dGV^iya;nl~FT9Jn)w`|!u zFtKNMQ+s%e6?t^`Zm7R70jhuX;BG4%A6Vn_VIJV$hJG7O3i(8|tzB@HP2=_$iiU=w z9i36x8T1Xc2gL%dr0$B+`-h^j&Y*0IHF{ zi4HfyEp)hri2wBH4kC+e9F2Sw9d3jUr9KrRc6oFMkq4mBjdQ`v6K;e7r9KrRaw=dN z!eFYAA3=vHVV6>$3K91!de-z?a8TPv`~+|oT5rcEsyVw*5U)d!ax%Gbbqt2fCD%UT zj+XMSSPFA$M)FS8_0$LKs#|t!b+oC{<_9P9ZYHM=vI>>Y9NU#DWec_=p4UOfAyZMA zJ~xM#64%XZOxv_dqFPCm3t5p#Cyvxg8FdyCF3*OrORjS=Q7QAsri4@zZYC|ZkMA2x zjE|1(I3TKSDswF1mMfxKt5)n%HZhqxW+xzaYt_08vC0WJnsilaP4iMKRr3=iI~&X7 zQjW4~E;dth95r?|hr=AJn=>z+W6DVtg~}>1Jd_xDWbd%3IQg=ZcTa+_k1KZ`b47T? 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All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + 1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + 3. No personal names or organizations' names associated with the + Atomthreads project may be used to endorse or promote products + derived from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS + "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. +*/ + + + +/**/ + + + +.global archIRQHandler + +.global contextEnterCritical +.global contextExitCritical +.global contextEnableInterrupts +.global contextId +.global contextStart +.global contextSwitch +.global contextInit + + +.global __context_preempt_handler + +/**/ +.equ USR_MODE, 0x10 +.equ FIQ_MODE, 0x11 +.equ IRQ_MODE, 0x12 +.equ SVC_MODE, 0x13 +.equ ABT_MODE, 0x17 +.equ UND_MODE, 0x1B +.equ SYS_MODE, 0x1F + +.equ I_BIT, 0x80 /* when I bit is set, IRQ is disabled */ +.equ F_BIT, 0x40 /* when F bit is set, FIQ is disabled */ + + +.text +.code 32 + +/** + * \b contextInit + * + * Architecture-specific one time initialization. + * + * @return None + */ +contextInit: + + BX lr + +/** + * \b contextSwitch + * + * Architecture-specific context switch routine. + * + * Note that interrupts are always locked out when this routine is + * called. For cooperative switches, the scheduler will have entered + * a critical region. For preemptions (called from an ISR), the + * interrupts will have disabled in the tick_Handler. + * + * @param[in] [r0] -> Address to save old stack pointer + * @param[in] [r1] -> Address where new stack pointer is stored + * + * @return None + */ +contextSwitch: + STMFD sp!, {r4 - r11, lr} /* Save registers */ + +#ifdef CONTEXT_THREAD_ID + MRC p15, 0, r3, c13, c0, 2 + STMFD sp!, {r3} +#endif + + STR sp, [r0] /* Save old stack pointer */ + LDR r1, [r1] /* Load new stack pointer */ + MOV sp, r1 + +#ifdef CONTEXT_THREAD_ID + LDMFD sp!, {r3} + MCR p15, 0, r3, c13, c0, 2 +#endif + + LDMFD sp!, {r4 - r11, pc} /* Load new registers */ + +/** + * \b contextStart + * + * Architecture-specific context start routine. + * + * @param[in] [r0] -> Address where stack pointer is stored + * + * @return Does not return + */ +contextStart: + LDR r0, [r0] + MOV sp, r0 /* Load new stack pointer */ + +#ifdef CONTEXT_THREAD_ID + LDMFD sp!, {r3} + MCR p15, 0, r3, c13, c0, 2 +#endif + + LDMFD sp!, {r4 - r11, pc} /* Load new registers */ + +/** + * \b contextId + * + * Returns a unique ID for the context + * + * @return ID + */ +contextId: +#ifdef CONTEXT_THREAD_ID + MRC p15, 0, r0, c13, c0, 2 +#else + MOV r0, #0 +#endif + BX lr + +/** + * \b contextEnableInterrupts + * + * Enables interrupts on the processor + * + * @return None + */ +contextEnableInterrupts: + MRS r0, CPSR + MOV r1, #I_BIT + BIC r0, r0, r1 + MSR CPSR_c, r0 + BX lr + +/** + * \b contextExitCritical + * + * Exit critical section (restores interrupt posture) + * + * @param[in] r0 Interrupt Posture + * + * @return None + */ +contextExitCritical: + MSR CPSR_cxsf, r0 + BX lr + +/** + * \b contextEnterCritical + * + * Enter critical section (disables interrupts) + * + * @return Current interrupt posture + */ +contextEnterCritical: + MRS r0, CPSR + ORR r1, r0, #I_BIT + MSR CPSR_cxsf, r1 + BX lr + + + +/** + * \b archIRQHandler + * + * IRQ entry point. + * + * Save the process/thread context onto its own stackm before calling __context_preempt_handler (). + * __context_preempt_handler() might switch stacks. On return the same context is poped from the + * stack and control is returned to the process. + * + * @return None + */ +archIRQHandler: + + MSR cpsr_c, #(SVC_MODE | I_BIT) /* Save current process context in process stack */ + STMFD sp!, {r0 - r3, ip, lr} + + MSR cpsr_c, #(IRQ_MODE | I_BIT) /* Save lr_irq and spsr_irq in process stack */ + SUB lr, lr, #4 + MOV r1, lr + MRS r2, spsr + MSR cpsr_c, #(SVC_MODE | I_BIT) + STMFD sp!, {r1, r2} + + BL __context_preempt_handler /* Dispatch the interrupt to archTickHandler for + the timer tick interrupt or a simular function + for other interrupts which might call atomthread + functions. */ + + LDMFD sp!, {r1, r2} /* Restore lr_irq and spsr_irq from process stack */ + MSR cpsr_c, #(IRQ_MODE | I_BIT) + STMFD sp!, {r1} + MSR spsr_cxsf, r2 + + MSR cpsr_c, #(SVC_MODE | I_BIT) /* Restore process regs */ + LDMFD sp!, {r0 - r3, ip, lr} + + MSR cpsr_c, #(IRQ_MODE | I_BIT) /* Exit from IRQ */ + LDMFD sp!, {pc}^ + + + diff --git a/ports/armv7/types.h b/ports/arm/types.h similarity index 96% rename from ports/armv7/types.h rename to ports/arm/types.h index 0fd6feb..d383d84 100644 --- a/ports/armv7/types.h +++ b/ports/arm/types.h @@ -40,7 +40,7 @@ typedef int int32_t ; typedef short int16_t ; typedef char int8_t ; -typedef volatile unsigned int REG_DWORD ;// Hardware register definition +// typedef volatile unsigned int REG_DWORD ;// Hardware register definition #define UWORD64 unsigned long long #define UWORD32 unsigned int diff --git a/ports/armv7/atomport_arm.asm b/ports/armv7/atomport_arm.asm deleted file mode 100644 index 496e779..0000000 --- a/ports/armv7/atomport_arm.asm +++ /dev/null @@ -1,211 +0,0 @@ -; -; Copyright (c) 2012, Natie van Rooyen. All rights reserved. -; -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions -; are met: -; -; 1. Redistributions of source code must retain the above copyright -; notice, this list of conditions and the following disclaimer. -; 2. Redistributions in binary form must reproduce the above copyright -; notice, this list of conditions and the following disclaimer in the -; documentation and/or other materials provided with the distribution. -; 3. No personal names or organizations' names associated with the -; Atomthreads project may be used to endorse or promote products -; derived from this software without specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS -; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED -; TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -; PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE -; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -; POSSIBILITY OF SUCH DAMAGE. -; - - - PRESERVE8 {TRUE} - AREA UTILS, CODE, READONLY -;-- - EXPORT contextInit - EXPORT contextSwitch - EXPORT contextStart - EXPORT contextEnableInterrupts - EXPORT contextEnterCritical - EXPORT contextExitCritical - EXPORT archIRQHandler - - EXTERN __context_preempt_handler [WEAK] - -;-- -ARM_SVC_MODE EQU 0xd3 -ARM_IRQ_MODE EQU 0xD2 -ARM_FIQ_MODE EQU 0xD1 -ARM_MODE_MASK EQU 0x1F -ARM_FIQ_MODE_BITS EQU 0x11 -ARM_IRQ_MODE_BITS EQU 0x12 - - - ARM - -;-- -; \b contextInit -; -; Architecture-specific one time initialization. -; -; @return None -; -contextInit - - BX lr - -;-- -; \b contextSwitch -; -; Architecture-specific context switch routine. -; -; Note that interrupts are always locked out when this routine is -; called. For cooperative switches, the scheduler will have entered -; a critical region. For preemptions (called from an ISR), the -; interrupts will have disabled in the tick_Handler. -; -; @param[in] [r0] -> Address to save old stack pointer -; @param[in] [r1] -> Address where new stack pointer is stored -; -; @return None -; -contextSwitch - STMFD sp!, {r4 - r11, lr} ;- Save registers - - ;- IF :DEF:CONTEXT_THREAD_ID - MRC p15, 0, r3, c13, c0, 2 - STMFD sp!, {r3} - ;- ENDIF - - STR sp, [r0] ;- Save old stack pointer - LDR r1, [r1] ;- Load new stack pointer - MOV sp, r1 - - ISB - - ;- IF :DEF:CONTEXT_THREAD_ID - LDMFD sp!, {r3} - MCR p15, 0, r3, c13, c0, 2 - ;- ENDIF - - LDMFD sp!, {r4 - r11, pc} ;- Load new registers - -;-- -; \b contextStart -; -; Architecture-specific context start routine. -; -; @param[in] [r0] -> Address where stack pointer is stored -; -; @return Does not return -; -contextStart - LDR r0, [r0] - MOV sp, r0 ;- Load new stack pointer - - ;- IF :DEF:CONTEXT_THREAD_ID - LDMFD sp!, {r3} - MCR p15, 0, r3, c13, c0, 2 - ;- ENDIF - - LDMFD sp!, {r4 - r11, pc} ;- Load new registers - -;-- -; \b contextId -; -; Returns a unique ID for the context -; -; @return ID -; -contextId - MRC p15, 0, r0, c13, c0, 2 - BX lr - -;-- -; \b contextEnableInterrupts -; -; Enables interrupts on the processor -; -; @return None -; -contextEnableInterrupts - MRS r0, CPSR - MOV r1, #0x80 - BIC r0, r0, r1 - MSR CPSR_c, r0 - BX lr - -;-- -; \b contextExitCritical -; -; Exit critical section (restores interrupt posture) -; -; @param[in] r0 Interrupt Posture -; -; @return None -; -contextExitCritical - MSR CPSR_cxsf, r0 - BX lr - -;-- -; \b contextEnterCritical -; -; Enter critical section (disables interrupts) -; -; @return Current interrupt posture -; -contextEnterCritical - MRS r0, CPSR - ORR r1, r0, #0x80 - MSR CPSR_cxsf, r1 - BX lr - -;-- -; \b archIRQHandler -; -; IRQ entry point. -; -; Save the process/thread context onto its own stackm before calling __context_preempt_handler (). -; __context_preempt_handler() might switch stacks. On return the same context is poped from the -; stack and control is returned to the process. -; -; @return None -; -archIRQHandler - - MSR cpsr_c, #ARM_SVC_MODE ;- Save current process context in process stack - STMFD sp!, {r0 - r3, ip, lr} - - MSR cpsr_c, #ARM_IRQ_MODE ;- Save lr_irq and spsr_irq in process stack - SUB lr, lr, #4 - MOV r1, lr - MRS r2, spsr - MSR cpsr_c, #ARM_SVC_MODE - STMFD sp!, {r1, r2} - - BL __context_preempt_handler ;- Dispatch the interrupt to archTickHandler for the timer tick interrupt or a simular function for other interrupts which might call atomthread functions. - - LDMFD sp!, {r1, r2} ;- Restore lr_irq and spsr_irq from process stack - MSR cpsr_c, #ARM_IRQ_MODE - STMFD sp!, {r1} - MSR spsr_cxsf, r2 - - MSR cpsr_c, #ARM_SVC_MODE ;- Restore process regs - LDMFD sp!, {r0 - r3, ip, lr} - - MSR cpsr_c, #ARM_IRQ_MODE ;- Exit from IRQ - LDMFD sp!, {pc}^ - - -;-- - END diff --git a/tests/atomtests.h b/tests/atomtests.h index 9e0d0f2..2018a28 100644 --- a/tests/atomtests.h +++ b/tests/atomtests.h @@ -44,4 +44,4 @@ extern uint32_t test_start (void); -#endif /* __ATOM_TESTS_H */ +#endif /* __ATOM_TESTS_H */ \ No newline at end of file diff --git a/tests/kern1.c b/tests/kern1.c index 1695039..d0cce0c 100644 --- a/tests/kern1.c +++ b/tests/kern1.c @@ -64,7 +64,7 @@ uint32_t test_start (void) /* atomThreadCreate: Pass a bad TCB pointer */ if (atomThreadCreate (NULL, TEST_THREAD_PRIO, test_thread_func, 0, - &test_thread_stack[TEST_THREAD_STACK_SIZE - 1], + &test_thread_stack[TEST_THREAD_STACK_SIZE - sizeof(uint32_t)], TEST_THREAD_STACK_SIZE) != ATOM_ERR_PARAM) { ATOMLOG (_STR("Bad TCB check\n")); @@ -73,7 +73,7 @@ uint32_t test_start (void) /* atomThreadCreate: Pass a bad entry point */ if (atomThreadCreate (&tcb1, TEST_THREAD_PRIO, NULL, 0, - &test_thread_stack[TEST_THREAD_STACK_SIZE - 1], + &test_thread_stack[TEST_THREAD_STACK_SIZE - sizeof(uint32_t)], TEST_THREAD_STACK_SIZE) != ATOM_ERR_PARAM) { ATOMLOG (_STR("Bad entry check\n")); @@ -90,7 +90,7 @@ uint32_t test_start (void) /* atomThreadCreate: Pass a bad stack size */ if (atomThreadCreate (&tcb1, TEST_THREAD_PRIO, test_thread_func, 0, - &test_thread_stack[TEST_THREAD_STACK_SIZE - 1], 0) != ATOM_ERR_PARAM) + &test_thread_stack[TEST_THREAD_STACK_SIZE - sizeof(uint32_t)], 0) != ATOM_ERR_PARAM) { ATOMLOG (_STR("Bad stack size check\n")); failures++; diff --git a/tests/kern3.c b/tests/kern3.c index 20304f8..47fc6bb 100644 --- a/tests/kern3.c +++ b/tests/kern3.c @@ -95,7 +95,7 @@ uint32_t test_start (void) /* Create low priority thread */ if (atomThreadCreate (&tcb[0], 253, test_thread_func, 0, - &test_thread_stack[0][TEST_THREAD_STACK_SIZE - 1], + &test_thread_stack[0][TEST_THREAD_STACK_SIZE - sizeof(uint32_t)], TEST_THREAD_STACK_SIZE) != ATOM_OK) { ATOMLOG (_STR("Bad thread create\n")); @@ -104,7 +104,7 @@ uint32_t test_start (void) /* Create high priority thread */ else if (atomThreadCreate (&tcb[1], 252, test_thread_func, 1, - &test_thread_stack[1][TEST_THREAD_STACK_SIZE - 1], + &test_thread_stack[1][TEST_THREAD_STACK_SIZE - sizeof(uint32_t)], TEST_THREAD_STACK_SIZE) != ATOM_OK) { ATOMLOG (_STR("Bad thread create\n")); diff --git a/tests/kern4.c b/tests/kern4.c index 909232e..b38be51 100644 --- a/tests/kern4.c +++ b/tests/kern4.c @@ -97,28 +97,28 @@ uint32_t test_start (void) * a spell in which this thread was run. */ if (atomThreadCreate (&tcb[0], TEST_THREAD_PRIO + 1, test_thread_func, 0, - &test_thread_stack[0][TEST_THREAD_STACK_SIZE - 1], + &test_thread_stack[0][TEST_THREAD_STACK_SIZE - sizeof(uint32_t)], TEST_THREAD_STACK_SIZE) != ATOM_OK) { ATOMLOG (_STR("Bad thread create\n")); failures++; } else if (atomThreadCreate (&tcb[1], TEST_THREAD_PRIO + 1, test_thread_func, 1, - &test_thread_stack[1][TEST_THREAD_STACK_SIZE - 1], + &test_thread_stack[1][TEST_THREAD_STACK_SIZE - sizeof(uint32_t)], TEST_THREAD_STACK_SIZE) != ATOM_OK) { ATOMLOG (_STR("Bad thread create\n")); failures++; } else if (atomThreadCreate (&tcb[2], TEST_THREAD_PRIO + 1, test_thread_func, 2, - &test_thread_stack[2][TEST_THREAD_STACK_SIZE - 1], + &test_thread_stack[2][TEST_THREAD_STACK_SIZE - sizeof(uint32_t)], TEST_THREAD_STACK_SIZE) != ATOM_OK) { ATOMLOG (_STR("Bad thread create\n")); failures++; } else if (atomThreadCreate (&tcb[3], TEST_THREAD_PRIO + 1, test_thread_func, 3, - &test_thread_stack[3][TEST_THREAD_STACK_SIZE - 1], + &test_thread_stack[3][TEST_THREAD_STACK_SIZE - sizeof(uint32_t)], TEST_THREAD_STACK_SIZE) != ATOM_OK) { ATOMLOG (_STR("Bad thread create\n")); diff --git a/tests/mutex1.c b/tests/mutex1.c index e3bc16a..af1e157 100644 --- a/tests/mutex1.c +++ b/tests/mutex1.c @@ -138,7 +138,7 @@ uint32_t test_start (void) } else if (atomThreadCreate(&tcb[0], TEST_THREAD_PRIO, test1_thread_func, 0, - &test_thread_stack[0][TEST_THREAD_STACK_SIZE - 1], + &test_thread_stack[0][TEST_THREAD_STACK_SIZE - sizeof(uint32_t)], TEST_THREAD_STACK_SIZE) != ATOM_OK) { /* Fail */ @@ -201,7 +201,7 @@ uint32_t test_start (void) } else if (atomThreadCreate(&tcb[1], TEST_THREAD_PRIO, test2_thread_func, 0, - &test_thread_stack[1][TEST_THREAD_STACK_SIZE - 1], + &test_thread_stack[1][TEST_THREAD_STACK_SIZE - sizeof(uint32_t)], TEST_THREAD_STACK_SIZE) != ATOM_OK) { /* Fail */ diff --git a/tests/mutex2.c b/tests/mutex2.c index 9725f44..033d8b6 100644 --- a/tests/mutex2.c +++ b/tests/mutex2.c @@ -144,7 +144,7 @@ uint32_t test_start (void) /* Create a test thread, the sole purpose of which is to own mutex2 */ g_owned = 0; if (atomThreadCreate(&tcb[0], TEST_THREAD_PRIO, test_thread_func, 0, - &test_thread_stack[0][TEST_THREAD_STACK_SIZE - 1], + &test_thread_stack[0][TEST_THREAD_STACK_SIZE - sizeof(uint32_t)], TEST_THREAD_STACK_SIZE) != ATOM_OK) { /* Fail */ diff --git a/tests/mutex3.c b/tests/mutex3.c index f604430..1f2becc 100644 --- a/tests/mutex3.c +++ b/tests/mutex3.c @@ -108,7 +108,7 @@ uint32_t test_start (void) { /* Create Thread 1 (lower priority thread A) */ if (atomThreadCreate(&tcb[0], TEST_THREAD_PRIO+1, test_thread_func, 1, - &test_thread_stack[0][TEST_THREAD_STACK_SIZE - 1], + &test_thread_stack[0][TEST_THREAD_STACK_SIZE - sizeof(uint32_t)], TEST_THREAD_STACK_SIZE) != ATOM_OK) { /* Fail */ @@ -121,7 +121,7 @@ uint32_t test_start (void) /* Create Thread 2 (lower priority thread B) */ if (atomThreadCreate(&tcb[1], TEST_THREAD_PRIO+1, test_thread_func, 2, - &test_thread_stack[1][TEST_THREAD_STACK_SIZE - 1], + &test_thread_stack[1][TEST_THREAD_STACK_SIZE - sizeof(uint32_t)], TEST_THREAD_STACK_SIZE) != ATOM_OK) { /* Fail */ @@ -134,7 +134,7 @@ uint32_t test_start (void) /* Create Thread 3 (higher priority thread A) */ if (atomThreadCreate(&tcb[2], TEST_THREAD_PRIO, test_thread_func, 3, - &test_thread_stack[2][TEST_THREAD_STACK_SIZE - 1], + &test_thread_stack[2][TEST_THREAD_STACK_SIZE - sizeof(uint32_t)], TEST_THREAD_STACK_SIZE) != ATOM_OK) { /* Fail */ @@ -147,7 +147,7 @@ uint32_t test_start (void) /* Create Thread 4 (higher priority thread B) */ if (atomThreadCreate(&tcb[3], TEST_THREAD_PRIO, test_thread_func, 4, - &test_thread_stack[3][TEST_THREAD_STACK_SIZE - 1], + &test_thread_stack[3][TEST_THREAD_STACK_SIZE - sizeof(uint32_t)], TEST_THREAD_STACK_SIZE) != ATOM_OK) { /* Fail */ diff --git a/tests/mutex4.c b/tests/mutex4.c index b478517..7d9eeda 100644 --- a/tests/mutex4.c +++ b/tests/mutex4.c @@ -101,7 +101,7 @@ uint32_t test_start (void) /* Create Thread 1 */ if (atomThreadCreate(&tcb[0], TEST_THREAD_PRIO, test_thread_func, 1, - &test_thread_stack[0][TEST_THREAD_STACK_SIZE - 1], + &test_thread_stack[0][TEST_THREAD_STACK_SIZE - sizeof(uint32_t)], TEST_THREAD_STACK_SIZE) != ATOM_OK) { /* Fail */ @@ -113,7 +113,7 @@ uint32_t test_start (void) /* Create Thread 2 */ if (atomThreadCreate(&tcb[1], TEST_THREAD_PRIO, test_thread_func, 2, - &test_thread_stack[1][TEST_THREAD_STACK_SIZE - 1], + &test_thread_stack[1][TEST_THREAD_STACK_SIZE - sizeof(uint32_t)], TEST_THREAD_STACK_SIZE) != ATOM_OK) { /* Fail */ @@ -125,7 +125,7 @@ uint32_t test_start (void) /* Create Thread 3 */ if (atomThreadCreate(&tcb[2], TEST_THREAD_PRIO, test_thread_func, 3, - &test_thread_stack[2][TEST_THREAD_STACK_SIZE - 1], + &test_thread_stack[2][TEST_THREAD_STACK_SIZE - sizeof(uint32_t)], TEST_THREAD_STACK_SIZE) != ATOM_OK) { /* Fail */ @@ -137,7 +137,7 @@ uint32_t test_start (void) /* Create Thread 4 */ if (atomThreadCreate(&tcb[3], TEST_THREAD_PRIO, test_thread_func, 4, - &test_thread_stack[3][TEST_THREAD_STACK_SIZE - 1], + &test_thread_stack[3][TEST_THREAD_STACK_SIZE - sizeof(uint32_t)], TEST_THREAD_STACK_SIZE) != ATOM_OK) { /* Fail */ diff --git a/tests/mutex5.c b/tests/mutex5.c index 9aa18f2..7e91197 100644 --- a/tests/mutex5.c +++ b/tests/mutex5.c @@ -95,7 +95,7 @@ uint32_t test_start (void) /* Create second thread */ else if (atomThreadCreate(&tcb[0], TEST_THREAD_PRIO, test_thread_func, 1, - &test_thread_stack[0][TEST_THREAD_STACK_SIZE - 1], + &test_thread_stack[0][TEST_THREAD_STACK_SIZE - sizeof(uint32_t)], TEST_THREAD_STACK_SIZE) != ATOM_OK) { /* Fail */ diff --git a/tests/mutex6.c b/tests/mutex6.c index ca2c2d6..de4754f 100644 --- a/tests/mutex6.c +++ b/tests/mutex6.c @@ -100,7 +100,7 @@ uint32_t test_start (void) /* Create second thread */ if (atomThreadCreate(&tcb[0], TEST_THREAD_PRIO, test_thread_func, 1, - &test_thread_stack[0][TEST_THREAD_STACK_SIZE - 1], + &test_thread_stack[0][TEST_THREAD_STACK_SIZE - sizeof(uint32_t)], TEST_THREAD_STACK_SIZE) != ATOM_OK) { /* Fail */ diff --git a/tests/mutex7.c b/tests/mutex7.c index 9189dee..5a9f312 100644 --- a/tests/mutex7.c +++ b/tests/mutex7.c @@ -94,7 +94,7 @@ uint32_t test_start (void) /* Create second thread */ else if (atomThreadCreate(&tcb[0], TEST_THREAD_PRIO, test_thread_func, 1, - &test_thread_stack[0][TEST_THREAD_STACK_SIZE - 1], + &test_thread_stack[0][TEST_THREAD_STACK_SIZE - sizeof(uint32_t)], TEST_THREAD_STACK_SIZE) != ATOM_OK) { /* Fail */ diff --git a/tests/mutex8.c b/tests/mutex8.c index 14febb9..3c1776d 100644 --- a/tests/mutex8.c +++ b/tests/mutex8.c @@ -94,7 +94,7 @@ uint32_t test_start (void) /* Create test thread 1 */ if (atomThreadCreate(&tcb[0], TEST_THREAD_PRIO, test_thread_func, 0, - &test_thread_stack[0][TEST_THREAD_STACK_SIZE - 1], + &test_thread_stack[0][TEST_THREAD_STACK_SIZE - sizeof(uint32_t)], TEST_THREAD_STACK_SIZE) != ATOM_OK) { /* Fail */ @@ -104,7 +104,7 @@ uint32_t test_start (void) /* Create test thread 2 */ else if (atomThreadCreate(&tcb[1], TEST_THREAD_PRIO, test_thread_func, 1, - &test_thread_stack[1][TEST_THREAD_STACK_SIZE - 1], + &test_thread_stack[1][TEST_THREAD_STACK_SIZE - sizeof(uint32_t)], TEST_THREAD_STACK_SIZE) != ATOM_OK) { /* Fail */ @@ -114,7 +114,7 @@ uint32_t test_start (void) /* Create test thread 3 */ else if (atomThreadCreate(&tcb[2], TEST_THREAD_PRIO, test_thread_func, 2, - &test_thread_stack[2][TEST_THREAD_STACK_SIZE - 1], + &test_thread_stack[2][TEST_THREAD_STACK_SIZE - sizeof(uint32_t)], TEST_THREAD_STACK_SIZE) != ATOM_OK) { /* Fail */ diff --git a/tests/mutex9.c b/tests/mutex9.c index e509762..23d2782 100644 --- a/tests/mutex9.c +++ b/tests/mutex9.c @@ -88,7 +88,7 @@ uint32_t test_start (void) /* Create second thread */ if (atomThreadCreate(&tcb[0], TEST_THREAD_PRIO, test_thread_func, 1, - &test_thread_stack[0][TEST_THREAD_STACK_SIZE - 1], + &test_thread_stack[0][TEST_THREAD_STACK_SIZE - sizeof(uint32_t)], TEST_THREAD_STACK_SIZE) != ATOM_OK) { /* Fail */ diff --git a/tests/queue2.c b/tests/queue2.c index 8528ade..24bcd60 100644 --- a/tests/queue2.c +++ b/tests/queue2.c @@ -90,7 +90,7 @@ uint32_t test_start (void) /* Create a test thread that will block because the queue is empty */ else if (atomThreadCreate(&tcb[0], TEST_THREAD_PRIO, test1_thread_func, 0, - &test_thread_stack[0][TEST_THREAD_STACK_SIZE - 1], + &test_thread_stack[0][TEST_THREAD_STACK_SIZE - sizeof(uint32_t)], TEST_THREAD_STACK_SIZE) != ATOM_OK) { /* Fail */ @@ -147,7 +147,7 @@ uint32_t test_start (void) /* Create a test thread that will block because the queue is empty */ else if (atomThreadCreate(&tcb[1], TEST_THREAD_PRIO, test2_thread_func, 0, - &test_thread_stack[1][TEST_THREAD_STACK_SIZE - 1], + &test_thread_stack[1][TEST_THREAD_STACK_SIZE - sizeof(uint32_t)], TEST_THREAD_STACK_SIZE) != ATOM_OK) { /* Fail */ diff --git a/tests/queue3.c b/tests/queue3.c index 277a4e3..fed9ca8 100644 --- a/tests/queue3.c +++ b/tests/queue3.c @@ -107,7 +107,7 @@ uint32_t test_start (void) /* Create a test thread that will block because the queue is full */ if (atomThreadCreate(&tcb[0], TEST_THREAD_PRIO, test1_thread_func, 0, - &test_thread_stack[0][TEST_THREAD_STACK_SIZE - 1], + &test_thread_stack[0][TEST_THREAD_STACK_SIZE - sizeof(uint32_t)], TEST_THREAD_STACK_SIZE) != ATOM_OK) { /* Fail */ @@ -178,7 +178,7 @@ uint32_t test_start (void) /* Create a test thread that will block because the queue is full */ if (atomThreadCreate(&tcb[1], TEST_THREAD_PRIO, test2_thread_func, 0, - &test_thread_stack[1][TEST_THREAD_STACK_SIZE - 1], + &test_thread_stack[1][TEST_THREAD_STACK_SIZE - sizeof(uint32_t)], TEST_THREAD_STACK_SIZE) != ATOM_OK) { /* Fail */ diff --git a/tests/queue5.c b/tests/queue5.c index bf07960..bf7303b 100644 --- a/tests/queue5.c +++ b/tests/queue5.c @@ -115,7 +115,7 @@ uint32_t test_start (void) /* Create Thread 1 (lower priority thread A) */ if (atomThreadCreate(&tcb[0], TEST_THREAD_PRIO+1, test_thread_func, 1, - &test_thread_stack[0][TEST_THREAD_STACK_SIZE - 1], + &test_thread_stack[0][TEST_THREAD_STACK_SIZE - sizeof(uint32_t)], TEST_THREAD_STACK_SIZE) != ATOM_OK) { /* Fail */ @@ -128,7 +128,7 @@ uint32_t test_start (void) /* Create Thread 2 (lower priority thread B) */ if (atomThreadCreate(&tcb[1], TEST_THREAD_PRIO+1, test_thread_func, 2, - &test_thread_stack[1][TEST_THREAD_STACK_SIZE - 1], + &test_thread_stack[1][TEST_THREAD_STACK_SIZE - sizeof(uint32_t)], TEST_THREAD_STACK_SIZE) != ATOM_OK) { /* Fail */ @@ -141,7 +141,7 @@ uint32_t test_start (void) /* Create Thread 3 (higher priority thread A) */ if (atomThreadCreate(&tcb[2], TEST_THREAD_PRIO, test_thread_func, 3, - &test_thread_stack[2][TEST_THREAD_STACK_SIZE - 1], + &test_thread_stack[2][TEST_THREAD_STACK_SIZE - sizeof(uint32_t)], TEST_THREAD_STACK_SIZE) != ATOM_OK) { /* Fail */ @@ -154,7 +154,7 @@ uint32_t test_start (void) /* Create Thread 4 (higher priority thread B) */ if (atomThreadCreate(&tcb[3], TEST_THREAD_PRIO, test_thread_func, 4, - &test_thread_stack[3][TEST_THREAD_STACK_SIZE - 1], + &test_thread_stack[3][TEST_THREAD_STACK_SIZE - sizeof(uint32_t)], TEST_THREAD_STACK_SIZE) != ATOM_OK) { /* Fail */ diff --git a/tests/queue6.c b/tests/queue6.c index 4de62f0..eb77e04 100644 --- a/tests/queue6.c +++ b/tests/queue6.c @@ -107,7 +107,7 @@ uint32_t test_start (void) /* Create a test thread that will block because the queue is empty */ else if (atomThreadCreate(&tcb[0], TEST_THREAD_PRIO + 1, test1_thread_func, 0, - &test_thread_stack[0][TEST_THREAD_STACK_SIZE - 1], + &test_thread_stack[0][TEST_THREAD_STACK_SIZE - sizeof(uint32_t)], TEST_THREAD_STACK_SIZE) != ATOM_OK) { /* Fail */ diff --git a/tests/queue7.c b/tests/queue7.c index 5b249d8..fda8132 100644 --- a/tests/queue7.c +++ b/tests/queue7.c @@ -94,7 +94,7 @@ uint32_t test_start (void) /* Create test thread 1 */ if (atomThreadCreate(&tcb[0], TEST_THREAD_PRIO, test_thread_func, 0, - &test_thread_stack[0][TEST_THREAD_STACK_SIZE - 1], + &test_thread_stack[0][TEST_THREAD_STACK_SIZE - sizeof(uint32_t)], TEST_THREAD_STACK_SIZE) != ATOM_OK) { /* Fail */ @@ -104,7 +104,7 @@ uint32_t test_start (void) /* Create test thread 2 */ else if (atomThreadCreate(&tcb[1], TEST_THREAD_PRIO, test_thread_func, 1, - &test_thread_stack[1][TEST_THREAD_STACK_SIZE - 1], + &test_thread_stack[1][TEST_THREAD_STACK_SIZE - sizeof(uint32_t)], TEST_THREAD_STACK_SIZE) != ATOM_OK) { /* Fail */ @@ -114,7 +114,7 @@ uint32_t test_start (void) /* Create test thread 3 */ else if (atomThreadCreate(&tcb[2], TEST_THREAD_PRIO, test_thread_func, 2, - &test_thread_stack[2][TEST_THREAD_STACK_SIZE - 1], + &test_thread_stack[2][TEST_THREAD_STACK_SIZE - sizeof(uint32_t)], TEST_THREAD_STACK_SIZE) != ATOM_OK) { /* Fail */ diff --git a/tests/queue9.c b/tests/queue9.c index 1bc1034..7251dd6 100644 --- a/tests/queue9.c +++ b/tests/queue9.c @@ -103,7 +103,7 @@ uint32_t test_start (void) { /* Create Thread 1 */ if (atomThreadCreate(&tcb[0], TEST_THREAD_PRIO, test_thread_func, 1, - &test_thread_stack[0][TEST_THREAD_STACK_SIZE - 1], + &test_thread_stack[0][TEST_THREAD_STACK_SIZE - sizeof(uint32_t)], TEST_THREAD_STACK_SIZE) != ATOM_OK) { /* Fail */ @@ -115,7 +115,7 @@ uint32_t test_start (void) /* Create Thread 2 */ if (atomThreadCreate(&tcb[1], TEST_THREAD_PRIO, test_thread_func, 2, - &test_thread_stack[1][TEST_THREAD_STACK_SIZE - 1], + &test_thread_stack[1][TEST_THREAD_STACK_SIZE - sizeof(uint32_t)], TEST_THREAD_STACK_SIZE) != ATOM_OK) { /* Fail */ @@ -127,7 +127,7 @@ uint32_t test_start (void) /* Create Thread 3 */ if (atomThreadCreate(&tcb[2], TEST_THREAD_PRIO, test_thread_func, 3, - &test_thread_stack[2][TEST_THREAD_STACK_SIZE - 1], + &test_thread_stack[2][TEST_THREAD_STACK_SIZE - sizeof(uint32_t)], TEST_THREAD_STACK_SIZE) != ATOM_OK) { /* Fail */ @@ -139,7 +139,7 @@ uint32_t test_start (void) /* Create Thread 4 */ if (atomThreadCreate(&tcb[3], TEST_THREAD_PRIO, test_thread_func, 4, - &test_thread_stack[3][TEST_THREAD_STACK_SIZE - 1], + &test_thread_stack[3][TEST_THREAD_STACK_SIZE - sizeof(uint32_t)], TEST_THREAD_STACK_SIZE) != ATOM_OK) { /* Fail */ diff --git a/tests/sem1.c b/tests/sem1.c index b7b6335..69be29b 100644 --- a/tests/sem1.c +++ b/tests/sem1.c @@ -134,7 +134,7 @@ uint32_t test_start (void) } else if (atomThreadCreate(&tcb[0], TEST_THREAD_PRIO, test1_thread_func, 0, - &test_thread_stack[0][TEST_THREAD_STACK_SIZE - 1], + &test_thread_stack[0][TEST_THREAD_STACK_SIZE - sizeof(uint32_t)], TEST_THREAD_STACK_SIZE) != ATOM_OK) { /* Fail */ @@ -201,7 +201,7 @@ uint32_t test_start (void) failures++; } else if (atomThreadCreate(&tcb[1], TEST_THREAD_PRIO, test2_thread_func, 0, - &test_thread_stack[1][TEST_THREAD_STACK_SIZE - 1], + &test_thread_stack[1][TEST_THREAD_STACK_SIZE - sizeof(uint32_t)], TEST_THREAD_STACK_SIZE) != ATOM_OK) { /* Fail */ diff --git a/tests/sem3.c b/tests/sem3.c index 6648b39..7bdb489 100644 --- a/tests/sem3.c +++ b/tests/sem3.c @@ -103,7 +103,7 @@ uint32_t test_start (void) { /* Create Thread 1 (lower priority thread A) */ if (atomThreadCreate(&tcb[0], TEST_THREAD_PRIO+1, test_thread_func, 1, - &test_thread_stack[0][TEST_THREAD_STACK_SIZE - 1], + &test_thread_stack[0][TEST_THREAD_STACK_SIZE - sizeof(uint32_t)], TEST_THREAD_STACK_SIZE) != ATOM_OK) { /* Fail */ @@ -116,7 +116,7 @@ uint32_t test_start (void) /* Create Thread 2 (lower priority thread B) */ if (atomThreadCreate(&tcb[1], TEST_THREAD_PRIO+1, test_thread_func, 2, - &test_thread_stack[1][TEST_THREAD_STACK_SIZE - 1], + &test_thread_stack[1][TEST_THREAD_STACK_SIZE - sizeof(uint32_t)], TEST_THREAD_STACK_SIZE) != ATOM_OK) { /* Fail */ @@ -129,7 +129,7 @@ uint32_t test_start (void) /* Create Thread 3 (higher priority thread A) */ if (atomThreadCreate(&tcb[2], TEST_THREAD_PRIO, test_thread_func, 3, - &test_thread_stack[2][TEST_THREAD_STACK_SIZE - 1], + &test_thread_stack[2][TEST_THREAD_STACK_SIZE - sizeof(uint32_t)], TEST_THREAD_STACK_SIZE) != ATOM_OK) { /* Fail */ @@ -142,7 +142,7 @@ uint32_t test_start (void) /* Create Thread 4 (higher priority thread B) */ if (atomThreadCreate(&tcb[3], TEST_THREAD_PRIO, test_thread_func, 4, - &test_thread_stack[3][TEST_THREAD_STACK_SIZE - 1], + &test_thread_stack[3][TEST_THREAD_STACK_SIZE - sizeof(uint32_t)], TEST_THREAD_STACK_SIZE) != ATOM_OK) { /* Fail */ diff --git a/tests/sem4.c b/tests/sem4.c index 419195c..092b0f9 100644 --- a/tests/sem4.c +++ b/tests/sem4.c @@ -97,7 +97,7 @@ uint32_t test_start (void) { /* Create Thread 1 */ if (atomThreadCreate(&tcb[0], TEST_THREAD_PRIO, test_thread_func, 1, - &test_thread_stack[0][TEST_THREAD_STACK_SIZE - 1], + &test_thread_stack[0][TEST_THREAD_STACK_SIZE - sizeof(uint32_t)], TEST_THREAD_STACK_SIZE) != ATOM_OK) { /* Fail */ @@ -109,7 +109,7 @@ uint32_t test_start (void) /* Create Thread 2 */ if (atomThreadCreate(&tcb[1], TEST_THREAD_PRIO, test_thread_func, 2, - &test_thread_stack[1][TEST_THREAD_STACK_SIZE - 1], + &test_thread_stack[1][TEST_THREAD_STACK_SIZE - sizeof(uint32_t)], TEST_THREAD_STACK_SIZE) != ATOM_OK) { /* Fail */ @@ -121,7 +121,7 @@ uint32_t test_start (void) /* Create Thread 3 */ if (atomThreadCreate(&tcb[2], TEST_THREAD_PRIO, test_thread_func, 3, - &test_thread_stack[2][TEST_THREAD_STACK_SIZE - 1], + &test_thread_stack[2][TEST_THREAD_STACK_SIZE - sizeof(uint32_t)], TEST_THREAD_STACK_SIZE) != ATOM_OK) { /* Fail */ @@ -133,7 +133,7 @@ uint32_t test_start (void) /* Create Thread 4 */ if (atomThreadCreate(&tcb[3], TEST_THREAD_PRIO, test_thread_func, 4, - &test_thread_stack[3][TEST_THREAD_STACK_SIZE - 1], + &test_thread_stack[3][TEST_THREAD_STACK_SIZE - sizeof(uint32_t)], TEST_THREAD_STACK_SIZE) != ATOM_OK) { /* Fail */ diff --git a/tests/sem5.c b/tests/sem5.c index dc87f9f..ae0c0a5 100644 --- a/tests/sem5.c +++ b/tests/sem5.c @@ -84,7 +84,7 @@ uint32_t test_start (void) { /* Create second thread */ if (atomThreadCreate(&tcb[0], TEST_THREAD_PRIO, test_thread_func, 1, - &test_thread_stack[0][TEST_THREAD_STACK_SIZE - 1], + &test_thread_stack[0][TEST_THREAD_STACK_SIZE - sizeof(uint32_t)], TEST_THREAD_STACK_SIZE) != ATOM_OK) { /* Fail */ diff --git a/tests/sem6.c b/tests/sem6.c index 851f9b8..309de97 100644 --- a/tests/sem6.c +++ b/tests/sem6.c @@ -94,7 +94,7 @@ uint32_t test_start (void) /* Create second thread */ else if (atomThreadCreate(&tcb[0], TEST_THREAD_PRIO, test_thread_func, 1, - &test_thread_stack[0][TEST_THREAD_STACK_SIZE - 1], + &test_thread_stack[0][TEST_THREAD_STACK_SIZE - sizeof(uint32_t)], TEST_THREAD_STACK_SIZE) != ATOM_OK) { /* Fail */ diff --git a/tests/sem7.c b/tests/sem7.c index 62fa16f..5507c70 100644 --- a/tests/sem7.c +++ b/tests/sem7.c @@ -100,7 +100,7 @@ uint32_t test_start (void) /* Create second thread */ else if (atomThreadCreate(&tcb[0], TEST_THREAD_PRIO, test_thread_func, 1, - &test_thread_stack[0][TEST_THREAD_STACK_SIZE - 1], + &test_thread_stack[0][TEST_THREAD_STACK_SIZE - sizeof(uint32_t)], TEST_THREAD_STACK_SIZE) != ATOM_OK) { /* Fail */ diff --git a/tests/sem8.c b/tests/sem8.c index 432cf32..67e2ea3 100644 --- a/tests/sem8.c +++ b/tests/sem8.c @@ -110,7 +110,7 @@ uint32_t test_start (void) /* Create thread 1: Higher priority than main thread so should sleep */ else if (atomThreadCreate(&tcb[0], TEST_THREAD_PRIO - 1, test_thread_func, 1, - &test_thread_stack[0][TEST_THREAD_STACK_SIZE - 1], + &test_thread_stack[0][TEST_THREAD_STACK_SIZE - sizeof(uint32_t)], TEST_THREAD_STACK_SIZE) != ATOM_OK) { /* Fail */ @@ -120,7 +120,7 @@ uint32_t test_start (void) /* Create thread 2: Same priority as main thread so should not sleep */ else if (atomThreadCreate(&tcb[1], TEST_THREAD_PRIO, test_thread_func, 0, - &test_thread_stack[1][TEST_THREAD_STACK_SIZE - 1], + &test_thread_stack[1][TEST_THREAD_STACK_SIZE - sizeof(uint32_t)], TEST_THREAD_STACK_SIZE) != ATOM_OK) { /* Fail */ @@ -130,7 +130,7 @@ uint32_t test_start (void) /* Create thread 3: Same priority as main thread so should not sleep */ else if (atomThreadCreate(&tcb[2], TEST_THREAD_PRIO + 1, test_thread_func, 0, - &test_thread_stack[2][TEST_THREAD_STACK_SIZE - 1], + &test_thread_stack[2][TEST_THREAD_STACK_SIZE - sizeof(uint32_t)], TEST_THREAD_STACK_SIZE) != ATOM_OK) { /* Fail */ diff --git a/tests/sem9.c b/tests/sem9.c index d7a86d6..ab4653d 100644 --- a/tests/sem9.c +++ b/tests/sem9.c @@ -87,7 +87,7 @@ uint32_t test_start (void) { /* Create test thread 1 */ if (atomThreadCreate(&tcb[0], TEST_THREAD_PRIO, test_thread_func, 0, - &test_thread_stack[0][TEST_THREAD_STACK_SIZE - 1], + &test_thread_stack[0][TEST_THREAD_STACK_SIZE - sizeof(uint32_t)], TEST_THREAD_STACK_SIZE) != ATOM_OK) { /* Fail */ @@ -97,7 +97,7 @@ uint32_t test_start (void) /* Create test thread 2 */ else if (atomThreadCreate(&tcb[1], TEST_THREAD_PRIO, test_thread_func, 1, - &test_thread_stack[1][TEST_THREAD_STACK_SIZE - 1], + &test_thread_stack[1][TEST_THREAD_STACK_SIZE - sizeof(uint32_t)], TEST_THREAD_STACK_SIZE) != ATOM_OK) { /* Fail */ @@ -107,7 +107,7 @@ uint32_t test_start (void) /* Create test thread 3 */ else if (atomThreadCreate(&tcb[2], TEST_THREAD_PRIO, test_thread_func, 2, - &test_thread_stack[2][TEST_THREAD_STACK_SIZE - 1], + &test_thread_stack[2][TEST_THREAD_STACK_SIZE - sizeof(uint32_t)], TEST_THREAD_STACK_SIZE) != ATOM_OK) { /* Fail */ diff --git a/tests/timer2.c b/tests/timer2.c index a606830..95c1dc6 100644 --- a/tests/timer2.c +++ b/tests/timer2.c @@ -73,7 +73,7 @@ uint32_t test_start (void) /* Create Thread 1 */ if (atomThreadCreate(&tcb[0], TEST_THREAD_PRIO, test_thread_func, 1, - &test_thread_stack[0][TEST_THREAD_STACK_SIZE - 1], + &test_thread_stack[0][TEST_THREAD_STACK_SIZE - sizeof(uint32_t)], TEST_THREAD_STACK_SIZE) != ATOM_OK) { /* Fail */ @@ -83,7 +83,7 @@ uint32_t test_start (void) /* Create Thread 2 */ if (atomThreadCreate(&tcb[1], TEST_THREAD_PRIO, test_thread_func, 2, - &test_thread_stack[1][TEST_THREAD_STACK_SIZE - 1], + &test_thread_stack[1][TEST_THREAD_STACK_SIZE - sizeof(uint32_t)], TEST_THREAD_STACK_SIZE) != ATOM_OK) { /* Fail */ @@ -93,7 +93,7 @@ uint32_t test_start (void) /* Create Thread 3 */ if (atomThreadCreate(&tcb[2], TEST_THREAD_PRIO, test_thread_func, 3, - &test_thread_stack[2][TEST_THREAD_STACK_SIZE - 1], + &test_thread_stack[2][TEST_THREAD_STACK_SIZE - sizeof(uint32_t)], TEST_THREAD_STACK_SIZE) != ATOM_OK) { /* Fail */ From 28e7382732c8ec14f6f3a07c83adc2d3e600bf9b Mon Sep 17 00:00:00 2001 From: Natie van Rooyen Date: Tue, 18 Sep 2012 15:24:59 +0200 Subject: [PATCH 15/28] Updated CortexM port --- ports/arm/atomport.c | 2 +- ports/{cortex_m3 => cortex_m}/Makefile | 10 +- ports/{cortex_m3 => cortex_m}/README | 0 ports/cortex_m/atomport-tests.h | 50 ++++ ports/{cortex_m3 => cortex_m}/atomport.c | 7 +- ports/{cortex_m3 => cortex_m}/atomport.h | 13 +- .../atomport_private.h | 0 ports/cortex_m/atomport_s.S | 220 ++++++++++++++++++ ports/{cortex_m3 => cortex_m}/types.h | 0 ports/cortex_m3/atomport_arm.asm | 217 ----------------- 10 files changed, 288 insertions(+), 231 deletions(-) rename ports/{cortex_m3 => cortex_m}/Makefile (67%) rename ports/{cortex_m3 => cortex_m}/README (100%) create mode 100644 ports/cortex_m/atomport-tests.h rename ports/{cortex_m3 => cortex_m}/atomport.c (95%) rename ports/{cortex_m3 => cortex_m}/atomport.h (90%) rename ports/{cortex_m3 => cortex_m}/atomport_private.h (100%) create mode 100644 ports/cortex_m/atomport_s.S rename ports/{cortex_m3 => cortex_m}/types.h (100%) delete mode 100644 ports/cortex_m3/atomport_arm.asm diff --git a/ports/arm/atomport.c b/ports/arm/atomport.c index da96930..d6fc47b 100644 --- a/ports/arm/atomport.c +++ b/ports/arm/atomport.c @@ -33,7 +33,7 @@ /* * * - * Functions defined in atomport_s.asm + * Functions defined in atomport_s.S * */ typedef void * SYSCONTEXT ; diff --git a/ports/cortex_m3/Makefile b/ports/cortex_m/Makefile similarity index 67% rename from ports/cortex_m3/Makefile rename to ports/cortex_m/Makefile index fcf84e7..c389b0d 100644 --- a/ports/cortex_m3/Makefile +++ b/ports/cortex_m/Makefile @@ -1,5 +1,5 @@ -ATOMTHREADS_PORT = ..... /libraries/atomthreads/ports/cortex_m3 -ATOMTHREADS_KERNEL = ..... /libraries/atomthreads/kernel +ATOMTHREADS_PORT = $(ATOMTHREADS)/ports/cortex_m +ATOMTHREADS_KERNEL = $(ATOMTHREADS)/kernel INCLUDES := $(INCLUDES) \ -I$(ATOMTHREADS_KERNEL) \ @@ -14,6 +14,6 @@ SRCS := $(SRCS) \ $(ATOMTHREADS_PORT)/atomport.c ASMS := $(ASMS) \ - $(ATOMTHREADS_PORT)/atomport_arm.asm - - + $(ATOMTHREADS_PORT)/atomport_s.S + + diff --git a/ports/cortex_m3/README b/ports/cortex_m/README similarity index 100% rename from ports/cortex_m3/README rename to ports/cortex_m/README diff --git a/ports/cortex_m/atomport-tests.h b/ports/cortex_m/atomport-tests.h new file mode 100644 index 0000000..cfb909a --- /dev/null +++ b/ports/cortex_m/atomport-tests.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2012, Natie van Rooyen. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. No personal names or organizations' names associated with the + * Atomthreads project may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __ATOMPORT_TEST_H__ +#define __ATOMPORT_TEST_H__ + +/* Include Atomthreads kernel API */ +#include "atom.h" + +extern void dbg_format_msg (char *format, ...) ; + + +#define TEST_THREAD_STACK_SIZE 1024 +#define ATOMLOG dbg_format_msg +#define _STR(x) x + + + + +/* API for starting each test */ +extern uint32_t test_start (void); + + +#endif /* __ATOMPORT_TEST_H__ */ diff --git a/ports/cortex_m3/atomport.c b/ports/cortex_m/atomport.c similarity index 95% rename from ports/cortex_m3/atomport.c rename to ports/cortex_m/atomport.c index 1f659c3..6d6fc6a 100644 --- a/ports/cortex_m3/atomport.c +++ b/ports/cortex_m/atomport.c @@ -33,15 +33,14 @@ /* * * - * Functions defined in atomport_arm.asm + * Functions defined in atomport_s.S * */ +typedef void * SYSCONTEXT ; + extern void contextInit (void) ; extern void contextSwitch (SYSCONTEXT* save_context, SYSCONTEXT* new_context) ; extern void contextStart (SYSCONTEXT* context) ; -extern uint32_t contextCreate (SYSCONTEXT* context, uint32_t stack_top, uint32_t entry) ; -extern uint32_t contextEnterCritical (void) ; -extern void contextExitCritical (uint32_t posture) ; extern void contextEnableInterrupts (void) ; /** diff --git a/ports/cortex_m3/atomport.h b/ports/cortex_m/atomport.h similarity index 90% rename from ports/cortex_m3/atomport.h rename to ports/cortex_m/atomport.h index 2a6cf50..39bd0c0 100644 --- a/ports/cortex_m3/atomport.h +++ b/ports/cortex_m/atomport.h @@ -30,10 +30,9 @@ #ifndef __ATOM_PORT_H__ #define __ATOM_PORT_H__ -#include "arch/context.h" #include "types.h" -#define SYSTEM_TICKS_PER_SEC 1000 +#define SYSTEM_TICKS_PER_SEC 100 /** @@ -43,12 +42,18 @@ */ #define POINTER void * +/* * + * + * Functions defined in atomport_arm.asm + * + */ +extern uint32_t contextEnterCritical (void) ; +extern void contextExitCritical (uint32_t posture) ; + /* Critical region protection */ - #define CRITICAL_STORE uint32_t __atom_critical #define CRITICAL_START() __atom_critical = contextEnterCritical() #define CRITICAL_END() contextExitCritical(__atom_critical) - #endif /* __ATOM_PORT_H__ */ diff --git a/ports/cortex_m3/atomport_private.h b/ports/cortex_m/atomport_private.h similarity index 100% rename from ports/cortex_m3/atomport_private.h rename to ports/cortex_m/atomport_private.h diff --git a/ports/cortex_m/atomport_s.S b/ports/cortex_m/atomport_s.S new file mode 100644 index 0000000..46c3138 --- /dev/null +++ b/ports/cortex_m/atomport_s.S @@ -0,0 +1,220 @@ +/* + Copyright (c) 2012, Natie van Rooyen. All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + 1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + 3. No personal names or organizations' names associated with the + Atomthreads project may be used to endorse or promote products + derived from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS + "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. +*/ + + +.global contextInit +.global contextSwitch +.global contextStart +.global contextEnableInterrupts +.global contextEnterCritical +.global contextExitCritical +.global pendSV_Handler +.global tick_Handler + +.global archTickHandler + + + +/**/ +.equ NVIC_INT_CTRL, 0xE000ED04 // Interrupt control state register +.equ NVIC_PENDSVSET, 0x10000000 // Value to trigger PendSV exception +.equ NVIC_PR_12_15_ADDR, 0xE000ED20 // System Handlers 12-15 Priority Register Address +.equ NVIC_PENDS_VPRIORITY, 0x00FF0000 // PendSV priority is minimal (0xFF) + +.syntax unified +.text +.thumb + +/** + * \b contextInit + * + * Architecture-specific one time initialization. + * + * Configures PendSV priority to lowest. + * + * @return None + */ +contextInit: + LDR r1, =NVIC_PR_12_15_ADDR // Load the System 12-15 Priority Register + LDR r0, [r1] + ORR r0, r0, #NVIC_PENDS_VPRIORITY // set PRI_14 (PendSV) to 0xFF - minimal + STR r0, [r1] + + BX lr + +/** + * \b contextSwitch + * + * Architecture-specific context switch routine. + * + * Note that interrupts are always locked out when this routine is + * called. For cooperative switches, the scheduler will have entered + * a critical region. For preemptions (called from an ISR), the + * interrupts will have disabled in the tick_Handler. + * + * @param[in] [r0] -> Address to save old stack pointer + * @param[in] [r1] -> Address where new stack pointer is stored + * + * @return None + */ +contextSwitch: + LDR r2, =context_new_stack_ptr + STR r1, [r2] + + LDR r2, =context_save_stack_ptr + LDR r1, [r2] + CMP r1, #0 // if contextSwitch is going to be called again before pend_sv + IT EQ + STREQ r0, [r2] + + LDR R0, =NVIC_INT_CTRL // Trigger the PendSV exception (causes context switch) + LDR R1, =NVIC_PENDSVSET + STR R1, [R0] + + BX lr + +/** + * \b contextStart + * + * Architecture-specific context start routine. + * + * @param[in] [r0] -> Address where stack pointer is stored + * + * @return Does not return + */ +contextStart: + LDR r1, =context_new_stack_ptr + STR r0, [r1] + LDR r1, =context_save_stack_ptr + MOV r0, #0 + STR r0, [r1] + LDR r0, =NVIC_INT_CTRL // Trigger the PendSV exception (causes context switch) + LDR r1, =NVIC_PENDSVSET + STR r1, [r0] + + BX lr + +/** + * \b contextEnableInterrupts + * + * Enables interrupts on the processor + * + * @return None + */ +contextEnableInterrupts: + CPSIE i + BX lr + + +/** + * \b contextExitCritical + * + * Exit critical section (restores interrupt posture) + * + * @param[in] r0 Interrupt Posture + * + * @return None + */ +contextExitCritical: + MSR PRIMASK, r0 + BX lr + + +/** + * \b contextEnterCritical + * + * Enter critical section (disables interrupts) + * + * @return Current interrupt posture + */ +contextEnterCritical: + MRS r0, PRIMASK + CPSID i + BX lr + +/** + * \b PendSV_Handler + * + * CortexM3 PendSV_Handler. Switch context to a new stack. + * + * @return None + */ +pendSV_Handler: + CPSID i // Disable core int + + LDR r1, =context_save_stack_ptr + LDR r0, [r1] // Load old (current) stack pointer address + + LDR r2, =context_new_stack_ptr + LDR r2, [r2] // Load new stack pointer address + CMP r0, r2 + BEQ pendsv_handler_exit + + CMP r0, #0 + BEQ pendsv_handler_new_stack + // Save context + MRS r3, PSP // Get PSP point + STMDB r3!, {R4-R11} // Store r4-r11 + STR r3, [r0] // Save old stack pointer + MOV r3, #0 + STR r3, [r1] + +pendsv_handler_new_stack: + // Restore context + LDR r2, [r2] // Load new stack pointer + LDMIA r2!, {r4-r11} // Restore context + MSR PSP, r2 // Mov new stack point to PSP + +pendsv_handler_exit: + CPSIE i // Enable core int + + ORR lr, lr, #0x04 // Ensure exception return uses process stack + BX lr // Exit interrupt + + +/** + * \b Tick_Handler + * + * System timer tick interrupt handler. + * + * @return None + */ +tick_Handler: + PUSH {r4-r11, lr} + cpsid I // Disable core int + BL archTickHandler + cpsie I // Enable core int + POP {r4-r11, pc} + + +/**/ +context_new_stack_ptr: .long 0x00000000 +context_save_stack_ptr: .long 0x00000000 + + diff --git a/ports/cortex_m3/types.h b/ports/cortex_m/types.h similarity index 100% rename from ports/cortex_m3/types.h rename to ports/cortex_m/types.h diff --git a/ports/cortex_m3/atomport_arm.asm b/ports/cortex_m3/atomport_arm.asm deleted file mode 100644 index 2195db6..0000000 --- a/ports/cortex_m3/atomport_arm.asm +++ /dev/null @@ -1,217 +0,0 @@ -; -; Copyright (c) 2012, Natie van Rooyen. All rights reserved. -; -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions -; are met: -; -; 1. Redistributions of source code must retain the above copyright -; notice, this list of conditions and the following disclaimer. -; 2. Redistributions in binary form must reproduce the above copyright -; notice, this list of conditions and the following disclaimer in the -; documentation and/or other materials provided with the distribution. -; 3. No personal names or organizations' names associated with the -; Atomthreads project may be used to endorse or promote products -; derived from this software without specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS -; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED -; TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -; PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE -; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -; POSSIBILITY OF SUCH DAMAGE. -; - - - PRESERVE8 {TRUE} - AREA UTILS, CODE, READONLY -;-- - EXPORT contextInit - EXPORT contextSwitch - EXPORT contextStart - EXPORT contextEnableInterrupts - EXPORT contextEnterCritical - EXPORT contextExitCritical - EXPORT pendSV_Handler - EXPORT tick_Handler - - EXTERN archTickHandler - -;-- -NVIC_INT_CTRL EQU 0xE000ED04 ; Interrupt control state register -NVIC_PENDSVSET EQU 0x10000000 ; Value to trigger PendSV exception -NVIC_PR_12_15_ADDR EQU 0xE000ED20 ; System Handlers 12-15 Priority Register Address -NVIC_PENDS_VPRIORITY EQU 0x00FF0000 ; PendSV priority is minimal (0xFF) - -;-- -; \b contextInit -; -; Architecture-specific one time initialization. -; -; Configures PendSV priority to lowest. -; -; @return None -; -contextInit - LDR r1, =NVIC_PR_12_15_ADDR ;-- Load the System 12-15 Priority Register - LDR r0, [r1] - ORR r0, r0, #NVIC_PENDS_VPRIORITY ;-- set PRI_14 (PendSV) to 0xFF - minimal - STR r0, [r1] - - BX lr - -;-- -; \b contextSwitch -; -; Architecture-specific context switch routine. -; -; Note that interrupts are always locked out when this routine is -; called. For cooperative switches, the scheduler will have entered -; a critical region. For preemptions (called from an ISR), the -; interrupts will have disabled in the tick_Handler. -; -; @param[in] [r0] -> Address to save old stack pointer -; @param[in] [r1] -> Address where new stack pointer is stored -; -; @return None -; -contextSwitch - LDR r2, =context_new_stack_ptr - STR r1, [r2] - - LDR r2, =context_save_stack_ptr - LDR r1, [r2] - TEQ r1, #0 ; if contextSwitch is going to be called again before pend_sv - STREQ r0, [r2] - - LDR R0, =NVIC_INT_CTRL ; Trigger the PendSV exception (causes context switch) - LDR R1, =NVIC_PENDSVSET - STR R1, [R0] - - BX lr - -;-- -; \b contextStart -; -; Architecture-specific context start routine. -; -; @param[in] [r0] -> Address where stack pointer is stored -; -; @return Does not return -; -contextStart - LDR r1, =context_new_stack_ptr - STR r0, [r1] - LDR r1, =context_save_stack_ptr - MOV r0, #0 - STR r0, [r1] - LDR r0, =NVIC_INT_CTRL ; Trigger the PendSV exception (causes context switch) - LDR r1, =NVIC_PENDSVSET - STR r1, [r0] - - BX lr - -;-- -; \b contextEnableInterrupts -; -; Enables interrupts on the processor -; -; @return None -; -contextEnableInterrupts - CPSIE i - BX lr - - -;-- -; \b contextExitCritical -; -; Exit critical section (restores interrupt posture) -; -; @param[in] r0 Interrupt Posture -; -; @return None -; -contextExitCritical - MSR PRIMASK, r0 - BX lr - - -;-- -; \b contextEnterCritical -; -; Enter critical section (disables interrupts) -; -; @return Current interrupt posture -; -contextEnterCritical - MRS r0, PRIMASK - CPSID i - BX lr - -;-- -; \b PendSV_Handler -; -; CortexM3 PendSV_Handler. Switch context to a new stack. -; -; @return None -; -pendSV_Handler - CPSID i ; Disable core int - - LDR r1, =context_save_stack_ptr - LDR r0, [r1] ; Load old (current) stack pointer address - - LDR r2, =context_new_stack_ptr - LDR r2, [r2] ; Load new stack pointer address - TEQ r0, r2 - BEQ pendsv_handler_exit - - TEQ r0, #0 - BEQ pendsv_handler_new_stack - ; Save context - MRS r3, PSP ; Get PSP point - STMDB r3!, {R4-R11} ; Store r4-r11 - STR r3, [r0] ; Save old stack pointer - MOV r3, #0 - STR r3, [r1] - -pendsv_handler_new_stack - ; Restore context - LDR r2, [r2] ; Load new stack pointer - LDMIA r2!, {r4-r11} ; Restore context - MSR PSP, r2 ; Mov new stack point to PSP - -pendsv_handler_exit - CPSIE i ; Enable core int - - ORR lr, lr, #0x04 ; Ensure exception return uses process stack - BX lr ; Exit interrupt - - -;-- -; \b Tick_Handler -; -; System timer tick interrupt handler. -; -; @return None -; -tick_Handler - PUSH {r4-r11, lr} - cpsid I ; Disable core int - BL archTickHandler - cpsie I ; Enable core int - POP {r4-r11, pc} - - -;-- -context_new_stack_ptr DCD 0x00000000 -context_save_stack_ptr DCD 0x00000000 - -;-- - END From daa748332b55f4f590a2edb421b6a0121582f1ba Mon Sep 17 00:00:00 2001 From: Natie van Rooyen Date: Mon, 24 Sep 2012 23:16:03 +0200 Subject: [PATCH 16/28] cortex m port qemu_lm3s platform --- platforms/qemu_integratorcp/Makefile | 2 +- platforms/qemu_integratorcp/system.ld | 4 - platforms/qemu_lm3s/Makefile | 96 ++++++++++++ platforms/qemu_lm3s/main.c | 89 +++++++++++ platforms/qemu_lm3s/modules.c | 161 +++++++++++++++++++ platforms/qemu_lm3s/modules.h | 213 +++++++++++++++++++++++++ platforms/qemu_lm3s/startup.S | 215 ++++++++++++++++++++++++++ platforms/qemu_lm3s/system.ld | 100 ++++++++++++ ports/arm/types.h | 10 -- ports/cortex_m/atomport.c | 53 ++++--- ports/cortex_m/atomport.h | 1 + ports/cortex_m/atomport_s.S | 64 +++++++- ports/cortex_m/types.h | 9 ++ 13 files changed, 973 insertions(+), 44 deletions(-) create mode 100644 platforms/qemu_lm3s/Makefile create mode 100644 platforms/qemu_lm3s/main.c create mode 100644 platforms/qemu_lm3s/modules.c create mode 100644 platforms/qemu_lm3s/modules.h create mode 100644 platforms/qemu_lm3s/startup.S create mode 100644 platforms/qemu_lm3s/system.ld diff --git a/platforms/qemu_integratorcp/Makefile b/platforms/qemu_integratorcp/Makefile index 551529f..e88e47d 100644 --- a/platforms/qemu_integratorcp/Makefile +++ b/platforms/qemu_integratorcp/Makefile @@ -15,7 +15,7 @@ LN = arm-none-eabi-gcc AS = arm-none-eabi-gcc CFLAGS := $(CFLAGS) -Wall -g -c -mcpu=arm926ej-s -ffreestanding -AFLAGS := $(CFLAGS) -Wall -g -c -mcpu=arm926ej-s -ffreestanding +AFLAGS := $(AFLAGS) -Wall -g -c -mcpu=arm926ej-s -ffreestanding LFLAGS := $(LFLAGS) -Wall -mcpu=arm926ej-s -Wl,-Map=system.map,--verbose -Tsystem.ld CDEFS := $(CDEFS) -DATOMTHREADS_TEST='"$(TEST_NAME)"' diff --git a/platforms/qemu_integratorcp/system.ld b/platforms/qemu_integratorcp/system.ld index 4d4fc2c..40682db 100644 --- a/platforms/qemu_integratorcp/system.ld +++ b/platforms/qemu_integratorcp/system.ld @@ -84,10 +84,6 @@ SECTIONS } >sram - /*DISCARD : - { - *(.eh_*) - }*/ } _end = .; diff --git a/platforms/qemu_lm3s/Makefile b/platforms/qemu_lm3s/Makefile new file mode 100644 index 0000000..5b86d1f --- /dev/null +++ b/platforms/qemu_lm3s/Makefile @@ -0,0 +1,96 @@ +ifeq ($(TARGET_NAME),) +TARGET_NAME=boot +endif +ifeq ($(ATOMTHREADS),) +ATOMTHREADS = $(shell pwd)/../../ +endif +ifeq ($(TEST_NAME),) +TEST_NAME = mutex1 +endif + + + +CC = arm-none-eabi-gcc +LN = arm-none-eabi-gcc +AS = arm-none-eabi-gcc + +CFLAGS := $(CFLAGS) -Wall -g -c -mcpu=cortex-m3 -mthumb -mthumb-interwork -ffreestanding +AFLAGS := $(AFLAGS) -Wall -g -c -mcpu=cortex-m3 -mthumb -mthumb-interwork -ffreestanding +LFLAGS := $(LFLAGS) -Wall -mcpu=cortex-m3 -mthumb -Wl,-Map=system.map -Tsystem.ld + +CDEFS := $(CDEFS) -DATOMTHREADS_TEST='"$(TEST_NAME)"' -DPLATFORM_QEMU_LM3S_HACK +ADEFS := $(ADEFS) -D__thumb2__ -DARM_RDI_MONITOR -DPLATFORM_QEMU_LM3S_HACK + +LLIBS := $(LLIBS) + + +SRCS := $(SRCS) \ + modules.c \ + main.c \ + $(ATOMTHREADS)/tests/$(TEST_NAME).c \ + +# startup_c.c \ + +ASMS := $(ASMS) \ + startup.S \ + +INCLUDES := $(INCLUDES) \ + -I$(ATOMTHREADS) + +include $(ATOMTHREADS)/ports/cortex_m/Makefile + +OBJS = $(SRCS:.c=.o) $(ASMS:.S=.o) + +include ../rules.mk + + +run_test: clean all + echo "START TEST $(TEST_NAME)" + qemu-system-arm -M lm3s6965evb -kernel boot.elf -semihosting >> atomthreads_test.out + +all_tests: + echo "Starting atomthreads test suite" > atomthreads_test.out + make run_test "TEST_NAME=mutex1" + make run_test "TEST_NAME=mutex2" + make run_test "TEST_NAME=mutex3" + make run_test "TEST_NAME=mutex5" + make run_test "TEST_NAME=mutex6" + make run_test "TEST_NAME=mutex7" + make run_test "TEST_NAME=mutex8" + make run_test "TEST_NAME=mutex9" + make run_test "TEST_NAME=kern1" + make run_test "TEST_NAME=kern2" + make run_test "TEST_NAME=kern3" + make run_test "TEST_NAME=kern4" + make run_test "TEST_NAME=timer1" + make run_test "TEST_NAME=timer2" + make run_test "TEST_NAME=timer3" + make run_test "TEST_NAME=timer5" + make run_test "TEST_NAME=timer6" + make run_test "TEST_NAME=timer7" + make run_test "TEST_NAME=queue1" + make run_test "TEST_NAME=queue2" + make run_test "TEST_NAME=queue3" + make run_test "TEST_NAME=queue4" + make run_test "TEST_NAME=queue5" + make run_test "TEST_NAME=queue6" + make run_test "TEST_NAME=queue7" + make run_test "TEST_NAME=queue8" + make run_test "TEST_NAME=queue9" + make run_test "TEST_NAME=sem1" + make run_test "TEST_NAME=sem2" + make run_test "TEST_NAME=sem3" + make run_test "TEST_NAME=sem5" + make run_test "TEST_NAME=sem6" + make run_test "TEST_NAME=sem7" + make run_test "TEST_NAME=sem8" + make run_test "TEST_NAME=sem9" + +all_fail: + make run_test "TEST_NAME=mutex4" + make run_test "TEST_NAME=sem4" + + +run_last: + qemu-system-arm -M lm3s6965evb -kernel boot.elf -monitor stdio -semihosting + diff --git a/platforms/qemu_lm3s/main.c b/platforms/qemu_lm3s/main.c new file mode 100644 index 0000000..3f68d6c --- /dev/null +++ b/platforms/qemu_lm3s/main.c @@ -0,0 +1,89 @@ +/* + * Copyright (c) 2012, Natie van Rooyen. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. No personal names or organizations' names associated with the + * Atomthreads project may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include "modules.h" +#include "atom.h" +#include "tests/atomtests.h" + +#ifndef ATOMTHREADS_TEST +#define ATOMTHREADS_TEST "kern1" +#endif + +#define TEST_STACK_BYTE_SIZE 1024 +#define IDLE_STACK_BYTE_SIZE 512 + +static unsigned char test_stack[TEST_STACK_BYTE_SIZE] ; +static unsigned char idle_stack[IDLE_STACK_BYTE_SIZE] ; +ATOM_TCB test_tcb ; + + + +/** + * \b test_thread + * + * Function calling the test function of the Atomthreads test suite. + * + */ +void +test_thread (uint32_t param) +{ + uint32_t failures ; + CRITICAL_STORE ; + + failures = test_start () ; + + atomTimerDelay (10) ; + CRITICAL_START() ; + printf ("%s %s\r\n", ATOMTHREADS_TEST, failures ? "FAIL" : "PASS") ; + exit (failures) ; + CRITICAL_END() ; +} + + +/** + * \b main + * + * Initialize atomthreads and start a test_thread to run the Atomthreads test suite. + * + */ +int +main (void) +{ + int i = 0 ; + + uint32_t failures ; + printf ("atomthreads starting %s... \r\n", ATOMTHREADS_TEST) ; + + atomOSInit(&idle_stack[IDLE_STACK_BYTE_SIZE - sizeof(unsigned int)], IDLE_STACK_BYTE_SIZE - sizeof(unsigned int)) ; + atomThreadCreate ((ATOM_TCB *)&test_tcb, TEST_THREAD_PRIO, test_thread, 0, &test_stack[(TEST_STACK_BYTE_SIZE) - sizeof(unsigned int)], TEST_STACK_BYTE_SIZE - sizeof(unsigned int)); + atomOSStart() ; + + return 0 ; +} + diff --git a/platforms/qemu_lm3s/modules.c b/platforms/qemu_lm3s/modules.c new file mode 100644 index 0000000..fc7cbc8 --- /dev/null +++ b/platforms/qemu_lm3s/modules.c @@ -0,0 +1,161 @@ +/* + * Copyright (c) 2012, Natie van Rooyen. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. No personal names or organizations' names associated with the + * Atomthreads project may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include "modules.h" +#include +#include +#include "atomport_private.h" +#include "atom.h" +#include "atomport.h" +#include "types.h" + +SYSTICK_T* const board_systick = (SYSTICK_T*) BOARD_BASE_ADDRESS_SYSTICK ; +NVIC_T* const board_nvic = (NVIC_T*) BOARD_BASE_ADDRESS_NVIC ; +SCB_T * const board_scb = (SCB_T*) BOARD_BASE_ADDRESS_SCB ; +GPTM_TIMER_T * const board_gptm0 = (GPTM_TIMER_T*) BOARD_BASE_ADDRESS_GPTIMER0 ; + + +/** + * \b dbg_format_msg + * + * Same as printf. + * + */ +void +dbg_format_msg (char *format, ...) +{ + va_list args; + static char msg[256] ; + CRITICAL_STORE ; + + va_start (args, format) ; + CRITICAL_START() ; + vsnprintf ((char*)msg, 256, (char*)format, args) ; + printf (msg) ; + CRITICAL_END() ; + +} + + +/** + * \b low_level_init + * + * Initializes the PIC and start the system timer tick intrerupt. + * + */ +int +low_level_init (void) +{ + contextInit () ; + + //board_systick->STRELOAD = 0x010000 ; + //board_systick->STCTRL = NVIC_STCTRL_CLK | + // NVIC_STCTRL_INTEN | + // NVIC_STCTRL_ENABLE ; + + board_gptm0->CTL &= ~GPTM_TIMER_CTL_TAEN ; + board_gptm0->CFG = 0 ; + board_gptm0->TAMR = GPTM_TIMER_TMR_TMR_PERIODIC ; + board_gptm0->TAILR = 0x10000 ; + board_gptm0->IMR |= GPTM_TIMER_INT_TATOIM ; + board_gptm0->CTL |= GPTM_TIMER_CTL_TAEN ; + + // board_nvic->ISER[0] = 0x80000 ; + + return 0 ; +} + + +/** + * \b __context_preempt_handler + * + * System timer tic interupt handler. + * + */ +void +__context_tick_handler (void) +{ + + if (1) { + atomIntEnter(); + + /* Call the OS system tick handler */ + atomTimerTick(); + + board_gptm0->ICR |= GPTM_TIMER_INT_TATOIM ; + + /* Call the interrupt exit routine */ + atomIntExit(TRUE); + + } + +} + +void +dbg_hard_fault_handler_c (unsigned int * hardfault_args) +{ + unsigned int stacked_r0; + unsigned int stacked_r1; + unsigned int stacked_r2; + unsigned int stacked_r3; + unsigned int stacked_r12; + unsigned int stacked_lr; + unsigned int stacked_pc; + unsigned int stacked_psr; + + stacked_r0 = ((unsigned long) hardfault_args[0]); + stacked_r1 = ((unsigned long) hardfault_args[1]); + stacked_r2 = ((unsigned long) hardfault_args[2]); + stacked_r3 = ((unsigned long) hardfault_args[3]); + + stacked_r12 = ((unsigned long) hardfault_args[4]); + stacked_lr = ((unsigned long) hardfault_args[5]); + stacked_pc = ((unsigned long) hardfault_args[6]); + stacked_psr = ((unsigned long) hardfault_args[7]); + + printf ("\r\n\r\n[Hard fault handler - all numbers in hex]\r\n"); + printf ("SP = 0x%x\r\n", hardfault_args); + printf ("R0 = 0x%x\r\n", stacked_r0); + printf ("R1 = 0x%x\r\n", stacked_r1); + printf ("R2 = 0x%x\r\n", stacked_r2); + printf ("R3 = 0x%x\r\n", stacked_r3); + printf ("R12 = 0x%x\r\n", stacked_r12); + printf ("LR [R14] = 0x%x subroutine call return address\r\n", stacked_lr); + printf ("PC [R15] = 0x%x program counter\r\n", stacked_pc); + printf ("PSR = 0x%x\r\n", stacked_psr); + //printf ("BFAR = 0x%x\r\n", (*((volatile unsigned long *)(0xE000ED38)))); + //printf ("CFSR = 0x%x\r\n", (*((volatile unsigned long *)(0xE000ED28)))); + //printf ("HFSR = 0x%x\r\n", (*((volatile unsigned long *)(0xE000ED2C)))); + //printf ("DFSR = 0x%x\r\n", (*((volatile unsigned long *)(0xE000ED30)))); + //printf ("AFSR = 0x%x\r\n", (*((volatile unsigned long *)(0xE000ED3C)))); + // printf ("SCB_SHCSR = %x\n", SCB->SHCSR); + + while (1); + +} + diff --git a/platforms/qemu_lm3s/modules.h b/platforms/qemu_lm3s/modules.h new file mode 100644 index 0000000..3a341e0 --- /dev/null +++ b/platforms/qemu_lm3s/modules.h @@ -0,0 +1,213 @@ +/* + * Copyright (c) 2012, Natie van Rooyen. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. No personal names or organizations' names associated with the + * Atomthreads project may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __MODULES_H__ +#define __MODULES_H__ + +/* + * Module definitions to use with the Stellaris LM3S6965 Microcontroller + */ + +#include "atomport.h" + + +typedef volatile unsigned int REG_DWORD ; +typedef volatile unsigned short REG_WORD ; +typedef volatile unsigned char REG_BYTE ; + + +// ***************************************************************************** +// The Stellaris General-Purpose Timer Module (GPTM) +// ***************************************************************************** +typedef struct GPTM_TIMER_S { + + // offset read/write reset Description + REG_DWORD CFG ; // 0x000 R/W 0x00000000 GPTM Configuration 345 + REG_DWORD TAMR ; // 0x004 R/W 0x00000000 GPTM TimerA Mode 346 + REG_DWORD TBMR ; // 0x008 R/W 0x00000000 GPTM TimerB Mode 348 + REG_DWORD CTL ; // 0x00C R/W 0x00000000 GPTM Control 350 + REG_DWORD Reserved[2] ; // 0x010 + REG_DWORD IMR ; // 0x018 R/W 0x00000000 GPTM Interrupt Mask 353 + REG_DWORD RIS ; // 0x01C RO 0x00000000 GPTM Raw Interrupt Status 355 + REG_DWORD MIS ; // 0x020 RO 0x00000000 GPTM Masked Interrupt Status 356 + REG_DWORD ICR ; // 0x024 W1C 0x00000000 GPTM Interrupt Clear 357 + REG_DWORD TAILR ; // 0x028 R/W 0xFFFFFFFF GPTM TimerA Interval Load 359 + REG_DWORD TBILR ; // 0x02C R/W 0x0000FFFF GPTM TimerB Interval Load 360 + REG_DWORD TAMATCHR ; // 0x030 R/W 0xFFFFFFFF GPTM TimerA Match 361 + REG_DWORD TBMATCHR ; // 0x034 R/W 0x0000FFFF GPTM TimerB Match 362 + REG_DWORD TAPR ; // 0x038 R/W 0x00000000 GPTM TimerA Prescale 363 + REG_DWORD TBPR ; // 0x03C R/W 0x00000000 GPTM TimerB Prescale 364 + REG_DWORD TAPMR ; // 0x040 R/W 0x00000000 GPTM TimerA Prescale Match 365 + REG_DWORD TBPMR ; // 0x044 R/W 0x00000000 GPTM TimerB Prescale Match 366 + REG_DWORD TAR ; // 0x048 RO 0xFFFFFFFF GPTM TimerA 367 + REG_DWORD TBR ; // 0x04C RO 0x0000FFFF GPTM TimerB 368 + +} GPTM_TIMER_T, *PGPTM_TIMER_T ; + +// -------- GPTM_TIMER_CFG : (CFG Offset: 0x00) This register configures the global operation of the GPTM module -------- +#define GPTM_TIMER_CFG_MASK ((unsigned int)0x07 << 0) // + #define GPTM_TIMER_CFG_32BIT ((unsigned int)0x00 << 0) // 32-bit timer configuration + #define GPTM_TIMER_CFG_32BIT_RT ((unsigned int)0x01 << 0) // 32-bit real-time clock (RTC) counter configuration +// -------- GPTM_TIMER_TAMR : (TAMR Offset: 0x04) This register configures the GPTM based on the configuration selected in the GPTMCFG register -------- +// -------- GPTM_TIMER_TBMR : (TBMR Offset: 0x08) This register configures the GPTM based on the configuration selected in the GPTMCFG register -------- +#define GPTM_TIMER_TMR_TAMS ((unsigned int)0x01 << 3) // GPTM TimerA Alternate Mode Select. 0 Capture mode is enabled. 1 PWM mode is enabled +#define GPTM_TIMER_TMR_TCMR ((unsigned int)0x01 << 2) // GPTM TimerA Capture Mode. 0 Edge-Count mode. 1 Edge-Time mode. +#define GPTM_TIMER_TMR_TMR_ONE_SHOT ((unsigned int)0x01 << 0) // One-Shot Timer mode +#define GPTM_TIMER_TMR_TMR_PERIODIC ((unsigned int)0x02 << 0) // Periodic Timer mode +#define GPTM_TIMER_TMR_TMR_CAPTURE ((unsigned int)0x03 << 0) // Capture mode +// -------- GPTM_TIMER_CTL : (CTL Offset: 0x0C) This register is used alongside the GPTMCFG and GMTMTnMR registers to fine-tune the timer configuration -------- +#define GPTM_TIMER_CTL_TBPWML ((unsigned int)0x01 << 14) // GPTM TimerB PWM Output Level. 0 Output is unaffected. 1 Output is inverted. +#define GPTM_TIMER_CTL_TBOTE ((unsigned int)0x01 << 13) // GPTM TimerB Output Trigger Enable. 0 The output TimerB ADC trigger is disabled. 1 The output TimerB ADC trigger is enabled. +#define GPTM_TIMER_CTL_TBEVENT_MASK ((unsigned int)0x03 << 10) // GPTM TimerB Event Mode + #define GPTM_TIMER_CTL_TBEVENT_PE ((unsigned int)0x00 << 10) // Positive edge + #define GPTM_TIMER_CTL_TBEVENT_NE ((unsigned int)0x01 << 10) // Negative edge + #define GPTM_TIMER_CTL_TBEVENT_NE ((unsigned int)0x03 << 10) // Both edges +#define GPTM_TIMER_CTL_TBSTALL ((unsigned int)0x01 << 9) // GPTM Timer B Stall Enable. 0 Timer B continues counting while the processor is halted by the debugger +#define GPTM_TIMER_CTL_TBEN ((unsigned int)0x01 << 8) // GPTM TimerB Enable +// -------- +#define GPTM_TIMER_CTL_TAPWML ((unsigned int)0x01 << 6) // GPTM TimerA PWM Output Level. 0 Output is unaffected. 1 Output is inverted. +#define GPTM_TIMER_CTL_TAOTE ((unsigned int)0x01 << 5) // GPTM TimerA Output Trigger Enable. 0 The output TimerB ADC trigger is disabled. 1 The output TimerB ADC trigger is enabled. +#define GPTM_TIMER_CTL_RTCEN ((unsigned int)0x01 << 4) // GPTM RTC Enable +#define GPTM_TIMER_CTL_TAEVENT_MASK ((unsigned int)0x03 << 2) // GPTM TimerA Event Mode + #define GPTM_TIMER_CTL_TAEVENT_PE ((unsigned int)0x00 << 2) // Positive edge + #define GPTM_TIMER_CTL_TAEVENT_NE ((unsigned int)0x01 << 2) // Negative edge + #define GPTM_TIMER_CTL_TAEVENT_NE ((unsigned int)0x03 << 2) // Both edges +#define GPTM_TIMER_CTL_TASTALL ((unsigned int)0x01 << 1) // GPTM Timer A Stall Enable. 0 Timer B continues counting while the processor is halted by the debugger +#define GPTM_TIMER_CTL_TAEN ((unsigned int)0x01 << 0) // GPTM TimerA Enable +// -------- GPTM_TIMER_IMR : (IMR Offset: 0x18) This register allows software to enable/disable GPTM controller-level interrupts. -------- +// -------- GPTM_TIMER_RIS : (RIS Offset: 0x1C) This register shows the state of the GPTM's internal interrupt signal. -------- +// -------- GPTM_TIMER_MIS : (MIS Offset: 0x20) This register show the state of the GPTM's controller-level interrupt. -------- +// -------- GPTM_TIMER_ICR : (ICR Offset: 0x24) This register is used to clear the status bits in the GPTMRIS and GPTMMIS registers. -------- +#define GPTM_TIMER_INT_CBEIM ((unsigned int)0x01 << 10) // GPTM CaptureB Event Interrupt Mask +#define GPTM_TIMER_INT_CBMIM ((unsigned int)0x01 << 9) // GPTM CaptureB Match Interrupt Mask +#define GPTM_TIMER_INT_TBTOIM ((unsigned int)0x01 << 8) // GPTM TimerB Time-Out Interrupt Mask +// -------- +#define GPTM_TIMER_INT_RTCIM ((unsigned int)0x01 << 3) // GPTM RTC Interrupt Mask +#define GPTM_TIMER_INT_CAEIM ((unsigned int)0x01 << 2) // GPTM CaptureA Event Interrupt Mask +#define GPTM_TIMER_INT_CAMIM ((unsigned int)0x01 << 1) // GPTM CaptureA Match Interrupt Mask +#define GPTM_TIMER_INT_TATOIM ((unsigned int)0x01 << 0) // GPTM TimerA Time-Out Interrupt Mask + + + +// ***************************************************************************** +// Cortex M System Timer (SysTick) +// ***************************************************************************** +typedef struct SYSTICK_S { + + REG_DWORD Res0[1] ; // 0xE000E000 + REG_DWORD ICT ; // 0xE000E004 + REG_DWORD Res1[2] ; // 0xE000E008 + REG_DWORD STCTRL ; // 0xE000E010 + REG_DWORD STRELOAD ; // 0xE000E014 + REG_DWORD STCURRENT; // 0xE000E018 + REG_DWORD STCALIB ; // 0xE000E01C + REG_DWORD Res2[56] ; // 0xE000E020 + +} SYSTICK_T, *PSYSTICK_T ; + +// -------- SYSTICK_STCTRL : (STCTRL Offset: 0xE000E010) SysTick Control and Status Register -------- +#define SYSTICK_STCTRL_COUNT ((unsigned int)0x1 << 16) // 0 - The SysTick timer has not counted to 0 since the last time this bit was read. +#define SYSTICK_STCTRL_CLK ((unsigned int)0x1 << 2) // 1 - System clock +#define SYSTICK_STCTRL_INTEN ((unsigned int)0x1 << 1) // 1 - An interrupt is generated to the NVIC when SysTick counts to 0. +#define SYSTICK_STCTRL_ENABLE ((unsigned int)0x1 << 1) // Enables SysTick to operate in a multi-shot way. +// -------- SYSTICK_STRELOAD : (STRELOAD Offset: 0xE000E014) Reload Value -------- +#define SYSTICK_STRELOAD_MASK ((unsigned int)0xFFFFFF << 0) // IRQ mask +// -------- SYSTICK_STCURRENT : (STCURRENT Offset: 0xE000E018) SysTick Current Value Register -------- + + +// ***************************************************************************** +// Cortex M Nested Vectored Interrupt Controller +// ***************************************************************************** +typedef struct NVIC_S { + + REG_DWORD ISER[2] ; // 0xE000E100 + REG_DWORD Res3[30] ; // 0xE000E120 + REG_DWORD ICER[2] ; // 0xE000E180 + REG_DWORD Res4[30] ; // 0xE000E1A0 + REG_DWORD ISPR[2] ; // 0xE000E200 + REG_DWORD Res5[30] ; // 0xE000E220 + REG_DWORD ICPR[2] ; // 0xE000E280 + REG_DWORD Res6[30] ; // 0xE000E2A0 + REG_DWORD IABR[2] ; // 0xE000E300 + REG_DWORD Res7[64] ; // 0xE000E320 + REG_DWORD IPR[2] ; // 0xE000E400 + // REG_DWORD Res7[515] ; // 0xE000E4F4 + +} NVIC_T, *PNVIC_T ; + +#define NVIC_EXCEPTION_RESET 1 +#define NVIC_EXCEPTION_NMI 2 +#define NVIC_EXCEPTION_HARD_FAULT 3 +#define NVIC_EXCEPTION_MEM_MANAGEMENT 4 +#define NVIC_EXCEPTION_BUS_FAULT 5 +#define NVIC_EXCEPTION_USAGE_FAULT 6 +#define NVIC_EXCEPTION_SVCALL 11 +#define NVIC_EXCEPTION_DEBUG_MON 12 +#define NVIC_EXCEPTION_PEND_SV 14 +#define NVIC_EXCEPTION_SYS_TICK 15 + +// ***************************************************************************** +// System Control Block (SCB) Registers +// ***************************************************************************** +typedef struct SCB_S { + + REG_DWORD CPUID ; // 0xE000ED00 + REG_DWORD ICSR ; // 0xE000ED04 + REG_DWORD VTOR ; // 0xE000ED08 + REG_DWORD AIRCR ; // 0xE000ED0C + REG_DWORD SCR ; // 0xE000ED10 + REG_DWORD CCR ; // 0xE000ED14 + + REG_DWORD SYS_PRIO[3] ; // 0xE000ED18 + REG_DWORD SYSHNDCTRL ; // 0xE000ED24 + //REG_DWORD FAULTSTAT ; // 0xE000ED28 + //REG_DWORD HFAULTSTAT ; // 0xE000ED2C + +} SCB_T, *PSCB_T ; + + + +#define BOARD_BASE_ADDRESS_SYSTICK 0xE000E000 +#define BOARD_BASE_ADDRESS_NVIC 0xE000E100 +#define BOARD_BASE_ADDRESS_SCB 0xE000ED00 +#define BOARD_BASE_ADDRESS_GPTIMER0 0x40030000 + +extern SYSTICK_T* const board_systick ; +extern NVIC_T* const board_nvic ; +extern SCB_T* const board_scb ; +extern GPTM_TIMER_T* const board_gptm0 ; + + + +extern int low_level_init (void) ; +extern void dbg_format_msg (char *format, ...) ; +extern void dbg_hard_fault_handler_c (unsigned int * hardfault_args) ; + +#define DBG_MESSAGE(fmt_str) { dbg_format_msg fmt_str ; } + +#endif /* __MODULES_H__ */ diff --git a/platforms/qemu_lm3s/startup.S b/platforms/qemu_lm3s/startup.S new file mode 100644 index 0000000..da5823b --- /dev/null +++ b/platforms/qemu_lm3s/startup.S @@ -0,0 +1,215 @@ +/* + Copyright (c) 2012, Natie van Rooyen. All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + 1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + 3. No personal names or organizations' names associated with the + Atomthreads project may be used to endorse or promote products + derived from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS + "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. +*/ + +/* lm3s Startup Script */ + +.section .vectors,"x",%progbits +.syntax unified +.thumb + + +.global __interrupt_vector_table +.global tick_Handler +.global pendSV_Handler +.global dbg_hard_fault_handler_c + +/** + * \b __interrupt_vector_table + * + */ +__interrupt_vector_table: +.long __c_stack_top__ +.long reset_Handler +.long fault_Handler +.long fault_Handler +.long fault_Handler +.long fault_Handler +.long fault_Handler +.long 0 +.long 0 +.long 0 +.long 0 +.long sys_Handler +.long sys_Handler +.long 0 +.long pendSV_Handler +.long sys_Handler + +/* External interrupts */ +.long default_Handler // GPIO Port A +.long default_Handler // GPIO Port B +.long default_Handler // GPIO Port C +.long default_Handler // GPIO Port D +.long default_Handler // GPIO Port E +.long default_Handler // UART0 Rx and Tx +.long default_Handler // UART1 Rx and Tx +.long default_Handler // SSI0 Rx and Tx +.long default_Handler // I2C0 Master and Slave +.long default_Handler // PWM Fault +.long default_Handler // PWM Generator 0 +.long default_Handler // PWM Generator 1 +.long default_Handler // PWM Generator 2 +.long default_Handler // Quadrature Encoder 0 +.long default_Handler // ADC Sequence 0 +.long default_Handler // ADC Sequence 1 +.long default_Handler // ADC Sequence 2 +.long default_Handler // ADC Sequence 3 +.long default_Handler // Watchdog timer +.long tick_Handler // Timer 0 subtimer A +.long default_Handler // Timer 0 subtimer B +.long default_Handler // Timer 1 subtimer A +.long default_Handler // Timer 1 subtimer B +.long default_Handler // Timer 2 subtimer A +.long default_Handler // Timer 2 subtimer B +.long default_Handler // Analog Comparator 0 +.long default_Handler // Analog Comparator 1 +.long default_Handler // Analog Comparator 2 +.long default_Handler // System Control (PLL, OSC, BO) +.long default_Handler // FLASH Control +.long default_Handler // GPIO Port F +.long default_Handler // GPIO Port G +.long default_Handler // GPIO Port H +.long default_Handler // UART2 Rx and Tx +.long default_Handler // SSI1 Rx and Tx +.long default_Handler // Timer 3 subtimer A +.long default_Handler // Timer 3 subtimer B +.long default_Handler // I2C1 Master and Slave +.long default_Handler // Quadrature Encoder 1 +.long default_Handler // CAN0 +.long default_Handler // CAN1 +.long default_Handler // CAN2 +.long default_Handler // Ethernet +.long default_Handler // Hibernate + +/** + * \b sys_Handler + * + * @return None + */ +.thumb_func +sys_Handler: + B . + +/** + * \b default_Handler + * + * @return None + */ +.thumb_func +default_Handler: + B . + +/** + * \b fault_Handler + * + * @return None + */ + .thumb_func +fault_Handler: + tst lr, #4 + ite eq + mrseq r0, MSP + mrsne r0, PSP + b dbg_hard_fault_handler_c + + +.section .startup,"x",%progbits +.syntax unified +.thumb + +.global reset_Handler +.global initialise_monitor_handles +.global low_level_init +.global main + + +/** + * \b reset_Handler + * + * + * + * @return None + */ +.thumb_func +reset_Handler: + +/* + * Initialize the data and bss sections. + */ +init_data: + ldr r0, .ETEXT + ldr r1, .DATA + ldr r2, .EDATA + sub r2, r2, r1 + cmp r2, #0 + beq init_bss +init_data_copy: + ldrb r4, [r0], #1 + strb r4, [r1], #1 + subs r2, r2, #1 + bne init_data_copy +init_bss: + mov r0, #0 + ldr r1, = .BSS + ldr r2, = .EBSS + sub r2, r2, r1 + cmp r2, #0 + beq init_done +init_bss_zero: + strb r0, [r1], #1 + subs r2, r2, #1 + bne init_bss_zero +init_done: + + /* + * The following call initializes the function pointers for stdio etc. + * These are used by the semihosting interface. + * + * This function is implemented in newlib. + */ + bl initialise_monitor_handles + + /* + * Platform specific low level initialization. + */ + bl low_level_init + + /* + * Call the application's entry point. + */ + bl main + + +.BSS: .long _bss +.EBSS: .long _ebss +.ETEXT: .long _etext +.DATA: .long _data +.EDATA: .long _edata + +.end \ No newline at end of file diff --git a/platforms/qemu_lm3s/system.ld b/platforms/qemu_lm3s/system.ld new file mode 100644 index 0000000..de5ffc8 --- /dev/null +++ b/platforms/qemu_lm3s/system.ld @@ -0,0 +1,100 @@ +/****************************************************************************** + * + * hello_codered.ld - Code Red linker configuration file for hello. + * + * Copyright (c) 2006-2012 Texas Instruments Incorporated. All rights reserved. + * Software License Agreement + * + * Texas Instruments (TI) is supplying this software for use solely and + * exclusively on TI's microcontroller products. The software is owned by + * TI and/or its suppliers, and is protected under applicable copyright + * laws. You may not combine this software with "viral" open-source + * software in order to form a larger program. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. + * NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT + * NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY + * CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL + * DAMAGES, FOR ANY REASON WHATSOEVER. + * + * This is part of revision 9107 of the EK-LM3S6965 Firmware Package. + * + *****************************************************************************/ + +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000 + SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00010000 +} + +SECTIONS +{ + _vRamTop = 0x20000000 + 0x00010000; + .text : + { + *(.vectors) + *(.startup) + *(.text*) + *(.rodata*) + } > FLASH + + /* + * for exception handling/unwind - some Newlib functions (in common with + * C++ and STDC++) use this. + */ + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + _etext = .; + + .data : AT (__exidx_end) + { + _data = .; + *(vtable) + *(.data*) + _edata = .; + } > SRAM + + /* zero initialized data */ + + .bss : + { + __bss_start__ = . ; + _bss = .; + *(.bss*) + *(COMMON) + __bss_end__ = . ; + _ebss = .; + } > SRAM + + /* Where we put the heap with cr_clib */ + + .cr_heap : + { + end = .; + _pvHeapStart = .; + } > SRAM + + /* + * Note: (ref: M0000066) + * Moving the stack down by 16 is to work around a GDB bug. + * This space can be reclaimed for Production Builds. + */ + + _vStackTop = _vRamTop - 16; + .stack _vStackTop : + { + __c_stack_top__ = . ; + } +} diff --git a/ports/arm/types.h b/ports/arm/types.h index d383d84..c07e295 100644 --- a/ports/arm/types.h +++ b/ports/arm/types.h @@ -40,16 +40,6 @@ typedef int int32_t ; typedef short int16_t ; typedef char int8_t ; -// typedef volatile unsigned int REG_DWORD ;// Hardware register definition - -#define UWORD64 unsigned long long -#define UWORD32 unsigned int -#define UWORD16 unsigned short -#define UWORD8 unsigned char -#define WORD32 int -#define WORD16 short -#define WORD8 char - #ifndef OFFSETOF #define OFFSETOF(TYPE, MEMBER) ((int) &((TYPE *)0)->MEMBER) #endif diff --git a/ports/cortex_m/atomport.c b/ports/cortex_m/atomport.c index 6d6fc6a..d41359d 100644 --- a/ports/cortex_m/atomport.c +++ b/ports/cortex_m/atomport.c @@ -38,7 +38,6 @@ */ typedef void * SYSCONTEXT ; -extern void contextInit (void) ; extern void contextSwitch (SYSCONTEXT* save_context, SYSCONTEXT* new_context) ; extern void contextStart (SYSCONTEXT* context) ; extern void contextEnableInterrupts (void) ; @@ -93,7 +92,11 @@ archThreadContextInit (ATOM_TCB *tcb_ptr, void *stack_top, void (*entry_point)(u *stack_ptr = 0x01000000L; //-- xPSR stack_ptr--; - *stack_ptr = ((uint32_t)thread_shell) | 1; //-- Entry Point (1 for THUMB mode) +#ifndef PLATFORM_QEMU_LM3S_HACK + *stack_ptr = ((uint32_t)thread_shell) | 1 ; //-- Entry Point (1 for THUMB mode) +#else + *stack_ptr = ((uint32_t)thread_shell) & ~1 ; //-- Entry Point (1 for THUMB mode) +#endif stack_ptr--; *stack_ptr = ((uint32_t)/*exit*/0) | 1; //-- R14 (LR) (1 for THUMB mode) stack_ptr--; @@ -159,20 +162,20 @@ archContextSwitch (ATOM_TCB * p_sp_old, ATOM_TCB * p_sp_new) * System timer tick interrupt handler. * */ -void -archTickHandler (void) -{ - atomIntEnter(); - - /* Call the OS system tick handler */ - atomTimerTick(); - - /* ack the interrupt if needed */ - /* ... */ - - /* Call the interrupt exit routine */ - atomIntExit(TRUE); -} +//void +//archTickHandler (void) +//{ +// atomIntEnter(); +// +// /* Call the OS system tick handler */ +// atomTimerTick(); +// +// /* ack the interrupt if needed */ +// /* ... */ +// +// /* Call the interrupt exit routine */ +// atomIntExit(TRUE); +//} /** * \b archTickInit @@ -180,14 +183,14 @@ archTickHandler (void) * System timer initialization. * */ -void -archTickInit (void) -{ - /* Initialize NVIC PendSV */ - contextInit () ; - - /* Initializa Timer Hardware */ - /* ... */ -} +//void +//archTickInit (void) +//{ +// /* Initialize NVIC PendSV */ +// contextInit () ; +// +// /* Initializa Timer Hardware */ +// /* ... */ +//} diff --git a/ports/cortex_m/atomport.h b/ports/cortex_m/atomport.h index 39bd0c0..f7ac10d 100644 --- a/ports/cortex_m/atomport.h +++ b/ports/cortex_m/atomport.h @@ -47,6 +47,7 @@ * Functions defined in atomport_arm.asm * */ +extern void contextInit (void) ; extern uint32_t contextEnterCritical (void) ; extern void contextExitCritical (uint32_t posture) ; diff --git a/ports/cortex_m/atomport_s.S b/ports/cortex_m/atomport_s.S index 46c3138..0ae97c4 100644 --- a/ports/cortex_m/atomport_s.S +++ b/ports/cortex_m/atomport_s.S @@ -37,20 +37,28 @@ .global pendSV_Handler .global tick_Handler -.global archTickHandler +.global __context_tick_handler /**/ .equ NVIC_INT_CTRL, 0xE000ED04 // Interrupt control state register .equ NVIC_PENDSVSET, 0x10000000 // Value to trigger PendSV exception .equ NVIC_PR_12_15_ADDR, 0xE000ED20 // System Handlers 12-15 Priority Register Address -.equ NVIC_PENDS_VPRIORITY, 0x00FF0000 // PendSV priority is minimal (0xFF) +.equ NVIC_PENDS_VPRIORITY, 0x00F00000 // PendSV priority is minimal (0xFF -- 0x00FF0000) + +#ifdef PLATFORM_QEMU_LM3S_HACK +.equ NVIC_ISER, 0xE000E100 +.equ NVIC_ICER, 0xE000E180 +.equ NVIC_I_TIMER0, 0x80000 +#endif + .syntax unified .text .thumb + /** * \b contextInit * @@ -128,7 +136,13 @@ contextStart: * @return None */ contextEnableInterrupts: +#ifndef PLATFORM_QEMU_LM3S_HACK CPSIE i +#else + LDR r1, =NVIC_ISER + LDR r0, =NVIC_I_TIMER0 + STR r0, [r1] +#endif BX lr @@ -142,10 +156,14 @@ contextEnableInterrupts: * @return None */ contextExitCritical: +#ifndef PLATFORM_QEMU_LM3S_HACK MSR PRIMASK, r0 +#else + LDR r1, =NVIC_ISER + STR r0, [r1] +#endif BX lr - /** * \b contextEnterCritical * @@ -154,8 +172,15 @@ contextExitCritical: * @return Current interrupt posture */ contextEnterCritical: +#ifndef PLATFORM_QEMU_LM3S_HACK MRS r0, PRIMASK CPSID i +#else + LDR r1, =NVIC_ISER + LDR r0, [r1] + LDR r1, =NVIC_ICER + STR r0, [r1] +#endif BX lr /** @@ -165,8 +190,15 @@ contextEnterCritical: * * @return None */ + .thumb_func pendSV_Handler: +#ifndef PLATFORM_QEMU_LM3S_HACK CPSID i // Disable core int +#else + LDR r0, =NVIC_ICER + LDR r1, =NVIC_I_TIMER0 + STR r1, [r0] +#endif LDR r1, =context_save_stack_ptr LDR r0, [r1] // Load old (current) stack pointer address @@ -192,7 +224,13 @@ pendsv_handler_new_stack: MSR PSP, r2 // Mov new stack point to PSP pendsv_handler_exit: +#ifndef PLATFORM_QEMU_LM3S_HACK CPSIE i // Enable core int +#else + LDR r0, =NVIC_ISER + LDR r1, =NVIC_I_TIMER0 + STR r1, [r0] +#endif ORR lr, lr, #0x04 // Ensure exception return uses process stack BX lr // Exit interrupt @@ -205,15 +243,33 @@ pendsv_handler_exit: * * @return None */ + .thumb_func tick_Handler: PUSH {r4-r11, lr} + +#ifndef PLATFORM_QEMU_LM3S_HACK cpsid I // Disable core int - BL archTickHandler +#else + LDR r0, =NVIC_ICER + LDR r1, =NVIC_I_TIMER0 + STR r1, [r0] +#endif + + BL __context_tick_handler + +#ifndef PLATFORM_QEMU_LM3S_HACK cpsie I // Enable core int +#else + LDR r0, =NVIC_ISER + LDR r1, =NVIC_I_TIMER0 + STR r1, [r0] +#endif + POP {r4-r11, pc} /**/ +.data context_new_stack_ptr: .long 0x00000000 context_save_stack_ptr: .long 0x00000000 diff --git a/ports/cortex_m/types.h b/ports/cortex_m/types.h index 82317f7..c07e295 100644 --- a/ports/cortex_m/types.h +++ b/ports/cortex_m/types.h @@ -40,5 +40,14 @@ typedef int int32_t ; typedef short int16_t ; typedef char int8_t ; +#ifndef OFFSETOF +#define OFFSETOF(TYPE, MEMBER) ((int) &((TYPE *)0)->MEMBER) +#endif + +#ifndef INLINE +#define INLINE __inline +#endif + + #endif /* __TYPES_H__ */ From 650f5e2ac36ada49d9c44ff8b1b2a220fcc557ff Mon Sep 17 00:00:00 2001 From: Natie van Rooyen Date: Thu, 27 Sep 2012 10:49:09 +0200 Subject: [PATCH 17/28] Cortex M port added qemu_lm3s platform added --- platforms/qemu_integratorcp/README | 12 +++++++++ platforms/qemu_integratorcp/modules.h | 18 ++++++++----- platforms/qemu_integratorcp/startup.s | 6 ++--- platforms/qemu_lm3s/Makefile | 3 +-- platforms/qemu_lm3s/README | 33 +++++++++++++++++++++++ platforms/qemu_lm3s/main.c | 3 +-- platforms/qemu_lm3s/modules.c | 15 +++++------ platforms/qemu_lm3s/modules.h | 10 +++---- platforms/qemu_lm3s/startup.S | 16 +++++------ platforms/qemu_lm3s/system.ld | 32 ++-------------------- ports/arm/README | 29 +++----------------- ports/arm/atomport.c | 39 --------------------------- ports/arm/atomport.h | 1 + ports/arm/atomport_private.h | 5 ++-- ports/arm/atomport_s.S | 3 +-- ports/cortex_m/README | 24 ++++------------- ports/cortex_m/atomport.c | 38 -------------------------- ports/cortex_m/atomport_private.h | 7 +++-- ports/cortex_m/atomport_s.S | 16 +++++------ 19 files changed, 109 insertions(+), 201 deletions(-) create mode 100644 platforms/qemu_integratorcp/README create mode 100644 platforms/qemu_lm3s/README diff --git a/platforms/qemu_integratorcp/README b/platforms/qemu_integratorcp/README new file mode 100644 index 0000000..5deb509 --- /dev/null +++ b/platforms/qemu_integratorcp/README @@ -0,0 +1,12 @@ +--------------------------------------------------------------------------- + +Library: Atomthreads QEMU ARM Integrator/CP (ARM926EJ-S) Platform. +Author: Natie van Rooyen +License: BSD Revised + +--------------------------------------------------------------------------- + +QEMU ARM Integrator/CP (ARM926EJ-S) Platform + +The "qemu_integratorcp" platform contains sources for building a sample +Atomthreads application for the ARM Integrator/CP (ARM926EJ-S) platform. \ No newline at end of file diff --git a/platforms/qemu_integratorcp/modules.h b/platforms/qemu_integratorcp/modules.h index 38aa37f..58a48ed 100644 --- a/platforms/qemu_integratorcp/modules.h +++ b/platforms/qemu_integratorcp/modules.h @@ -29,14 +29,14 @@ #ifndef __MODULES_H__ #define __MODULES_H__ +/* + * Module definitions to use with the ARM Integrator/CP (ARM926EJ-S) + */ + #include "atomport.h" -extern void dbg_format_msg (char *format, ...) ; -#define DBG_MESSAGE(fmt_str) { dbg_format_msg fmt_str ; } - - -typedef volatile unsigned int REG_DWORD ;// Hardware register definition +typedef volatile unsigned int REG_DWORD ; typedef volatile unsigned short REG_WORD ; typedef volatile unsigned char REG_BYTE ; @@ -110,7 +110,7 @@ typedef struct ICP_PIC_S { - +/* module definitions */ #define BOARD_BASE_ADDRESS_TIMER_0 0x13000000 #define BOARD_BASE_ADDRESS_PIC 0x14000000 @@ -118,7 +118,11 @@ extern ICP_TIMER_T* const board_timer_0 ; extern ICP_PIC_T* const board_pic ; - +/* Function prototypes */ extern int low_level_init (void) ; +extern void dbg_format_msg (char *format, ...) ; + +#define DBG_MESSAGE(fmt_str) { dbg_format_msg fmt_str ; } + #endif /* __MODULES_H__ */ diff --git a/platforms/qemu_integratorcp/startup.s b/platforms/qemu_integratorcp/startup.s index dc4a167..0c3675d 100644 --- a/platforms/qemu_integratorcp/startup.s +++ b/platforms/qemu_integratorcp/startup.s @@ -1,9 +1,9 @@ .section .vectors, "x" .global __interrupt_vector_table -.global __irq_stack_top__ -.global __fiq_stack_top__ -.global __svc_stack_top__ +.extern __irq_stack_top__ +.extern __fiq_stack_top__ +.extern __svc_stack_top__ .global bsp_ints_enable .global bsp_ints_disable diff --git a/platforms/qemu_lm3s/Makefile b/platforms/qemu_lm3s/Makefile index 5b86d1f..c8568ad 100644 --- a/platforms/qemu_lm3s/Makefile +++ b/platforms/qemu_lm3s/Makefile @@ -5,7 +5,7 @@ ifeq ($(ATOMTHREADS),) ATOMTHREADS = $(shell pwd)/../../ endif ifeq ($(TEST_NAME),) -TEST_NAME = mutex1 +TEST_NAME = kern1 endif @@ -29,7 +29,6 @@ SRCS := $(SRCS) \ main.c \ $(ATOMTHREADS)/tests/$(TEST_NAME).c \ -# startup_c.c \ ASMS := $(ASMS) \ startup.S \ diff --git a/platforms/qemu_lm3s/README b/platforms/qemu_lm3s/README new file mode 100644 index 0000000..6e340d1 --- /dev/null +++ b/platforms/qemu_lm3s/README @@ -0,0 +1,33 @@ +--------------------------------------------------------------------------- + +Library: Atomthreads QEMU Stellaris LM3S6965 Platform. +Author: Natie van Rooyen +License: BSD Revised + +--------------------------------------------------------------------------- + +QEMU Stellaris LM3S6965 Platform + +The "qemu_lm3s" platform contains sources for building a sample Atomthreads +application for the Stellaris LM3S6965 platform. + + +ISSUES: + +There seems to be several problems for the QEMU Cortex M3 processor. The +platform and port contains specific hacks to make it work on the QEMU 1.2.0 +release it was tested on. Also see the latest patches for QEMU. + +Fixes implemented for the QEMU 1.2.0 release: + +1. Install the patch http://patchwork.ozlabs.org/patch/180315/ +2. Use the PLATFORM_QEMU_LM3S_HACK define in the Makefile: + + - Disabling interrupts on the processor does not work (verified). + - Disabling interrupts of the Cortex M Sys Tick Interrupt does not + work (verified). + - NVIC Interrupt priorities not implemented correctly (not verified). + +Because of the problems with the Sys Tick Interrupt the The Stellaris +General-Purpose Timer Module (GPTM) was used to generate the system timer +tick. diff --git a/platforms/qemu_lm3s/main.c b/platforms/qemu_lm3s/main.c index 3f68d6c..9aa5bdc 100644 --- a/platforms/qemu_lm3s/main.c +++ b/platforms/qemu_lm3s/main.c @@ -43,7 +43,6 @@ static unsigned char idle_stack[IDLE_STACK_BYTE_SIZE] ; ATOM_TCB test_tcb ; - /** * \b test_thread * @@ -78,7 +77,7 @@ main (void) int i = 0 ; uint32_t failures ; - printf ("atomthreads starting %s... \r\n", ATOMTHREADS_TEST) ; + printf ("Atomthreads starting %s... \r\n", ATOMTHREADS_TEST) ; atomOSInit(&idle_stack[IDLE_STACK_BYTE_SIZE - sizeof(unsigned int)], IDLE_STACK_BYTE_SIZE - sizeof(unsigned int)) ; atomThreadCreate ((ATOM_TCB *)&test_tcb, TEST_THREAD_PRIO, test_thread, 0, &test_stack[(TEST_STACK_BYTE_SIZE) - sizeof(unsigned int)], TEST_STACK_BYTE_SIZE - sizeof(unsigned int)); diff --git a/platforms/qemu_lm3s/modules.c b/platforms/qemu_lm3s/modules.c index fc7cbc8..c375e4e 100644 --- a/platforms/qemu_lm3s/modules.c +++ b/platforms/qemu_lm3s/modules.c @@ -101,18 +101,15 @@ void __context_tick_handler (void) { - if (1) { - atomIntEnter(); + atomIntEnter(); - /* Call the OS system tick handler */ - atomTimerTick(); + /* Call the OS system tick handler */ + atomTimerTick(); - board_gptm0->ICR |= GPTM_TIMER_INT_TATOIM ; + board_gptm0->ICR |= GPTM_TIMER_INT_TATOIM ; - /* Call the interrupt exit routine */ - atomIntExit(TRUE); - - } + /* Call the interrupt exit routine */ + atomIntExit(TRUE); } diff --git a/platforms/qemu_lm3s/modules.h b/platforms/qemu_lm3s/modules.h index 3a341e0..8d3bb4c 100644 --- a/platforms/qemu_lm3s/modules.h +++ b/platforms/qemu_lm3s/modules.h @@ -86,7 +86,7 @@ typedef struct GPTM_TIMER_S { #define GPTM_TIMER_CTL_TBEVENT_MASK ((unsigned int)0x03 << 10) // GPTM TimerB Event Mode #define GPTM_TIMER_CTL_TBEVENT_PE ((unsigned int)0x00 << 10) // Positive edge #define GPTM_TIMER_CTL_TBEVENT_NE ((unsigned int)0x01 << 10) // Negative edge - #define GPTM_TIMER_CTL_TBEVENT_NE ((unsigned int)0x03 << 10) // Both edges + #define GPTM_TIMER_CTL_TBEVENT ((unsigned int)0x03 << 10) // Both edges #define GPTM_TIMER_CTL_TBSTALL ((unsigned int)0x01 << 9) // GPTM Timer B Stall Enable. 0 Timer B continues counting while the processor is halted by the debugger #define GPTM_TIMER_CTL_TBEN ((unsigned int)0x01 << 8) // GPTM TimerB Enable // -------- @@ -96,7 +96,7 @@ typedef struct GPTM_TIMER_S { #define GPTM_TIMER_CTL_TAEVENT_MASK ((unsigned int)0x03 << 2) // GPTM TimerA Event Mode #define GPTM_TIMER_CTL_TAEVENT_PE ((unsigned int)0x00 << 2) // Positive edge #define GPTM_TIMER_CTL_TAEVENT_NE ((unsigned int)0x01 << 2) // Negative edge - #define GPTM_TIMER_CTL_TAEVENT_NE ((unsigned int)0x03 << 2) // Both edges + #define GPTM_TIMER_CTL_TAEVENT ((unsigned int)0x03 << 2) // Both edges #define GPTM_TIMER_CTL_TASTALL ((unsigned int)0x01 << 1) // GPTM Timer A Stall Enable. 0 Timer B continues counting while the processor is halted by the debugger #define GPTM_TIMER_CTL_TAEN ((unsigned int)0x01 << 0) // GPTM TimerA Enable // -------- GPTM_TIMER_IMR : (IMR Offset: 0x18) This register allows software to enable/disable GPTM controller-level interrupts. -------- @@ -191,7 +191,7 @@ typedef struct SCB_S { } SCB_T, *PSCB_T ; - +/* module definitions */ #define BOARD_BASE_ADDRESS_SYSTICK 0xE000E000 #define BOARD_BASE_ADDRESS_NVIC 0xE000E100 #define BOARD_BASE_ADDRESS_SCB 0xE000ED00 @@ -203,11 +203,11 @@ extern SCB_T* const board_scb ; extern GPTM_TIMER_T* const board_gptm0 ; - +/* Function prototypes */ extern int low_level_init (void) ; extern void dbg_format_msg (char *format, ...) ; extern void dbg_hard_fault_handler_c (unsigned int * hardfault_args) ; -#define DBG_MESSAGE(fmt_str) { dbg_format_msg fmt_str ; } +#define DBG_MESSAGE(fmt_str) { dbg_format_msg fmt_str ; } #endif /* __MODULES_H__ */ diff --git a/platforms/qemu_lm3s/startup.S b/platforms/qemu_lm3s/startup.S index da5823b..f570fea 100644 --- a/platforms/qemu_lm3s/startup.S +++ b/platforms/qemu_lm3s/startup.S @@ -35,9 +35,9 @@ .global __interrupt_vector_table -.global tick_Handler -.global pendSV_Handler -.global dbg_hard_fault_handler_c +.extern archTickHandler +.extern archPendSVHandler +.extern dbg_hard_fault_handler_c /** * \b __interrupt_vector_table @@ -58,7 +58,7 @@ __interrupt_vector_table: .long sys_Handler .long sys_Handler .long 0 -.long pendSV_Handler +.long archPendSVHandler .long sys_Handler /* External interrupts */ @@ -81,7 +81,7 @@ __interrupt_vector_table: .long default_Handler // ADC Sequence 2 .long default_Handler // ADC Sequence 3 .long default_Handler // Watchdog timer -.long tick_Handler // Timer 0 subtimer A +.long archTickHandler // Timer 0 subtimer A .long default_Handler // Timer 0 subtimer B .long default_Handler // Timer 1 subtimer A .long default_Handler // Timer 1 subtimer B @@ -144,9 +144,9 @@ fault_Handler: .thumb .global reset_Handler -.global initialise_monitor_handles -.global low_level_init -.global main +.extern initialise_monitor_handles +.extern low_level_init +.extern main /** diff --git a/platforms/qemu_lm3s/system.ld b/platforms/qemu_lm3s/system.ld index de5ffc8..dd59b49 100644 --- a/platforms/qemu_lm3s/system.ld +++ b/platforms/qemu_lm3s/system.ld @@ -1,26 +1,4 @@ -/****************************************************************************** - * - * hello_codered.ld - Code Red linker configuration file for hello. - * - * Copyright (c) 2006-2012 Texas Instruments Incorporated. All rights reserved. - * Software License Agreement - * - * Texas Instruments (TI) is supplying this software for use solely and - * exclusively on TI's microcontroller products. The software is owned by - * TI and/or its suppliers, and is protected under applicable copyright - * laws. You may not combine this software with "viral" open-source - * software in order to form a larger program. - * - * THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. - * NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT - * NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY - * CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL - * DAMAGES, FOR ANY REASON WHATSOEVER. - * - * This is part of revision 9107 of the EK-LM3S6965 Firmware Package. - * - *****************************************************************************/ + MEMORY { @@ -33,7 +11,7 @@ SECTIONS _vRamTop = 0x20000000 + 0x00010000; .text : { - *(.vectors) + KEEP(*(.vectors)) *(.startup) *(.text*) *(.rodata*) @@ -86,12 +64,6 @@ SECTIONS _pvHeapStart = .; } > SRAM - /* - * Note: (ref: M0000066) - * Moving the stack down by 16 is to work around a GDB bug. - * This space can be reclaimed for Production Builds. - */ - _vStackTop = _vRamTop - 16; .stack _vStackTop : { diff --git a/ports/arm/README b/ports/arm/README index fae939d..8846ff5 100644 --- a/ports/arm/README +++ b/ports/arm/README @@ -6,33 +6,12 @@ License: BSD Revised --------------------------------------------------------------------------- -ARM ARMv7 PORT +ARM PORT This folder contains a port of the Atomthreads real time kernel for the -ARMv7 processor architecture. This port was only tested on a ARMv7 but -should work on other versions of the ARM processor as well. +ARM processor architecture. This port was tested on Cortex A9, Cortex A15 +and the ARM926EJ-S (QEMU). To Use: -1. From your platforms IRQ vector branch to the "__irq_context_handler()". - All interrupts from where calls to Atomthreads will be made should do - this. The "__irq_context_handler()" will call a platform specific - function called "__context_preempt_handler()" to dispatch the interrupt. - -2. Implement the function "__context_preempt_handler()" - from where your platforms interrupt controller will be serviced and the - interrupt will be dispatched to a specific interrupt service routine. In - the case of your platforms timer tick interrupt call the "archTickHandler()" - implemented in "atomport.c". - -3. Initialize your platforms timer tick hardware to generate an OS timer tick - interrupt. - -4. Add code to acknowledge your timer hardware's interrupt in the - function "archTickHandler()" implemented in "atomport.c". This must - be done here because "atomIntExit()" might switch the context. - -5. After your platforms c-runtime initialization has completed, start - Atomthreads from your runtime's "main()" function. - -6. Include the port's Makefile in your platform build flow. \ No newline at end of file +See the example project in the "platforms/qemu_integratorcp" directory. \ No newline at end of file diff --git a/ports/arm/atomport.c b/ports/arm/atomport.c index d6fc47b..8775004 100644 --- a/ports/arm/atomport.c +++ b/ports/arm/atomport.c @@ -38,7 +38,6 @@ */ typedef void * SYSCONTEXT ; -extern void contextInit (void) ; extern void contextSwitch (SYSCONTEXT* save_context, SYSCONTEXT* new_context) ; extern void contextStart (SYSCONTEXT* context) ; extern void contextEnableInterrupts (void) ; @@ -145,41 +144,3 @@ archContextSwitch (ATOM_TCB * p_sp_old, ATOM_TCB * p_sp_new) } -/** - * \b archTimerTickIrqHandler - * - * System timer tick interrupt handler. - * - */ -void -archTickHandler (void) -{ - atomIntEnter(); - - /* Call the OS system tick handler */ - atomTimerTick(); - - /* ack the interrupt if needed */ - /* ... */ - - /* Call the interrupt exit routine */ - atomIntExit(TRUE); -} - -/** - * \b archTickInit - * - * System timer initialization. - * - */ -void -archTickInit (void) -{ - /* Initialize NVIC PendSV */ - contextInit () ; - - /* Initializa Timer Hardware */ - /* ... */ -} - - diff --git a/ports/arm/atomport.h b/ports/arm/atomport.h index 39bd0c0..f7ac10d 100644 --- a/ports/arm/atomport.h +++ b/ports/arm/atomport.h @@ -47,6 +47,7 @@ * Functions defined in atomport_arm.asm * */ +extern void contextInit (void) ; extern uint32_t contextEnterCritical (void) ; extern void contextExitCritical (uint32_t posture) ; diff --git a/ports/arm/atomport_private.h b/ports/arm/atomport_private.h index 87a032f..a99c447 100644 --- a/ports/arm/atomport_private.h +++ b/ports/arm/atomport_private.h @@ -32,8 +32,9 @@ /* Function prototypes */ -extern void archTickHandler (void) ; -extern void archTickInit (void) ; extern void archIRQHandler (void) ; +/* required interface */ +extern void __context_preempt_handler (void) ; + #endif /* __ATOM_PORT_PRIVATE_H__ */ diff --git a/ports/arm/atomport_s.S b/ports/arm/atomport_s.S index 1227c52..d3a9ece 100644 --- a/ports/arm/atomport_s.S +++ b/ports/arm/atomport_s.S @@ -34,7 +34,6 @@ .global archIRQHandler - .global contextEnterCritical .global contextExitCritical .global contextEnableInterrupts @@ -44,7 +43,7 @@ .global contextInit -.global __context_preempt_handler +.extern __context_preempt_handler /**/ .equ USR_MODE, 0x10 diff --git a/ports/cortex_m/README b/ports/cortex_m/README index 6784187..83527b1 100644 --- a/ports/cortex_m/README +++ b/ports/cortex_m/README @@ -1,31 +1,17 @@ --------------------------------------------------------------------------- -Library: Atomthreads CortexM3 Port +Library: Atomthreads ARM Cortex M Port Author: Natie van Rooyen License: BSD Revised --------------------------------------------------------------------------- -ARM CortexM3 PORT +ARM Cortex M PORT This folder contains a port of the Atomthreads real time kernel for the -ARM CortexM3 processor architecture. +ARM CortexM type processor architecture. This port was tested on the +Cortex M3 and the Cortex M4. To Use: -1. Install the "pendSV_Handler" and "tick_Handler" implemented in the file - "atomport_arm.asm" in your platforms interrupt vectors. - -2. Complete the function "archTickInit()" implemented in "atomport.c" to - initialize your platforms timer tick interrupt. If you use the build in - SysTick of the CortexM3 you also have to add code here to start it. - -3. If required, add code to acknowledge your timer hardware's interrupt in - the function "archTickHandler()" also implemented in "atomport.c". - -4. During your platform initialization call the function "archTickInit()" - exported from "atomport_private.h" to initialize the CortexM3 - "PendSV_Handler". - -5. After your platforms c-runtime initialization has completed, start - Atomthreads from your runtime's "main()" function. \ No newline at end of file +See the example project in the "platforms/qemu_lm3s" directory. \ No newline at end of file diff --git a/ports/cortex_m/atomport.c b/ports/cortex_m/atomport.c index d41359d..019b05f 100644 --- a/ports/cortex_m/atomport.c +++ b/ports/cortex_m/atomport.c @@ -156,41 +156,3 @@ archContextSwitch (ATOM_TCB * p_sp_old, ATOM_TCB * p_sp_new) } -/** - * \b archTimerTickIrqHandler - * - * System timer tick interrupt handler. - * - */ -//void -//archTickHandler (void) -//{ -// atomIntEnter(); -// -// /* Call the OS system tick handler */ -// atomTimerTick(); -// -// /* ack the interrupt if needed */ -// /* ... */ -// -// /* Call the interrupt exit routine */ -// atomIntExit(TRUE); -//} - -/** - * \b archTickInit - * - * System timer initialization. - * - */ -//void -//archTickInit (void) -//{ -// /* Initialize NVIC PendSV */ -// contextInit () ; -// -// /* Initializa Timer Hardware */ -// /* ... */ -//} - - diff --git a/ports/cortex_m/atomport_private.h b/ports/cortex_m/atomport_private.h index 0f4a004..0bdf11c 100644 --- a/ports/cortex_m/atomport_private.h +++ b/ports/cortex_m/atomport_private.h @@ -32,7 +32,10 @@ /* Function prototypes */ -extern void archTickHandler (void) ; -extern void archTickInit (void) ; +extern void archPendSVHandler (void) ; +extern void archTickHandler (void) ; + +/* required interface */ +extern void __context_tick_handler (void) ; #endif /* __ATOM_PORT_PRIVATE_H__ */ diff --git a/ports/cortex_m/atomport_s.S b/ports/cortex_m/atomport_s.S index 0ae97c4..2e25d93 100644 --- a/ports/cortex_m/atomport_s.S +++ b/ports/cortex_m/atomport_s.S @@ -28,17 +28,17 @@ */ +.global archPendSVHandler +.global archTickHandler .global contextInit .global contextSwitch .global contextStart .global contextEnableInterrupts .global contextEnterCritical .global contextExitCritical -.global pendSV_Handler -.global tick_Handler -.global __context_tick_handler +.extern __context_tick_handler /**/ @@ -184,14 +184,14 @@ contextEnterCritical: BX lr /** - * \b PendSV_Handler + * \b archPendSVHandler * - * CortexM3 PendSV_Handler. Switch context to a new stack. + * CortexM3 archPendSVHandler. Switch context to a new stack. * * @return None */ .thumb_func -pendSV_Handler: +archPendSVHandler: #ifndef PLATFORM_QEMU_LM3S_HACK CPSID i // Disable core int #else @@ -237,14 +237,14 @@ pendsv_handler_exit: /** - * \b Tick_Handler + * \b archTickHandler * * System timer tick interrupt handler. * * @return None */ .thumb_func -tick_Handler: +archTickHandler: PUSH {r4-r11, lr} #ifndef PLATFORM_QEMU_LM3S_HACK From 4c669225c608eaacd468960c2ab5585b999385ec Mon Sep 17 00:00:00 2001 From: Natie van Rooyen Date: Thu, 27 Sep 2012 12:18:00 +0200 Subject: [PATCH 18/28] Updated for new stack alignment changes in atom.h. --- platforms/qemu_integratorcp/Makefile | 4 ++-- platforms/qemu_integratorcp/main.c | 4 ++-- platforms/qemu_lm3s/Makefile | 4 ++-- platforms/qemu_lm3s/main.c | 4 ++-- ports/arm/atomport.h | 24 +++++++++++++++++++----- ports/cortex_m/atomport.h | 25 +++++++++++++++++++++---- 6 files changed, 48 insertions(+), 17 deletions(-) diff --git a/platforms/qemu_integratorcp/Makefile b/platforms/qemu_integratorcp/Makefile index e88e47d..cc54f51 100644 --- a/platforms/qemu_integratorcp/Makefile +++ b/platforms/qemu_integratorcp/Makefile @@ -44,7 +44,7 @@ include ../rules.mk run_test: clean all echo "START TEST $(TEST_NAME)" - qemu-system-arm -M integratorcp -kernel boot.elf -semihosting | tee atomthreads_test.out + qemu-system-arm -M integratorcp -kernel boot.elf -semihosting >> atomthreads_test.out all_tests: echo "Starting atomthreads test suite" > atomthreads_test.out @@ -87,5 +87,5 @@ all_tests: make run_test "TEST_NAME=sem9" run_last: - qemu-system-arm -M integratorcp -kernel boot.elf -monitor stdio -semihosting + qemu-system-arm -M integratorcp -kernel boot.elf -semihosting diff --git a/platforms/qemu_integratorcp/main.c b/platforms/qemu_integratorcp/main.c index 3222170..aebdd3d 100644 --- a/platforms/qemu_integratorcp/main.c +++ b/platforms/qemu_integratorcp/main.c @@ -77,8 +77,8 @@ main (void) printf ("atomthreads starting %s... ", ATOMTHREADS_TEST) ; - atomOSInit(&idle_stack[IDLE_STACK_BYTE_SIZE - sizeof(unsigned int)], IDLE_STACK_BYTE_SIZE - sizeof(unsigned int)) ; - atomThreadCreate ((ATOM_TCB *)&test_tcb, TEST_THREAD_PRIO, test_thread, 0, &test_stack[(TEST_STACK_BYTE_SIZE) - sizeof(unsigned int)], TEST_STACK_BYTE_SIZE - sizeof(unsigned int)); + atomOSInit(&idle_stack[0], IDLE_STACK_BYTE_SIZE, TRUE) ; + atomThreadCreate ((ATOM_TCB *)&test_tcb, TEST_THREAD_PRIO, test_thread, 0, &test_stack[0], TEST_STACK_BYTE_SIZE, TRUE); atomOSStart() ; return 0 ; diff --git a/platforms/qemu_lm3s/Makefile b/platforms/qemu_lm3s/Makefile index c8568ad..dc9c117 100644 --- a/platforms/qemu_lm3s/Makefile +++ b/platforms/qemu_lm3s/Makefile @@ -85,11 +85,11 @@ all_tests: make run_test "TEST_NAME=sem8" make run_test "TEST_NAME=sem9" -all_fail: +fail_tests: make run_test "TEST_NAME=mutex4" make run_test "TEST_NAME=sem4" run_last: - qemu-system-arm -M lm3s6965evb -kernel boot.elf -monitor stdio -semihosting + qemu-system-arm -M lm3s6965evb -kernel boot.elf -semihosting diff --git a/platforms/qemu_lm3s/main.c b/platforms/qemu_lm3s/main.c index 9aa5bdc..725a642 100644 --- a/platforms/qemu_lm3s/main.c +++ b/platforms/qemu_lm3s/main.c @@ -79,8 +79,8 @@ main (void) uint32_t failures ; printf ("Atomthreads starting %s... \r\n", ATOMTHREADS_TEST) ; - atomOSInit(&idle_stack[IDLE_STACK_BYTE_SIZE - sizeof(unsigned int)], IDLE_STACK_BYTE_SIZE - sizeof(unsigned int)) ; - atomThreadCreate ((ATOM_TCB *)&test_tcb, TEST_THREAD_PRIO, test_thread, 0, &test_stack[(TEST_STACK_BYTE_SIZE) - sizeof(unsigned int)], TEST_STACK_BYTE_SIZE - sizeof(unsigned int)); + atomOSInit(&idle_stack[0], IDLE_STACK_BYTE_SIZE, TRUE) ; + atomThreadCreate ((ATOM_TCB *)&test_tcb, TEST_THREAD_PRIO, test_thread, 0, &test_stack[0], TEST_STACK_BYTE_SIZE, TRUE); atomOSStart() ; return 0 ; diff --git a/ports/arm/atomport.h b/ports/arm/atomport.h index f7ac10d..f07e75a 100644 --- a/ports/arm/atomport.h +++ b/ports/arm/atomport.h @@ -32,8 +32,17 @@ #include "types.h" -#define SYSTEM_TICKS_PER_SEC 100 +#define SYSTEM_TICKS_PER_SEC 100 +/** + * Definition of NULL. + * If stddef.h is available on the platform it is simplest to include it + * from this header, otherwise define below. + */ +#define NULL ((void *)(0)) + +/* Size of each stack entry / stack alignment size (e.g. 32 bits) */ +#define STACK_ALIGN_SIZE sizeof(unsigned int) /** * Architecture-specific types. @@ -47,12 +56,17 @@ * Functions defined in atomport_arm.asm * */ -extern void contextInit (void) ; -extern uint32_t contextEnterCritical (void) ; -extern void contextExitCritical (uint32_t posture) ; +extern void contextInit (void) ; +extern uint32_t contextEnterCritical (void) ; +extern void contextExitCritical (uint32_t posture) ; -/* Critical region protection */ +/** + * Critical region protection: this should disable interrupts + * to protect OS data structures during modification. It must + * allow nested calls, which means that interrupts should only + * be re-enabled when the outer CRITICAL_END() is reached. + */ #define CRITICAL_STORE uint32_t __atom_critical #define CRITICAL_START() __atom_critical = contextEnterCritical() #define CRITICAL_END() contextExitCritical(__atom_critical) diff --git a/ports/cortex_m/atomport.h b/ports/cortex_m/atomport.h index f7ac10d..1a4cfd9 100644 --- a/ports/cortex_m/atomport.h +++ b/ports/cortex_m/atomport.h @@ -32,7 +32,23 @@ #include "types.h" -#define SYSTEM_TICKS_PER_SEC 100 +#define SYSTEM_TICKS_PER_SEC 100 + +/** + * Definition of NULL. + * If stddef.h is available on the platform it is simplest to include it + * from this header, otherwise define below. + */ +#define NULL ((void *)(0)) + +/* Size of each stack entry / stack alignment size (e.g. 32 bits) */ +#define STACK_ALIGN_SIZE sizeof(unsigned int) + +/** + * Architecture-specific types. + * Most of these are available from types.h on this platform, which is + * included above. + */ /** @@ -47,9 +63,9 @@ * Functions defined in atomport_arm.asm * */ -extern void contextInit (void) ; -extern uint32_t contextEnterCritical (void) ; -extern void contextExitCritical (uint32_t posture) ; +extern void contextInit (void) ; +extern uint32_t contextEnterCritical (void) ; +extern void contextExitCritical (uint32_t posture) ; /* Critical region protection */ @@ -58,3 +74,4 @@ extern void contextExitCritical (uint32_t posture) ; #define CRITICAL_END() contextExitCritical(__atom_critical) #endif /* __ATOM_PORT_H__ */ + From 599549535062d7275e52a754d5632f896d0ae986 Mon Sep 17 00:00:00 2001 From: Natie van Rooyen Date: Thu, 27 Sep 2012 12:18:00 +0200 Subject: [PATCH 19/28] Updated for new stack alignment changes in atom.h. --- platforms/qemu_integratorcp/Makefile | 11 +++++++---- platforms/qemu_integratorcp/README | 4 +++- platforms/qemu_integratorcp/main.c | 4 ++-- platforms/qemu_lm3s/Makefile | 4 ++-- platforms/qemu_lm3s/README | 4 ++++ platforms/qemu_lm3s/main.c | 4 ++-- ports/arm/README | 4 ++-- ports/arm/atomport.h | 24 +++++++++++++++++++----- ports/cortex_m/atomport.h | 25 +++++++++++++++++++++---- 9 files changed, 62 insertions(+), 22 deletions(-) diff --git a/platforms/qemu_integratorcp/Makefile b/platforms/qemu_integratorcp/Makefile index e88e47d..efed519 100644 --- a/platforms/qemu_integratorcp/Makefile +++ b/platforms/qemu_integratorcp/Makefile @@ -44,7 +44,7 @@ include ../rules.mk run_test: clean all echo "START TEST $(TEST_NAME)" - qemu-system-arm -M integratorcp -kernel boot.elf -semihosting | tee atomthreads_test.out + qemu-system-arm -M integratorcp -kernel boot.elf -semihosting >> atomthreads_test.out all_tests: echo "Starting atomthreads test suite" > atomthreads_test.out @@ -60,7 +60,6 @@ all_tests: make run_test "TEST_NAME=kern1" make run_test "TEST_NAME=kern2" make run_test "TEST_NAME=kern3" - make run_test "TEST_NAME=kern4" make run_test "TEST_NAME=timer1" make run_test "TEST_NAME=timer2" make run_test "TEST_NAME=timer3" @@ -86,6 +85,10 @@ all_tests: make run_test "TEST_NAME=sem8" make run_test "TEST_NAME=sem9" -run_last: - qemu-system-arm -M integratorcp -kernel boot.elf -monitor stdio -semihosting +fail_tests: + make run_test "TEST_NAME=kern4" + + +run_last: + qemu-system-arm -M integratorcp -kernel boot.elf -semihosting diff --git a/platforms/qemu_integratorcp/README b/platforms/qemu_integratorcp/README index 5deb509..0177f81 100644 --- a/platforms/qemu_integratorcp/README +++ b/platforms/qemu_integratorcp/README @@ -9,4 +9,6 @@ License: BSD Revised QEMU ARM Integrator/CP (ARM926EJ-S) Platform The "qemu_integratorcp" platform contains sources for building a sample -Atomthreads application for the ARM Integrator/CP (ARM926EJ-S) platform. \ No newline at end of file +Atomthreads application for the ARM Integrator/CP (ARM926EJ-S) platform. +BUGS: +kern4 testcase fails (sometimes). \ No newline at end of file diff --git a/platforms/qemu_integratorcp/main.c b/platforms/qemu_integratorcp/main.c index 3222170..aebdd3d 100644 --- a/platforms/qemu_integratorcp/main.c +++ b/platforms/qemu_integratorcp/main.c @@ -77,8 +77,8 @@ main (void) printf ("atomthreads starting %s... ", ATOMTHREADS_TEST) ; - atomOSInit(&idle_stack[IDLE_STACK_BYTE_SIZE - sizeof(unsigned int)], IDLE_STACK_BYTE_SIZE - sizeof(unsigned int)) ; - atomThreadCreate ((ATOM_TCB *)&test_tcb, TEST_THREAD_PRIO, test_thread, 0, &test_stack[(TEST_STACK_BYTE_SIZE) - sizeof(unsigned int)], TEST_STACK_BYTE_SIZE - sizeof(unsigned int)); + atomOSInit(&idle_stack[0], IDLE_STACK_BYTE_SIZE, TRUE) ; + atomThreadCreate ((ATOM_TCB *)&test_tcb, TEST_THREAD_PRIO, test_thread, 0, &test_stack[0], TEST_STACK_BYTE_SIZE, TRUE); atomOSStart() ; return 0 ; diff --git a/platforms/qemu_lm3s/Makefile b/platforms/qemu_lm3s/Makefile index c8568ad..dc9c117 100644 --- a/platforms/qemu_lm3s/Makefile +++ b/platforms/qemu_lm3s/Makefile @@ -85,11 +85,11 @@ all_tests: make run_test "TEST_NAME=sem8" make run_test "TEST_NAME=sem9" -all_fail: +fail_tests: make run_test "TEST_NAME=mutex4" make run_test "TEST_NAME=sem4" run_last: - qemu-system-arm -M lm3s6965evb -kernel boot.elf -monitor stdio -semihosting + qemu-system-arm -M lm3s6965evb -kernel boot.elf -semihosting diff --git a/platforms/qemu_lm3s/README b/platforms/qemu_lm3s/README index 6e340d1..bdd09ab 100644 --- a/platforms/qemu_lm3s/README +++ b/platforms/qemu_lm3s/README @@ -31,3 +31,7 @@ Fixes implemented for the QEMU 1.2.0 release: Because of the problems with the Sys Tick Interrupt the The Stellaris General-Purpose Timer Module (GPTM) was used to generate the system timer tick. + +BUGS: +mutex4 testcase fails. +sem4 testcase fails. \ No newline at end of file diff --git a/platforms/qemu_lm3s/main.c b/platforms/qemu_lm3s/main.c index 9aa5bdc..725a642 100644 --- a/platforms/qemu_lm3s/main.c +++ b/platforms/qemu_lm3s/main.c @@ -79,8 +79,8 @@ main (void) uint32_t failures ; printf ("Atomthreads starting %s... \r\n", ATOMTHREADS_TEST) ; - atomOSInit(&idle_stack[IDLE_STACK_BYTE_SIZE - sizeof(unsigned int)], IDLE_STACK_BYTE_SIZE - sizeof(unsigned int)) ; - atomThreadCreate ((ATOM_TCB *)&test_tcb, TEST_THREAD_PRIO, test_thread, 0, &test_stack[(TEST_STACK_BYTE_SIZE) - sizeof(unsigned int)], TEST_STACK_BYTE_SIZE - sizeof(unsigned int)); + atomOSInit(&idle_stack[0], IDLE_STACK_BYTE_SIZE, TRUE) ; + atomThreadCreate ((ATOM_TCB *)&test_tcb, TEST_THREAD_PRIO, test_thread, 0, &test_stack[0], TEST_STACK_BYTE_SIZE, TRUE); atomOSStart() ; return 0 ; diff --git a/ports/arm/README b/ports/arm/README index 8fa5797..e471306 100644 --- a/ports/arm/README +++ b/ports/arm/README @@ -9,8 +9,8 @@ License: BSD Revised ARM PORT This folder contains a port of the Atomthreads real time kernel for the -ARM processor architecture. This port was tested on Cortex A9, Cortex A15 -and the ARM926EJ-S (QEMU). +ARM processor architecture. This port was tested on the ARMv5 and ARMv7 +architectures. To Use: diff --git a/ports/arm/atomport.h b/ports/arm/atomport.h index f7ac10d..f07e75a 100644 --- a/ports/arm/atomport.h +++ b/ports/arm/atomport.h @@ -32,8 +32,17 @@ #include "types.h" -#define SYSTEM_TICKS_PER_SEC 100 +#define SYSTEM_TICKS_PER_SEC 100 +/** + * Definition of NULL. + * If stddef.h is available on the platform it is simplest to include it + * from this header, otherwise define below. + */ +#define NULL ((void *)(0)) + +/* Size of each stack entry / stack alignment size (e.g. 32 bits) */ +#define STACK_ALIGN_SIZE sizeof(unsigned int) /** * Architecture-specific types. @@ -47,12 +56,17 @@ * Functions defined in atomport_arm.asm * */ -extern void contextInit (void) ; -extern uint32_t contextEnterCritical (void) ; -extern void contextExitCritical (uint32_t posture) ; +extern void contextInit (void) ; +extern uint32_t contextEnterCritical (void) ; +extern void contextExitCritical (uint32_t posture) ; -/* Critical region protection */ +/** + * Critical region protection: this should disable interrupts + * to protect OS data structures during modification. It must + * allow nested calls, which means that interrupts should only + * be re-enabled when the outer CRITICAL_END() is reached. + */ #define CRITICAL_STORE uint32_t __atom_critical #define CRITICAL_START() __atom_critical = contextEnterCritical() #define CRITICAL_END() contextExitCritical(__atom_critical) diff --git a/ports/cortex_m/atomport.h b/ports/cortex_m/atomport.h index f7ac10d..1a4cfd9 100644 --- a/ports/cortex_m/atomport.h +++ b/ports/cortex_m/atomport.h @@ -32,7 +32,23 @@ #include "types.h" -#define SYSTEM_TICKS_PER_SEC 100 +#define SYSTEM_TICKS_PER_SEC 100 + +/** + * Definition of NULL. + * If stddef.h is available on the platform it is simplest to include it + * from this header, otherwise define below. + */ +#define NULL ((void *)(0)) + +/* Size of each stack entry / stack alignment size (e.g. 32 bits) */ +#define STACK_ALIGN_SIZE sizeof(unsigned int) + +/** + * Architecture-specific types. + * Most of these are available from types.h on this platform, which is + * included above. + */ /** @@ -47,9 +63,9 @@ * Functions defined in atomport_arm.asm * */ -extern void contextInit (void) ; -extern uint32_t contextEnterCritical (void) ; -extern void contextExitCritical (uint32_t posture) ; +extern void contextInit (void) ; +extern uint32_t contextEnterCritical (void) ; +extern void contextExitCritical (uint32_t posture) ; /* Critical region protection */ @@ -58,3 +74,4 @@ extern void contextExitCritical (uint32_t posture) ; #define CRITICAL_END() contextExitCritical(__atom_critical) #endif /* __ATOM_PORT_H__ */ + From 9ebb4d14b4b362b1c2b7be19483ce97e99b4c511 Mon Sep 17 00:00:00 2001 From: Natie van Rooyen Date: Thu, 27 Sep 2012 21:46:59 +0200 Subject: [PATCH 20/28] white space --- platforms/qemu_integratorcp/README | 1 + platforms/qemu_integratorcp/modules.c | 8 +- platforms/qemu_integratorcp/modules.h | 38 ++++----- platforms/qemu_integratorcp/startup.s | 4 - platforms/qemu_lm3s/modules.c | 84 +++++++++--------- platforms/qemu_lm3s/modules.h | 118 +++++++++++++------------- 6 files changed, 128 insertions(+), 125 deletions(-) diff --git a/platforms/qemu_integratorcp/README b/platforms/qemu_integratorcp/README index 0177f81..d8b53c9 100644 --- a/platforms/qemu_integratorcp/README +++ b/platforms/qemu_integratorcp/README @@ -10,5 +10,6 @@ QEMU ARM Integrator/CP (ARM926EJ-S) Platform The "qemu_integratorcp" platform contains sources for building a sample Atomthreads application for the ARM Integrator/CP (ARM926EJ-S) platform. + BUGS: kern4 testcase fails (sometimes). \ No newline at end of file diff --git a/platforms/qemu_integratorcp/modules.c b/platforms/qemu_integratorcp/modules.c index c611d68..a6ee156 100644 --- a/platforms/qemu_integratorcp/modules.c +++ b/platforms/qemu_integratorcp/modules.c @@ -46,16 +46,16 @@ ICP_PIC_T * const board_pic = (ICP_PI void dbg_format_msg (char *format, ...) { - va_list args; - static char msg[256] ; + va_list args; + static char msg[256] ; CRITICAL_STORE ; va_start (args, format) ; CRITICAL_START() ; - vsnprintf ((char*)msg, 256, (char*)format, args) ; + vsnprintf ((char*)msg, 256, (char*)format, args) ; + printf (msg) ; CRITICAL_END() ; - printf (msg) ; } /** diff --git a/platforms/qemu_integratorcp/modules.h b/platforms/qemu_integratorcp/modules.h index 58a48ed..a94140a 100644 --- a/platforms/qemu_integratorcp/modules.h +++ b/platforms/qemu_integratorcp/modules.h @@ -59,21 +59,21 @@ typedef struct ICP_TIMER_S { // -------- ICP_TIMER_LOAD : (LOAD Offset: 0x00) Load value for Timer -------- // -------- ICP_TIMER_VALUE : (LOAD Offset: 0x04) The current value for Timer -------- // -------- ICP_TIMER_CONTROL : (CONTROL Offset: 0x04) Timer control register -------- -#define ICP_TIMER_CONTROL_MASK ((unsigned int)0x0F << 0) // Timer control mask - #define ICP_TIMER_CONTROL_ENABLE ((unsigned int)0x01 << 7) // Timer enable: 0 = disabled 1 = enabled. - #define ICP_TIMER_CONTROL_MODE ((unsigned int)0x01 << 6) // Timer mode: 0 = free running, counts once and then wraps to 0xFFFF 1 = periodic, reloads from load register at the end of each count.. - #define ICP_TIMER_CONTROL_IE ((unsigned int)0x01 << 5) // Interrupt enable. - #define ICP_TIMER_CONTROL_R ((unsigned int)0x01 << 4) // Unused, always write as 0s. - #define ICP_TIMER_CONTROL_PRESCALE_MASK ((unsigned int)0x03 << 2) // Prescale divisor - #define ICP_TIMER_CONTROL_PRESCALE_NONE ((unsigned int)0x00 << 2) // - #define ICP_TIMER_CONTROL_PRESCALE_16 ((unsigned int)0x01 << 2) // - #define ICP_TIMER_CONTROL_PRESCALE_256 ((unsigned int)0x02 << 2) // -#define ICP_TIMER_CONTROL_TIMER_SIZE ((unsigned int)0x01 << 1) // Selects 16/32 bit counter operation: 0 = 16-bit counter (default) 1 = 32-bit counter For 16-bit mode, write the high 16 bits of the 32-bit value as 0. -#define ICP_TIMER_CONTROL_ONE_SHOT ((unsigned int)0x01 << 0) // Selects one-shot or wrapping counter mode: 0 = wrapping mode (default) 1 = one-shot mode +#define ICP_TIMER_CONTROL_MASK ((unsigned int)0x0F << 0) // Timer control mask + #define ICP_TIMER_CONTROL_ENABLE ((unsigned int)0x01 << 7) // Timer enable: 0 = disabled 1 = enabled. + #define ICP_TIMER_CONTROL_MODE ((unsigned int)0x01 << 6) // Timer mode: 0 = free running, counts once and then wraps to 0xFFFF 1 = periodic, reloads from load register at the end of each count.. + #define ICP_TIMER_CONTROL_IE ((unsigned int)0x01 << 5) // Interrupt enable. + #define ICP_TIMER_CONTROL_R ((unsigned int)0x01 << 4) // Unused, always write as 0s. + #define ICP_TIMER_CONTROL_PRESCALE_MASK ((unsigned int)0x03 << 2) // Prescale divisor + #define ICP_TIMER_CONTROL_PRESCALE_NONE ((unsigned int)0x00 << 2) // + #define ICP_TIMER_CONTROL_PRESCALE_16 ((unsigned int)0x01 << 2) // + #define ICP_TIMER_CONTROL_PRESCALE_256 ((unsigned int)0x02 << 2) // +#define ICP_TIMER_CONTROL_TIMER_SIZE ((unsigned int)0x01 << 1) // Selects 16/32 bit counter operation: 0 = 16-bit counter (default) 1 = 32-bit counter For 16-bit mode, write the high 16 bits of the 32-bit value as 0. +#define ICP_TIMER_CONTROL_ONE_SHOT ((unsigned int)0x01 << 0) // Selects one-shot or wrapping counter mode: 0 = wrapping mode (default) 1 = one-shot mode // -------- ICP_TIMER_INTCLR : (INTCLR Offset: 0x0C) Timer interrupt clear -------- // -------- ICP_TIMER_RIS : (RIS Offset: 0x10) Timer raw interrupt status -------- // -------- ICP_TIMER_MIS : (MIS Offset: 0x14) Timer masked interrupt status -------- -#define ICP_TIMER_INT ((unsigned int)0x01 << 0) // Interrupt +#define ICP_TIMER_INT ((unsigned int)0x01 << 0) // Interrupt // -------- ICP_TIMER_BGLOAD : (BGLOAD Offset: 0x18) Timer masked interrupt status -------- @@ -100,19 +100,19 @@ typedef struct ICP_PIC_S { // -------- ICP_PIC_IRQ_RAWSTAT : (IRQ_RAWSTAT Offset: 0x04) IRQ raw interrupt status -------- // -------- ICP_PIC_IRQ_ENABLESET : (IRQ_ENABLESET Offset: 0x08) IRQ enable set -------- // -------- ICP_PIC_IRQ_ENABLECLR : (IRQ_ENABLECLR Offset: 0x0C) IRQ enable clear -------- -#define ICP_PIC_IRQ_MASK ((unsigned int)0x3FFFFF << 0) // IRQ mask - #define ICP_PIC_IRQ_TIMERINT2 ((unsigned int)0x01 << 7) // TIMERINT2 Counter-timer 2 interrupt - #define ICP_PIC_IRQ_TIMERINT1 ((unsigned int)0x01 << 6) // TIMERINT1 Counter-timer 1 interrupt - #define ICP_PIC_IRQ_TIMERINT0 ((unsigned int)0x01 << 5) // TIMERINT0 Counter-timer 0 interrupt - #define ICP_PIC_IRQ_SOFTINT ((unsigned int)0x01 << 0) // OFTINT Software interrupt +#define ICP_PIC_IRQ_MASK ((unsigned int)0x3FFFFF << 0) // IRQ mask + #define ICP_PIC_IRQ_TIMERINT2 ((unsigned int)0x01 << 7) // TIMERINT2 Counter-timer 2 interrupt + #define ICP_PIC_IRQ_TIMERINT1 ((unsigned int)0x01 << 6) // TIMERINT1 Counter-timer 1 interrupt + #define ICP_PIC_IRQ_TIMERINT0 ((unsigned int)0x01 << 5) // TIMERINT0 Counter-timer 0 interrupt + #define ICP_PIC_IRQ_SOFTINT ((unsigned int)0x01 << 0) // OFTINT Software interrupt // -------- ICP_PIC_INT_SOFTSET : (INT_SOFTSET Offset: 0x10) Software interrupt set -------- // -------- ICP_PIC_INT_SOFTCLR : (INT_SOFTCLR Offset: 0x14) Software interrupt clear -------- /* module definitions */ -#define BOARD_BASE_ADDRESS_TIMER_0 0x13000000 -#define BOARD_BASE_ADDRESS_PIC 0x14000000 +#define BOARD_BASE_ADDRESS_TIMER_0 0x13000000 +#define BOARD_BASE_ADDRESS_PIC 0x14000000 extern ICP_TIMER_T* const board_timer_0 ; extern ICP_PIC_T* const board_pic ; diff --git a/platforms/qemu_integratorcp/startup.s b/platforms/qemu_integratorcp/startup.s index 0c3675d..a19ea76 100644 --- a/platforms/qemu_integratorcp/startup.s +++ b/platforms/qemu_integratorcp/startup.s @@ -5,10 +5,6 @@ .extern __fiq_stack_top__ .extern __svc_stack_top__ -.global bsp_ints_enable -.global bsp_ints_disable -.global bsp_ints_restore - .equ USR_MODE, 0x10 .equ FIQ_MODE, 0x11 diff --git a/platforms/qemu_lm3s/modules.c b/platforms/qemu_lm3s/modules.c index c375e4e..10c0058 100644 --- a/platforms/qemu_lm3s/modules.c +++ b/platforms/qemu_lm3s/modules.c @@ -49,13 +49,13 @@ GPTM_TIMER_T * const board_gptm0 = (GPTM_TIMER_T*) void dbg_format_msg (char *format, ...) { - va_list args; - static char msg[256] ; + va_list args; + static char msg[256] ; CRITICAL_STORE ; va_start (args, format) ; CRITICAL_START() ; - vsnprintf ((char*)msg, 256, (char*)format, args) ; + vsnprintf ((char*)msg, 256, (char*)format, args) ; printf (msg) ; CRITICAL_END() ; @@ -92,7 +92,7 @@ low_level_init (void) /** - * \b __context_preempt_handler + * \b __context_tick_handler * * System timer tic interupt handler. * @@ -113,44 +113,50 @@ __context_tick_handler (void) } +/** + * \b dbg_hard_fault_handler_c + * + * Dumps the registers pushed on the stack after a fault. + * + */ void dbg_hard_fault_handler_c (unsigned int * hardfault_args) { - unsigned int stacked_r0; - unsigned int stacked_r1; - unsigned int stacked_r2; - unsigned int stacked_r3; - unsigned int stacked_r12; - unsigned int stacked_lr; - unsigned int stacked_pc; - unsigned int stacked_psr; - - stacked_r0 = ((unsigned long) hardfault_args[0]); - stacked_r1 = ((unsigned long) hardfault_args[1]); - stacked_r2 = ((unsigned long) hardfault_args[2]); - stacked_r3 = ((unsigned long) hardfault_args[3]); - - stacked_r12 = ((unsigned long) hardfault_args[4]); - stacked_lr = ((unsigned long) hardfault_args[5]); - stacked_pc = ((unsigned long) hardfault_args[6]); - stacked_psr = ((unsigned long) hardfault_args[7]); - - printf ("\r\n\r\n[Hard fault handler - all numbers in hex]\r\n"); - printf ("SP = 0x%x\r\n", hardfault_args); - printf ("R0 = 0x%x\r\n", stacked_r0); - printf ("R1 = 0x%x\r\n", stacked_r1); - printf ("R2 = 0x%x\r\n", stacked_r2); - printf ("R3 = 0x%x\r\n", stacked_r3); - printf ("R12 = 0x%x\r\n", stacked_r12); - printf ("LR [R14] = 0x%x subroutine call return address\r\n", stacked_lr); - printf ("PC [R15] = 0x%x program counter\r\n", stacked_pc); - printf ("PSR = 0x%x\r\n", stacked_psr); - //printf ("BFAR = 0x%x\r\n", (*((volatile unsigned long *)(0xE000ED38)))); - //printf ("CFSR = 0x%x\r\n", (*((volatile unsigned long *)(0xE000ED28)))); - //printf ("HFSR = 0x%x\r\n", (*((volatile unsigned long *)(0xE000ED2C)))); - //printf ("DFSR = 0x%x\r\n", (*((volatile unsigned long *)(0xE000ED30)))); - //printf ("AFSR = 0x%x\r\n", (*((volatile unsigned long *)(0xE000ED3C)))); - // printf ("SCB_SHCSR = %x\n", SCB->SHCSR); + unsigned int stacked_r0; + unsigned int stacked_r1; + unsigned int stacked_r2; + unsigned int stacked_r3; + unsigned int stacked_r12; + unsigned int stacked_lr; + unsigned int stacked_pc; + unsigned int stacked_psr; + + stacked_r0 = ((unsigned long) hardfault_args[0]); + stacked_r1 = ((unsigned long) hardfault_args[1]); + stacked_r2 = ((unsigned long) hardfault_args[2]); + stacked_r3 = ((unsigned long) hardfault_args[3]); + + stacked_r12 = ((unsigned long) hardfault_args[4]); + stacked_lr = ((unsigned long) hardfault_args[5]); + stacked_pc = ((unsigned long) hardfault_args[6]); + stacked_psr = ((unsigned long) hardfault_args[7]); + + printf ("\r\n\r\n[Hard fault handler - all numbers in hex]\r\n"); + printf ("SP = 0x%x\r\n", hardfault_args); + printf ("R0 = 0x%x\r\n", stacked_r0); + printf ("R1 = 0x%x\r\n", stacked_r1); + printf ("R2 = 0x%x\r\n", stacked_r2); + printf ("R3 = 0x%x\r\n", stacked_r3); + printf ("R12 = 0x%x\r\n", stacked_r12); + printf ("LR [R14] = 0x%x subroutine call return address\r\n", stacked_lr); + printf ("PC [R15] = 0x%x program counter\r\n", stacked_pc); + printf ("PSR = 0x%x\r\n", stacked_psr); + //printf ("BFAR = 0x%x\r\n", (*((volatile unsigned long *)(0xE000ED38)))); + //printf ("CFSR = 0x%x\r\n", (*((volatile unsigned long *)(0xE000ED28)))); + //printf ("HFSR = 0x%x\r\n", (*((volatile unsigned long *)(0xE000ED2C)))); + //printf ("DFSR = 0x%x\r\n", (*((volatile unsigned long *)(0xE000ED30)))); + //printf ("AFSR = 0x%x\r\n", (*((volatile unsigned long *)(0xE000ED3C)))); + // printf ("SCB_SHCSR = %x\n", SCB->SHCSR); while (1); diff --git a/platforms/qemu_lm3s/modules.h b/platforms/qemu_lm3s/modules.h index 8d3bb4c..5a074b4 100644 --- a/platforms/qemu_lm3s/modules.h +++ b/platforms/qemu_lm3s/modules.h @@ -46,26 +46,26 @@ typedef volatile unsigned char REG_BYTE ; // ***************************************************************************** typedef struct GPTM_TIMER_S { - // offset read/write reset Description - REG_DWORD CFG ; // 0x000 R/W 0x00000000 GPTM Configuration 345 - REG_DWORD TAMR ; // 0x004 R/W 0x00000000 GPTM TimerA Mode 346 - REG_DWORD TBMR ; // 0x008 R/W 0x00000000 GPTM TimerB Mode 348 - REG_DWORD CTL ; // 0x00C R/W 0x00000000 GPTM Control 350 - REG_DWORD Reserved[2] ; // 0x010 - REG_DWORD IMR ; // 0x018 R/W 0x00000000 GPTM Interrupt Mask 353 - REG_DWORD RIS ; // 0x01C RO 0x00000000 GPTM Raw Interrupt Status 355 - REG_DWORD MIS ; // 0x020 RO 0x00000000 GPTM Masked Interrupt Status 356 - REG_DWORD ICR ; // 0x024 W1C 0x00000000 GPTM Interrupt Clear 357 - REG_DWORD TAILR ; // 0x028 R/W 0xFFFFFFFF GPTM TimerA Interval Load 359 - REG_DWORD TBILR ; // 0x02C R/W 0x0000FFFF GPTM TimerB Interval Load 360 - REG_DWORD TAMATCHR ; // 0x030 R/W 0xFFFFFFFF GPTM TimerA Match 361 - REG_DWORD TBMATCHR ; // 0x034 R/W 0x0000FFFF GPTM TimerB Match 362 - REG_DWORD TAPR ; // 0x038 R/W 0x00000000 GPTM TimerA Prescale 363 - REG_DWORD TBPR ; // 0x03C R/W 0x00000000 GPTM TimerB Prescale 364 - REG_DWORD TAPMR ; // 0x040 R/W 0x00000000 GPTM TimerA Prescale Match 365 - REG_DWORD TBPMR ; // 0x044 R/W 0x00000000 GPTM TimerB Prescale Match 366 - REG_DWORD TAR ; // 0x048 RO 0xFFFFFFFF GPTM TimerA 367 - REG_DWORD TBR ; // 0x04C RO 0x0000FFFF GPTM TimerB 368 + // offset read/write reset Description + REG_DWORD CFG ; // 0x000 R/W 0x00000000 GPTM Configuration 345 + REG_DWORD TAMR ; // 0x004 R/W 0x00000000 GPTM TimerA Mode 346 + REG_DWORD TBMR ; // 0x008 R/W 0x00000000 GPTM TimerB Mode 348 + REG_DWORD CTL ; // 0x00C R/W 0x00000000 GPTM Control 350 + REG_DWORD Reserved[2] ; // 0x010 + REG_DWORD IMR ; // 0x018 R/W 0x00000000 GPTM Interrupt Mask 353 + REG_DWORD RIS ; // 0x01C RO 0x00000000 GPTM Raw Interrupt Status 355 + REG_DWORD MIS ; // 0x020 RO 0x00000000 GPTM Masked Interrupt Status 356 + REG_DWORD ICR ; // 0x024 W1C 0x00000000 GPTM Interrupt Clear 357 + REG_DWORD TAILR ; // 0x028 R/W 0xFFFFFFFF GPTM TimerA Interval Load 359 + REG_DWORD TBILR ; // 0x02C R/W 0x0000FFFF GPTM TimerB Interval Load 360 + REG_DWORD TAMATCHR ; // 0x030 R/W 0xFFFFFFFF GPTM TimerA Match 361 + REG_DWORD TBMATCHR ; // 0x034 R/W 0x0000FFFF GPTM TimerB Match 362 + REG_DWORD TAPR ; // 0x038 R/W 0x00000000 GPTM TimerA Prescale 363 + REG_DWORD TBPR ; // 0x03C R/W 0x00000000 GPTM TimerB Prescale 364 + REG_DWORD TAPMR ; // 0x040 R/W 0x00000000 GPTM TimerA Prescale Match 365 + REG_DWORD TBPMR ; // 0x044 R/W 0x00000000 GPTM TimerB Prescale Match 366 + REG_DWORD TAR ; // 0x048 RO 0xFFFFFFFF GPTM TimerA 367 + REG_DWORD TBR ; // 0x04C RO 0x0000FFFF GPTM TimerB 368 } GPTM_TIMER_T, *PGPTM_TIMER_T ; @@ -81,36 +81,36 @@ typedef struct GPTM_TIMER_S { #define GPTM_TIMER_TMR_TMR_PERIODIC ((unsigned int)0x02 << 0) // Periodic Timer mode #define GPTM_TIMER_TMR_TMR_CAPTURE ((unsigned int)0x03 << 0) // Capture mode // -------- GPTM_TIMER_CTL : (CTL Offset: 0x0C) This register is used alongside the GPTMCFG and GMTMTnMR registers to fine-tune the timer configuration -------- -#define GPTM_TIMER_CTL_TBPWML ((unsigned int)0x01 << 14) // GPTM TimerB PWM Output Level. 0 Output is unaffected. 1 Output is inverted. -#define GPTM_TIMER_CTL_TBOTE ((unsigned int)0x01 << 13) // GPTM TimerB Output Trigger Enable. 0 The output TimerB ADC trigger is disabled. 1 The output TimerB ADC trigger is enabled. -#define GPTM_TIMER_CTL_TBEVENT_MASK ((unsigned int)0x03 << 10) // GPTM TimerB Event Mode - #define GPTM_TIMER_CTL_TBEVENT_PE ((unsigned int)0x00 << 10) // Positive edge - #define GPTM_TIMER_CTL_TBEVENT_NE ((unsigned int)0x01 << 10) // Negative edge - #define GPTM_TIMER_CTL_TBEVENT ((unsigned int)0x03 << 10) // Both edges -#define GPTM_TIMER_CTL_TBSTALL ((unsigned int)0x01 << 9) // GPTM Timer B Stall Enable. 0 Timer B continues counting while the processor is halted by the debugger -#define GPTM_TIMER_CTL_TBEN ((unsigned int)0x01 << 8) // GPTM TimerB Enable -// -------- -#define GPTM_TIMER_CTL_TAPWML ((unsigned int)0x01 << 6) // GPTM TimerA PWM Output Level. 0 Output is unaffected. 1 Output is inverted. -#define GPTM_TIMER_CTL_TAOTE ((unsigned int)0x01 << 5) // GPTM TimerA Output Trigger Enable. 0 The output TimerB ADC trigger is disabled. 1 The output TimerB ADC trigger is enabled. -#define GPTM_TIMER_CTL_RTCEN ((unsigned int)0x01 << 4) // GPTM RTC Enable -#define GPTM_TIMER_CTL_TAEVENT_MASK ((unsigned int)0x03 << 2) // GPTM TimerA Event Mode - #define GPTM_TIMER_CTL_TAEVENT_PE ((unsigned int)0x00 << 2) // Positive edge - #define GPTM_TIMER_CTL_TAEVENT_NE ((unsigned int)0x01 << 2) // Negative edge - #define GPTM_TIMER_CTL_TAEVENT ((unsigned int)0x03 << 2) // Both edges -#define GPTM_TIMER_CTL_TASTALL ((unsigned int)0x01 << 1) // GPTM Timer A Stall Enable. 0 Timer B continues counting while the processor is halted by the debugger -#define GPTM_TIMER_CTL_TAEN ((unsigned int)0x01 << 0) // GPTM TimerA Enable +#define GPTM_TIMER_CTL_TBPWML ((unsigned int)0x01 << 14) // GPTM TimerB PWM Output Level. 0 Output is unaffected. 1 Output is inverted. +#define GPTM_TIMER_CTL_TBOTE ((unsigned int)0x01 << 13) // GPTM TimerB Output Trigger Enable. 0 The output TimerB ADC trigger is disabled. 1 The output TimerB ADC trigger is enabled. +#define GPTM_TIMER_CTL_TBEVENT_MASK ((unsigned int)0x03 << 10) // GPTM TimerB Event Mode + #define GPTM_TIMER_CTL_TBEVENT_PE ((unsigned int)0x00 << 10) // Positive edge + #define GPTM_TIMER_CTL_TBEVENT_NE ((unsigned int)0x01 << 10) // Negative edge + #define GPTM_TIMER_CTL_TBEVENT ((unsigned int)0x03 << 10) // Both edges +#define GPTM_TIMER_CTL_TBSTALL ((unsigned int)0x01 << 9) // GPTM Timer B Stall Enable. 0 Timer B continues counting while the processor is halted by the debugger +#define GPTM_TIMER_CTL_TBEN ((unsigned int)0x01 << 8) // GPTM TimerB Enable +// -------- // +#define GPTM_TIMER_CTL_TAPWML ((unsigned int)0x01 << 6) // GPTM TimerA PWM Output Level. 0 Output is unaffected. 1 Output is inverted. +#define GPTM_TIMER_CTL_TAOTE ((unsigned int)0x01 << 5) // GPTM TimerA Output Trigger Enable. 0 The output TimerB ADC trigger is disabled. 1 The output TimerB ADC trigger is enabled. +#define GPTM_TIMER_CTL_RTCEN ((unsigned int)0x01 << 4) // GPTM RTC Enable +#define GPTM_TIMER_CTL_TAEVENT_MASK ((unsigned int)0x03 << 2) // GPTM TimerA Event Mode + #define GPTM_TIMER_CTL_TAEVENT_PE ((unsigned int)0x00 << 2) // Positive edge + #define GPTM_TIMER_CTL_TAEVENT_NE ((unsigned int)0x01 << 2) // Negative edge + #define GPTM_TIMER_CTL_TAEVENT ((unsigned int)0x03 << 2) // Both edges +#define GPTM_TIMER_CTL_TASTALL ((unsigned int)0x01 << 1) // GPTM Timer A Stall Enable. 0 Timer B continues counting while the processor is halted by the debugger +#define GPTM_TIMER_CTL_TAEN ((unsigned int)0x01 << 0) // GPTM TimerA Enable // -------- GPTM_TIMER_IMR : (IMR Offset: 0x18) This register allows software to enable/disable GPTM controller-level interrupts. -------- // -------- GPTM_TIMER_RIS : (RIS Offset: 0x1C) This register shows the state of the GPTM's internal interrupt signal. -------- // -------- GPTM_TIMER_MIS : (MIS Offset: 0x20) This register show the state of the GPTM's controller-level interrupt. -------- // -------- GPTM_TIMER_ICR : (ICR Offset: 0x24) This register is used to clear the status bits in the GPTMRIS and GPTMMIS registers. -------- -#define GPTM_TIMER_INT_CBEIM ((unsigned int)0x01 << 10) // GPTM CaptureB Event Interrupt Mask -#define GPTM_TIMER_INT_CBMIM ((unsigned int)0x01 << 9) // GPTM CaptureB Match Interrupt Mask -#define GPTM_TIMER_INT_TBTOIM ((unsigned int)0x01 << 8) // GPTM TimerB Time-Out Interrupt Mask -// -------- -#define GPTM_TIMER_INT_RTCIM ((unsigned int)0x01 << 3) // GPTM RTC Interrupt Mask -#define GPTM_TIMER_INT_CAEIM ((unsigned int)0x01 << 2) // GPTM CaptureA Event Interrupt Mask -#define GPTM_TIMER_INT_CAMIM ((unsigned int)0x01 << 1) // GPTM CaptureA Match Interrupt Mask -#define GPTM_TIMER_INT_TATOIM ((unsigned int)0x01 << 0) // GPTM TimerA Time-Out Interrupt Mask +#define GPTM_TIMER_INT_CBEIM ((unsigned int)0x01 << 10) // GPTM CaptureB Event Interrupt Mask +#define GPTM_TIMER_INT_CBMIM ((unsigned int)0x01 << 9) // GPTM CaptureB Match Interrupt Mask +#define GPTM_TIMER_INT_TBTOIM ((unsigned int)0x01 << 8) // GPTM TimerB Time-Out Interrupt Mask +// -------- // +#define GPTM_TIMER_INT_RTCIM ((unsigned int)0x01 << 3) // GPTM RTC Interrupt Mask +#define GPTM_TIMER_INT_CAEIM ((unsigned int)0x01 << 2) // GPTM CaptureA Event Interrupt Mask +#define GPTM_TIMER_INT_CAMIM ((unsigned int)0x01 << 1) // GPTM CaptureA Match Interrupt Mask +#define GPTM_TIMER_INT_TATOIM ((unsigned int)0x01 << 0) // GPTM TimerA Time-Out Interrupt Mask @@ -131,10 +131,10 @@ typedef struct SYSTICK_S { } SYSTICK_T, *PSYSTICK_T ; // -------- SYSTICK_STCTRL : (STCTRL Offset: 0xE000E010) SysTick Control and Status Register -------- -#define SYSTICK_STCTRL_COUNT ((unsigned int)0x1 << 16) // 0 - The SysTick timer has not counted to 0 since the last time this bit was read. -#define SYSTICK_STCTRL_CLK ((unsigned int)0x1 << 2) // 1 - System clock -#define SYSTICK_STCTRL_INTEN ((unsigned int)0x1 << 1) // 1 - An interrupt is generated to the NVIC when SysTick counts to 0. -#define SYSTICK_STCTRL_ENABLE ((unsigned int)0x1 << 1) // Enables SysTick to operate in a multi-shot way. +#define SYSTICK_STCTRL_COUNT ((unsigned int)0x1 << 16) // 0 - The SysTick timer has not counted to 0 since the last time this bit was read. +#define SYSTICK_STCTRL_CLK ((unsigned int)0x1 << 2) // 1 - System clock +#define SYSTICK_STCTRL_INTEN ((unsigned int)0x1 << 1) // 1 - An interrupt is generated to the NVIC when SysTick counts to 0. +#define SYSTICK_STCTRL_ENABLE ((unsigned int)0x1 << 1) // Enables SysTick to operate in a multi-shot way. // -------- SYSTICK_STRELOAD : (STRELOAD Offset: 0xE000E014) Reload Value -------- #define SYSTICK_STRELOAD_MASK ((unsigned int)0xFFFFFF << 0) // IRQ mask // -------- SYSTICK_STCURRENT : (STCURRENT Offset: 0xE000E018) SysTick Current Value Register -------- @@ -155,7 +155,7 @@ typedef struct NVIC_S { REG_DWORD Res6[30] ; // 0xE000E2A0 REG_DWORD IABR[2] ; // 0xE000E300 REG_DWORD Res7[64] ; // 0xE000E320 - REG_DWORD IPR[2] ; // 0xE000E400 + REG_DWORD IPR[2] ; // 0xE000E400 // REG_DWORD Res7[515] ; // 0xE000E4F4 } NVIC_T, *PNVIC_T ; @@ -192,15 +192,15 @@ typedef struct SCB_S { /* module definitions */ -#define BOARD_BASE_ADDRESS_SYSTICK 0xE000E000 -#define BOARD_BASE_ADDRESS_NVIC 0xE000E100 -#define BOARD_BASE_ADDRESS_SCB 0xE000ED00 -#define BOARD_BASE_ADDRESS_GPTIMER0 0x40030000 +#define BOARD_BASE_ADDRESS_SYSTICK 0xE000E000 +#define BOARD_BASE_ADDRESS_NVIC 0xE000E100 +#define BOARD_BASE_ADDRESS_SCB 0xE000ED00 +#define BOARD_BASE_ADDRESS_GPTIMER0 0x40030000 -extern SYSTICK_T* const board_systick ; -extern NVIC_T* const board_nvic ; -extern SCB_T* const board_scb ; -extern GPTM_TIMER_T* const board_gptm0 ; +extern SYSTICK_T* const board_systick ; +extern NVIC_T* const board_nvic ; +extern SCB_T* const board_scb ; +extern GPTM_TIMER_T* const board_gptm0 ; /* Function prototypes */ From 6f34e08e2f52813dd2f23b9ed234123420a8d4cb Mon Sep 17 00:00:00 2001 From: Natie van Rooyen Date: Wed, 3 Oct 2012 21:19:44 +0200 Subject: [PATCH 21/28] Updates to the atomvm port. --- ports/atomvm/{README.txt => README} | 22 +- ports/atomvm/atomport-tests.h | 5 +- ports/atomvm/atomport.c | 19 +- ports/atomvm/atomport.h | 28 +- ports/atomvm/atomvm.c | 394 ++++-------------- ports/atomvm/atomvm.h | 59 ++- ports/atomvm/{test => msvc}/main.c | 540 ++++++++++++------------- ports/atomvm/msvc/msvc.sln | 20 + ports/atomvm/msvc/msvc.vcxproj | 102 +++++ ports/atomvm/msvc/msvc.vcxproj.filters | 67 +++ ports/atomvm/{atomuser.h => types.h} | 124 +++--- 11 files changed, 646 insertions(+), 734 deletions(-) rename ports/atomvm/{README.txt => README} (51%) rename ports/atomvm/{test => msvc}/main.c (85%) create mode 100644 ports/atomvm/msvc/msvc.sln create mode 100644 ports/atomvm/msvc/msvc.vcxproj create mode 100644 ports/atomvm/msvc/msvc.vcxproj.filters rename ports/atomvm/{atomuser.h => types.h} (96%) diff --git a/ports/atomvm/README.txt b/ports/atomvm/README similarity index 51% rename from ports/atomvm/README.txt rename to ports/atomvm/README index 7a07533..b912b47 100644 --- a/ports/atomvm/README.txt +++ b/ports/atomvm/README @@ -6,11 +6,18 @@ License: BSD Revised --------------------------------------------------------------------------- -Atomvm is a tiny virtual machine that can run on Windows inside an IDE with a -debugger like Microsoft Visual C++ Express. The primary purpose of this virtual -machine is for the evaluation of Real Time Operating Systems (like atomthreads) -and the development and testing of modules for this Real Time Operating System -in a user friendly environment. +Atomvm is a tiny virtual machine that runs on Windows and can be debugged +from an IDE like Microsoft Visual C++ Express. The primary purpose of this +virtual machine is for the evaluation of Real Time Operating Systems like +Atomthreads and the development and testing of programs for it on a Windows +machine. + +Atomvm makes use of the Windows API functions GetThreadContext() and +SetThreadContext() to create multiple virtual contexts or threads inside a +single Windows thread. Atomvm also simulates interrupts with an interrupt +mask accessible from the Atomvm threads. External events can be queued as +interrupts to Atomvm, for example a timer loop generating system timer tick +interrupts for a Real Time Operating System ported to Atomvm. --------------------------------------------------------------------------- @@ -28,9 +35,6 @@ core system. RUNNING THE TESTS -The test, main.c, is intentioned to stress the virtual machine as opposed to -testing the Real Time Operating System. However, this test can also run the -unit tests of atomthreads by using the preprocessor directive "UNIT_TESTS" and -linking in the desired unit test into the project. +The test, main.c, is intentioned to stress the virtual machine. diff --git a/ports/atomvm/atomport-tests.h b/ports/atomvm/atomport-tests.h index 9f5320d..354acc7 100644 --- a/ports/atomvm/atomport-tests.h +++ b/ports/atomvm/atomport-tests.h @@ -27,8 +27,8 @@ * POSSIBILITY OF SUCH DAMAGE. */ -#ifndef __ATOM_PORT_TESTS_H -#define __ATOM_PORT_TESTS_H +#ifndef __ATOMPORT_TEST_H__ +#define __ATOMPORT_TEST_H__ /* Include Atomthreads kernel API */ #include "atom.h" @@ -56,3 +56,4 @@ #endif /* __ATOM_PORT_TESTS_H */ +#endif /* __ATOMPORT_TEST_H__ */ diff --git a/ports/atomvm/atomport.c b/ports/atomvm/atomport.c index a4de433..a9bc46f 100644 --- a/ports/atomvm/atomport.c +++ b/ports/atomvm/atomport.c @@ -53,7 +53,7 @@ static HANDLE cntrl_thread ; void atomvmRun () { - atomvmCtrlInit (&the_atomvm) ; + atomvmCtrlCreate (&the_atomvm) ; cntrl_thread = CreateThread (NULL, 0, cntrl_thread_proc, (uint32_t*)the_atomvm, CREATE_SUSPENDED, NULL) ; ResumeThread (cntrl_thread) ; } @@ -85,7 +85,8 @@ thread_shell (void) * is first restored. */ // sei(); - atomvmExitCritical () ; + //atomvmExitCritical () ; + atomvmInterruptMask (0) ; /* Call the thread entry point */ if (curr_tcb && curr_tcb->entry_point) @@ -156,17 +157,3 @@ void archTimerTickIrqHandler () /* Call the interrupt exit routine */ atomIntExit(TRUE); } - - -unsigned int -__enter_critical () -{ - return atomvmEnterCritical () ; -} - - -void -__exit_critical (unsigned int isr) -{ - atomvmExitCritical () ; -} diff --git a/ports/atomvm/atomport.h b/ports/atomvm/atomport.h index 1022e3e..84edb64 100644 --- a/ports/atomvm/atomport.h +++ b/ports/atomvm/atomport.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010, Kelvin Lawson. All rights reserved. + * Copyright (c) 2012, Natie van Rooyen. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -32,19 +32,9 @@ #include "atomvm.h" -#define SYSTEM_MEMALIGN sizeof (unsigned int) #define SYSTEM_TICKS_PER_SEC 100 - - -typedef unsigned int uintptr_t ; -typedef int intptr_t ; -typedef unsigned int uint32_t ; -typedef unsigned short uint16_t ; -typedef unsigned char uint8_t ; -typedef int int32_t ; -typedef short int16_t ; -typedef char int8_t ; - +/* Size of each stack entry / stack alignment size (e.g. 32 bits) */ +#define STACK_ALIGN_SIZE sizeof(unsigned int) /** * Architecture-specific types. @@ -52,15 +42,13 @@ typedef char int8_t ; * included above. */ #define POINTER void * +#define ATOM_TLS HATOMVM_CONTEXT context ; /* Critical region protection */ -extern unsigned int __enter_critical() ; -extern void __exit_critical(unsigned int) ; - -#define CRITICAL_STORE unsigned int __atom -#define CRITICAL_START() __atom = __enter_critical() -#define CRITICAL_END() __exit_critical(__atom) +#define CRITICAL_STORE unsigned int __atom_int_mask +#define CRITICAL_START() __atom_int_mask = atomvmInterruptMask(1) +#define CRITICAL_END() atomvmInterruptMask(__atom_int_mask) #define ATOM_TLS HATOMVM_CONTEXT context ; @@ -71,4 +59,4 @@ extern void archTimerTickIrqHandler () ; /* The instance of the atomvm for this port */ extern HATOMVM the_atomvm ; -#endif /* __ATOM_PORT_H */ +#endif /* __ATOM_PORT_H__ */ diff --git a/ports/atomvm/atomvm.c b/ports/atomvm/atomvm.c index 286428a..f6ff3a9 100644 --- a/ports/atomvm/atomvm.c +++ b/ports/atomvm/atomvm.c @@ -39,18 +39,21 @@ * * \b Function prototypes used for controlling the atom virtual machine: \n * - * \li atomvmCtrlInit(): . + * \li atomvmCtrlCreate(): . * \li atomvmCtrlRun(): . * \li atomvmCtrlIntRequest(): . * \li atomvmCtrlClose(): . * * \b Function prototypes for use by the atom virtual machine: \n * - * \li atomvmExitCritical(): . - * \li atomvmEnterCritical(): . + * \li atomvmInterruptMask(): . * \li atomvmContextCreate(): . * \li atomvmContextSwitch(): . * \li atomvmContextDesrtroy(): . + * \li atomvmWriteThreadId(): . + * \li atomvmReadThreadId(): . + * \li atomvmInterruptWait(): . + * \li atomvmGetVmId(): . * * \b Function prototypes to be implemted in the atom virtual machine: \n * @@ -67,8 +70,6 @@ #define CONTEXT_VM (CONTEXT_INTEGER | CONTEXT_CONTROL | CONTEXT_SEGMENTS) -#define ATOMVM_ATOMVM_PERF_COUNTER(patomvm, counter) (InterlockedIncrement(&patomvm->perf_counters.counter)) - /* Data types */ /* Forward declarations */ @@ -118,32 +119,6 @@ typedef struct ATOMVM_CALLBACK_CONTEXT_SWITCH_S { } ATOMVM_CALLBACK_CONTEXT_SWITCH, *PATOMVM_CALLBACK_CONTEXT_SWITCH ; -/* ATOMVM_CALLBACK_IPI is the parameter for a ATOMVM_CALLBACK_F call -that take as parameter a pointer to a ipi target and the isr to call */ -typedef struct ATOMVM_CALLBACK_IPI_S { - - ATOMVM_CALLBACK callback ; - - /* Parameters the callback function will operate on */ - volatile uint32_t target ; - volatile uint32_t isr ; - -} ATOMVM_CALLBACK_IPI, *PATOMVM_CALLBACK_IPI ; - -typedef struct ATOMVM_PERF_COUNTERS_S { - - /* Number of interrupt requests */ - uint32_t int_request ; - - /* Number of service calls (context switches and - context init from atom virtual machime) */ - uint32_t service_call ; - - /* Total number of context switches */ - uint32_t context_switch ; - -} ATOMVM_PERF_COUNTERS, *PATOMVM_PERF_COUNTERS ; - /* ATOMVM_CONTEXT saves the state of a context created by atomvmContextCreate() and sheduled by atomvmContextSwitch(). */ typedef struct ATOMVM_CONTEXT_S { @@ -152,18 +127,16 @@ typedef struct ATOMVM_CONTEXT_S { during context initialization and context switches */ CONTEXT context ; - /* When entering a critical section the critical_count is - incremented for the context. Interrupts will only occur while - the critical_count is zero. The functions atomvmExitCritical() - and atomvmEnterCritical() will respectively decrement and - increment the critical count */ - volatile uint32_t critical_count ; + /* When entering a critical section the interrupt_mask is + set for the context. Interrupts will only occur while + the interrupt_mask is zero. */ + volatile uint32_t interrupt_mask ; uint32_t thread_id ; } ATOMVM_CONTEXT, *PATOMVM_CONTEXT ; /* ATOMVM defines the state of an instance to an atomvm. It is created -by a call to atomvmCtrlInit(). */ +by a call to atomvmCtrlCreate(). */ typedef struct ATOMVM_S { uint32_t atomvm_id ; @@ -176,7 +149,6 @@ typedef struct ATOMVM_S { HANDLE atomvm_int ; HANDLE atomvm_int_complete ; HANDLE atomvm_close ; - HANDLE atomvm_event ; /* next ISR */ volatile void (*isr)(void) ; @@ -191,21 +163,15 @@ typedef struct ATOMVM_S { and, return value for the current service call */ PATOMVM_CALLBACK service_call ; - /* Context for startup, before any context was scheduled - (workaround to not check everytime if the first context - was already started) */ + /* Context for startup, before any context was scheduled */ ATOMVM_CONTEXT atom_init_context ; - /* Performance counters */ - volatile ATOMVM_PERF_COUNTERS perf_counters ; - } ATOMVM, *PATOMVM ; /* Global declarations */ -volatile uint32_t g_atomvm_counter = 0 ; -volatile DWORD g_atomvm_tls_idx ; -PATOMVM g_vms[ATOMVM_MAX_VM] ; +volatile uint32_t g_atomvm_id = 0 ; +volatile DWORD g_atomvm_tls_idx ; /* Forward declaration for the atom virtual machine thread */ @@ -214,57 +180,52 @@ static DWORD WINAPI vm_thread (LPVOID lpParameter) ; /** * \ingroup atomvm -* \b atomvmCtrlInit +* \b atomvmCtrlCreate * * This is an atomvm controll function used by a controlling thread * and must not be called from the atom virtual machine. * * Initializes the virtual machine. * -* ToDo: More Error checking. -* * @param[out] atomvm Handle to the virtual machine created. * * @return Zero on failure. */ uint32_t -atomvmCtrlInit (HATOMVM *atomvm) +atomvmCtrlCreate (HATOMVM *atomvm) { PATOMVM patomvm = 0 ; int32_t i ; - if (g_atomvm_counter < ATOMVM_MAX_VM) { + patomvm = (PATOMVM) malloc (sizeof(struct ATOMVM_S)) ; - patomvm = (PATOMVM) malloc (sizeof(struct ATOMVM_S)) ; + if (patomvm) { - if (patomvm) { + memset (patomvm, 0, sizeof(struct ATOMVM_S)) ; - memset (patomvm, 0, sizeof(struct ATOMVM_S)) ; - - patomvm->atomvm_id = InterlockedIncrement(&g_atomvm_counter) - 1 ; - - if (patomvm->atomvm_id == 0) { - g_atomvm_tls_idx = TlsAlloc () ; - for (i=0; iatomvm_id] = patomvm ; - - patomvm->atomvm_call = CreateEvent (NULL, TRUE, FALSE, 0) ; - patomvm->atomvm_int = CreateEvent (NULL, TRUE, FALSE, 0) ; - patomvm->atomvm_int_complete = CreateEvent (NULL, FALSE, TRUE, 0) ; - patomvm->atomvm_close = CreateEvent (NULL, TRUE, FALSE, 0) ; - patomvm->atomvm_event = CreateEvent (NULL, FALSE, FALSE, 0) ; - - patomvm->vm_thread = CreateThread (NULL, 0, vm_thread, (void*)patomvm, CREATE_SUSPENDED, NULL) ; - - patomvm->atom_init_context.critical_count = 1 ; - patomvm->current_context = &patomvm->atom_init_context ; - - *atomvm = (HATOMVM)patomvm ; + patomvm->atomvm_id = InterlockedIncrement(&g_atomvm_id) - 1 ; + if (patomvm->atomvm_id == 0) { + g_atomvm_tls_idx = TlsAlloc () ; } + + patomvm->atomvm_call = CreateEvent (NULL, TRUE, FALSE, 0) ; + patomvm->atomvm_int = CreateEvent (NULL, TRUE, FALSE, 0) ; + patomvm->atomvm_int_complete = CreateEvent (NULL, FALSE, TRUE, 0) ; + patomvm->atomvm_close = CreateEvent (NULL, TRUE, FALSE, 0) ; + + ATOMVM_ASSERT(patomvm->atomvm_call && patomvm->atomvm_int && patomvm->atomvm_int_complete && + patomvm->atomvm_close, _T("ResumeThread failed")) ; + + patomvm->vm_thread = CreateThread (NULL, 0, vm_thread, (void*)patomvm, CREATE_SUSPENDED, NULL) ; + + ATOMVM_ASSERT(patomvm->vm_thread, _T("CreateThread failed")) ; + + patomvm->atom_init_context.interrupt_mask = 1 ; + patomvm->current_context = &patomvm->atom_init_context ; + + *atomvm = (HATOMVM)patomvm ; + } return patomvm != 0 ; @@ -275,16 +236,13 @@ atomvmCtrlInit (HATOMVM *atomvm) * \ingroup atomvm * \b atomvmCtrlRun * -* This is an atomvm controll function used by a controlling thread -* and must not be called from the atom virtual machine. -* -* After a call to atomvmCtrlInit this function start the atom virtual machine. +* After a call to atomvmCtrlCreate this function start the atom virtual machine. * The calling thread will be used to manage interrupts and service calls in * the virtual machine. This function will not return untill atomvmCtrlClose * is called. * -* @param[in] atomvm Handle to the virtual machine created by atomvmCtrlInit. -* @param[in] flags Reserved for later use. +* @param[in] atomvm Handle to the virtual machine created by atomvmCtrlCreate. +* @param[in] flags not used. * * @return None */ @@ -299,9 +257,7 @@ atomvmCtrlRun (HATOMVM atomvm, uint32_t flags) #if defined DEBUG || defined _DEBUG BOOL tls_res = #endif - TlsSetValue (g_atomvm_tls_idx, (void*) atomvm) ; - - + TlsSetValue (g_atomvm_tls_idx, (void*) atomvm) ; ATOMVM_ASSERT(tls_res, _T("TlsSetValue failed")) ; ResumeThread (patomvm->vm_thread) ; @@ -316,8 +272,6 @@ atomvmCtrlRun (HATOMVM atomvm, uint32_t flags) if (wait_object == WAIT_OBJECT_0) { - ATOMVM_ATOMVM_PERF_COUNTER(patomvm, service_call) ; - service_call = patomvm->service_call ; while (!service_call->lock) { SwitchToThread () ; @@ -336,25 +290,23 @@ atomvmCtrlRun (HATOMVM atomvm, uint32_t flags) ResetEvent (patomvm->atomvm_call) ; res = ResumeThread (patomvm->vm_thread) ; ATOMVM_ASSERT(res == 1 , _T("ResumeThread failed")) ; - } else if (wait_object == WAIT_OBJECT_0 + 1) { - if (patomvm->current_context->critical_count == 0) { + if (patomvm->current_context->interrupt_mask == 0) { while ((res = SuspendThread (patomvm->vm_thread)) == (DWORD)-1) ; ATOMVM_ASSERT(res == 0 , _T("SuspendThread failed")) ; #if (_WIN32_WINNT >= 0x0600) /* This is used for multi processor machines to ensure the thread - is stopped before executing the next instruction. */ + is stopped before executing the next instruction. Set + _WIN32_WINNT < 0x0600 if you are running Windows XP */ FlushProcessWriteBuffers (); #endif - if (patomvm->current_context->critical_count == 0) { - - ATOMVM_ATOMVM_PERF_COUNTER(patomvm, int_request) ; + if (patomvm->current_context->interrupt_mask == 0) { patomvm->status_isr++ ; patomvm->isr () ; @@ -404,11 +356,11 @@ atomvmCtrlRun (HATOMVM atomvm, uint32_t flags) * and must not be called from the atom virtual machine. * * Closes the virtual machine and release all memory and handles created -* in atomvmCtrlInit. +* in atomvmCtrlCreate. * * ToDo: this function was never tested. * -* @param[in] atomvm Handle to the virtual machine created by atomvmCtrlInit. +* @param[in] atomvm Handle to the virtual machine created by atomvmCtrlCreate. * * @return None */ @@ -432,7 +384,7 @@ atomvmCtrlClose (HATOMVM atomvm) CloseHandle (patomvm->atomvm_close) ; CloseHandle (patomvm->vm_thread) ; - TlsFree (g_atomvm_tls_idx) ; + // TlsFree (g_atomvm_tls_idx) ; free (atomvm) ; } @@ -446,9 +398,9 @@ atomvmCtrlClose (HATOMVM atomvm) * an isr it is already in the conrtext of the controll thread and the callback * routine is called directly. * -* The atom virtual machine is suspended during the callback. +* The atom virtual machine thread is suspended during the callback. * -* @param[in] patomvm Pointer to the virtual machine created by atomvmCtrlInit. +* @param[in] patomvm Pointer to the virtual machine created by atomvmCtrlCreate. * @param[in] callback Callback function. * @param[in/out] context Context the function will operate on. * @@ -483,12 +435,12 @@ invokeCallback (PATOMVM patomvm, ATOMVM_CALLBACK_F callback, PATOMVM_CALLBACK se /* * \b getAtomvm * -* Get the atomvm instance for the calling thredd +* Get the atomvm instance for the calling thread * * @return atomvm instance */ __inline PATOMVM -getAtomvm () +getAtomvm (void) { PATOMVM patomvm = (PATOMVM) TlsGetValue (g_atomvm_tls_idx) ; @@ -498,76 +450,29 @@ getAtomvm () } - /** * \ingroup atomvm -* \b atomvmExitCritical +* \b atomvmInterruptMask * * This function is to be used by the atom virtual machine. * -* This function will decrement the critical count for the current atomvm context. -* When the critical count reaches zero, interrupts will be enabled again. Calling -* this function from inside an isr has no effect. +* This function will mask interrupts for the current atomvm context. * -* @return Critical count before the function call. +* @param[in] mask zero enables interrupts any other value masks interrupts. +* +* @return Interrupt mask before the function call. */ int32_t -atomvmExitCritical () +atomvmInterruptMask (uint32_t mask) { PATOMVM patomvm = getAtomvm () ; - int32_t count = 0; + int32_t interrupts = 0; if (patomvm->status_isr == 0) { - count = InterlockedDecrement (&patomvm->current_context->critical_count) ; + interrupts = InterlockedExchange (&patomvm->current_context->interrupt_mask, mask) ; } - return count ; -} - - -/** -* \ingroup atomvm -* \b atomvmEnterCritical -* -* This function is to be used by the atom virtual machine. -* -* This function will increment the critical count for the current atomvm -* context. Interrupts will be disabled when the critical count is not zero. -* Calling this function from inside an isr has no effect. -* -* All threads are created with a critical count of 1. -* -* -* @return Critical count before the function call. -*/ -int32_t -atomvmEnterCritical () -{ - PATOMVM patomvm = getAtomvm () ; - int32_t count = 0 ; - - if (patomvm->status_isr == 0) { - count = InterlockedIncrement (&patomvm->current_context->critical_count) ; - } - - return count ; -} - - -/** -* \ingroup atomvm -* \b atomvmCriticalCount -* -* Rerurns the critical cont of the current context. -* -* @return the critical cont of the current context. -*/ -int32_t -atomvmCriticalCount () -{ - PATOMVM patomvm = getAtomvm () ; - - return patomvm->current_context->critical_count ; + return interrupts ; } @@ -575,17 +480,17 @@ atomvmCriticalCount () * \ingroup atomvm * \b atomvmCtrlIntRequest * -* This is an atomvm controll function used by a controlling thread(s) +* This is an atomvm controll function used by external threads * and must not be called from the atom virtual machine. * * This function requests an interrupt service routine to be called in the * context of the atom virtual machine. * +* The call will return immediately after the interrupt was scheduled. * The call will block while a previously scheduled interrupt is in progress. * -* @param[in] atomvm Handle to the virtual machine created by atomvmCtrlInit. -* @param[in] isr The address of the interrupt service routine. The routine must use -* the default calling convention of the compiler. +* @param[in] atomvm Handle to the virtual machine created by atomvmCtrlCreate. +* @param[in] isr The address of the interrupt service routine. * * @return None */ @@ -610,7 +515,7 @@ atomvmCtrlIntRequest (HATOMVM atomvm, uint32_t isr) * * The atom virtual machine is suspended while this function is called. * -* @param[in] patomvm Pointer to the virtual machine created by atomvmCtrlInit. +* @param[in] patomvm Pointer to the virtual machine created by atomvmCtrlCreate. * @param[out] context Context to be initialized. * * @return Zero on failure, try to call GetLastError(). @@ -654,7 +559,7 @@ atomvmContextCreate (HATOMVM_CONTEXT* atomvm_context, uint32_t stack, uint32_t e context_init.pcontext = new_context ; - new_context->critical_count = 1 ; + new_context->interrupt_mask = 1 ; res = invokeCallback (patomvm, callbackContextCreate, (PATOMVM_CALLBACK)&context_init) ; @@ -676,7 +581,7 @@ atomvmContextCreate (HATOMVM_CONTEXT* atomvm_context, uint32_t stack, uint32_t e * * The atom virtual machine is suspended while this function is called. * -* @param[in] patomvm Pointer to the virtual machine created by atomvmCtrlInit. +* @param[in] patomvm Pointer to the virtual machine created by atomvmCtrlCreate. * @param[out] context Context to be scheduled. * * @return Zero on failure, try to call GetLastError(). @@ -690,8 +595,6 @@ callbackContextSwitch (PATOMVM patomvm, PATOMVM_CALLBACK callback) CONTEXT* p_old_context = &context_switch->p_old_context->context ; CONTEXT* p_new_context = &context_switch->p_new_context->context ; - ATOMVM_ATOMVM_PERF_COUNTER(patomvm, context_switch) ; - if (p_old_context) { res1 = GetThreadContext (patomvm->vm_thread, p_old_context) ; ATOMVM_ASSERT(res1 , _T("GetThreadContext failed")) ; @@ -783,7 +686,7 @@ atomvmWriteThreadId (uint32_t thread_id) * @return thread_id */ uint32_t -atomvmReadThreadId () +atomvmReadThreadId (void) { PATOMVM patomvm = getAtomvm () ; @@ -796,103 +699,18 @@ atomvmReadThreadId () * \b atomvmGetVmId * * Returns an identifier for the virtual machine. This is zero for the first -* virtual machine created with atomvmCtrlInit(), 1 for the second and so on. +* virtual machine created with atomvmCtrlCreate(), 1 for the second and so on. * * @return The atom vm ID */ uint32_t -atomvmGetVmId () +atomvmGetVmId (void) { PATOMVM patomvm = getAtomvm () ; return patomvm->atomvm_id ; } -/** -* \b callbackEventWait -* -* This function is invoked from the controll thread after a call to atomvmEventWait. -* -* The atom virtual machine is suspended while this function is called. -* -* @param[in] patomvm Pointer to the virtual machine created by atomvmCtrlInit. -* @param[out] context Context to be scheduled. -* -* @return Zero on failure, try to call GetLastError(). -*/ -uint32_t -callbackEventWait (PATOMVM patomvm, PATOMVM_CALLBACK callback) -{ - return WaitForSingleObject (patomvm->atomvm_event, INFINITE) == WAIT_OBJECT_0 ; -} - - -/** -* \ingroup atomvm -* \b atomvmEventWait -* -* This function is to be used by the atom virtual machine. -* -* This function if for synchronization between multiple -* atom vms. -* -* -* @return void. -*/ -void -atomvmEventWait () -{ - PATOMVM patomvm = getAtomvm () ; - ATOMVM_CALLBACK callback ; - - invokeCallback (patomvm, callbackEventWait, (PATOMVM_CALLBACK)&callback) ; -} - -/** -* \b callbackEventSend -* -* This function is invoked from the controll thread after a call to atomvmEventSend. -* -* The atom virtual machine is suspended while this function is called. -* -* @param[in] patomvm Pointer to the virtual machine created by atomvmCtrlInit. -* @param[out] context Context to be scheduled. -* -* @return Zero on failure, try to call GetLastError(). -*/ -uint32_t -callbackEventSend (PATOMVM patomvm, PATOMVM_CALLBACK callback) -{ - int32_t i ; - for (i=0; iatomvm_event) ; - } - } - - return 1 ; -} - -/** -* \ingroup atomvm -* \b atomvmEventSend -* -* This function is to be used by the atom virtual machine. -* -* This function if for synchronization between multiple -* atom vms. -* -* -* @return void. -*/ -void -atomvmEventSend () -{ - PATOMVM patomvm = getAtomvm () ; - ATOMVM_CALLBACK callback ; - - invokeCallback (patomvm, callbackEventSend, (PATOMVM_CALLBACK)&callback) ; -} /** * \b callbackInterruptWait @@ -901,7 +719,7 @@ atomvmEventSend () * * The atom virtual machine is suspended while this function is called. * -* @param[in] patomvm Pointer to the virtual machine created by atomvmCtrlInit. +* @param[in] patomvm Pointer to the virtual machine created by atomvmCtrlCreate. * @param[out] callback Callback parameter. * * @return Zero on failure, try to call GetLastError(). @@ -926,7 +744,7 @@ callbackInterruptWait (PATOMVM patomvm, PATOMVM_CALLBACK callback) * @return void. */ void -atomvmInterruptWait () +atomvmInterruptWait (void) { PATOMVM patomvm = getAtomvm () ; ATOMVM_CALLBACK callback ; @@ -934,66 +752,6 @@ atomvmInterruptWait () invokeCallback (patomvm, callbackInterruptWait, (PATOMVM_CALLBACK)&callback) ; } -/** -* \ingroup atomvm -* \b callbackScheduleIpi -* -* This function is invoked from the controll thread after a call to atomvmScheduleIpi(). -* -* This function if for synchronization between multiple -* atom vms. -* -* @param[in] target Target atomvm ID, less than ATOMVM_MAX_VM -* @param[in] isr interrupt service routine -* -* @return Zero on failure, try to call GetLastError(). -*/ -uint32_t -callbackScheduleIpi (PATOMVM patomvm, PATOMVM_CALLBACK callback) -{ - PATOMVM_CALLBACK_IPI callback_ipi = (PATOMVM_CALLBACK_IPI)callback ; - uint32_t res = 0 ; - - if ((callback_ipi->target < ATOMVM_MAX_VM) && - (g_vms[callback_ipi->target] != patomvm) ) { - - atomvmCtrlIntRequest ((HATOMVM)g_vms[callback_ipi->target], callback_ipi->isr) ; - res = 1 ; - - } - - return res ; -} - - -/** -* \ingroup atomvm -* \b atomvmScheduleIpi -* -* This function is to be used by the atom virtual machine. -* -* This function if for synchronization between multiple -* atom vms. -* -* @param[in] target Target atomvm ID -* @param[in] isr interrupt service routine -* -* @return Zero on failure, the vm is not running. -*/ -uint32_t -atomvmScheduleIpi (uint32_t target, uintptr_t isr) -{ - PATOMVM patomvm = getAtomvm () ; - ATOMVM_CALLBACK_IPI callback ; - - callback.target = target ; - callback.isr = isr ; - - return invokeCallback (patomvm, callbackScheduleIpi, (PATOMVM_CALLBACK)&callback) ; - - -} - /** * \b vm_thread diff --git a/ports/atomvm/atomvm.h b/ports/atomvm/atomvm.h index 0b61570..24e2a99 100644 --- a/ports/atomvm/atomvm.h +++ b/ports/atomvm/atomvm.h @@ -35,32 +35,26 @@ * @authors Natie van Rooyen * * @section intro Introduction -* Atomvm is a tiny virtual machine that can run on Windows inside an IDE with a -* debugger like Microsoft Visual C++ Express. The primary purpose of this virtual -* machine is for the evaluation of Real Time Operating Systems (like atomthreads) -* and the development and testing of modules for this Real Time Operating System -* in a user friendly environment.: +* Atomvm is a tiny virtual machine that runs on Windows and can be debugged +* from an IDE like Microsoft Visual C++ Express. The primary purpose of this +* virtual machine is for the evaluation of Real Time Operating Systems (like +* Atomthreads) and the development and testing of modules for this Real Time +* Operating System on a Windows machine. +* +* Atomvm makes use of the Windows API functions GetThreadContext() and +* SetThreadContext() to create multiple virtual contexts or threads inside a +* single Windows thread. Atomvm also simulates interrupts with an interrupt +* mask accessible from the Atomvm threads. External events can be queued as +* interrupts to Atomvm, for example a timer loop generating system timer tick +* interrupts for a Real Time Operating System ported to Atomvm. * -* @section build Building The Source -* To test this project, just add all the files from the "atomthreads/kernel" -* directory and the "atomthreads/ports/atomvm" directory as well as the test -* program main.c to your project. Add both the -* before mentioned directories to the include paths of your project and compile. \n -* Atomvm was designed for multi core systems but also runs fine on any single -* core system. -* -* @section test Running The Test -* The test, main.c, is intentioned to stress the virtual machine as opposed to -* testing the Real Time Operating System. However, this test can also run the -* unit tests of atomthreads by using the preprocessor directive "UNIT_TESTS" and -* linking in the desired unit test into the project. * */ #ifndef __ATOMVM_H__ #define __ATOMVM_H__ #include -#include "atomuser.h" +#include "types.h" #if defined _DEBUG || defined DEBUG @@ -75,7 +69,7 @@ /* Forward declarations */ /* This is an opaque handle to an instance of an atomvm created - by a call to atomvmCtrlInit() */ + by a call to atomvmCtrlCreate() */ typedef struct ATOMVM* HATOMVM ; /* This is an opaque handle to an atomvm context created @@ -84,40 +78,33 @@ typedef struct ATOMVM_CONTEXT* HATOMVM_CONTEXT ; /* Function prototypes used for controlling the atom virtual machine */ -extern uint32_t atomvmCtrlInit (HATOMVM* atomvm) ; +extern uint32_t atomvmCtrlCreate (HATOMVM* atomvm) ; extern void atomvmCtrlRun (HATOMVM atomvm, uint32_t flags) ; extern void atomvmCtrlIntRequest (HATOMVM atomvm, uintptr_t isr) ; extern void atomvmCtrlClose (HATOMVM atomvm) ; -/* Function prototypes for use by the atom virtual machine */ -extern int32_t atomvmExitCritical () ; -extern int32_t atomvmEnterCritical () ; -extern int32_t atomvmCriticalCount () ; +/* Function prototypes for use by the atom virtual machine from within the + call to __atomvmReset(). */ +extern int32_t atomvmInterruptMask (uint32_t mask) ; extern uint32_t atomvmContextCreate (HATOMVM_CONTEXT* context, uint32_t stack, uint32_t entry) ; extern uint32_t atomvmContextSwitch (HATOMVM_CONTEXT old_context, HATOMVM_CONTEXT new_context) ; extern void atomvmContextDesrtroy (HATOMVM_CONTEXT context) ; extern void atomvmWriteThreadId (uint32_t thread_id) ; -extern uint32_t atomvmReadThreadId () ; -/* Function prototypes for use by the atom virtual machine - for synchronization with other running atom virtual machines */ -extern uint32_t atomvmGetVmId () ; -extern void atomvmInterruptWait () ; -extern void atomvmEventWait () ; -extern void atomvmEventSend () ; -extern uint32_t atomvmScheduleIpi (uint32_t target, uintptr_t isr) ; - - +extern uint32_t atomvmReadThreadId (void) ; +extern void atomvmInterruptWait (void) ; +extern uint32_t atomvmGetVmId (void) ; /** * \ingroup atomvm * \b __atomvmReset * -* Function prototype to be implemted in the atom virtual machine +* Function prototype to be implemted as entry point for the atom virtual machine. * * @return void. */ extern void __atomvmReset (void) ; + /** * \ingroup atomvm * \b __atomvmClose diff --git a/ports/atomvm/test/main.c b/ports/atomvm/msvc/main.c similarity index 85% rename from ports/atomvm/test/main.c rename to ports/atomvm/msvc/main.c index 4bd4efb..28f78a8 100644 --- a/ports/atomvm/test/main.c +++ b/ports/atomvm/msvc/main.c @@ -1,270 +1,270 @@ -#include -#include - -#include "atom.h" -#include "atomvm.h" -#include "atomport.h" - - -// #define UNIT_TESTS -#ifdef UNIT_TESTS -extern uint32_t test_start (void) ; -#endif - -#define TEST_THREADS 47 - -#define TEST_STACK_BYTE_SIZE 0x10000 -#define IDLE_STACK_BYTE_SIZE 0x10000 -#define MONITOR_STACK_BYTE_SIZE 0x10000 - - - -static unsigned char idle_stack[IDLE_STACK_BYTE_SIZE] ; -static unsigned char monitor_stack[MONITOR_STACK_BYTE_SIZE] ; -static unsigned char test_stack[TEST_THREADS+1][TEST_STACK_BYTE_SIZE] ; -static unsigned int test_counter[TEST_THREADS+1] = {0} ; - -static unsigned int test2_counter = 0 ; -static unsigned int test3_counter = 0 ; -static unsigned int test_isr_count = 0 ; - - -static unsigned char test2_stack[TEST_STACK_BYTE_SIZE] ; -static unsigned char test3_stack[TEST_STACK_BYTE_SIZE] ; -static unsigned char test_idle_stack[TEST_STACK_BYTE_SIZE] ; - - -static uint8_t test_prio[60] = { - 001,010,100,200,250, 200,200,200,200,200, - 150,150,150,150,150, 250,250,250,250,250, - 101,102,103,104,105, 202,204,206,208,210, - 150,150,150,150,150, 250,250,250,250,250, - 121,122,123,124,125, 061,063,065,067,061, - 150,150,150,150,150, 250,250,250,250,250 - }; - -static uint32_t test_interv[60] = { - 001,001,001,001,001, 002,003,004,005,006, - 015,015,015,015,015, 025,024,023,022,021, - 905,005,005,005,805, 050,051,052,053,054, - 015,015,015,015,015, 025,024,023,022,021, - 030,030,030,030,030, 070,071,072,073,474, - 005,006,007,007,001, 001,001,003,003,005 - }; - - -ATOM_TCB test_tcb[TEST_THREADS+1] ; -ATOM_TCB monitor_tcb ; -ATOM_TCB test2_tcb ; -ATOM_TCB test3_tcb ; -ATOM_TCB test_idle_tcb ; - -DWORD WINAPI isr_thread_proc (LPVOID lpParameter) ; -static HANDLE isr_thread_1 ; -static HANDLE isr_thread_2 ; -static HANDLE isr_thread_3 ; -static HANDLE isr_thread_4 ; - -void -ipi_sr() -{ - printf("ipi\r\n") ; -} - -void -monitor_thread (uint32_t parm) -{ - CRITICAL_STORE; - int i ; - int c = 0 ; - ATOM_TCB *tcb ; - static unsigned int idle_1 = 0, idle_2 = 0, int_count = 0 ; - unsigned int delta_idle_1 , delta_idle_2 , delta_int_count ; - - tcb = atomCurrentContext() ; - - for (;;) - { - - CRITICAL_START(); - - printf("Monitor # %04d (%08d)\n", c++, atomTimeGet()) ; - printf("-------------------------\n") ; - - for (i=0; i +#include + +#include "atom.h" +#include "atomvm.h" +#include "atomport.h" + + +// #define UNIT_TESTS +#ifdef UNIT_TESTS +extern uint32_t test_start (void) ; +#endif + +#define TEST_THREADS 47 + +#define TEST_STACK_BYTE_SIZE 0x10000 +#define IDLE_STACK_BYTE_SIZE 0x10000 +#define MONITOR_STACK_BYTE_SIZE 0x10000 + + + +static unsigned char idle_stack[IDLE_STACK_BYTE_SIZE] ; +static unsigned char monitor_stack[MONITOR_STACK_BYTE_SIZE] ; +static unsigned char test_stack[TEST_THREADS+1][TEST_STACK_BYTE_SIZE] ; +static unsigned int test_counter[TEST_THREADS+1] = {0} ; + +static unsigned int test2_counter = 0 ; +static unsigned int test3_counter = 0 ; +static unsigned int test_isr_count = 0 ; + + +static unsigned char test2_stack[TEST_STACK_BYTE_SIZE] ; +static unsigned char test3_stack[TEST_STACK_BYTE_SIZE] ; +static unsigned char test_idle_stack[TEST_STACK_BYTE_SIZE] ; + + +static uint8_t test_prio[60] = { + 001,010,100,200,250, 200,200,200,200,200, + 150,150,150,150,150, 250,250,250,250,250, + 101,102,103,104,105, 202,204,206,208,210, + 150,150,150,150,150, 250,250,250,250,250, + 121,122,123,124,125, 061,063,065,067,061, + 150,150,150,150,150, 250,250,250,250,250 + }; + +static uint32_t test_interv[60] = { + 001,001,001,001,001, 002,003,004,005,006, + 015,015,015,015,015, 025,024,023,022,021, + 905,005,005,005,805, 050,051,052,053,054, + 015,015,015,015,015, 025,024,023,022,021, + 030,030,030,030,030, 070,071,072,073,474, + 005,006,007,007,001, 001,001,003,003,005 + }; + + +ATOM_TCB test_tcb[TEST_THREADS+1] ; +ATOM_TCB monitor_tcb ; +ATOM_TCB test2_tcb ; +ATOM_TCB test3_tcb ; +ATOM_TCB test_idle_tcb ; + +DWORD WINAPI isr_thread_proc (LPVOID lpParameter) ; +static HANDLE isr_thread_1 ; +static HANDLE isr_thread_2 ; +static HANDLE isr_thread_3 ; +static HANDLE isr_thread_4 ; + +void +ipi_sr() +{ + printf("ipi\r\n") ; +} + +void +monitor_thread (uint32_t parm) +{ + CRITICAL_STORE; + int i ; + int c = 0 ; + ATOM_TCB *tcb ; + static unsigned int idle_1 = 0, idle_2 = 0, int_count = 0 ; + unsigned int delta_idle_1 , delta_idle_2 , delta_int_count ; + + tcb = atomCurrentContext() ; + + for (;;) + { + + CRITICAL_START(); + + printf("Monitor # %04d (%08d)\n", c++, atomTimeGet()) ; + printf("-------------------------\n") ; + + for (i=0; i + + + + Debug + Win32 + + + Release + Win32 + + + + {77095EB1-4988-4A04-8751-69C63C7C541B} + Win32Proj + msvc + + + + Application + true + Unicode + + + Application + false + true + Unicode + + + + + + + + + + + + + true + $(MSBuildProjectDirectory)/../../../kernel;$(MSBuildProjectDirectory)/..;$(IncludePath) + + + false + $(MSBuildProjectDirectory)/..;$(MSBuildProjectDirectory)/../../../kernel;$(IncludePath) + + + + + + Level3 + Disabled + WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) + + + Console + true + + + + + Level3 + + + MaxSpeed + true + true + WIN32;NDEBUG;_CONSOLE;%(PreprocessorDefinitions) + + + Console + true + true + true + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/ports/atomvm/msvc/msvc.vcxproj.filters b/ports/atomvm/msvc/msvc.vcxproj.filters new file mode 100644 index 0000000..e719db8 --- /dev/null +++ b/ports/atomvm/msvc/msvc.vcxproj.filters @@ -0,0 +1,67 @@ + + + + + {d05cbb5a-256f-4127-bd5b-c3bd69b3672c} + + + {f30700d8-652d-477c-a4f2-d23e7784de50} + + + {a4f641bc-296d-4546-a831-2e1d0d7e9242} + + + + + atomthreads + + + atomthreads + + + atomthreads + + + atomthreads + + + atomthreads + + + port + + + port + + + port + + + atomvm + + + + + atomthreads + + + atomthreads + + + atomthreads + + + atomthreads + + + atomthreads + + + port + + + + atomvm + + + \ No newline at end of file diff --git a/ports/atomvm/atomuser.h b/ports/atomvm/types.h similarity index 96% rename from ports/atomvm/atomuser.h rename to ports/atomvm/types.h index c12374d..340133c 100644 --- a/ports/atomvm/atomuser.h +++ b/ports/atomvm/types.h @@ -1,63 +1,61 @@ -/* - * Copyright (c) 2010,Kelvin Lawson. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. No personal names or organizations' names associated with the - * Atomthreads project may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ -#if 1 -#ifndef __ATOM_USER_H__ -#define __ATOM_USER_H__ - - -/* Portable uint8_t and friends not available from stdint.h on this platform */ -#include - - -#define SYSTEM_MEMALIGN sizeof (unsigned int) - - -typedef unsigned int uintptr_t ; -typedef int intptr_t ; -typedef unsigned int uint32_t ; -typedef unsigned short uint16_t ; -typedef unsigned char uint8_t ; -typedef int int32_t ; -typedef short int16_t ; -typedef char int8_t ; - - -/** - * Architecture-specific types. - * Most of these are available from stdint.h on this platform, which is - * included above. - */ -#define POINTER void * - - -#define ATOM_TLS HATOMVM_CONTEXT context ; - - -#endif /* __ATOM_USER_H__ */ -#endif +/* + * Copyright (c) 2010,Kelvin Lawson. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. No personal names or organizations' names associated with the + * Atomthreads project may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __ATOM_USER_H__ +#define __ATOM_USER_H__ + + +/* Portable uint8_t and friends not available from stdint.h on this platform */ +#include + + +#define SYSTEM_MEMALIGN sizeof (unsigned int) + + +typedef unsigned int uintptr_t ; +typedef int intptr_t ; +typedef unsigned int uint32_t ; +typedef unsigned short uint16_t ; +typedef unsigned char uint8_t ; +typedef int int32_t ; +typedef short int16_t ; +typedef char int8_t ; + + +/** + * Architecture-specific types. + * Most of these are available from stdint.h on this platform, which is + * included above. + */ +#define POINTER void * + + +#define ATOM_TLS HATOMVM_CONTEXT context ; + + +#endif /* __ATOM_USER_H__ */ From 648d35dbe6598bc9322267a85db072ff065a1483 Mon Sep 17 00:00:00 2001 From: Natie van Rooyen Date: Tue, 23 Oct 2012 14:23:34 +0200 Subject: [PATCH 22/28] LPC17xx platform for Cortex M port --- .../docs/CMSIS END USER LICENCE AGREEMENT.pdf | Bin 0 -> 51511 bytes .../lpc17xx/CMSISv2p00_LPC17xx/inc/LPC17xx.h | 1035 ++++++++++++++ .../lpc17xx/CMSISv2p00_LPC17xx/inc/core_cm3.h | 1236 +++++++++++++++++ .../CMSISv2p00_LPC17xx/inc/core_cmFunc.h | 844 +++++++++++ .../CMSISv2p00_LPC17xx/inc/core_cmInstr.h | 775 +++++++++++ .../CMSISv2p00_LPC17xx/inc/system_LPC17xx.h | 64 + .../lpc17xx/CMSISv2p00_LPC17xx/src/core_cm3.c | 339 +++++ .../CMSISv2p00_LPC17xx/src/system_LPC17xx.c | 532 +++++++ platforms/lpc17xx/Makefile | 95 ++ platforms/lpc17xx/atomthreads_test.out | 153 ++ platforms/lpc17xx/drivers/lpc17xx.h | 1035 ++++++++++++++ platforms/lpc17xx/drivers/lpc17xx_uart.c | 166 +++ platforms/lpc17xx/drivers/lpc17xx_uart.h | 37 + platforms/lpc17xx/main.c | 116 ++ platforms/lpc17xx/modules.c | 178 +++ platforms/lpc17xx/modules.h | 46 + platforms/lpc17xx/startup.c | 295 ++++ platforms/lpc17xx/system.ld | 148 ++ 18 files changed, 7094 insertions(+) create mode 100644 platforms/lpc17xx/CMSISv2p00_LPC17xx/docs/CMSIS END USER LICENCE AGREEMENT.pdf create mode 100644 platforms/lpc17xx/CMSISv2p00_LPC17xx/inc/LPC17xx.h create mode 100644 platforms/lpc17xx/CMSISv2p00_LPC17xx/inc/core_cm3.h create mode 100644 platforms/lpc17xx/CMSISv2p00_LPC17xx/inc/core_cmFunc.h create mode 100644 platforms/lpc17xx/CMSISv2p00_LPC17xx/inc/core_cmInstr.h create mode 100644 platforms/lpc17xx/CMSISv2p00_LPC17xx/inc/system_LPC17xx.h create mode 100644 platforms/lpc17xx/CMSISv2p00_LPC17xx/src/core_cm3.c create mode 100644 platforms/lpc17xx/CMSISv2p00_LPC17xx/src/system_LPC17xx.c create mode 100644 platforms/lpc17xx/Makefile create mode 100644 platforms/lpc17xx/atomthreads_test.out create mode 100644 platforms/lpc17xx/drivers/lpc17xx.h create mode 100644 platforms/lpc17xx/drivers/lpc17xx_uart.c create mode 100644 platforms/lpc17xx/drivers/lpc17xx_uart.h create mode 100644 platforms/lpc17xx/main.c create mode 100644 platforms/lpc17xx/modules.c create mode 100644 platforms/lpc17xx/modules.h create mode 100644 platforms/lpc17xx/startup.c create mode 100644 platforms/lpc17xx/system.ld diff --git a/platforms/lpc17xx/CMSISv2p00_LPC17xx/docs/CMSIS END USER LICENCE AGREEMENT.pdf b/platforms/lpc17xx/CMSISv2p00_LPC17xx/docs/CMSIS END USER LICENCE AGREEMENT.pdf new file mode 100644 index 0000000000000000000000000000000000000000..e04afaee6286ce461b2ab5f286c6f99b232f5ae0 GIT binary patch literal 51511 zcma&MQ;;Q0)UH`ww%ujhwry)ybzzrn+h!NKY}>YN+qN;^f8v~pn3V5h0Q_&w ze}38ilk~rR%K>f8oXv^Y|CdM!3u|YfBcp`1p)*hnX#AgR0RbmxN1&k%0<3%H68~Bv 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  • x#e1h{baLP@AcAEbh($8fkN8HUQ;0!C|bj-I? zC3xCvDY2pY6K-#iix|4&WDlAW_cl$v;i`yLk&4OBOGEeDv-(0OzCASLaHO54{V;o^ zthF@f|61vhBCD5N6O1S4sl6{^dh7Az=!_-oQ(|;y&b??e*(!a1$Pwp99_Le^g-+9c zym8ag)duUk+MoVelHG9NjqTzWQ$M|47x4Z)*Ov9@~|3kA2U z#Yg|$S0(-X?cF@lYKD*R;^rQGxTval)0%USpDWI7o2#mH-fLQihgCr%yNTJt{o>!O zH!S?gmvbQe%|$WWr#;K>%$K*hHf{UcQvbixS>{dbWEU%c>~K-udu@TVtd6bpqvQ8K zZe3R=*AOk6yDoq6gsX+WU#7lUm(Qj(`PGW}iN_g2N(_4WKb%VX;LWuE^q~sbkoC#l z_ZhaZGW_57tc_oHnN_a+^3G4C!E?)M`8VF=y1DaB-r{3lZrk|BFSg~o9RBk_#uocs z7k6A+S0VFCy;A4yndGILjx)Uf9I?`%GH2~9n`;J7_8s3+bpGI%uIVQ)#siCyJmKHf zLg`n#-~QZYbu$0YtGn~-Ie$)G(sfwhZFBj*{mRcTV!PkN$O3VbM{s6Us)CUvwi`Xb zl|n>NYMQ=hUP@|3v;k0EtbTa3p@NZuVJxg>ur${X%FizWiWw*b0ad2uD;PqUF3~p0 zMyAQ8rpbn;X~}6xiK(du1}TXarY5Gz2IgsLsmVrmHl~*5i6+U(KygchB(o#~qtrA5 z!?e^?qZC5}6Z14vyIACEN3>@zuLFaG%l)6rCrwbuYGu_?+_qtktjeNIje;g#+&}g` zdU`Lmkb%*5(U&Px7CtQF@43)nvM1wSO}D9h#@ai=%2%xx)qa}isGE^8FFXFt&aL+( re}uiLx$yNPvx6y58kUYuaS5JcjE;B$L(NY literal 0 HcmV?d00001 diff --git a/platforms/lpc17xx/CMSISv2p00_LPC17xx/inc/LPC17xx.h b/platforms/lpc17xx/CMSISv2p00_LPC17xx/inc/LPC17xx.h new file mode 100644 index 0000000..377fdf2 --- /dev/null +++ b/platforms/lpc17xx/CMSISv2p00_LPC17xx/inc/LPC17xx.h @@ -0,0 +1,1035 @@ +/**************************************************************************//** + * @file LPC17xx.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for + * NXP LPC17xx Device Series + * @version: V1.09 + * @date: 17. March 2010 + + * + * @note + * Copyright (C) 2009 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + + +#ifndef __LPC17xx_H__ +#define __LPC17xx_H__ + +/* + * ========================================================================== + * ---------- Interrupt Number Definition ----------------------------------- + * ========================================================================== + */ + +typedef enum IRQn +{ +/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ + +/****** LPC17xx Specific Interrupt Numbers *******************************************************/ + WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */ + TIMER0_IRQn = 1, /*!< Timer0 Interrupt */ + TIMER1_IRQn = 2, /*!< Timer1 Interrupt */ + TIMER2_IRQn = 3, /*!< Timer2 Interrupt */ + TIMER3_IRQn = 4, /*!< Timer3 Interrupt */ + UART0_IRQn = 5, /*!< UART0 Interrupt */ + UART1_IRQn = 6, /*!< UART1 Interrupt */ + UART2_IRQn = 7, /*!< UART2 Interrupt */ + UART3_IRQn = 8, /*!< UART3 Interrupt */ + PWM1_IRQn = 9, /*!< PWM1 Interrupt */ + I2C0_IRQn = 10, /*!< I2C0 Interrupt */ + I2C1_IRQn = 11, /*!< I2C1 Interrupt */ + I2C2_IRQn = 12, /*!< I2C2 Interrupt */ + SPI_IRQn = 13, /*!< SPI Interrupt */ + SSP0_IRQn = 14, /*!< SSP0 Interrupt */ + SSP1_IRQn = 15, /*!< SSP1 Interrupt */ + PLL0_IRQn = 16, /*!< PLL0 Lock (Main PLL) Interrupt */ + RTC_IRQn = 17, /*!< Real Time Clock Interrupt */ + EINT0_IRQn = 18, /*!< External Interrupt 0 Interrupt */ + EINT1_IRQn = 19, /*!< External Interrupt 1 Interrupt */ + EINT2_IRQn = 20, /*!< External Interrupt 2 Interrupt */ + EINT3_IRQn = 21, /*!< External Interrupt 3 Interrupt */ + ADC_IRQn = 22, /*!< A/D Converter Interrupt */ + BOD_IRQn = 23, /*!< Brown-Out Detect Interrupt */ + USB_IRQn = 24, /*!< USB Interrupt */ + CAN_IRQn = 25, /*!< CAN Interrupt */ + DMA_IRQn = 26, /*!< General Purpose DMA Interrupt */ + I2S_IRQn = 27, /*!< I2S Interrupt */ + ENET_IRQn = 28, /*!< Ethernet Interrupt */ + RIT_IRQn = 29, /*!< Repetitive Interrupt Timer Interrupt */ + MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */ + QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */ + PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */ + USBActivity_IRQn = 33, /* USB Activity interrupt */ + CANActivity_IRQn = 34, /* CAN Activity interrupt */ +} IRQn_Type; + + +/* + * ========================================================================== + * ----------- Processor and Core Peripheral Section ------------------------ + * ========================================================================== + */ + +/* Configuration of the Cortex-M3 Processor and Core Peripherals */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + + +#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */ +#include "system_LPC17xx.h" /* System Header */ + + +/******************************************************************************/ +/* Device Specific Peripheral registers structures */ +/******************************************************************************/ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/*------------- System Control (SC) ------------------------------------------*/ +typedef struct +{ + __IO uint32_t FLASHCFG; /* Flash Accelerator Module */ + uint32_t RESERVED0[31]; + __IO uint32_t PLL0CON; /* Clocking and Power Control */ + __IO uint32_t PLL0CFG; + __I uint32_t PLL0STAT; + __O uint32_t PLL0FEED; + uint32_t RESERVED1[4]; + __IO uint32_t PLL1CON; + __IO uint32_t PLL1CFG; + __I uint32_t PLL1STAT; + __O uint32_t PLL1FEED; + uint32_t RESERVED2[4]; + __IO uint32_t PCON; + __IO uint32_t PCONP; + uint32_t RESERVED3[15]; + __IO uint32_t CCLKCFG; + __IO uint32_t USBCLKCFG; + __IO uint32_t CLKSRCSEL; + __IO uint32_t CANSLEEPCLR; + __IO uint32_t CANWAKEFLAGS; + uint32_t RESERVED4[10]; + __IO uint32_t EXTINT; /* External Interrupts */ + uint32_t RESERVED5; + __IO uint32_t EXTMODE; + __IO uint32_t EXTPOLAR; + uint32_t RESERVED6[12]; + __IO uint32_t RSID; /* Reset */ + uint32_t RESERVED7[7]; + __IO uint32_t SCS; /* Syscon Miscellaneous Registers */ + __IO uint32_t IRCTRIM; /* Clock Dividers */ + __IO uint32_t PCLKSEL0; + __IO uint32_t PCLKSEL1; + uint32_t RESERVED8[4]; + __IO uint32_t USBIntSt; /* USB Device/OTG Interrupt Register */ + __IO uint32_t DMAREQSEL; + __IO uint32_t CLKOUTCFG; /* Clock Output Configuration */ + } LPC_SC_TypeDef; + +/*------------- Pin Connect Block (PINCON) -----------------------------------*/ +typedef struct +{ + __IO uint32_t PINSEL0; + __IO uint32_t PINSEL1; + __IO uint32_t PINSEL2; + __IO uint32_t PINSEL3; + __IO uint32_t PINSEL4; + __IO uint32_t PINSEL5; + __IO uint32_t PINSEL6; + __IO uint32_t PINSEL7; + __IO uint32_t PINSEL8; + __IO uint32_t PINSEL9; + __IO uint32_t PINSEL10; + uint32_t RESERVED0[5]; + __IO uint32_t PINMODE0; + __IO uint32_t PINMODE1; + __IO uint32_t PINMODE2; + __IO uint32_t PINMODE3; + __IO uint32_t PINMODE4; + __IO uint32_t PINMODE5; + __IO uint32_t PINMODE6; + __IO uint32_t PINMODE7; + __IO uint32_t PINMODE8; + __IO uint32_t PINMODE9; + __IO uint32_t PINMODE_OD0; + __IO uint32_t PINMODE_OD1; + __IO uint32_t PINMODE_OD2; + __IO uint32_t PINMODE_OD3; + __IO uint32_t PINMODE_OD4; + __IO uint32_t I2CPADCFG; +} LPC_PINCON_TypeDef; + +/*------------- General Purpose Input/Output (GPIO) --------------------------*/ +typedef struct +{ + union { + __IO uint32_t FIODIR; + struct { + __IO uint16_t FIODIRL; + __IO uint16_t FIODIRH; + }; + struct { + __IO uint8_t FIODIR0; + __IO uint8_t FIODIR1; + __IO uint8_t FIODIR2; + __IO uint8_t FIODIR3; + }; + }; + uint32_t RESERVED0[3]; + union { + __IO uint32_t FIOMASK; + struct { + __IO uint16_t FIOMASKL; + __IO uint16_t FIOMASKH; + }; + struct { + __IO uint8_t FIOMASK0; + __IO uint8_t FIOMASK1; + __IO uint8_t FIOMASK2; + __IO uint8_t FIOMASK3; + }; + }; + union { + __IO uint32_t FIOPIN; + struct { + __IO uint16_t FIOPINL; + __IO uint16_t FIOPINH; + }; + struct { + __IO uint8_t FIOPIN0; + __IO uint8_t FIOPIN1; + __IO uint8_t FIOPIN2; + __IO uint8_t FIOPIN3; + }; + }; + union { + __IO uint32_t FIOSET; + struct { + __IO uint16_t FIOSETL; + __IO uint16_t FIOSETH; + }; + struct { + __IO uint8_t FIOSET0; + __IO uint8_t FIOSET1; + __IO uint8_t FIOSET2; + __IO uint8_t FIOSET3; + }; + }; + union { + __O uint32_t FIOCLR; + struct { + __O uint16_t FIOCLRL; + __O uint16_t FIOCLRH; + }; + struct { + __O uint8_t FIOCLR0; + __O uint8_t FIOCLR1; + __O uint8_t FIOCLR2; + __O uint8_t FIOCLR3; + }; + }; +} LPC_GPIO_TypeDef; + +typedef struct +{ + __I uint32_t IntStatus; + __I uint32_t IO0IntStatR; + __I uint32_t IO0IntStatF; + __O uint32_t IO0IntClr; + __IO uint32_t IO0IntEnR; + __IO uint32_t IO0IntEnF; + uint32_t RESERVED0[3]; + __I uint32_t IO2IntStatR; + __I uint32_t IO2IntStatF; + __O uint32_t IO2IntClr; + __IO uint32_t IO2IntEnR; + __IO uint32_t IO2IntEnF; +} LPC_GPIOINT_TypeDef; + +/*------------- Timer (TIM) --------------------------------------------------*/ +typedef struct +{ + __IO uint32_t IR; + __IO uint32_t TCR; + __IO uint32_t TC; + __IO uint32_t PR; + __IO uint32_t PC; + __IO uint32_t MCR; + __IO uint32_t MR0; + __IO uint32_t MR1; + __IO uint32_t MR2; + __IO uint32_t MR3; + __IO uint32_t CCR; + __I uint32_t CR0; + __I uint32_t CR1; + uint32_t RESERVED0[2]; + __IO uint32_t EMR; + uint32_t RESERVED1[12]; + __IO uint32_t CTCR; +} LPC_TIM_TypeDef; + +/*------------- Pulse-Width Modulation (PWM) ---------------------------------*/ +typedef struct +{ + __IO uint32_t IR; + __IO uint32_t TCR; + __IO uint32_t TC; + __IO uint32_t PR; + __IO uint32_t PC; + __IO uint32_t MCR; + __IO uint32_t MR0; + __IO uint32_t MR1; + __IO uint32_t MR2; + __IO uint32_t MR3; + __IO uint32_t CCR; + __I uint32_t CR0; + __I uint32_t CR1; + __I uint32_t CR2; + __I uint32_t CR3; + uint32_t RESERVED0; + __IO uint32_t MR4; + __IO uint32_t MR5; + __IO uint32_t MR6; + __IO uint32_t PCR; + __IO uint32_t LER; + uint32_t RESERVED1[7]; + __IO uint32_t CTCR; +} LPC_PWM_TypeDef; + +/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/ +typedef struct +{ + union { + __I uint8_t RBR; + __O uint8_t THR; + __IO uint8_t DLL; + uint32_t RESERVED0; + }; + union { + __IO uint8_t DLM; + __IO uint32_t IER; + }; + union { + __I uint32_t IIR; + __O uint8_t FCR; + }; + __IO uint8_t LCR; + uint8_t RESERVED1[7]; + __I uint8_t LSR; + uint8_t RESERVED2[7]; + __IO uint8_t SCR; + uint8_t RESERVED3[3]; + __IO uint32_t ACR; + __IO uint8_t ICR; + uint8_t RESERVED4[3]; + __IO uint8_t FDR; + uint8_t RESERVED5[7]; + __IO uint8_t TER; + uint8_t RESERVED6[39]; + __IO uint32_t FIFOLVL; +} LPC_UART_TypeDef; + +typedef struct +{ + union { + __I uint8_t RBR; + __O uint8_t THR; + __IO uint8_t DLL; + uint32_t RESERVED0; + }; + union { + __IO uint8_t DLM; + __IO uint32_t IER; + }; + union { + __I uint32_t IIR; + __O uint8_t FCR; + }; + __IO uint8_t LCR; + uint8_t RESERVED1[7]; + __I uint8_t LSR; + uint8_t RESERVED2[7]; + __IO uint8_t SCR; + uint8_t RESERVED3[3]; + __IO uint32_t ACR; + __IO uint8_t ICR; + uint8_t RESERVED4[3]; + __IO uint8_t FDR; + uint8_t RESERVED5[7]; + __IO uint8_t TER; + uint8_t RESERVED6[39]; + __IO uint32_t FIFOLVL; +} LPC_UART0_TypeDef; + +typedef struct +{ + union { + __I uint8_t RBR; + __O uint8_t THR; + __IO uint8_t DLL; + uint32_t RESERVED0; + }; + union { + __IO uint8_t DLM; + __IO uint32_t IER; + }; + union { + __I uint32_t IIR; + __O uint8_t FCR; + }; + __IO uint8_t LCR; + uint8_t RESERVED1[3]; + __IO uint8_t MCR; + uint8_t RESERVED2[3]; + __I uint8_t LSR; + uint8_t RESERVED3[3]; + __I uint8_t MSR; + uint8_t RESERVED4[3]; + __IO uint8_t SCR; + uint8_t RESERVED5[3]; + __IO uint32_t ACR; + uint32_t RESERVED6; + __IO uint32_t FDR; + uint32_t RESERVED7; + __IO uint8_t TER; + uint8_t RESERVED8[27]; + __IO uint8_t RS485CTRL; + uint8_t RESERVED9[3]; + __IO uint8_t ADRMATCH; + uint8_t RESERVED10[3]; + __IO uint8_t RS485DLY; + uint8_t RESERVED11[3]; + __IO uint32_t FIFOLVL; +} LPC_UART1_TypeDef; + +/*------------- Serial Peripheral Interface (SPI) ----------------------------*/ +typedef struct +{ + __IO uint32_t SPCR; + __I uint32_t SPSR; + __IO uint32_t SPDR; + __IO uint32_t SPCCR; + uint32_t RESERVED0[3]; + __IO uint32_t SPINT; +} LPC_SPI_TypeDef; + +/*------------- Synchronous Serial Communication (SSP) -----------------------*/ +typedef struct +{ + __IO uint32_t CR0; + __IO uint32_t CR1; + __IO uint32_t DR; + __I uint32_t SR; + __IO uint32_t CPSR; + __IO uint32_t IMSC; + __IO uint32_t RIS; + __IO uint32_t MIS; + __IO uint32_t ICR; + __IO uint32_t DMACR; +} LPC_SSP_TypeDef; + +/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/ +typedef struct +{ + __IO uint32_t I2CONSET; + __I uint32_t I2STAT; + __IO uint32_t I2DAT; + __IO uint32_t I2ADR0; + __IO uint32_t I2SCLH; + __IO uint32_t I2SCLL; + __O uint32_t I2CONCLR; + __IO uint32_t MMCTRL; + __IO uint32_t I2ADR1; + __IO uint32_t I2ADR2; + __IO uint32_t I2ADR3; + __I uint32_t I2DATA_BUFFER; + __IO uint32_t I2MASK0; + __IO uint32_t I2MASK1; + __IO uint32_t I2MASK2; + __IO uint32_t I2MASK3; +} LPC_I2C_TypeDef; + +/*------------- Inter IC Sound (I2S) -----------------------------------------*/ +typedef struct +{ + __IO uint32_t I2SDAO; + __IO uint32_t I2SDAI; + __O uint32_t I2STXFIFO; + __I uint32_t I2SRXFIFO; + __I uint32_t I2SSTATE; + __IO uint32_t I2SDMA1; + __IO uint32_t I2SDMA2; + __IO uint32_t I2SIRQ; + __IO uint32_t I2STXRATE; + __IO uint32_t I2SRXRATE; + __IO uint32_t I2STXBITRATE; + __IO uint32_t I2SRXBITRATE; + __IO uint32_t I2STXMODE; + __IO uint32_t I2SRXMODE; +} LPC_I2S_TypeDef; + +/*------------- Repetitive Interrupt Timer (RIT) -----------------------------*/ +typedef struct +{ + __IO uint32_t RICOMPVAL; + __IO uint32_t RIMASK; + __IO uint8_t RICTRL; + uint8_t RESERVED0[3]; + __IO uint32_t RICOUNTER; +} LPC_RIT_TypeDef; + +/*------------- Real-Time Clock (RTC) ----------------------------------------*/ +typedef struct +{ + __IO uint8_t ILR; + uint8_t RESERVED0[7]; + __IO uint8_t CCR; + uint8_t RESERVED1[3]; + __IO uint8_t CIIR; + uint8_t RESERVED2[3]; + __IO uint8_t AMR; + uint8_t RESERVED3[3]; + __I uint32_t CTIME0; + __I uint32_t CTIME1; + __I uint32_t CTIME2; + __IO uint8_t SEC; + uint8_t RESERVED4[3]; + __IO uint8_t MIN; + uint8_t RESERVED5[3]; + __IO uint8_t HOUR; + uint8_t RESERVED6[3]; + __IO uint8_t DOM; + uint8_t RESERVED7[3]; + __IO uint8_t DOW; + uint8_t RESERVED8[3]; + __IO uint16_t DOY; + uint16_t RESERVED9; + __IO uint8_t MONTH; + uint8_t RESERVED10[3]; + __IO uint16_t YEAR; + uint16_t RESERVED11; + __IO uint32_t CALIBRATION; + __IO uint32_t GPREG0; + __IO uint32_t GPREG1; + __IO uint32_t GPREG2; + __IO uint32_t GPREG3; + __IO uint32_t GPREG4; + __IO uint8_t RTC_AUXEN; + uint8_t RESERVED12[3]; + __IO uint8_t RTC_AUX; + uint8_t RESERVED13[3]; + __IO uint8_t ALSEC; + uint8_t RESERVED14[3]; + __IO uint8_t ALMIN; + uint8_t RESERVED15[3]; + __IO uint8_t ALHOUR; + uint8_t RESERVED16[3]; + __IO uint8_t ALDOM; + uint8_t RESERVED17[3]; + __IO uint8_t ALDOW; + uint8_t RESERVED18[3]; + __IO uint16_t ALDOY; + uint16_t RESERVED19; + __IO uint8_t ALMON; + uint8_t RESERVED20[3]; + __IO uint16_t ALYEAR; + uint16_t RESERVED21; +} LPC_RTC_TypeDef; + +/*------------- Watchdog Timer (WDT) -----------------------------------------*/ +typedef struct +{ + __IO uint8_t WDMOD; + uint8_t RESERVED0[3]; + __IO uint32_t WDTC; + __O uint8_t WDFEED; + uint8_t RESERVED1[3]; + __I uint32_t WDTV; + __IO uint32_t WDCLKSEL; +} LPC_WDT_TypeDef; + +/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/ +typedef struct +{ + __IO uint32_t ADCR; + __IO uint32_t ADGDR; + uint32_t RESERVED0; + __IO uint32_t ADINTEN; + __I uint32_t ADDR0; + __I uint32_t ADDR1; + __I uint32_t ADDR2; + __I uint32_t ADDR3; + __I uint32_t ADDR4; + __I uint32_t ADDR5; + __I uint32_t ADDR6; + __I uint32_t ADDR7; + __I uint32_t ADSTAT; + __IO uint32_t ADTRM; +} LPC_ADC_TypeDef; + +/*------------- Digital-to-Analog Converter (DAC) ----------------------------*/ +typedef struct +{ + __IO uint32_t DACR; + __IO uint32_t DACCTRL; + __IO uint16_t DACCNTVAL; +} LPC_DAC_TypeDef; + +/*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/ +typedef struct +{ + __I uint32_t MCCON; + __O uint32_t MCCON_SET; + __O uint32_t MCCON_CLR; + __I uint32_t MCCAPCON; + __O uint32_t MCCAPCON_SET; + __O uint32_t MCCAPCON_CLR; + __IO uint32_t MCTIM0; + __IO uint32_t MCTIM1; + __IO uint32_t MCTIM2; + __IO uint32_t MCPER0; + __IO uint32_t MCPER1; + __IO uint32_t MCPER2; + __IO uint32_t MCPW0; + __IO uint32_t MCPW1; + __IO uint32_t MCPW2; + __IO uint32_t MCDEADTIME; + __IO uint32_t MCCCP; + __IO uint32_t MCCR0; + __IO uint32_t MCCR1; + __IO uint32_t MCCR2; + __I uint32_t MCINTEN; + __O uint32_t MCINTEN_SET; + __O uint32_t MCINTEN_CLR; + __I uint32_t MCCNTCON; + __O uint32_t MCCNTCON_SET; + __O uint32_t MCCNTCON_CLR; + __I uint32_t MCINTFLAG; + __O uint32_t MCINTFLAG_SET; + __O uint32_t MCINTFLAG_CLR; + __O uint32_t MCCAP_CLR; +} LPC_MCPWM_TypeDef; + +/*------------- Quadrature Encoder Interface (QEI) ---------------------------*/ +typedef struct +{ + __O uint32_t QEICON; + __I uint32_t QEISTAT; + __IO uint32_t QEICONF; + __I uint32_t QEIPOS; + __IO uint32_t QEIMAXPOS; + __IO uint32_t CMPOS0; + __IO uint32_t CMPOS1; + __IO uint32_t CMPOS2; + __I uint32_t INXCNT; + __IO uint32_t INXCMP; + __IO uint32_t QEILOAD; + __I uint32_t QEITIME; + __I uint32_t QEIVEL; + __I uint32_t QEICAP; + __IO uint32_t VELCOMP; + __IO uint32_t FILTER; + uint32_t RESERVED0[998]; + __O uint32_t QEIIEC; + __O uint32_t QEIIES; + __I uint32_t QEIINTSTAT; + __I uint32_t QEIIE; + __O uint32_t QEICLR; + __O uint32_t QEISET; +} LPC_QEI_TypeDef; + +/*------------- Controller Area Network (CAN) --------------------------------*/ +typedef struct +{ + __IO uint32_t mask[512]; /* ID Masks */ +} LPC_CANAF_RAM_TypeDef; + +typedef struct /* Acceptance Filter Registers */ +{ + __IO uint32_t AFMR; + __IO uint32_t SFF_sa; + __IO uint32_t SFF_GRP_sa; + __IO uint32_t EFF_sa; + __IO uint32_t EFF_GRP_sa; + __IO uint32_t ENDofTable; + __I uint32_t LUTerrAd; + __I uint32_t LUTerr; + __IO uint32_t FCANIE; + __IO uint32_t FCANIC0; + __IO uint32_t FCANIC1; +} LPC_CANAF_TypeDef; + +typedef struct /* Central Registers */ +{ + __I uint32_t CANTxSR; + __I uint32_t CANRxSR; + __I uint32_t CANMSR; +} LPC_CANCR_TypeDef; + +typedef struct /* Controller Registers */ +{ + __IO uint32_t MOD; + __O uint32_t CMR; + __IO uint32_t GSR; + __I uint32_t ICR; + __IO uint32_t IER; + __IO uint32_t BTR; + __IO uint32_t EWL; + __I uint32_t SR; + __IO uint32_t RFS; + __IO uint32_t RID; + __IO uint32_t RDA; + __IO uint32_t RDB; + __IO uint32_t TFI1; + __IO uint32_t TID1; + __IO uint32_t TDA1; + __IO uint32_t TDB1; + __IO uint32_t TFI2; + __IO uint32_t TID2; + __IO uint32_t TDA2; + __IO uint32_t TDB2; + __IO uint32_t TFI3; + __IO uint32_t TID3; + __IO uint32_t TDA3; + __IO uint32_t TDB3; +} LPC_CAN_TypeDef; + +/*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/ +typedef struct /* Common Registers */ +{ + __I uint32_t DMACIntStat; + __I uint32_t DMACIntTCStat; + __O uint32_t DMACIntTCClear; + __I uint32_t DMACIntErrStat; + __O uint32_t DMACIntErrClr; + __I uint32_t DMACRawIntTCStat; + __I uint32_t DMACRawIntErrStat; + __I uint32_t DMACEnbldChns; + __IO uint32_t DMACSoftBReq; + __IO uint32_t DMACSoftSReq; + __IO uint32_t DMACSoftLBReq; + __IO uint32_t DMACSoftLSReq; + __IO uint32_t DMACConfig; + __IO uint32_t DMACSync; +} LPC_GPDMA_TypeDef; + +typedef struct /* Channel Registers */ +{ + __IO uint32_t DMACCSrcAddr; + __IO uint32_t DMACCDestAddr; + __IO uint32_t DMACCLLI; + __IO uint32_t DMACCControl; + __IO uint32_t DMACCConfig; +} LPC_GPDMACH_TypeDef; + +/*------------- Universal Serial Bus (USB) -----------------------------------*/ +typedef struct +{ + __I uint32_t HcRevision; /* USB Host Registers */ + __IO uint32_t HcControl; + __IO uint32_t HcCommandStatus; + __IO uint32_t HcInterruptStatus; + __IO uint32_t HcInterruptEnable; + __IO uint32_t HcInterruptDisable; + __IO uint32_t HcHCCA; + __I uint32_t HcPeriodCurrentED; + __IO uint32_t HcControlHeadED; + __IO uint32_t HcControlCurrentED; + __IO uint32_t HcBulkHeadED; + __IO uint32_t HcBulkCurrentED; + __I uint32_t HcDoneHead; + __IO uint32_t HcFmInterval; + __I uint32_t HcFmRemaining; + __I uint32_t HcFmNumber; + __IO uint32_t HcPeriodicStart; + __IO uint32_t HcLSTreshold; + __IO uint32_t HcRhDescriptorA; + __IO uint32_t HcRhDescriptorB; + __IO uint32_t HcRhStatus; + __IO uint32_t HcRhPortStatus1; + __IO uint32_t HcRhPortStatus2; + uint32_t RESERVED0[40]; + __I uint32_t Module_ID; + + __I uint32_t OTGIntSt; /* USB On-The-Go Registers */ + __IO uint32_t OTGIntEn; + __O uint32_t OTGIntSet; + __O uint32_t OTGIntClr; + __IO uint32_t OTGStCtrl; + __IO uint32_t OTGTmr; + uint32_t RESERVED1[58]; + + __I uint32_t USBDevIntSt; /* USB Device Interrupt Registers */ + __IO uint32_t USBDevIntEn; + __O uint32_t USBDevIntClr; + __O uint32_t USBDevIntSet; + + __O uint32_t USBCmdCode; /* USB Device SIE Command Registers */ + __I uint32_t USBCmdData; + + __I uint32_t USBRxData; /* USB Device Transfer Registers */ + __O uint32_t USBTxData; + __I uint32_t USBRxPLen; + __O uint32_t USBTxPLen; + __IO uint32_t USBCtrl; + __O uint32_t USBDevIntPri; + + __I uint32_t USBEpIntSt; /* USB Device Endpoint Interrupt Regs */ + __IO uint32_t USBEpIntEn; + __O uint32_t USBEpIntClr; + __O uint32_t USBEpIntSet; + __O uint32_t USBEpIntPri; + + __IO uint32_t USBReEp; /* USB Device Endpoint Realization Reg*/ + __O uint32_t USBEpInd; + __IO uint32_t USBMaxPSize; + + __I uint32_t USBDMARSt; /* USB Device DMA Registers */ + __O uint32_t USBDMARClr; + __O uint32_t USBDMARSet; + uint32_t RESERVED2[9]; + __IO uint32_t USBUDCAH; + __I uint32_t USBEpDMASt; + __O uint32_t USBEpDMAEn; + __O uint32_t USBEpDMADis; + __I uint32_t USBDMAIntSt; + __IO uint32_t USBDMAIntEn; + uint32_t RESERVED3[2]; + __I uint32_t USBEoTIntSt; + __O uint32_t USBEoTIntClr; + __O uint32_t USBEoTIntSet; + __I uint32_t USBNDDRIntSt; + __O uint32_t USBNDDRIntClr; + __O uint32_t USBNDDRIntSet; + __I uint32_t USBSysErrIntSt; + __O uint32_t USBSysErrIntClr; + __O uint32_t USBSysErrIntSet; + uint32_t RESERVED4[15]; + + union { + __I uint32_t I2C_RX; /* USB OTG I2C Registers */ + __O uint32_t I2C_TX; + }; + __I uint32_t I2C_STS; + __IO uint32_t I2C_CTL; + __IO uint32_t I2C_CLKHI; + __O uint32_t I2C_CLKLO; + uint32_t RESERVED5[824]; + + union { + __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */ + __IO uint32_t OTGClkCtrl; + }; + union { + __I uint32_t USBClkSt; + __I uint32_t OTGClkSt; + }; +} LPC_USB_TypeDef; + +/*------------- Ethernet Media Access Controller (EMAC) ----------------------*/ +typedef struct +{ + __IO uint32_t MAC1; /* MAC Registers */ + __IO uint32_t MAC2; + __IO uint32_t IPGT; + __IO uint32_t IPGR; + __IO uint32_t CLRT; + __IO uint32_t MAXF; + __IO uint32_t SUPP; + __IO uint32_t TEST; + __IO uint32_t MCFG; + __IO uint32_t MCMD; + __IO uint32_t MADR; + __O uint32_t MWTD; + __I uint32_t MRDD; + __I uint32_t MIND; + uint32_t RESERVED0[2]; + __IO uint32_t SA0; + __IO uint32_t SA1; + __IO uint32_t SA2; + uint32_t RESERVED1[45]; + __IO uint32_t Command; /* Control Registers */ + __I uint32_t Status; + __IO uint32_t RxDescriptor; + __IO uint32_t RxStatus; + __IO uint32_t RxDescriptorNumber; + __I uint32_t RxProduceIndex; + __IO uint32_t RxConsumeIndex; + __IO uint32_t TxDescriptor; + __IO uint32_t TxStatus; + __IO uint32_t TxDescriptorNumber; + __IO uint32_t TxProduceIndex; + __I uint32_t TxConsumeIndex; + uint32_t RESERVED2[10]; + __I uint32_t TSV0; + __I uint32_t TSV1; + __I uint32_t RSV; + uint32_t RESERVED3[3]; + __IO uint32_t FlowControlCounter; + __I uint32_t FlowControlStatus; + uint32_t RESERVED4[34]; + __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */ + __IO uint32_t RxFilterWoLStatus; + __IO uint32_t RxFilterWoLClear; + uint32_t RESERVED5; + __IO uint32_t HashFilterL; + __IO uint32_t HashFilterH; + uint32_t RESERVED6[882]; + __I uint32_t IntStatus; /* Module Control Registers */ + __IO uint32_t IntEnable; + __O uint32_t IntClear; + __O uint32_t IntSet; + uint32_t RESERVED7; + __IO uint32_t PowerDown; + uint32_t RESERVED8; + __IO uint32_t Module_ID; +} LPC_EMAC_TypeDef; + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + + +/******************************************************************************/ +/* Peripheral memory map */ +/******************************************************************************/ +/* Base addresses */ +#define LPC_FLASH_BASE (0x00000000UL) +#define LPC_RAM_BASE (0x10000000UL) +#define LPC_GPIO_BASE (0x2009C000UL) +#define LPC_APB0_BASE (0x40000000UL) +#define LPC_APB1_BASE (0x40080000UL) +#define LPC_AHB_BASE (0x50000000UL) +#define LPC_CM3_BASE (0xE0000000UL) + +/* APB0 peripherals */ +#define LPC_WDT_BASE (LPC_APB0_BASE + 0x00000) +#define LPC_TIM0_BASE (LPC_APB0_BASE + 0x04000) +#define LPC_TIM1_BASE (LPC_APB0_BASE + 0x08000) +#define LPC_UART0_BASE (LPC_APB0_BASE + 0x0C000) +#define LPC_UART1_BASE (LPC_APB0_BASE + 0x10000) +#define LPC_PWM1_BASE (LPC_APB0_BASE + 0x18000) +#define LPC_I2C0_BASE (LPC_APB0_BASE + 0x1C000) +#define LPC_SPI_BASE (LPC_APB0_BASE + 0x20000) +#define LPC_RTC_BASE (LPC_APB0_BASE + 0x24000) +#define LPC_GPIOINT_BASE (LPC_APB0_BASE + 0x28080) +#define LPC_PINCON_BASE (LPC_APB0_BASE + 0x2C000) +#define LPC_SSP1_BASE (LPC_APB0_BASE + 0x30000) +#define LPC_ADC_BASE (LPC_APB0_BASE + 0x34000) +#define LPC_CANAF_RAM_BASE (LPC_APB0_BASE + 0x38000) +#define LPC_CANAF_BASE (LPC_APB0_BASE + 0x3C000) +#define LPC_CANCR_BASE (LPC_APB0_BASE + 0x40000) +#define LPC_CAN1_BASE (LPC_APB0_BASE + 0x44000) +#define LPC_CAN2_BASE (LPC_APB0_BASE + 0x48000) +#define LPC_I2C1_BASE (LPC_APB0_BASE + 0x5C000) + +/* APB1 peripherals */ +#define LPC_SSP0_BASE (LPC_APB1_BASE + 0x08000) +#define LPC_DAC_BASE (LPC_APB1_BASE + 0x0C000) +#define LPC_TIM2_BASE (LPC_APB1_BASE + 0x10000) +#define LPC_TIM3_BASE (LPC_APB1_BASE + 0x14000) +#define LPC_UART2_BASE (LPC_APB1_BASE + 0x18000) +#define LPC_UART3_BASE (LPC_APB1_BASE + 0x1C000) +#define LPC_I2C2_BASE (LPC_APB1_BASE + 0x20000) +#define LPC_I2S_BASE (LPC_APB1_BASE + 0x28000) +#define LPC_RIT_BASE (LPC_APB1_BASE + 0x30000) +#define LPC_MCPWM_BASE (LPC_APB1_BASE + 0x38000) +#define LPC_QEI_BASE (LPC_APB1_BASE + 0x3C000) +#define LPC_SC_BASE (LPC_APB1_BASE + 0x7C000) + +/* AHB peripherals */ +#define LPC_EMAC_BASE (LPC_AHB_BASE + 0x00000) +#define LPC_GPDMA_BASE (LPC_AHB_BASE + 0x04000) +#define LPC_GPDMACH0_BASE (LPC_AHB_BASE + 0x04100) +#define LPC_GPDMACH1_BASE (LPC_AHB_BASE + 0x04120) +#define LPC_GPDMACH2_BASE (LPC_AHB_BASE + 0x04140) +#define LPC_GPDMACH3_BASE (LPC_AHB_BASE + 0x04160) +#define LPC_GPDMACH4_BASE (LPC_AHB_BASE + 0x04180) +#define LPC_GPDMACH5_BASE (LPC_AHB_BASE + 0x041A0) +#define LPC_GPDMACH6_BASE (LPC_AHB_BASE + 0x041C0) +#define LPC_GPDMACH7_BASE (LPC_AHB_BASE + 0x041E0) +#define LPC_USB_BASE (LPC_AHB_BASE + 0x0C000) + +/* GPIOs */ +#define LPC_GPIO0_BASE (LPC_GPIO_BASE + 0x00000) +#define LPC_GPIO1_BASE (LPC_GPIO_BASE + 0x00020) +#define LPC_GPIO2_BASE (LPC_GPIO_BASE + 0x00040) +#define LPC_GPIO3_BASE (LPC_GPIO_BASE + 0x00060) +#define LPC_GPIO4_BASE (LPC_GPIO_BASE + 0x00080) + + +/******************************************************************************/ +/* Peripheral declaration */ +/******************************************************************************/ +#define LPC_SC ((LPC_SC_TypeDef *) LPC_SC_BASE ) +#define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE ) +#define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE ) +#define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE ) +#define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE ) +#define LPC_GPIO4 ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE ) +#define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE ) +#define LPC_TIM0 ((LPC_TIM_TypeDef *) LPC_TIM0_BASE ) +#define LPC_TIM1 ((LPC_TIM_TypeDef *) LPC_TIM1_BASE ) +#define LPC_TIM2 ((LPC_TIM_TypeDef *) LPC_TIM2_BASE ) +#define LPC_TIM3 ((LPC_TIM_TypeDef *) LPC_TIM3_BASE ) +#define LPC_RIT ((LPC_RIT_TypeDef *) LPC_RIT_BASE ) +#define LPC_UART0 ((LPC_UART0_TypeDef *) LPC_UART0_BASE ) +#define LPC_UART1 ((LPC_UART1_TypeDef *) LPC_UART1_BASE ) +#define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE ) +#define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE ) +#define LPC_PWM1 ((LPC_PWM_TypeDef *) LPC_PWM1_BASE ) +#define LPC_I2C0 ((LPC_I2C_TypeDef *) LPC_I2C0_BASE ) +#define LPC_I2C1 ((LPC_I2C_TypeDef *) LPC_I2C1_BASE ) +#define LPC_I2C2 ((LPC_I2C_TypeDef *) LPC_I2C2_BASE ) +#define LPC_I2S ((LPC_I2S_TypeDef *) LPC_I2S_BASE ) +#define LPC_SPI ((LPC_SPI_TypeDef *) LPC_SPI_BASE ) +#define LPC_RTC ((LPC_RTC_TypeDef *) LPC_RTC_BASE ) +#define LPC_GPIOINT ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE ) +#define LPC_PINCON ((LPC_PINCON_TypeDef *) LPC_PINCON_BASE ) +#define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE ) +#define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE ) +#define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE ) +#define LPC_DAC ((LPC_DAC_TypeDef *) LPC_DAC_BASE ) +#define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE) +#define LPC_CANAF ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE ) +#define LPC_CANCR ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE ) +#define LPC_CAN1 ((LPC_CAN_TypeDef *) LPC_CAN1_BASE ) +#define LPC_CAN2 ((LPC_CAN_TypeDef *) LPC_CAN2_BASE ) +#define LPC_MCPWM ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE ) +#define LPC_QEI ((LPC_QEI_TypeDef *) LPC_QEI_BASE ) +#define LPC_EMAC ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE ) +#define LPC_GPDMA ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE ) +#define LPC_GPDMACH0 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE ) +#define LPC_GPDMACH1 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE ) +#define LPC_GPDMACH2 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE ) +#define LPC_GPDMACH3 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE ) +#define LPC_GPDMACH4 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE ) +#define LPC_GPDMACH5 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE ) +#define LPC_GPDMACH6 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE ) +#define LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE ) +#define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE ) + +#endif // __LPC17xx_H__ diff --git a/platforms/lpc17xx/CMSISv2p00_LPC17xx/inc/core_cm3.h b/platforms/lpc17xx/CMSISv2p00_LPC17xx/inc/core_cm3.h new file mode 100644 index 0000000..a2b29ee --- /dev/null +++ b/platforms/lpc17xx/CMSISv2p00_LPC17xx/inc/core_cm3.h @@ -0,0 +1,1236 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V2.01 + * @date 06. December 2010 + * + * @note + * Copyright (C) 2009-2010 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + + +/** \mainpage CMSIS Cortex-M3 + + This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer. + It consists of: + + - Cortex-M Core Register Definitions + - Cortex-M functions + - Cortex-M instructions + + The CMSIS Cortex-M3 Core Peripheral Access Layer contains C and assembly functions that ease + access to the Cortex-M Core + */ + +/** \defgroup CMSIS_LintCinfiguration CMSIS Lint Configuration + List of Lint messages which will be suppressed and not shown: + - not yet checked + . + Note: To re-enable a Message, insert a space before 'lint' * + + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \defgroup CMSIS_core_definitions CMSIS Core Definitions + This file defines all structures and symbols for CMSIS core: + - CMSIS version number + - Cortex-M core + - Cortex-M core Revision Number + @{ + */ + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (0x02) /*!< [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x03) /*!< Cortex core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + +#endif + +#include /*!< standard types definitions */ +#include "core_cmInstr.h" /*!< Core Instruction Access */ +#include "core_cmFunc.h" /*!< Core Function Access */ + +#endif /* __CORE_CM3_H_GENERIC */ + + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +/* IO definitions (access restrictions to peripheral registers) */ +#ifdef __cplusplus + #define __I volatile /*!< defines 'read only' permissions */ +#else + #define __I volatile const /*!< defines 'read only' permissions */ +#endif +#define __O volatile /*!< defines 'write only' permissions */ +#define __IO volatile /*!< defines 'read / write' permissions */ + +/*@} end of group CMSIS_core_definitions */ + + + +/******************************************************************************* + * Register Abstraction + ******************************************************************************/ +/** \defgroup CMSIS_core_register CMSIS Core Register + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE CMSIS Core + Type definitions for the Cortex-M Core Registers + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC CMSIS NVIC + Type definitions for the Cortex-M NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB CMSIS SCB + Type definitions for the Cortex-M System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPU ID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt / Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) Hard Fault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) Mem Manage Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) Bus Fault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) ISA Feature Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick CMSIS SysTick + Type definitions for the Cortex-M System Timer Registers + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_ITM CMSIS ITM + Type definitions for the Cortex-M Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __IO uint32_t IWR; /*!< Offset: (R/W) ITM Integration Write Register */ + __IO uint32_t IRR; /*!< Offset: (R/W) ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __IO uint32_t LAR; /*!< Offset: (R/W) ITM Lock Access Register */ + __IO uint32_t LSR; /*!< Offset: (R/W) ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: (R/ ) ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: (R/ ) ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: (R/ ) ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: (R/ ) ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: (R/ ) ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: (R/ ) ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: (R/ ) ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: (R/ ) ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: (R/ ) ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: (R/ ) ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: (R/ ) ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_ATBID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_ATBID_Msk (0x7FUL << ITM_TCR_ATBID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_InterruptType CMSIS Interrupt Type + Type definitions for the Cortex-M Interrupt Type Register + @{ + */ + +/** \brief Structure type to access the Interrupt Type Register. + */ +typedef struct +{ + uint32_t RESERVED0; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Control Type Register */ +#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1; +#endif +} InterruptType_Type; + +/* Interrupt Controller Type Register Definitions */ +#define IntType_ICTR_INTLINESNUM_Pos 0 /*!< InterruptType ICTR: INTLINESNUM Position */ +#define IntType_ICTR_INTLINESNUM_Msk (0x1FUL << IntType_ICTR_INTLINESNUM_Pos) /*!< InterruptType ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define IntType_ACTLR_DISFOLD_Pos 2 /*!< InterruptType ACTLR: DISFOLD Position */ +#define IntType_ACTLR_DISFOLD_Msk (1UL << IntType_ACTLR_DISFOLD_Pos) /*!< InterruptType ACTLR: DISFOLD Mask */ + +#define IntType_ACTLR_DISDEFWBUF_Pos 1 /*!< InterruptType ACTLR: DISDEFWBUF Position */ +#define IntType_ACTLR_DISDEFWBUF_Msk (1UL << IntType_ACTLR_DISDEFWBUF_Pos) /*!< InterruptType ACTLR: DISDEFWBUF Mask */ + +#define IntType_ACTLR_DISMCYCINT_Pos 0 /*!< InterruptType ACTLR: DISMCYCINT Position */ +#define IntType_ACTLR_DISMCYCINT_Msk (1UL << IntType_ACTLR_DISMCYCINT_Pos) /*!< InterruptType ACTLR: DISMCYCINT Mask */ + +/*@}*/ /* end of group CMSIS_InterruptType */ + + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU CMSIS MPU + Type definitions for the Cortex-M Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: AP Position */ +#define MPU_RASR_AP_Msk (7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: TEX Position */ +#define MPU_RASR_TEX_Msk (7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: Shareable bit Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: Shareable bit Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: Cacheable bit Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: Cacheable bit Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: Bufferable bit Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: Bufferable bit Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENA_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENA_Msk (0x1UL << MPU_RASR_ENA_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug CMSIS Core Debug + Type definitions for the Cortex-M Core Debug Registers + @{ + */ + +/** \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + @{ + */ + +/* Memory mapping of Cortex-M3 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */ +#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions + @{ + */ + +/** \brief Set Priority Grouping + + This function sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + + \param [in] PriorityGroup Priority grouping field + */ +static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + (0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** \brief Get Priority Grouping + + This function gets the priority grouping from NVIC Interrupt Controller. + Priority grouping is SCB->AIRCR [10:8] PRIGROUP field. + + \return Priority grouping field + */ +static __INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + + +/** \brief Enable External Interrupt + + This function enables a device specific interupt in the NVIC interrupt controller. + The interrupt number cannot be a negative value. + + \param [in] IRQn Number of the external interrupt to enable + */ +static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ +} + + +/** \brief Disable External Interrupt + + This function disables a device specific interupt in the NVIC interrupt controller. + The interrupt number cannot be a negative value. + + \param [in] IRQn Number of the external interrupt to disable + */ +static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + + +/** \brief Get Pending Interrupt + + This function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Number of the interrupt for get pending + \return 0 Interrupt status is not pending + \return 1 Interrupt status is pending + */ +static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ +} + + +/** \brief Set Pending Interrupt + + This function sets the pending bit for the specified interrupt. + The interrupt number cannot be a negative value. + + \param [in] IRQn Number of the interrupt for set pending + */ +static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + + +/** \brief Clear Pending Interrupt + + This function clears the pending bit for the specified interrupt. + The interrupt number cannot be a negative value. + + \param [in] IRQn Number of the interrupt for clear pending + */ +static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Get Active Interrupt + + This function reads the active register in NVIC and returns the active bit. + \param [in] IRQn Number of the interrupt for get active + \return 0 Interrupt status is not active + \return 1 Interrupt status is active + */ +static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ +} + + +/** \brief Set Interrupt Priority + + This function sets the priority for the specified interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + Note: The priority cannot be set for every core interrupt. + + \param [in] IRQn Number of the interrupt for set priority + \param [in] priority Priority to set + */ +static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ +} + + +/** \brief Get Interrupt Priority + + This function reads the priority for the specified interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + The returned priority value is automatically aligned to the implemented + priority bits of the microcontroller. + + \param [in] IRQn Number of the interrupt for get priority + \return Interrupt Priority + */ +static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief Encode Priority + + This function encodes the priority for an interrupt with the given priority group, + preemptive priority value and sub priority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + + The returned priority value can be used for NVIC_SetPriority(...) function + + \param [in] PriorityGroup Used priority group + \param [in] PreemptPriority Preemptive priority value (starting from 0) + \param [in] SubPriority Sub priority value (starting from 0) + \return Encoded priority for the interrupt + */ +static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** \brief Decode Priority + + This function decodes an interrupt priority value with the given priority group to + preemptive priority value and sub priority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + + The priority value can be retrieved with NVIC_GetPriority(...) function + + \param [in] Priority Priority value + \param [in] PriorityGroup Used priority group + \param [out] pPreemptPriority Preemptive priority value (starting from 0) + \param [out] pSubPriority Sub priority value (starting from 0) + */ +static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + +/** \brief System Reset + + This function initiate a system reset request to reset the MCU. + */ +static __INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + This function initialises the system tick timer and its interrupt and start the system tick timer. + Counter is in free running mode to generate periodical interrupts. + + \param [in] ticks Number of ticks between two interrupts + \return 0 Function succeeded + \return 1 Function failed + */ +static __INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions CMSIS Core Debug Functions + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< external variable to receive characters */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */ + + +/** \brief ITM Send Character + + This function transmits a character via the ITM channel 0. + It just returns when no debugger is connected that has booked the output. + It is blocking when a debugger is connected, but the previous character send is not transmitted. + + \param [in] ch Character to transmit + \return Character to transmit + */ +static __INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */ + (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** \brief ITM Receive Character + + This function inputs a character via external variable ITM_RxBuffer. + It just returns when no debugger is connected that has booked the output. + It is blocking when a debugger is connected, but the previous character send is not transmitted. + + \return Received character + \return -1 No character received + */ +static __INLINE int32_t ITM_ReceiveChar (void) { + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** \brief ITM Check Character + + This function checks external variable ITM_RxBuffer whether a character is available or not. + It returns '1' if a character is available and '0' if no character is available. + + \return 0 No character available + \return 1 Character available + */ +static __INLINE int32_t ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ + +#ifdef __cplusplus +} +#endif + +/*lint -restore */ diff --git a/platforms/lpc17xx/CMSISv2p00_LPC17xx/inc/core_cmFunc.h b/platforms/lpc17xx/CMSISv2p00_LPC17xx/inc/core_cmFunc.h new file mode 100644 index 0000000..e3d0edb --- /dev/null +++ b/platforms/lpc17xx/CMSISv2p00_LPC17xx/inc/core_cmFunc.h @@ -0,0 +1,844 @@ +/**************************************************************************//** + * @file core_cmFunc.h + * @brief CMSIS Cortex-M Core Function Access Header File + * @version V2.01 + * @date 06. December 2010 + * + * @note + * Copyright (C) 2009-2010 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#ifndef __CORE_CMFUNC_H__ +#define __CORE_CMFUNC_H__ + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/ +/* ARM armcc specific functions */ + +/* intrinsic void __enable_irq(); */ +/* intrinsic void __disable_irq(); */ + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +#if (__ARMCC_VERSION < 400000) +extern uint32_t __get_CONTROL(void); +#else /* (__ARMCC_VERSION >= 400000) */ +static __INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} +#endif /* __ARMCC_VERSION */ + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +#if (__ARMCC_VERSION < 400000) +extern void __set_CONTROL(uint32_t control); +#else /* (__ARMCC_VERSION >= 400000) */ +static __INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} +#endif /* __ARMCC_VERSION */ + + +/** \brief Get ISPR Register + + This function returns the content of the ISPR Register. + + \return ISPR Register value + */ +#if (__ARMCC_VERSION < 400000) +extern uint32_t __get_IPSR(void); +#else /* (__ARMCC_VERSION >= 400000) */ +static __INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} +#endif /* __ARMCC_VERSION */ + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +#if (__ARMCC_VERSION < 400000) +extern uint32_t __get_APSR(void); +#else /* (__ARMCC_VERSION >= 400000) */ +static __INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} +#endif /* __ARMCC_VERSION */ + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +#if (__ARMCC_VERSION < 400000) +extern uint32_t __get_xPSR(void); +#else /* (__ARMCC_VERSION >= 400000) */ +static __INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} +#endif /* __ARMCC_VERSION */ + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +#if (__ARMCC_VERSION < 400000) +extern uint32_t __get_PSP(void); +#else /* (__ARMCC_VERSION >= 400000) */ +static __INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} +#endif /* __ARMCC_VERSION */ + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +#if (__ARMCC_VERSION < 400000) +extern void __set_PSP(uint32_t topOfProcStack); +#else /* (__ARMCC_VERSION >= 400000) */ +static __INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} +#endif /* __ARMCC_VERSION */ + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +#if (__ARMCC_VERSION < 400000) +extern uint32_t __get_MSP(void); +#else /* (__ARMCC_VERSION >= 400000) */ +static __INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} +#endif /* __ARMCC_VERSION */ + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +#if (__ARMCC_VERSION < 400000) +extern void __set_MSP(uint32_t topOfMainStack); +#else /* (__ARMCC_VERSION >= 400000) */ +static __INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} +#endif /* __ARMCC_VERSION */ + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +#if (__ARMCC_VERSION < 400000) +extern uint32_t __get_PRIMASK(void); +#else /* (__ARMCC_VERSION >= 400000) */ +static __INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} +#endif /* __ARMCC_VERSION */ + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +#if (__ARMCC_VERSION < 400000) +extern void __set_PRIMASK(uint32_t priMask); +#else /* (__ARMCC_VERSION >= 400000) */ +static __INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} +#endif /* __ARMCC_VERSION */ + + +#if (__CORTEX_M >= 0x03) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +#if (__ARMCC_VERSION < 400000) +extern uint32_t __get_BASEPRI(void); +#else /* (__ARMCC_VERSION >= 400000) */ +static __INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} +#endif /* __ARMCC_VERSION */ + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +#if (__ARMCC_VERSION < 400000) +extern void __set_BASEPRI(uint32_t basePri); +#else /* (__ARMCC_VERSION >= 400000) */ +static __INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xff); +} +#endif /* __ARMCC_VERSION */ + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +#if (__ARMCC_VERSION < 400000) +extern uint32_t __get_FAULTMASK(void); +#else /* (__ARMCC_VERSION >= 400000) */ +static __INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} +#endif /* __ARMCC_VERSION */ + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +#if (__ARMCC_VERSION < 400000) +extern void __set_FAULTMASK(uint32_t faultMask); +#else /* (__ARMCC_VERSION >= 400000) */ +static __INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & 1); +} +#endif /* __ARMCC_VERSION */ + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +static __INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +static __INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#endif +} + +#endif /* (__CORTEX_M == 0x04) */ + + + #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/ +/* IAR iccarm specific functions */ + +#if defined (__ICCARM__) + #include /* IAR Intrinsics */ +#endif + +#pragma diag_suppress=Pe940 + +/** \brief Enable IRQ Interrupts + + This function enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_irq __enable_interrupt + + +/** \brief Disable IRQ Interrupts + + This function disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_irq __disable_interrupt + + +/* intrinsic unsigned long __get_CONTROL( void ); (see intrinsic.h) */ +/* intrinsic void __set_CONTROL( unsigned long ); (see intrinsic.h) */ + + +/** \brief Get ISPR Register + + This function returns the content of the ISPR Register. + + \return ISPR Register value + */ +static uint32_t __get_IPSR(void) +{ + __ASM("mrs r0, ipsr"); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +static uint32_t __get_APSR(void) +{ + __ASM("mrs r0, apsr"); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +static uint32_t __get_xPSR(void) +{ + __ASM("mrs r0, psr"); // assembler does not know "xpsr" +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +static uint32_t __get_PSP(void) +{ + __ASM("mrs r0, psp"); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +static void __set_PSP(uint32_t topOfProcStack) +{ + __ASM("msr psp, r0"); +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +static uint32_t __get_MSP(void) +{ + __ASM("mrs r0, msp"); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +static void __set_MSP(uint32_t topOfMainStack) +{ + __ASM("msr msp, r0"); +} + + +/* intrinsic unsigned long __get_PRIMASK( void ); (see intrinsic.h) */ +/* intrinsic void __set_PRIMASK( unsigned long ); (see intrinsic.h) */ + + +#if (__CORTEX_M >= 0x03) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +static __INLINE void __enable_fault_irq(void) +{ + __ASM ("cpsie f"); +} + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +static __INLINE void __disable_fault_irq(void) +{ + __ASM ("cpsid f"); +} + + +/* intrinsic unsigned long __get_BASEPRI( void ); (see intrinsic.h) */ +/* intrinsic void __set_BASEPRI( unsigned long ); (see intrinsic.h) */ +/* intrinsic unsigned long __get_FAULTMASK( void ); (see intrinsic.h) */ +/* intrinsic void __set_FAULTMASK(unsigned long); (see intrinsic.h) */ + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +static uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) + __ASM("vmrs r0, fpscr"); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +static void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) + __ASM("vmsr fpscr, r0"); +#endif +} + +#endif /* (__CORTEX_M == 0x04) */ + +#pragma diag_default=Pe940 + + +#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/** \brief Enable IRQ Interrupts + + This function enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) static __INLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i"); +} + + +/** \brief Disable IRQ Interrupts + + This function disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) static __INLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i"); +} + + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +__attribute__( ( always_inline ) ) static __INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) ); +} + + +/** \brief Get ISPR Register + + This function returns the content of the ISPR Register. + + \return ISPR Register value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) static __INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) ); +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) static __INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) ); +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +__attribute__( ( always_inline ) ) static __INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) ); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) static __INLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f"); +} + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) static __INLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f"); +} + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); + return(result); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +__attribute__( ( always_inline ) ) static __INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) ); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +__attribute__( ( always_inline ) ) static __INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) ); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) + uint32_t result; + + __ASM volatile ("MRS %0, fpscr" : "=r" (result) ); + return(result); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__( ( always_inline ) ) static __INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) + __ASM volatile ("MSR fpscr, %0" : : "r" (fpscr) ); +#endif +} + +#endif /* (__CORTEX_M == 0x04) */ + + +#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all instrinsics, + * Including the CMSIS ones. + */ + +#endif + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +#endif /* __CORE_CMFUNC_H__ */ diff --git a/platforms/lpc17xx/CMSISv2p00_LPC17xx/inc/core_cmInstr.h b/platforms/lpc17xx/CMSISv2p00_LPC17xx/inc/core_cmInstr.h new file mode 100644 index 0000000..fb3c092 --- /dev/null +++ b/platforms/lpc17xx/CMSISv2p00_LPC17xx/inc/core_cmInstr.h @@ -0,0 +1,775 @@ +/**************************************************************************//** + * @file core_cmInstr.h + * @brief CMSIS Cortex-M Core Instruction Access Header File + * @version V2.01 + * @date 06. December 2010 + * + * @note + * Copyright (C) 2009-2010 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#ifndef __CORE_CMINSTR_H__ +#define __CORE_CMINSTR_H__ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/ +/* ARM armcc specific functions */ + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +#if (__ARMCC_VERSION < 400677) +extern uint32_t __REV16(uint32_t value); +#else /* (__ARMCC_VERSION >= 400677) */ +static __INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif /* __ARMCC_VERSION */ + + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +#if (__ARMCC_VERSION < 400677) +extern int32_t __REVSH(int32_t value); +#else /* (__ARMCC_VERSION >= 400677) */ +static __INLINE __ASM int32_t __REVSH(int32_t value) +{ + revsh r0, r0 + bx lr +} +#endif /* __ARMCC_VERSION */ + + +#if (__CORTEX_M >= 0x03) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __rbit + + +/** \brief LDR Exclusive (8 bit) + + This function performs a exclusive LDR command for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) + + +/** \brief LDR Exclusive (16 bit) + + This function performs a exclusive LDR command for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) + + +/** \brief LDR Exclusive (32 bit) + + This function performs a exclusive LDR command for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) + + +/** \brief STR Exclusive (8 bit) + + This function performs a exclusive STR command for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (16 bit) + + This function performs a exclusive STR command for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (32 bit) + + This function performs a exclusive STR command for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW(value, ptr) __strex(value, ptr) + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +#if (__ARMCC_VERSION < 400000) +extern void __CLREX(void); +#else /* (__ARMCC_VERSION >= 400000) */ +#define __CLREX __clrex +#endif /* __ARMCC_VERSION */ + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + +#endif /* (__CORTEX_M >= 0x03) */ + + + +#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/ +/* IAR iccarm specific functions */ + +#include /* IAR Intrinsics */ + +#pragma diag_suppress=Pe940 + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __no_operation + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +static __INLINE void __WFI(void) +{ + __ASM ("wfi"); +} + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +static __INLINE void __WFE(void) +{ + __ASM ("wfe"); +} + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +static __INLINE void __SEV(void) +{ + __ASM ("sev"); +} + + +/* intrinsic void __ISB(void) (see intrinsics.h) */ +/* intrinsic void __DSB(void) (see intrinsics.h) */ +/* intrinsic void __DMB(void) (see intrinsics.h) */ +/* intrinsic uint32_t __REV(uint32_t value) (see intrinsics.h) */ +/* intrinsic __SSAT (see intrinsics.h) */ +/* intrinsic __USAT (see intrinsics.h) */ + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +static uint32_t __REV16(uint32_t value) +{ + __ASM("rev16 r0, r0"); +} + + +/* intrinsic uint32_t __REVSH(uint32_t value) (see intrinsics.h */ + + +#if (__CORTEX_M >= 0x03) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +static uint32_t __RBIT(uint32_t value) +{ + __ASM("rbit r0, r0"); +} + + +/** \brief LDR Exclusive (8 bit) + + This function performs a exclusive LDR command for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +static uint8_t __LDREXB(volatile uint8_t *addr) +{ + __ASM("ldrexb r0, [r0]"); +} + + +/** \brief LDR Exclusive (16 bit) + + This function performs a exclusive LDR command for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +static uint16_t __LDREXH(volatile uint16_t *addr) +{ + __ASM("ldrexh r0, [r0]"); +} + + +/** \brief LDR Exclusive (32 bit) + + This function performs a exclusive LDR command for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +/* intrinsic unsigned long __LDREX(unsigned long *) (see intrinsics.h) */ +static uint32_t __LDREXW(volatile uint32_t *addr) +{ + __ASM("ldrex r0, [r0]"); +} + + +/** \brief STR Exclusive (8 bit) + + This function performs a exclusive STR command for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +static uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + __ASM("strexb r0, r0, [r1]"); +} + + +/** \brief STR Exclusive (16 bit) + + This function performs a exclusive STR command for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +static uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + __ASM("strexh r0, r0, [r1]"); +} + + +/** \brief STR Exclusive (32 bit) + + This function performs a exclusive STR command for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +/* intrinsic unsigned long __STREX(unsigned long, unsigned long) (see intrinsics.h )*/ +static uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + __ASM("strex r0, r0, [r1]"); +} + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +static __INLINE void __CLREX(void) +{ + __ASM ("clrex"); +} + +/* intrinsic unsigned char __CLZ( unsigned long ) (see intrinsics.h) */ + +#endif /* (__CORTEX_M >= 0x03) */ + +#pragma diag_default=Pe940 + + + +#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +__attribute__( ( always_inline ) ) static __INLINE void __NOP(void) +{ + __ASM volatile ("nop"); +} + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +__attribute__( ( always_inline ) ) static __INLINE void __WFI(void) +{ + __ASM volatile ("wfi"); +} + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +__attribute__( ( always_inline ) ) static __INLINE void __WFE(void) +{ + __ASM volatile ("wfe"); +} + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +__attribute__( ( always_inline ) ) static __INLINE void __SEV(void) +{ + __ASM volatile ("sev"); +} + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +__attribute__( ( always_inline ) ) static __INLINE void __ISB(void) +{ + __ASM volatile ("isb"); +} + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__attribute__( ( always_inline ) ) static __INLINE void __DSB(void) +{ + __ASM volatile ("dsb"); +} + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__attribute__( ( always_inline ) ) static __INLINE void __DMB(void) +{ + __ASM volatile ("dmb"); +} + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) static __INLINE int32_t __REVSH(int32_t value) +{ + uint32_t result; + + __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +/** \brief LDR Exclusive (8 bit) + + This function performs a exclusive LDR command for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__( ( always_inline ) ) static __INLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint8_t result; + + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + + +/** \brief LDR Exclusive (16 bit) + + This function performs a exclusive LDR command for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__( ( always_inline ) ) static __INLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint16_t result; + + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + + +/** \brief LDR Exclusive (32 bit) + + This function performs a exclusive LDR command for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + + +/** \brief STR Exclusive (8 bit) + + This function performs a exclusive STR command for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); + return(result); +} + + +/** \brief STR Exclusive (16 bit) + + This function performs a exclusive STR command for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); + return(result); +} + + +/** \brief STR Exclusive (32 bit) + + This function performs a exclusive STR command for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); + return(result); +} + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +__attribute__( ( always_inline ) ) static __INLINE void __CLREX(void) +{ + __ASM volatile ("clrex"); +} + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__attribute__( ( always_inline ) ) static __INLINE uint8_t __CLZ(uint32_t value) +{ + uint8_t result; + + __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + + + +#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all instrinsics, + * Including the CMSIS ones. + */ + +#endif + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + +#endif /* __CORE_CMINSTR_H__ */ diff --git a/platforms/lpc17xx/CMSISv2p00_LPC17xx/inc/system_LPC17xx.h b/platforms/lpc17xx/CMSISv2p00_LPC17xx/inc/system_LPC17xx.h new file mode 100644 index 0000000..d72cb50 --- /dev/null +++ b/platforms/lpc17xx/CMSISv2p00_LPC17xx/inc/system_LPC17xx.h @@ -0,0 +1,64 @@ +/**************************************************************************//** + * @file system_LPC17xx.h + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File + * for the NXP LPC17xx Device Series + * @version V1.02 + * @date 08. September 2009 + * + * @note + * Copyright (C) 2009 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + + +#ifndef __SYSTEM_LPC17xx_H +#define __SYSTEM_LPC17xx_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit (void); + +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + +#ifdef __cplusplus +} +#endif + +#endif /* __SYSTEM_LPC17xx_H */ diff --git a/platforms/lpc17xx/CMSISv2p00_LPC17xx/src/core_cm3.c b/platforms/lpc17xx/CMSISv2p00_LPC17xx/src/core_cm3.c new file mode 100644 index 0000000..6e13f4c --- /dev/null +++ b/platforms/lpc17xx/CMSISv2p00_LPC17xx/src/core_cm3.c @@ -0,0 +1,339 @@ +/**************************************************************************//** + * @file core_cm3.c + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File + * @version V2.00 + * @date 13. September 2010 + * + * @note + * Copyright (C) 2009-2010 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#include + +/* define compiler specific symbols */ +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + +#endif + + +/* ########################## Core Instruction Access ######################### */ + +#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/ + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +#if (__ARMCC_VERSION < 400677) +__ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif /* __ARMCC_VERSION */ + + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +#if (__ARMCC_VERSION < 400677) +__ASM int32_t __REVSH(int32_t value) +{ + revsh r0, r0 + bx lr +} +#endif /* __ARMCC_VERSION */ + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +#if (__ARMCC_VERSION < 400000) +__ASM void __CLREX(void) +{ + clrex +} +#endif /* __ARMCC_VERSION */ + + +#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/ +/* obsolete */ +#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ +/* obsolete */ +#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/ +/* obsolete */ +#endif + + +/* ########################### Core Function Access ########################### */ + +#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/ + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +#if (__ARMCC_VERSION < 400000) +__ASM uint32_t __get_CONTROL(void) +{ + mrs r0, control + bx lr +} +#endif /* __ARMCC_VERSION */ + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +#if (__ARMCC_VERSION < 400000) +__ASM void __set_CONTROL(uint32_t control) +{ + msr control, r0 + bx lr +} +#endif /* __ARMCC_VERSION */ + + +/** \brief Get ISPR Register + + This function returns the content of the ISPR Register. + + \return ISPR Register value + */ +#if (__ARMCC_VERSION < 400000) +__ASM uint32_t __get_IPSR(void) +{ + mrs r0, ipsr + bx lr +} +#endif /* __ARMCC_VERSION */ + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +#if (__ARMCC_VERSION < 400000) +__ASM uint32_t __get_APSR(void) +{ + mrs r0, apsr + bx lr +} +#endif /* __ARMCC_VERSION */ + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +#if (__ARMCC_VERSION < 400000) +__ASM uint32_t __get_xPSR(void) +{ + mrs r0, xpsr + bx lr +} +#endif /* __ARMCC_VERSION */ + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +#if (__ARMCC_VERSION < 400000) +__ASM uint32_t __get_PSP(void) +{ + mrs r0, psp + bx lr +} +#endif /* __ARMCC_VERSION */ + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +#if (__ARMCC_VERSION < 400000) +__ASM void __set_PSP(uint32_t topOfProcStack) +{ + msr psp, r0 + bx lr +} +#endif /* __ARMCC_VERSION */ + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +#if (__ARMCC_VERSION < 400000) +__ASM uint32_t __get_MSP(void) +{ + mrs r0, msp + bx lr +} +#endif /* __ARMCC_VERSION */ + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +#if (__ARMCC_VERSION < 400000) +__ASM void __set_MSP(uint32_t mainStackPointer) +{ + msr msp, r0 + bx lr +} +#endif /* __ARMCC_VERSION */ + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +#if (__ARMCC_VERSION < 400000) +__ASM uint32_t __get_BASEPRI(void) +{ + mrs r0, basepri + bx lr +} +#endif /* __ARMCC_VERSION */ + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +#if (__ARMCC_VERSION < 400000) +__ASM void __set_BASEPRI(uint32_t basePri) +{ + msr basepri, r0 + bx lr +} +#endif /* __ARMCC_VERSION */ + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +#if (__ARMCC_VERSION < 400000) +__ASM uint32_t __get_PRIMASK(void) +{ + mrs r0, primask + bx lr +} +#endif /* __ARMCC_VERSION */ + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +#if (__ARMCC_VERSION < 400000) +__ASM void __set_PRIMASK(uint32_t priMask) +{ + msr primask, r0 + bx lr +} +#endif /* __ARMCC_VERSION */ + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask Register. + + \return Fault Mask value + */ +#if (__ARMCC_VERSION < 400000) +__ASM uint32_t __get_FAULTMASK(void) +{ + mrs r0, faultmask + bx lr +} +#endif /* __ARMCC_VERSION */ + + +/** \brief Set the Fault Mask + + This function assigns the given value to the Fault Mask Register. + + \param [in] faultMask Fault Mask value value to set + */ +#if (__ARMCC_VERSION < 400000) +__ASM void __set_FAULTMASK(uint32_t faultMask) +{ + msr faultmask, r0 + bx lr +} +#endif /* __ARMCC_VERSION */ + + + +#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/ +/* obsolete */ +#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ +/* obsolete */ +#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/ +/* obsolete */ +#endif diff --git a/platforms/lpc17xx/CMSISv2p00_LPC17xx/src/system_LPC17xx.c b/platforms/lpc17xx/CMSISv2p00_LPC17xx/src/system_LPC17xx.c new file mode 100644 index 0000000..11aa44f --- /dev/null +++ b/platforms/lpc17xx/CMSISv2p00_LPC17xx/src/system_LPC17xx.c @@ -0,0 +1,532 @@ +/**************************************************************************//** + * @file system_LPC17xx.c + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Source File + * for the NXP LPC17xx Device Series + * @version V1.08 + * @date 12. May 2010 + * + * @note + * Copyright (C) 2009 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + + +#include +#include "LPC17xx.h" + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + +/*--------------------- Clock Configuration ---------------------------------- +// +// Clock Configuration +// System Controls and Status Register (SCS) +// OSCRANGE: Main Oscillator Range Select +// <0=> 1 MHz to 20 MHz +// <1=> 15 MHz to 24 MHz +// OSCEN: Main Oscillator Enable +// +// +// +// Clock Source Select Register (CLKSRCSEL) +// CLKSRC: PLL Clock Source Selection +// <0=> Internal RC oscillator +// <1=> Main oscillator +// <2=> RTC oscillator +// +// +// PLL0 Configuration (Main PLL) +// PLL0 Configuration Register (PLL0CFG) +// F_cco0 = (2 * M * F_in) / N +// F_in must be in the range of 32 kHz to 50 MHz +// F_cco0 must be in the range of 275 MHz to 550 MHz +// MSEL: PLL Multiplier Selection +// <6-32768><#-1> +// M Value +// NSEL: PLL Divider Selection +// <1-256><#-1> +// N Value +// +// +// +// PLL1 Configuration (USB PLL) +// PLL1 Configuration Register (PLL1CFG) +// F_usb = M * F_osc or F_usb = F_cco1 / (2 * P) +// F_cco1 = F_osc * M * 2 * P +// F_cco1 must be in the range of 156 MHz to 320 MHz +// MSEL: PLL Multiplier Selection +// <1-32><#-1> +// M Value (for USB maximum value is 4) +// PSEL: PLL Divider Selection +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// P Value +// +// +// +// CPU Clock Configuration Register (CCLKCFG) +// CCLKSEL: Divide Value for CPU Clock from PLL0 +// <1-256><#-1> +// +// +// USB Clock Configuration Register (USBCLKCFG) +// USBSEL: Divide Value for USB Clock from PLL0 +// <0-15> +// Divide is USBSEL + 1 +// +// +// Peripheral Clock Selection Register 0 (PCLKSEL0) +// PCLK_WDT: Peripheral Clock Selection for WDT +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_TIMER0: Peripheral Clock Selection for TIMER0 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_TIMER1: Peripheral Clock Selection for TIMER1 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_UART0: Peripheral Clock Selection for UART0 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_UART1: Peripheral Clock Selection for UART1 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_PWM1: Peripheral Clock Selection for PWM1 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_I2C0: Peripheral Clock Selection for I2C0 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_SPI: Peripheral Clock Selection for SPI +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_SSP1: Peripheral Clock Selection for SSP1 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_DAC: Peripheral Clock Selection for DAC +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_ADC: Peripheral Clock Selection for ADC +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_CAN1: Peripheral Clock Selection for CAN1 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 6 +// PCLK_CAN2: Peripheral Clock Selection for CAN2 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 6 +// PCLK_ACF: Peripheral Clock Selection for ACF +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 6 +// +// +// Peripheral Clock Selection Register 1 (PCLKSEL1) +// PCLK_QEI: Peripheral Clock Selection for the Quadrature Encoder Interface +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_GPIO: Peripheral Clock Selection for GPIOs +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_PCB: Peripheral Clock Selection for the Pin Connect Block +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_I2C1: Peripheral Clock Selection for I2C1 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_SSP0: Peripheral Clock Selection for SSP0 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_TIMER2: Peripheral Clock Selection for TIMER2 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_TIMER3: Peripheral Clock Selection for TIMER3 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_UART2: Peripheral Clock Selection for UART2 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_UART3: Peripheral Clock Selection for UART3 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_I2C2: Peripheral Clock Selection for I2C2 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_I2S: Peripheral Clock Selection for I2S +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_RIT: Peripheral Clock Selection for the Repetitive Interrupt Timer +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_SYSCON: Peripheral Clock Selection for the System Control Block +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_MC: Peripheral Clock Selection for the Motor Control PWM +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// +// +// Power Control for Peripherals Register (PCONP) +// PCTIM0: Timer/Counter 0 power/clock enable +// PCTIM1: Timer/Counter 1 power/clock enable +// PCUART0: UART 0 power/clock enable +// PCUART1: UART 1 power/clock enable +// PCPWM1: PWM 1 power/clock enable +// PCI2C0: I2C interface 0 power/clock enable +// PCSPI: SPI interface power/clock enable +// PCRTC: RTC power/clock enable +// PCSSP1: SSP interface 1 power/clock enable +// PCAD: A/D converter power/clock enable +// PCCAN1: CAN controller 1 power/clock enable +// PCCAN2: CAN controller 2 power/clock enable +// PCGPIO: GPIOs power/clock enable +// PCRIT: Repetitive interrupt timer power/clock enable +// PCMC: Motor control PWM power/clock enable +// PCQEI: Quadrature encoder interface power/clock enable +// PCI2C1: I2C interface 1 power/clock enable +// PCSSP0: SSP interface 0 power/clock enable +// PCTIM2: Timer 2 power/clock enable +// PCTIM3: Timer 3 power/clock enable +// PCUART2: UART 2 power/clock enable +// PCUART3: UART 3 power/clock enable +// PCI2C2: I2C interface 2 power/clock enable +// PCI2S: I2S interface power/clock enable +// PCGPDMA: GP DMA function power/clock enable +// PCENET: Ethernet block power/clock enable +// PCUSB: USB interface power/clock enable +// +// +// Clock Output Configuration Register (CLKOUTCFG) +// CLKOUTSEL: Selects clock source for CLKOUT +// <0=> CPU clock +// <1=> Main oscillator +// <2=> Internal RC oscillator +// <3=> USB clock +// <4=> RTC oscillator +// CLKOUTDIV: Selects clock divider for CLKOUT +// <1-16><#-1> +// CLKOUT_EN: CLKOUT enable control +// +// +// +*/ +#define CLOCK_SETUP 1 +#define SCS_Val 0x00000020 +#define CLKSRCSEL_Val 0x00000001 +#define PLL0_SETUP 1 +#define PLL0CFG_Val 0x00050063 +#define PLL1_SETUP 1 +#define PLL1CFG_Val 0x00000023 +#define CCLKCFG_Val 0x00000003 +#define USBCLKCFG_Val 0x00000000 +#define PCLKSEL0_Val 0x00000000 +#define PCLKSEL1_Val 0x00000000 +#define PCONP_Val 0x042887DE +#define CLKOUTCFG_Val 0x00000000 + + +/*--------------------- Flash Accelerator Configuration ---------------------- +// +// Flash Accelerator Configuration +// FLASHTIM: Flash Access Time +// <0=> 1 CPU clock (for CPU clock up to 20 MHz) +// <1=> 2 CPU clocks (for CPU clock up to 40 MHz) +// <2=> 3 CPU clocks (for CPU clock up to 60 MHz) +// <3=> 4 CPU clocks (for CPU clock up to 80 MHz) +// <4=> 5 CPU clocks (for CPU clock up to 100 MHz) +// <5=> 6 CPU clocks (for any CPU clock) +// +*/ +#define FLASH_SETUP 0 +#define FLASHCFG_Val 0x00004000 + +/* +//-------- <<< end of configuration section >>> ------------------------------ +*/ + +/*---------------------------------------------------------------------------- + Check the register settings + *----------------------------------------------------------------------------*/ +#define CHECK_RANGE(val, min, max) ((val < min) || (val > max)) +#define CHECK_RSVD(val, mask) (val & mask) + +/* Clock Configuration -------------------------------------------------------*/ +#if (CHECK_RSVD((SCS_Val), ~0x00000030)) + #error "SCS: Invalid values of reserved bits!" +#endif + +#if (CHECK_RANGE((CLKSRCSEL_Val), 0, 2)) + #error "CLKSRCSEL: Value out of range!" +#endif + +#if (CHECK_RSVD((PLL0CFG_Val), ~0x00FF7FFF)) + #error "PLL0CFG: Invalid values of reserved bits!" +#endif + +#if (CHECK_RSVD((PLL1CFG_Val), ~0x0000007F)) + #error "PLL1CFG: Invalid values of reserved bits!" +#endif + +#if (PLL0_SETUP) /* if PLL0 is used */ + #if (CCLKCFG_Val < 2) /* CCLKSEL must be greater then 1 */ + #error "CCLKCFG: CCLKSEL must be greater then 1 if PLL0 is used!" + #endif +#endif + +#if (CHECK_RANGE((CCLKCFG_Val), 2, 255)) + #error "CCLKCFG: Value out of range!" +#endif + +#if (CHECK_RSVD((USBCLKCFG_Val), ~0x0000000F)) + #error "USBCLKCFG: Invalid values of reserved bits!" +#endif + +#if (CHECK_RSVD((PCLKSEL0_Val), 0x000C0C00)) + #error "PCLKSEL0: Invalid values of reserved bits!" +#endif + +#if (CHECK_RSVD((PCLKSEL1_Val), 0x03000300)) + #error "PCLKSEL1: Invalid values of reserved bits!" +#endif + +#if (CHECK_RSVD((PCONP_Val), 0x10100821)) + #error "PCONP: Invalid values of reserved bits!" +#endif + +#if (CHECK_RSVD((CLKOUTCFG_Val), ~0x000001FF)) + #error "CLKOUTCFG: Invalid values of reserved bits!" +#endif + +/* Flash Accelerator Configuration -------------------------------------------*/ +#if (CHECK_RSVD((FLASHCFG_Val), ~0x0000F000)) + #error "FLASHCFG: Invalid values of reserved bits!" +#endif + + +/*---------------------------------------------------------------------------- + DEFINES + *----------------------------------------------------------------------------*/ + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (12000000UL) /* Oscillator frequency */ +#define OSC_CLK ( XTAL) /* Main oscillator frequency */ +#define RTC_CLK ( 32000UL) /* RTC oscillator frequency */ +#define IRC_OSC ( 4000000UL) /* Internal RC oscillator frequency */ + + +/* F_cco0 = (2 * M * F_in) / N */ +#define __M (((PLL0CFG_Val ) & 0x7FFF) + 1) +#define __N (((PLL0CFG_Val >> 16) & 0x00FF) + 1) +#define __FCCO(__F_IN) ((2/*ULL*/ * __M * __F_IN) / __N) +#define __CCLK_DIV (((CCLKCFG_Val ) & 0x00FF) + 1) + +/* Determine core clock frequency according to settings */ + #if (PLL0_SETUP) + #if ((CLKSRCSEL_Val & 0x03) == 1) + #define __CORE_CLK (__FCCO(OSC_CLK) / __CCLK_DIV) + #elif ((CLKSRCSEL_Val & 0x03) == 2) + #define __CORE_CLK (__FCCO(RTC_CLK) / __CCLK_DIV) + #else + #define __CORE_CLK (__FCCO(IRC_OSC) / __CCLK_DIV) + #endif + #else + #if ((CLKSRCSEL_Val & 0x03) == 1) + #define __CORE_CLK (OSC_CLK / __CCLK_DIV) + #elif ((CLKSRCSEL_Val & 0x03) == 2) + #define __CORE_CLK (RTC_CLK / __CCLK_DIV) + #else + #define __CORE_CLK (IRC_OSC / __CCLK_DIV) + #endif + #endif + + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = __CORE_CLK;/*!< System Clock Frequency (Core Clock)*/ + + +/*---------------------------------------------------------------------------- + Clock functions + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ +{ + /* Determine clock frequency according to clock register values */ + if (((LPC_SC->PLL0STAT >> 24) & 3) == 3) { /* If PLL0 enabled and connected */ + switch (LPC_SC->CLKSRCSEL & 0x03) { + case 0: /* Int. RC oscillator => PLL0 */ + case 3: /* Reserved, default to Int. RC */ + SystemCoreClock = (IRC_OSC * + ((2/*ULL*/ * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) / + (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) / + ((LPC_SC->CCLKCFG & 0xFF)+ 1)); + break; + case 1: /* Main oscillator => PLL0 */ + SystemCoreClock = (OSC_CLK * + ((2/*ULL*/ * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) / + (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) / + ((LPC_SC->CCLKCFG & 0xFF)+ 1)); + break; + case 2: /* RTC oscillator => PLL0 */ + SystemCoreClock = (RTC_CLK * + ((2/*ULL*/ * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) / + (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) / + ((LPC_SC->CCLKCFG & 0xFF)+ 1)); + break; + } + } else { + switch (LPC_SC->CLKSRCSEL & 0x03) { + case 0: /* Int. RC oscillator => PLL0 */ + case 3: /* Reserved, default to Int. RC */ + SystemCoreClock = IRC_OSC / ((LPC_SC->CCLKCFG & 0xFF)+ 1); + break; + case 1: /* Main oscillator => PLL0 */ + SystemCoreClock = OSC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1); + break; + case 2: /* RTC oscillator => PLL0 */ + SystemCoreClock = RTC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1); + break; + } + } + +} + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System. + */ +void SystemInit (void) +{ +#if (CLOCK_SETUP) /* Clock Setup */ + LPC_SC->SCS = SCS_Val; + if (SCS_Val & (1 << 5)) { /* If Main Oscillator is enabled */ + while ((LPC_SC->SCS & (1<<6)) == 0);/* Wait for Oscillator to be ready */ + } + + LPC_SC->CCLKCFG = CCLKCFG_Val; /* Setup Clock Divider */ + + LPC_SC->PCLKSEL0 = PCLKSEL0_Val; /* Peripheral Clock Selection */ + LPC_SC->PCLKSEL1 = PCLKSEL1_Val; + + LPC_SC->CLKSRCSEL = CLKSRCSEL_Val; /* Select Clock Source for PLL0 */ + +#if (PLL0_SETUP) + LPC_SC->PLL0CFG = PLL0CFG_Val; /* configure PLL0 */ + LPC_SC->PLL0FEED = 0xAA; + LPC_SC->PLL0FEED = 0x55; + + LPC_SC->PLL0CON = 0x01; /* PLL0 Enable */ + LPC_SC->PLL0FEED = 0xAA; + LPC_SC->PLL0FEED = 0x55; + while (!(LPC_SC->PLL0STAT & (1<<26)));/* Wait for PLOCK0 */ + + LPC_SC->PLL0CON = 0x03; /* PLL0 Enable & Connect */ + LPC_SC->PLL0FEED = 0xAA; + LPC_SC->PLL0FEED = 0x55; + while (!(LPC_SC->PLL0STAT & ((1<<25) | (1<<24))));/* Wait for PLLC0_STAT & PLLE0_STAT */ +#endif + +#if (PLL1_SETUP) + LPC_SC->PLL1CFG = PLL1CFG_Val; + LPC_SC->PLL1FEED = 0xAA; + LPC_SC->PLL1FEED = 0x55; + + LPC_SC->PLL1CON = 0x01; /* PLL1 Enable */ + LPC_SC->PLL1FEED = 0xAA; + LPC_SC->PLL1FEED = 0x55; + while (!(LPC_SC->PLL1STAT & (1<<10)));/* Wait for PLOCK1 */ + + LPC_SC->PLL1CON = 0x03; /* PLL1 Enable & Connect */ + LPC_SC->PLL1FEED = 0xAA; + LPC_SC->PLL1FEED = 0x55; + while (!(LPC_SC->PLL1STAT & ((1<< 9) | (1<< 8))));/* Wait for PLLC1_STAT & PLLE1_STAT */ +#else + LPC_SC->USBCLKCFG = USBCLKCFG_Val; /* Setup USB Clock Divider */ +#endif + + LPC_SC->PCONP = PCONP_Val; /* Power Control for Peripherals */ + + LPC_SC->CLKOUTCFG = CLKOUTCFG_Val; /* Clock Output Configuration */ +#endif + +#if (FLASH_SETUP == 1) /* Flash Accelerator Setup */ + LPC_SC->FLASHCFG = (LPC_SC->FLASHCFG & ~0x0000F000) | FLASHCFG_Val; +#endif +} diff --git a/platforms/lpc17xx/Makefile b/platforms/lpc17xx/Makefile new file mode 100644 index 0000000..172df5a --- /dev/null +++ b/platforms/lpc17xx/Makefile @@ -0,0 +1,95 @@ +ifeq ($(TARGET_NAME),) +TARGET_NAME=boot +endif +ifeq ($(ATOMTHREADS),) +ATOMTHREADS = $(shell pwd)/../../ +endif +ifeq ($(TEST_NAME),) +TEST_NAME = kern1 +endif + + + +CC = arm-none-eabi-gcc +LN = arm-none-eabi-gcc +AS = arm-none-eabi-gcc + +CFLAGS := $(CFLAGS) -O3 -Os -g3 -Wall -c -mcpu=cortex-m3 -mthumb +AFLAGS := $(AFLAGS) -O3 -Os -g3 -Wall -c -fmessage-length=0 -fno-builtin -ffunction-sections -fdata-sections -mcpu=cortex-m3 -mthumb +LFLAGS := $(LFLAGS) -O3 -Os -Wall -mcpu=cortex-m3 -mthumb -Wl,-Map=system.map -Tsystem.ld + +CDEFS := $(CDEFS) -DATOMTHREADS_TEST='"$(TEST_NAME)"' +ADEFS := $(ADEFS) -D__thumb2__ -DARM_RDI_MONITOR + +LLIBS := $(LLIBS) + + +SRCS := $(SRCS) \ + ./CMSISv2p00_LPC17xx/src/core_cm3.c \ + ./CMSISv2p00_LPC17xx/src/system_LPC17xx.c \ + ./drivers/lpc17xx_uart.c \ + startup.c \ + modules.c \ + $(ATOMTHREADS)/tests/$(TEST_NAME).c \ + main.c \ + + + +ASMS := $(ASMS) \ + + +INCLUDES := $(INCLUDES) \ + -I./CMSISv2p00_LPC17xx/inc \ + -I$(ATOMTHREADS) + +include $(ATOMTHREADS)/ports/cortex_m/Makefile + +OBJS = $(SRCS:.c=.o) $(ASMS:.S=.o) + +include ../rules.mk + +run_test: clean all + cp boot.bin bin/$(TEST_NAME).bin + +all_tests: + echo "Starting atomthreads test suite" + make run_test "TEST_NAME=mutex1" + make run_test "TEST_NAME=mutex2" + make run_test "TEST_NAME=mutex3" + make run_test "TEST_NAME=mutex4" + make run_test "TEST_NAME=mutex5" + make run_test "TEST_NAME=mutex6" + make run_test "TEST_NAME=mutex7" + make run_test "TEST_NAME=mutex8" + make run_test "TEST_NAME=mutex9" + make run_test "TEST_NAME=kern1" + make run_test "TEST_NAME=kern2" + make run_test "TEST_NAME=kern3" + make run_test "TEST_NAME=kern4" + make run_test "TEST_NAME=timer1" + make run_test "TEST_NAME=timer2" + make run_test "TEST_NAME=timer3" + make run_test "TEST_NAME=timer4" + make run_test "TEST_NAME=timer5" + make run_test "TEST_NAME=timer6" + make run_test "TEST_NAME=timer7" + make run_test "TEST_NAME=queue1" + make run_test "TEST_NAME=queue2" + make run_test "TEST_NAME=queue3" + make run_test "TEST_NAME=queue4" + make run_test "TEST_NAME=queue5" + make run_test "TEST_NAME=queue6" + make run_test "TEST_NAME=queue7" + make run_test "TEST_NAME=queue8" + make run_test "TEST_NAME=queue9" + make run_test "TEST_NAME=sem1" + make run_test "TEST_NAME=sem2" + make run_test "TEST_NAME=sem3" + make run_test "TEST_NAME=sem4" + make run_test "TEST_NAME=sem5" + make run_test "TEST_NAME=sem6" + make run_test "TEST_NAME=sem7" + make run_test "TEST_NAME=sem8" + make run_test "TEST_NAME=sem9" + + \ No newline at end of file diff --git a/platforms/lpc17xx/atomthreads_test.out b/platforms/lpc17xx/atomthreads_test.out new file mode 100644 index 0000000..510711a --- /dev/null +++ b/platforms/lpc17xx/atomthreads_test.out @@ -0,0 +1,153 @@ + +LPC17xx SystemCoreClock = 100000000 +Atomthreads starting mutex1... +mutex1 PASS + +LPC17xx SystemCoreClock = 100000000 +Atomthreads starting mutex2... +mutex2 PASS + +LPC17xx SystemCoreClock = 100000000 +Atomthreads starting mutex3... +mutex3 PASS + +LPC17xx SystemCoreClock = 100000000 +Atomthreads starting mutex5... +mutex5 PASS + +LPC17xx SystemCoreClock = 100000000 +Atomthreads starting mutex6... +mutex6 PASS + +LPC17xx SystemCoreClock = 100000000 +Atomthreads starting mutex7... +mutex7 PASS + +LPC17xx SystemCoreClock = 100000000 +Atomthreads starting mutex8... +mutex8 PASS + +LPC17xx SystemCoreClock = 100000000 +Atomthreads starting mutex9... +mutex9 PASS + +LPC17xx SystemCoreClock = 100000000 +Atomthreads starting kern1... +kern1 PASS + +LPC17xx SystemCoreClock = 100000000 +Atomthreads starting kern2... +kern2 PASS + +LPC17xx SystemCoreClock = 100000000 +Atomthreads starting kern3... +kern3 PASS + +LPC17xx SystemCoreClock = 100000000 +Atomthreads starting kern4... +kern4 PASS + +LPC17xx SystemCoreClock = 100000000 +Atomthreads starting timer1... +timer1 PASS + +LPC17xx SystemCoreClock = 100000000 +Atomthreads starting timer2... +timer2 PASS + +LPC17xx SystemCoreClock = 100000000 +Atomthreads starting timer3... +timer3 PASS + +LPC17xx SystemCoreClock = 100000000 +Atomthreads starting timer5... +timer5 PASS + +LPC17xx SystemCoreClock = 100000000 +Atomthreads starting timer6... +timer6 PASS + +LPC17xx SystemCoreClock = 100000000 +Atomthreads starting timer7... +timer7 PASS + +LPC17xx SystemCoreClock = 100000000 +Atomthreads starting queue1... +queue1 PASS + +LPC17xx SystemCoreClock = 100000000 +Atomthreads starting queue2... +queue2 PASS + +LPC17xx SystemCoreClock = 100000000 +Atomthreads starting queue3... +queue3 PASS + +LPC17xx SystemCoreClock = 100000000 +Atomthreads starting queue4... +queue4 PASS + +LPC17xx SystemCoreClock = 100000000 +Atomthreads starting queue5... +queue5 PASS + +LPC17xx SystemCoreClock = 100000000 +Atomthreads starting queue6... +queue6 PASS + +LPC17xx SystemCoreClock = 100000000 +Atomthreads starting queue7... +queue7 PASS + +LPC17xx SystemCoreClock = 100000000 +Atomthreads starting queue8... +queue8 PASS + +LPC17xx SystemCoreClock = 100000000 +Atomthreads starting queue9... +queue9 PASS + +LPC17xx SystemCoreClock = 100000000 +Atomthreads starting sem1... +sem1 PASS + +LPC17xx SystemCoreClock = 100000000 +Atomthreads starting sem2... +sem2 PASS + +LPC17xx SystemCoreClock = 100000000 +Atomthreads starting sem3... +sem3 PASS + +LPC17xx SystemCoreClock = 100000000 +Atomthreads starting sem5... +sem5 PASS + +LPC17xx SystemCoreClock = 100000000 +Atomthreads starting sem6... +sem6 PASS + +LPC17xx SystemCoreClock = 100000000 +Atomthreads starting sem7... +sem7 PASS + +LPC17xx SystemCoreClock = 100000000 +Atomthreads starting sem8... +sem8 PASS + +LPC17xx SystemCoreClock = 100000000 +Atomthreads starting sem9... +sem9 PASS + +LPC17xx SystemCoreClock = 100000000 +Atomthreads starting mutex4... +mutex4 PASS + +LPC17xx SystemCoreClock = 100000000 +Atomthreads starting sem4... +sem4 PASS + +LPC17xx SystemCoreClock = 100000000 +Atomthreads starting timer4... +timer4 PASS + diff --git a/platforms/lpc17xx/drivers/lpc17xx.h b/platforms/lpc17xx/drivers/lpc17xx.h new file mode 100644 index 0000000..377fdf2 --- /dev/null +++ b/platforms/lpc17xx/drivers/lpc17xx.h @@ -0,0 +1,1035 @@ +/**************************************************************************//** + * @file LPC17xx.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for + * NXP LPC17xx Device Series + * @version: V1.09 + * @date: 17. March 2010 + + * + * @note + * Copyright (C) 2009 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + + +#ifndef __LPC17xx_H__ +#define __LPC17xx_H__ + +/* + * ========================================================================== + * ---------- Interrupt Number Definition ----------------------------------- + * ========================================================================== + */ + +typedef enum IRQn +{ +/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ + +/****** LPC17xx Specific Interrupt Numbers *******************************************************/ + WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */ + TIMER0_IRQn = 1, /*!< Timer0 Interrupt */ + TIMER1_IRQn = 2, /*!< Timer1 Interrupt */ + TIMER2_IRQn = 3, /*!< Timer2 Interrupt */ + TIMER3_IRQn = 4, /*!< Timer3 Interrupt */ + UART0_IRQn = 5, /*!< UART0 Interrupt */ + UART1_IRQn = 6, /*!< UART1 Interrupt */ + UART2_IRQn = 7, /*!< UART2 Interrupt */ + UART3_IRQn = 8, /*!< UART3 Interrupt */ + PWM1_IRQn = 9, /*!< PWM1 Interrupt */ + I2C0_IRQn = 10, /*!< I2C0 Interrupt */ + I2C1_IRQn = 11, /*!< I2C1 Interrupt */ + I2C2_IRQn = 12, /*!< I2C2 Interrupt */ + SPI_IRQn = 13, /*!< SPI Interrupt */ + SSP0_IRQn = 14, /*!< SSP0 Interrupt */ + SSP1_IRQn = 15, /*!< SSP1 Interrupt */ + PLL0_IRQn = 16, /*!< PLL0 Lock (Main PLL) Interrupt */ + RTC_IRQn = 17, /*!< Real Time Clock Interrupt */ + EINT0_IRQn = 18, /*!< External Interrupt 0 Interrupt */ + EINT1_IRQn = 19, /*!< External Interrupt 1 Interrupt */ + EINT2_IRQn = 20, /*!< External Interrupt 2 Interrupt */ + EINT3_IRQn = 21, /*!< External Interrupt 3 Interrupt */ + ADC_IRQn = 22, /*!< A/D Converter Interrupt */ + BOD_IRQn = 23, /*!< Brown-Out Detect Interrupt */ + USB_IRQn = 24, /*!< USB Interrupt */ + CAN_IRQn = 25, /*!< CAN Interrupt */ + DMA_IRQn = 26, /*!< General Purpose DMA Interrupt */ + I2S_IRQn = 27, /*!< I2S Interrupt */ + ENET_IRQn = 28, /*!< Ethernet Interrupt */ + RIT_IRQn = 29, /*!< Repetitive Interrupt Timer Interrupt */ + MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */ + QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */ + PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */ + USBActivity_IRQn = 33, /* USB Activity interrupt */ + CANActivity_IRQn = 34, /* CAN Activity interrupt */ +} IRQn_Type; + + +/* + * ========================================================================== + * ----------- Processor and Core Peripheral Section ------------------------ + * ========================================================================== + */ + +/* Configuration of the Cortex-M3 Processor and Core Peripherals */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + + +#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */ +#include "system_LPC17xx.h" /* System Header */ + + +/******************************************************************************/ +/* Device Specific Peripheral registers structures */ +/******************************************************************************/ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/*------------- System Control (SC) ------------------------------------------*/ +typedef struct +{ + __IO uint32_t FLASHCFG; /* Flash Accelerator Module */ + uint32_t RESERVED0[31]; + __IO uint32_t PLL0CON; /* Clocking and Power Control */ + __IO uint32_t PLL0CFG; + __I uint32_t PLL0STAT; + __O uint32_t PLL0FEED; + uint32_t RESERVED1[4]; + __IO uint32_t PLL1CON; + __IO uint32_t PLL1CFG; + __I uint32_t PLL1STAT; + __O uint32_t PLL1FEED; + uint32_t RESERVED2[4]; + __IO uint32_t PCON; + __IO uint32_t PCONP; + uint32_t RESERVED3[15]; + __IO uint32_t CCLKCFG; + __IO uint32_t USBCLKCFG; + __IO uint32_t CLKSRCSEL; + __IO uint32_t CANSLEEPCLR; + __IO uint32_t CANWAKEFLAGS; + uint32_t RESERVED4[10]; + __IO uint32_t EXTINT; /* External Interrupts */ + uint32_t RESERVED5; + __IO uint32_t EXTMODE; + __IO uint32_t EXTPOLAR; + uint32_t RESERVED6[12]; + __IO uint32_t RSID; /* Reset */ + uint32_t RESERVED7[7]; + __IO uint32_t SCS; /* Syscon Miscellaneous Registers */ + __IO uint32_t IRCTRIM; /* Clock Dividers */ + __IO uint32_t PCLKSEL0; + __IO uint32_t PCLKSEL1; + uint32_t RESERVED8[4]; + __IO uint32_t USBIntSt; /* USB Device/OTG Interrupt Register */ + __IO uint32_t DMAREQSEL; + __IO uint32_t CLKOUTCFG; /* Clock Output Configuration */ + } LPC_SC_TypeDef; + +/*------------- Pin Connect Block (PINCON) -----------------------------------*/ +typedef struct +{ + __IO uint32_t PINSEL0; + __IO uint32_t PINSEL1; + __IO uint32_t PINSEL2; + __IO uint32_t PINSEL3; + __IO uint32_t PINSEL4; + __IO uint32_t PINSEL5; + __IO uint32_t PINSEL6; + __IO uint32_t PINSEL7; + __IO uint32_t PINSEL8; + __IO uint32_t PINSEL9; + __IO uint32_t PINSEL10; + uint32_t RESERVED0[5]; + __IO uint32_t PINMODE0; + __IO uint32_t PINMODE1; + __IO uint32_t PINMODE2; + __IO uint32_t PINMODE3; + __IO uint32_t PINMODE4; + __IO uint32_t PINMODE5; + __IO uint32_t PINMODE6; + __IO uint32_t PINMODE7; + __IO uint32_t PINMODE8; + __IO uint32_t PINMODE9; + __IO uint32_t PINMODE_OD0; + __IO uint32_t PINMODE_OD1; + __IO uint32_t PINMODE_OD2; + __IO uint32_t PINMODE_OD3; + __IO uint32_t PINMODE_OD4; + __IO uint32_t I2CPADCFG; +} LPC_PINCON_TypeDef; + +/*------------- General Purpose Input/Output (GPIO) --------------------------*/ +typedef struct +{ + union { + __IO uint32_t FIODIR; + struct { + __IO uint16_t FIODIRL; + __IO uint16_t FIODIRH; + }; + struct { + __IO uint8_t FIODIR0; + __IO uint8_t FIODIR1; + __IO uint8_t FIODIR2; + __IO uint8_t FIODIR3; + }; + }; + uint32_t RESERVED0[3]; + union { + __IO uint32_t FIOMASK; + struct { + __IO uint16_t FIOMASKL; + __IO uint16_t FIOMASKH; + }; + struct { + __IO uint8_t FIOMASK0; + __IO uint8_t FIOMASK1; + __IO uint8_t FIOMASK2; + __IO uint8_t FIOMASK3; + }; + }; + union { + __IO uint32_t FIOPIN; + struct { + __IO uint16_t FIOPINL; + __IO uint16_t FIOPINH; + }; + struct { + __IO uint8_t FIOPIN0; + __IO uint8_t FIOPIN1; + __IO uint8_t FIOPIN2; + __IO uint8_t FIOPIN3; + }; + }; + union { + __IO uint32_t FIOSET; + struct { + __IO uint16_t FIOSETL; + __IO uint16_t FIOSETH; + }; + struct { + __IO uint8_t FIOSET0; + __IO uint8_t FIOSET1; + __IO uint8_t FIOSET2; + __IO uint8_t FIOSET3; + }; + }; + union { + __O uint32_t FIOCLR; + struct { + __O uint16_t FIOCLRL; + __O uint16_t FIOCLRH; + }; + struct { + __O uint8_t FIOCLR0; + __O uint8_t FIOCLR1; + __O uint8_t FIOCLR2; + __O uint8_t FIOCLR3; + }; + }; +} LPC_GPIO_TypeDef; + +typedef struct +{ + __I uint32_t IntStatus; + __I uint32_t IO0IntStatR; + __I uint32_t IO0IntStatF; + __O uint32_t IO0IntClr; + __IO uint32_t IO0IntEnR; + __IO uint32_t IO0IntEnF; + uint32_t RESERVED0[3]; + __I uint32_t IO2IntStatR; + __I uint32_t IO2IntStatF; + __O uint32_t IO2IntClr; + __IO uint32_t IO2IntEnR; + __IO uint32_t IO2IntEnF; +} LPC_GPIOINT_TypeDef; + +/*------------- Timer (TIM) --------------------------------------------------*/ +typedef struct +{ + __IO uint32_t IR; + __IO uint32_t TCR; + __IO uint32_t TC; + __IO uint32_t PR; + __IO uint32_t PC; + __IO uint32_t MCR; + __IO uint32_t MR0; + __IO uint32_t MR1; + __IO uint32_t MR2; + __IO uint32_t MR3; + __IO uint32_t CCR; + __I uint32_t CR0; + __I uint32_t CR1; + uint32_t RESERVED0[2]; + __IO uint32_t EMR; + uint32_t RESERVED1[12]; + __IO uint32_t CTCR; +} LPC_TIM_TypeDef; + +/*------------- Pulse-Width Modulation (PWM) ---------------------------------*/ +typedef struct +{ + __IO uint32_t IR; + __IO uint32_t TCR; + __IO uint32_t TC; + __IO uint32_t PR; + __IO uint32_t PC; + __IO uint32_t MCR; + __IO uint32_t MR0; + __IO uint32_t MR1; + __IO uint32_t MR2; + __IO uint32_t MR3; + __IO uint32_t CCR; + __I uint32_t CR0; + __I uint32_t CR1; + __I uint32_t CR2; + __I uint32_t CR3; + uint32_t RESERVED0; + __IO uint32_t MR4; + __IO uint32_t MR5; + __IO uint32_t MR6; + __IO uint32_t PCR; + __IO uint32_t LER; + uint32_t RESERVED1[7]; + __IO uint32_t CTCR; +} LPC_PWM_TypeDef; + +/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/ +typedef struct +{ + union { + __I uint8_t RBR; + __O uint8_t THR; + __IO uint8_t DLL; + uint32_t RESERVED0; + }; + union { + __IO uint8_t DLM; + __IO uint32_t IER; + }; + union { + __I uint32_t IIR; + __O uint8_t FCR; + }; + __IO uint8_t LCR; + uint8_t RESERVED1[7]; + __I uint8_t LSR; + uint8_t RESERVED2[7]; + __IO uint8_t SCR; + uint8_t RESERVED3[3]; + __IO uint32_t ACR; + __IO uint8_t ICR; + uint8_t RESERVED4[3]; + __IO uint8_t FDR; + uint8_t RESERVED5[7]; + __IO uint8_t TER; + uint8_t RESERVED6[39]; + __IO uint32_t FIFOLVL; +} LPC_UART_TypeDef; + +typedef struct +{ + union { + __I uint8_t RBR; + __O uint8_t THR; + __IO uint8_t DLL; + uint32_t RESERVED0; + }; + union { + __IO uint8_t DLM; + __IO uint32_t IER; + }; + union { + __I uint32_t IIR; + __O uint8_t FCR; + }; + __IO uint8_t LCR; + uint8_t RESERVED1[7]; + __I uint8_t LSR; + uint8_t RESERVED2[7]; + __IO uint8_t SCR; + uint8_t RESERVED3[3]; + __IO uint32_t ACR; + __IO uint8_t ICR; + uint8_t RESERVED4[3]; + __IO uint8_t FDR; + uint8_t RESERVED5[7]; + __IO uint8_t TER; + uint8_t RESERVED6[39]; + __IO uint32_t FIFOLVL; +} LPC_UART0_TypeDef; + +typedef struct +{ + union { + __I uint8_t RBR; + __O uint8_t THR; + __IO uint8_t DLL; + uint32_t RESERVED0; + }; + union { + __IO uint8_t DLM; + __IO uint32_t IER; + }; + union { + __I uint32_t IIR; + __O uint8_t FCR; + }; + __IO uint8_t LCR; + uint8_t RESERVED1[3]; + __IO uint8_t MCR; + uint8_t RESERVED2[3]; + __I uint8_t LSR; + uint8_t RESERVED3[3]; + __I uint8_t MSR; + uint8_t RESERVED4[3]; + __IO uint8_t SCR; + uint8_t RESERVED5[3]; + __IO uint32_t ACR; + uint32_t RESERVED6; + __IO uint32_t FDR; + uint32_t RESERVED7; + __IO uint8_t TER; + uint8_t RESERVED8[27]; + __IO uint8_t RS485CTRL; + uint8_t RESERVED9[3]; + __IO uint8_t ADRMATCH; + uint8_t RESERVED10[3]; + __IO uint8_t RS485DLY; + uint8_t RESERVED11[3]; + __IO uint32_t FIFOLVL; +} LPC_UART1_TypeDef; + +/*------------- Serial Peripheral Interface (SPI) ----------------------------*/ +typedef struct +{ + __IO uint32_t SPCR; + __I uint32_t SPSR; + __IO uint32_t SPDR; + __IO uint32_t SPCCR; + uint32_t RESERVED0[3]; + __IO uint32_t SPINT; +} LPC_SPI_TypeDef; + +/*------------- Synchronous Serial Communication (SSP) -----------------------*/ +typedef struct +{ + __IO uint32_t CR0; + __IO uint32_t CR1; + __IO uint32_t DR; + __I uint32_t SR; + __IO uint32_t CPSR; + __IO uint32_t IMSC; + __IO uint32_t RIS; + __IO uint32_t MIS; + __IO uint32_t ICR; + __IO uint32_t DMACR; +} LPC_SSP_TypeDef; + +/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/ +typedef struct +{ + __IO uint32_t I2CONSET; + __I uint32_t I2STAT; + __IO uint32_t I2DAT; + __IO uint32_t I2ADR0; + __IO uint32_t I2SCLH; + __IO uint32_t I2SCLL; + __O uint32_t I2CONCLR; + __IO uint32_t MMCTRL; + __IO uint32_t I2ADR1; + __IO uint32_t I2ADR2; + __IO uint32_t I2ADR3; + __I uint32_t I2DATA_BUFFER; + __IO uint32_t I2MASK0; + __IO uint32_t I2MASK1; + __IO uint32_t I2MASK2; + __IO uint32_t I2MASK3; +} LPC_I2C_TypeDef; + +/*------------- Inter IC Sound (I2S) -----------------------------------------*/ +typedef struct +{ + __IO uint32_t I2SDAO; + __IO uint32_t I2SDAI; + __O uint32_t I2STXFIFO; + __I uint32_t I2SRXFIFO; + __I uint32_t I2SSTATE; + __IO uint32_t I2SDMA1; + __IO uint32_t I2SDMA2; + __IO uint32_t I2SIRQ; + __IO uint32_t I2STXRATE; + __IO uint32_t I2SRXRATE; + __IO uint32_t I2STXBITRATE; + __IO uint32_t I2SRXBITRATE; + __IO uint32_t I2STXMODE; + __IO uint32_t I2SRXMODE; +} LPC_I2S_TypeDef; + +/*------------- Repetitive Interrupt Timer (RIT) -----------------------------*/ +typedef struct +{ + __IO uint32_t RICOMPVAL; + __IO uint32_t RIMASK; + __IO uint8_t RICTRL; + uint8_t RESERVED0[3]; + __IO uint32_t RICOUNTER; +} LPC_RIT_TypeDef; + +/*------------- Real-Time Clock (RTC) ----------------------------------------*/ +typedef struct +{ + __IO uint8_t ILR; + uint8_t RESERVED0[7]; + __IO uint8_t CCR; + uint8_t RESERVED1[3]; + __IO uint8_t CIIR; + uint8_t RESERVED2[3]; + __IO uint8_t AMR; + uint8_t RESERVED3[3]; + __I uint32_t CTIME0; + __I uint32_t CTIME1; + __I uint32_t CTIME2; + __IO uint8_t SEC; + uint8_t RESERVED4[3]; + __IO uint8_t MIN; + uint8_t RESERVED5[3]; + __IO uint8_t HOUR; + uint8_t RESERVED6[3]; + __IO uint8_t DOM; + uint8_t RESERVED7[3]; + __IO uint8_t DOW; + uint8_t RESERVED8[3]; + __IO uint16_t DOY; + uint16_t RESERVED9; + __IO uint8_t MONTH; + uint8_t RESERVED10[3]; + __IO uint16_t YEAR; + uint16_t RESERVED11; + __IO uint32_t CALIBRATION; + __IO uint32_t GPREG0; + __IO uint32_t GPREG1; + __IO uint32_t GPREG2; + __IO uint32_t GPREG3; + __IO uint32_t GPREG4; + __IO uint8_t RTC_AUXEN; + uint8_t RESERVED12[3]; + __IO uint8_t RTC_AUX; + uint8_t RESERVED13[3]; + __IO uint8_t ALSEC; + uint8_t RESERVED14[3]; + __IO uint8_t ALMIN; + uint8_t RESERVED15[3]; + __IO uint8_t ALHOUR; + uint8_t RESERVED16[3]; + __IO uint8_t ALDOM; + uint8_t RESERVED17[3]; + __IO uint8_t ALDOW; + uint8_t RESERVED18[3]; + __IO uint16_t ALDOY; + uint16_t RESERVED19; + __IO uint8_t ALMON; + uint8_t RESERVED20[3]; + __IO uint16_t ALYEAR; + uint16_t RESERVED21; +} LPC_RTC_TypeDef; + +/*------------- Watchdog Timer (WDT) -----------------------------------------*/ +typedef struct +{ + __IO uint8_t WDMOD; + uint8_t RESERVED0[3]; + __IO uint32_t WDTC; + __O uint8_t WDFEED; + uint8_t RESERVED1[3]; + __I uint32_t WDTV; + __IO uint32_t WDCLKSEL; +} LPC_WDT_TypeDef; + +/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/ +typedef struct +{ + __IO uint32_t ADCR; + __IO uint32_t ADGDR; + uint32_t RESERVED0; + __IO uint32_t ADINTEN; + __I uint32_t ADDR0; + __I uint32_t ADDR1; + __I uint32_t ADDR2; + __I uint32_t ADDR3; + __I uint32_t ADDR4; + __I uint32_t ADDR5; + __I uint32_t ADDR6; + __I uint32_t ADDR7; + __I uint32_t ADSTAT; + __IO uint32_t ADTRM; +} LPC_ADC_TypeDef; + +/*------------- Digital-to-Analog Converter (DAC) ----------------------------*/ +typedef struct +{ + __IO uint32_t DACR; + __IO uint32_t DACCTRL; + __IO uint16_t DACCNTVAL; +} LPC_DAC_TypeDef; + +/*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/ +typedef struct +{ + __I uint32_t MCCON; + __O uint32_t MCCON_SET; + __O uint32_t MCCON_CLR; + __I uint32_t MCCAPCON; + __O uint32_t MCCAPCON_SET; + __O uint32_t MCCAPCON_CLR; + __IO uint32_t MCTIM0; + __IO uint32_t MCTIM1; + __IO uint32_t MCTIM2; + __IO uint32_t MCPER0; + __IO uint32_t MCPER1; + __IO uint32_t MCPER2; + __IO uint32_t MCPW0; + __IO uint32_t MCPW1; + __IO uint32_t MCPW2; + __IO uint32_t MCDEADTIME; + __IO uint32_t MCCCP; + __IO uint32_t MCCR0; + __IO uint32_t MCCR1; + __IO uint32_t MCCR2; + __I uint32_t MCINTEN; + __O uint32_t MCINTEN_SET; + __O uint32_t MCINTEN_CLR; + __I uint32_t MCCNTCON; + __O uint32_t MCCNTCON_SET; + __O uint32_t MCCNTCON_CLR; + __I uint32_t MCINTFLAG; + __O uint32_t MCINTFLAG_SET; + __O uint32_t MCINTFLAG_CLR; + __O uint32_t MCCAP_CLR; +} LPC_MCPWM_TypeDef; + +/*------------- Quadrature Encoder Interface (QEI) ---------------------------*/ +typedef struct +{ + __O uint32_t QEICON; + __I uint32_t QEISTAT; + __IO uint32_t QEICONF; + __I uint32_t QEIPOS; + __IO uint32_t QEIMAXPOS; + __IO uint32_t CMPOS0; + __IO uint32_t CMPOS1; + __IO uint32_t CMPOS2; + __I uint32_t INXCNT; + __IO uint32_t INXCMP; + __IO uint32_t QEILOAD; + __I uint32_t QEITIME; + __I uint32_t QEIVEL; + __I uint32_t QEICAP; + __IO uint32_t VELCOMP; + __IO uint32_t FILTER; + uint32_t RESERVED0[998]; + __O uint32_t QEIIEC; + __O uint32_t QEIIES; + __I uint32_t QEIINTSTAT; + __I uint32_t QEIIE; + __O uint32_t QEICLR; + __O uint32_t QEISET; +} LPC_QEI_TypeDef; + +/*------------- Controller Area Network (CAN) --------------------------------*/ +typedef struct +{ + __IO uint32_t mask[512]; /* ID Masks */ +} LPC_CANAF_RAM_TypeDef; + +typedef struct /* Acceptance Filter Registers */ +{ + __IO uint32_t AFMR; + __IO uint32_t SFF_sa; + __IO uint32_t SFF_GRP_sa; + __IO uint32_t EFF_sa; + __IO uint32_t EFF_GRP_sa; + __IO uint32_t ENDofTable; + __I uint32_t LUTerrAd; + __I uint32_t LUTerr; + __IO uint32_t FCANIE; + __IO uint32_t FCANIC0; + __IO uint32_t FCANIC1; +} LPC_CANAF_TypeDef; + +typedef struct /* Central Registers */ +{ + __I uint32_t CANTxSR; + __I uint32_t CANRxSR; + __I uint32_t CANMSR; +} LPC_CANCR_TypeDef; + +typedef struct /* Controller Registers */ +{ + __IO uint32_t MOD; + __O uint32_t CMR; + __IO uint32_t GSR; + __I uint32_t ICR; + __IO uint32_t IER; + __IO uint32_t BTR; + __IO uint32_t EWL; + __I uint32_t SR; + __IO uint32_t RFS; + __IO uint32_t RID; + __IO uint32_t RDA; + __IO uint32_t RDB; + __IO uint32_t TFI1; + __IO uint32_t TID1; + __IO uint32_t TDA1; + __IO uint32_t TDB1; + __IO uint32_t TFI2; + __IO uint32_t TID2; + __IO uint32_t TDA2; + __IO uint32_t TDB2; + __IO uint32_t TFI3; + __IO uint32_t TID3; + __IO uint32_t TDA3; + __IO uint32_t TDB3; +} LPC_CAN_TypeDef; + +/*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/ +typedef struct /* Common Registers */ +{ + __I uint32_t DMACIntStat; + __I uint32_t DMACIntTCStat; + __O uint32_t DMACIntTCClear; + __I uint32_t DMACIntErrStat; + __O uint32_t DMACIntErrClr; + __I uint32_t DMACRawIntTCStat; + __I uint32_t DMACRawIntErrStat; + __I uint32_t DMACEnbldChns; + __IO uint32_t DMACSoftBReq; + __IO uint32_t DMACSoftSReq; + __IO uint32_t DMACSoftLBReq; + __IO uint32_t DMACSoftLSReq; + __IO uint32_t DMACConfig; + __IO uint32_t DMACSync; +} LPC_GPDMA_TypeDef; + +typedef struct /* Channel Registers */ +{ + __IO uint32_t DMACCSrcAddr; + __IO uint32_t DMACCDestAddr; + __IO uint32_t DMACCLLI; + __IO uint32_t DMACCControl; + __IO uint32_t DMACCConfig; +} LPC_GPDMACH_TypeDef; + +/*------------- Universal Serial Bus (USB) -----------------------------------*/ +typedef struct +{ + __I uint32_t HcRevision; /* USB Host Registers */ + __IO uint32_t HcControl; + __IO uint32_t HcCommandStatus; + __IO uint32_t HcInterruptStatus; + __IO uint32_t HcInterruptEnable; + __IO uint32_t HcInterruptDisable; + __IO uint32_t HcHCCA; + __I uint32_t HcPeriodCurrentED; + __IO uint32_t HcControlHeadED; + __IO uint32_t HcControlCurrentED; + __IO uint32_t HcBulkHeadED; + __IO uint32_t HcBulkCurrentED; + __I uint32_t HcDoneHead; + __IO uint32_t HcFmInterval; + __I uint32_t HcFmRemaining; + __I uint32_t HcFmNumber; + __IO uint32_t HcPeriodicStart; + __IO uint32_t HcLSTreshold; + __IO uint32_t HcRhDescriptorA; + __IO uint32_t HcRhDescriptorB; + __IO uint32_t HcRhStatus; + __IO uint32_t HcRhPortStatus1; + __IO uint32_t HcRhPortStatus2; + uint32_t RESERVED0[40]; + __I uint32_t Module_ID; + + __I uint32_t OTGIntSt; /* USB On-The-Go Registers */ + __IO uint32_t OTGIntEn; + __O uint32_t OTGIntSet; + __O uint32_t OTGIntClr; + __IO uint32_t OTGStCtrl; + __IO uint32_t OTGTmr; + uint32_t RESERVED1[58]; + + __I uint32_t USBDevIntSt; /* USB Device Interrupt Registers */ + __IO uint32_t USBDevIntEn; + __O uint32_t USBDevIntClr; + __O uint32_t USBDevIntSet; + + __O uint32_t USBCmdCode; /* USB Device SIE Command Registers */ + __I uint32_t USBCmdData; + + __I uint32_t USBRxData; /* USB Device Transfer Registers */ + __O uint32_t USBTxData; + __I uint32_t USBRxPLen; + __O uint32_t USBTxPLen; + __IO uint32_t USBCtrl; + __O uint32_t USBDevIntPri; + + __I uint32_t USBEpIntSt; /* USB Device Endpoint Interrupt Regs */ + __IO uint32_t USBEpIntEn; + __O uint32_t USBEpIntClr; + __O uint32_t USBEpIntSet; + __O uint32_t USBEpIntPri; + + __IO uint32_t USBReEp; /* USB Device Endpoint Realization Reg*/ + __O uint32_t USBEpInd; + __IO uint32_t USBMaxPSize; + + __I uint32_t USBDMARSt; /* USB Device DMA Registers */ + __O uint32_t USBDMARClr; + __O uint32_t USBDMARSet; + uint32_t RESERVED2[9]; + __IO uint32_t USBUDCAH; + __I uint32_t USBEpDMASt; + __O uint32_t USBEpDMAEn; + __O uint32_t USBEpDMADis; + __I uint32_t USBDMAIntSt; + __IO uint32_t USBDMAIntEn; + uint32_t RESERVED3[2]; + __I uint32_t USBEoTIntSt; + __O uint32_t USBEoTIntClr; + __O uint32_t USBEoTIntSet; + __I uint32_t USBNDDRIntSt; + __O uint32_t USBNDDRIntClr; + __O uint32_t USBNDDRIntSet; + __I uint32_t USBSysErrIntSt; + __O uint32_t USBSysErrIntClr; + __O uint32_t USBSysErrIntSet; + uint32_t RESERVED4[15]; + + union { + __I uint32_t I2C_RX; /* USB OTG I2C Registers */ + __O uint32_t I2C_TX; + }; + __I uint32_t I2C_STS; + __IO uint32_t I2C_CTL; + __IO uint32_t I2C_CLKHI; + __O uint32_t I2C_CLKLO; + uint32_t RESERVED5[824]; + + union { + __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */ + __IO uint32_t OTGClkCtrl; + }; + union { + __I uint32_t USBClkSt; + __I uint32_t OTGClkSt; + }; +} LPC_USB_TypeDef; + +/*------------- Ethernet Media Access Controller (EMAC) ----------------------*/ +typedef struct +{ + __IO uint32_t MAC1; /* MAC Registers */ + __IO uint32_t MAC2; + __IO uint32_t IPGT; + __IO uint32_t IPGR; + __IO uint32_t CLRT; + __IO uint32_t MAXF; + __IO uint32_t SUPP; + __IO uint32_t TEST; + __IO uint32_t MCFG; + __IO uint32_t MCMD; + __IO uint32_t MADR; + __O uint32_t MWTD; + __I uint32_t MRDD; + __I uint32_t MIND; + uint32_t RESERVED0[2]; + __IO uint32_t SA0; + __IO uint32_t SA1; + __IO uint32_t SA2; + uint32_t RESERVED1[45]; + __IO uint32_t Command; /* Control Registers */ + __I uint32_t Status; + __IO uint32_t RxDescriptor; + __IO uint32_t RxStatus; + __IO uint32_t RxDescriptorNumber; + __I uint32_t RxProduceIndex; + __IO uint32_t RxConsumeIndex; + __IO uint32_t TxDescriptor; + __IO uint32_t TxStatus; + __IO uint32_t TxDescriptorNumber; + __IO uint32_t TxProduceIndex; + __I uint32_t TxConsumeIndex; + uint32_t RESERVED2[10]; + __I uint32_t TSV0; + __I uint32_t TSV1; + __I uint32_t RSV; + uint32_t RESERVED3[3]; + __IO uint32_t FlowControlCounter; + __I uint32_t FlowControlStatus; + uint32_t RESERVED4[34]; + __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */ + __IO uint32_t RxFilterWoLStatus; + __IO uint32_t RxFilterWoLClear; + uint32_t RESERVED5; + __IO uint32_t HashFilterL; + __IO uint32_t HashFilterH; + uint32_t RESERVED6[882]; + __I uint32_t IntStatus; /* Module Control Registers */ + __IO uint32_t IntEnable; + __O uint32_t IntClear; + __O uint32_t IntSet; + uint32_t RESERVED7; + __IO uint32_t PowerDown; + uint32_t RESERVED8; + __IO uint32_t Module_ID; +} LPC_EMAC_TypeDef; + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + + +/******************************************************************************/ +/* Peripheral memory map */ +/******************************************************************************/ +/* Base addresses */ +#define LPC_FLASH_BASE (0x00000000UL) +#define LPC_RAM_BASE (0x10000000UL) +#define LPC_GPIO_BASE (0x2009C000UL) +#define LPC_APB0_BASE (0x40000000UL) +#define LPC_APB1_BASE (0x40080000UL) +#define LPC_AHB_BASE (0x50000000UL) +#define LPC_CM3_BASE (0xE0000000UL) + +/* APB0 peripherals */ +#define LPC_WDT_BASE (LPC_APB0_BASE + 0x00000) +#define LPC_TIM0_BASE (LPC_APB0_BASE + 0x04000) +#define LPC_TIM1_BASE (LPC_APB0_BASE + 0x08000) +#define LPC_UART0_BASE (LPC_APB0_BASE + 0x0C000) +#define LPC_UART1_BASE (LPC_APB0_BASE + 0x10000) +#define LPC_PWM1_BASE (LPC_APB0_BASE + 0x18000) +#define LPC_I2C0_BASE (LPC_APB0_BASE + 0x1C000) +#define LPC_SPI_BASE (LPC_APB0_BASE + 0x20000) +#define LPC_RTC_BASE (LPC_APB0_BASE + 0x24000) +#define LPC_GPIOINT_BASE (LPC_APB0_BASE + 0x28080) +#define LPC_PINCON_BASE (LPC_APB0_BASE + 0x2C000) +#define LPC_SSP1_BASE (LPC_APB0_BASE + 0x30000) +#define LPC_ADC_BASE (LPC_APB0_BASE + 0x34000) +#define LPC_CANAF_RAM_BASE (LPC_APB0_BASE + 0x38000) +#define LPC_CANAF_BASE (LPC_APB0_BASE + 0x3C000) +#define LPC_CANCR_BASE (LPC_APB0_BASE + 0x40000) +#define LPC_CAN1_BASE (LPC_APB0_BASE + 0x44000) +#define LPC_CAN2_BASE (LPC_APB0_BASE + 0x48000) +#define LPC_I2C1_BASE (LPC_APB0_BASE + 0x5C000) + +/* APB1 peripherals */ +#define LPC_SSP0_BASE (LPC_APB1_BASE + 0x08000) +#define LPC_DAC_BASE (LPC_APB1_BASE + 0x0C000) +#define LPC_TIM2_BASE (LPC_APB1_BASE + 0x10000) +#define LPC_TIM3_BASE (LPC_APB1_BASE + 0x14000) +#define LPC_UART2_BASE (LPC_APB1_BASE + 0x18000) +#define LPC_UART3_BASE (LPC_APB1_BASE + 0x1C000) +#define LPC_I2C2_BASE (LPC_APB1_BASE + 0x20000) +#define LPC_I2S_BASE (LPC_APB1_BASE + 0x28000) +#define LPC_RIT_BASE (LPC_APB1_BASE + 0x30000) +#define LPC_MCPWM_BASE (LPC_APB1_BASE + 0x38000) +#define LPC_QEI_BASE (LPC_APB1_BASE + 0x3C000) +#define LPC_SC_BASE (LPC_APB1_BASE + 0x7C000) + +/* AHB peripherals */ +#define LPC_EMAC_BASE (LPC_AHB_BASE + 0x00000) +#define LPC_GPDMA_BASE (LPC_AHB_BASE + 0x04000) +#define LPC_GPDMACH0_BASE (LPC_AHB_BASE + 0x04100) +#define LPC_GPDMACH1_BASE (LPC_AHB_BASE + 0x04120) +#define LPC_GPDMACH2_BASE (LPC_AHB_BASE + 0x04140) +#define LPC_GPDMACH3_BASE (LPC_AHB_BASE + 0x04160) +#define LPC_GPDMACH4_BASE (LPC_AHB_BASE + 0x04180) +#define LPC_GPDMACH5_BASE (LPC_AHB_BASE + 0x041A0) +#define LPC_GPDMACH6_BASE (LPC_AHB_BASE + 0x041C0) +#define LPC_GPDMACH7_BASE (LPC_AHB_BASE + 0x041E0) +#define LPC_USB_BASE (LPC_AHB_BASE + 0x0C000) + +/* GPIOs */ +#define LPC_GPIO0_BASE (LPC_GPIO_BASE + 0x00000) +#define LPC_GPIO1_BASE (LPC_GPIO_BASE + 0x00020) +#define LPC_GPIO2_BASE (LPC_GPIO_BASE + 0x00040) +#define LPC_GPIO3_BASE (LPC_GPIO_BASE + 0x00060) +#define LPC_GPIO4_BASE (LPC_GPIO_BASE + 0x00080) + + +/******************************************************************************/ +/* Peripheral declaration */ +/******************************************************************************/ +#define LPC_SC ((LPC_SC_TypeDef *) LPC_SC_BASE ) +#define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE ) +#define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE ) +#define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE ) +#define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE ) +#define LPC_GPIO4 ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE ) +#define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE ) +#define LPC_TIM0 ((LPC_TIM_TypeDef *) LPC_TIM0_BASE ) +#define LPC_TIM1 ((LPC_TIM_TypeDef *) LPC_TIM1_BASE ) +#define LPC_TIM2 ((LPC_TIM_TypeDef *) LPC_TIM2_BASE ) +#define LPC_TIM3 ((LPC_TIM_TypeDef *) LPC_TIM3_BASE ) +#define LPC_RIT ((LPC_RIT_TypeDef *) LPC_RIT_BASE ) +#define LPC_UART0 ((LPC_UART0_TypeDef *) LPC_UART0_BASE ) +#define LPC_UART1 ((LPC_UART1_TypeDef *) LPC_UART1_BASE ) +#define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE ) +#define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE ) +#define LPC_PWM1 ((LPC_PWM_TypeDef *) LPC_PWM1_BASE ) +#define LPC_I2C0 ((LPC_I2C_TypeDef *) LPC_I2C0_BASE ) +#define LPC_I2C1 ((LPC_I2C_TypeDef *) LPC_I2C1_BASE ) +#define LPC_I2C2 ((LPC_I2C_TypeDef *) LPC_I2C2_BASE ) +#define LPC_I2S ((LPC_I2S_TypeDef *) LPC_I2S_BASE ) +#define LPC_SPI ((LPC_SPI_TypeDef *) LPC_SPI_BASE ) +#define LPC_RTC ((LPC_RTC_TypeDef *) LPC_RTC_BASE ) +#define LPC_GPIOINT ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE ) +#define LPC_PINCON ((LPC_PINCON_TypeDef *) LPC_PINCON_BASE ) +#define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE ) +#define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE ) +#define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE ) +#define LPC_DAC ((LPC_DAC_TypeDef *) LPC_DAC_BASE ) +#define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE) +#define LPC_CANAF ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE ) +#define LPC_CANCR ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE ) +#define LPC_CAN1 ((LPC_CAN_TypeDef *) LPC_CAN1_BASE ) +#define LPC_CAN2 ((LPC_CAN_TypeDef *) LPC_CAN2_BASE ) +#define LPC_MCPWM ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE ) +#define LPC_QEI ((LPC_QEI_TypeDef *) LPC_QEI_BASE ) +#define LPC_EMAC ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE ) +#define LPC_GPDMA ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE ) +#define LPC_GPDMACH0 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE ) +#define LPC_GPDMACH1 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE ) +#define LPC_GPDMACH2 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE ) +#define LPC_GPDMACH3 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE ) +#define LPC_GPDMACH4 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE ) +#define LPC_GPDMACH5 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE ) +#define LPC_GPDMACH6 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE ) +#define LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE ) +#define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE ) + +#endif // __LPC17xx_H__ diff --git a/platforms/lpc17xx/drivers/lpc17xx_uart.c b/platforms/lpc17xx/drivers/lpc17xx_uart.c new file mode 100644 index 0000000..3a0202f --- /dev/null +++ b/platforms/lpc17xx/drivers/lpc17xx_uart.c @@ -0,0 +1,166 @@ +/**************************************************************************//** + * @file lpc17xx_uart.c + * @brief Drivers for UART peripheral in lpc17xx. + * @version 1.0 + * @date 18. Nov. 2010 + * + * @note + * Copyright (C) 2010 NXP Semiconductors(NXP). All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * products. This software is supplied "AS IS" without any warranties. + * NXP Semiconductors assumes no responsibility or liability for the + * use of the software, conveys no license or title under any patent, + * copyright, or mask work right to the product. NXP Semiconductors + * reserves the right to make changes in the software without + * notification. NXP Semiconductors also make no representation or + * warranty that such application will be suitable for the specified + * use without further testing or modification. + ******************************************************************************/ + +#include +#include +#include "lpc17xx_uart.h" +#include "lpc17xx.h" + + +/** + * @brief Initializes the UART0. + * + * @param baudrate: Specifies the baud rate + * @retval None + */ +void LPC17xx_UART_Init(uint32_t baudrate) +{ + uint32_t Fdiv; + uint32_t pclkdiv, pclk; + + /***/ + LPC_PINCON->PINSEL0 &= ~0x000000F0; + + LPC_PINCON->PINSEL0 |= 0x00000050; /* RxD0 and TxD0 */ + + /* PCLK_UART0=CCLK/2 */ + //**LPC_SC->PCLKSEL1 &= ~(3<<6); /* PCLK_UART0 = CCLK/4 (18MHz) */ + //**LPC_SC->PCLKSEL1 |= (2<<6); /* PCLK_UART0 = CCLK/2 (36MHz) */ + //**pclk = SystemCoreClock/2; + + /* By default, the PCLKSELx value is zero, thus, the PCLK for + all the peripherals is 1/4 of the SystemFrequency. */ + /* Bit 6~7 is for UART0 */ + pclkdiv = (LPC_SC->PCLKSEL0 >> 6) & 0x03; + switch ( pclkdiv ) + { + case 0x00: + default: + pclk = SystemCoreClock/4; + break; + case 0x01: + pclk = SystemCoreClock; + break; + case 0x02: + pclk = SystemCoreClock/2; + break; + case 0x03: + pclk = SystemCoreClock/8; + break; + } + + LPC_UART0->LCR = 0x83; /* 8 bits, no Parity, 1 Stop bit */ + Fdiv = ( pclk / 16 ) / baudrate ; /*baud rate */ + LPC_UART0->DLM = Fdiv / 256; + LPC_UART0->DLL = Fdiv % 256; + LPC_UART0->LCR = 0x03; /* DLAB = 0 */ + LPC_UART0->FCR = 0x07; /* Enable and reset TX and RX FIFO. */ +} + +/** + * @brief Write one character to UART0. + * + * @param ch: Character to be written + * @retval None + */ +void LPC17xx_UART_PutChar (uint8_t ch) +{ + while (!(LPC_UART0->LSR & 0x20)); + + LPC_UART0->THR = ch; +} + +/** + * @brief Read one character from UART0 (blocking read). + * + * @param None + * @retval Received character + */ +uint8_t LPC17xx_UART_GetChar (void) +{ + while (!(LPC_UART0->LSR & 0x01)); + return (LPC_UART0->RBR); +} + +/** + * @brief Read one character from UART0 (non blocking read). + * + * @param None + * @retval Received character + */ +uint8_t LPC17xx_UART_GetChar_nb (void) +{ + if (LPC_UART0->LSR & 0x01) + return (LPC_UART0->RBR); + else + return 0; +} + +/** + * @brief Write a string to UART0. + * + * @param str: NULL-terminated char string to be written + * @retval None + */ +void LPC17xx_UART_PutString (uint8_t *str) +{ +/* usage: LPC1700_UART_Printf("xxx\n\r");*/ +#if 1 + while (*str != 0) + { + LPC17xx_UART_PutChar(*str++); + } + +#else +/* usage: LPC1700_UART_Printf("xxx\n");*/ + while ((*str) != 0) { + if (*str == '\n') { + LPC17xx_UART_PutChar(*str++); + LPC17xx_UART_PutChar('\r'); + } else { + LPC17xx_UART_PutChar(*str++); + } + } +#endif +} + +/** + * @brief Print formatted string. This function takes variable length arguments. + * + * @param format + * @param ... + * @retval None + * + * Note: using library functions "vsprintf" will increase the RO size by about 6KB + */ +//void LPC17xx_UART_Printf (const uint8_t *format, ...) +//{ +// static uint8_t buffer[40 + 1]; +// va_list vArgs; +// +// va_start(vArgs, format); +// vsprintf((char *)buffer, (char const *)format, vArgs); +// va_end(vArgs); +// LPC17xx_UART_PutString((uint8_t *) buffer); +//} + +/* --------------------------------- End Of File ------------------------------ */ diff --git a/platforms/lpc17xx/drivers/lpc17xx_uart.h b/platforms/lpc17xx/drivers/lpc17xx_uart.h new file mode 100644 index 0000000..9e7f045 --- /dev/null +++ b/platforms/lpc17xx/drivers/lpc17xx_uart.h @@ -0,0 +1,37 @@ +/**************************************************************************//** + * @file lpc17xx_uart.h + * @brief Header file for lpc17xx_uart.c. + * @version 1.0 + * @date 18. Nov. 2010 + * + * @note + * Copyright (C) 2010 NXP Semiconductors(NXP). All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * products. This software is supplied "AS IS" without any warranties. + * NXP Semiconductors assumes no responsibility or liability for the + * use of the software, conveys no license or title under any patent, + * copyright, or mask work right to the product. NXP Semiconductors + * reserves the right to make changes in the software without + * notification. NXP Semiconductors also make no representation or + * warranty that such application will be suitable for the specified + * use without further testing or modification. + ******************************************************************************/ + +#ifndef __LPC17xx_UART_H_ +#define __LPC17xx_UART_H_ + +#include + +/* external functions */ +void LPC17xx_UART_PutChar (uint8_t); +uint8_t LPC17xx_UART_GetChar (void); +void LPC17xx_UART_Init(uint32_t baudrate); +//void LPC17xx_UART_Printf (const uint8_t *format, ...); +void LPC17xx_UART_PutString (uint8_t *str) ; + +#endif // __LPC17xx_UART_H_ + +/* --------------------------------- End Of File ------------------------------ */ diff --git a/platforms/lpc17xx/main.c b/platforms/lpc17xx/main.c new file mode 100644 index 0000000..755f965 --- /dev/null +++ b/platforms/lpc17xx/main.c @@ -0,0 +1,116 @@ +/* + * Copyright (c) 2012, Natie van Rooyen. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. No personal names or organizations' names associated with the + * Atomthreads project may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + + +#include "LPC17xx.h" +#include "drivers/lpc17xx_uart.h" +#include +#include "modules.h" +#include "atom.h" +#include "tests/atomtests.h" + +// for mbed board +#define LED1_GPIO (1 << 18) +#define LED2_GPIO (1 << 20) +#define LED3_GPIO (1 << 21) +#define LED4_GPIO (1 << 23) + +#define LED_GET(led) (LPC_GPIO1->FIOSET & led) +#define LED_SET(led, on) { if (on) LPC_GPIO1->FIOSET = led ; else LPC_GPIO1->FIOCLR = led ; } +#define LED_TOGGLE(led) LED_SET(led, !LED_GET(led)) + + +#ifndef ATOMTHREADS_TEST +#define ATOMTHREADS_TEST "kern1" +#endif + +#define TEST_STACK_BYTE_SIZE 1024 +#define IDLE_STACK_BYTE_SIZE 512 + +static unsigned char test_stack[TEST_STACK_BYTE_SIZE] ; +static unsigned char idle_stack[IDLE_STACK_BYTE_SIZE] ; +ATOM_TCB test_tcb ; + + +/** + * \b test_thread + * + * Function calling the test function of the Atomthreads test suite. + * + */ +void +test_thread (uint32_t param) +{ + uint32_t failures ; + static volatile unsigned int i ; + CRITICAL_STORE ; + + failures = test_start () ; + + atomTimerDelay (10) ; + CRITICAL_START() ; + dbg_format_msg ("%s %s\r\n", ATOMTHREADS_TEST, failures ? "FAIL" : "PASS") ; + CRITICAL_END() ; + + while(1) { + LED_TOGGLE(LED1_GPIO) ; + for (i=0; i<1000000; i++) ; + } + +} + +int main(void) { + + static volatile unsigned int i ; + + // mbed board + LPC_GPIO1->FIODIR |= LED1_GPIO | LED2_GPIO | LED3_GPIO | LED4_GPIO ; + + dbg_format_msg ("\r\nLPC17xx SystemCoreClock = %d\r\n",SystemCoreClock) ; + + //atomthreads_stress_test (36) ; + + dbg_format_msg ("Atomthreads starting %s... \r\n", ATOMTHREADS_TEST) ; + + atomOSInit(&idle_stack[0], IDLE_STACK_BYTE_SIZE, TRUE) ; + atomThreadCreate ((ATOM_TCB *)&test_tcb, TEST_THREAD_PRIO, test_thread, 0, &test_stack[0], TEST_STACK_BYTE_SIZE, TRUE); + atomOSStart() ; + + + + while(1) { + + LED_TOGGLE(LED1_GPIO) ; + for (i=0; i<1000000; i++) ; + + + } + return 0 ; +} + diff --git a/platforms/lpc17xx/modules.c b/platforms/lpc17xx/modules.c new file mode 100644 index 0000000..7901bcd --- /dev/null +++ b/platforms/lpc17xx/modules.c @@ -0,0 +1,178 @@ +/* + * Copyright (c) 2012, Natie van Rooyen. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. No personal names or organizations' names associated with the + * Atomthreads project may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include "modules.h" +#include +#include +#include "atomport_private.h" +#include "atom.h" +#include "atomport.h" + + + +/** + * \b dbg_format_msg + * + * Same as printf. + * + */ +void +dbg_format_msg (char *format, ...) +{ + va_list args; + static char msg[256] ; + //CRITICAL_STORE ; + + va_start (args, format) ; + //CRITICAL_START() ; + vsnprintf ((char*)msg, 256, (char*)format, args) ; + LPC17xx_UART_PutString (msg) ; + //CRITICAL_END() ; + +} + + +/** + * \b low_level_init + * + * Initializes the PIC and start the system timer tick intrerupt. + * + */ +int +low_level_init (void) +{ + SystemInit () ; + SystemCoreClockUpdate (); + //contextInit () ; + NVIC_SetPriority (PendSV_IRQn, 0xFF) ; + LPC17xx_UART_Init (115200) ; + SysTick_Config (1000000) ; + + return 0 ; +} + + + +/** + * \b __context_preempt_handler + * + * System timer tic interupt handler. + * + */ +void +__context_tick_handler (void) +{ + + /* Call the interrupt enter routine */ + atomIntEnter(); + + /* Call the OS system tick handler */ + atomTimerTick(); + + /* Call the interrupt exit routine */ + atomIntExit(TRUE); + +} + +/** + * \b dbg_mem_dump_40 + * + * Dumps size bytes of memory from data. + * + */ +void dbg_mem_dump_40 (unsigned int* data, int size) +{ + int j ; + + dbg_format_msg ("Dump %d bytes at %.8X:\r\n",size * 4, (unsigned int)data) ; + data = (unsigned int*)((unsigned int)data & ~0x3) ; + for (j=0; jSHCSR); + + dbg_mem_dump_40 (hardfault_args, 0x40) ; + + while (1); + +} + diff --git a/platforms/lpc17xx/modules.h b/platforms/lpc17xx/modules.h new file mode 100644 index 0000000..e947d38 --- /dev/null +++ b/platforms/lpc17xx/modules.h @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2012, Natie van Rooyen. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. No personal names or organizations' names associated with the + * Atomthreads project may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __MODULES_H__ +#define __MODULES_H__ + +/* + * Module definitions to use with the Stellaris LM3S6965 Microcontroller + */ + + +#include "LPC17xx.h" +#include "drivers/lpc17xx_uart.h" + + +/* Function prototypes */ +extern int low_level_init (void) ; +extern void dbg_format_msg (char *format, ...) ; +extern void dbg_fault_handler (unsigned int * hardfault_args) ; + +#endif /* __MODULES_H__ */ diff --git a/platforms/lpc17xx/startup.c b/platforms/lpc17xx/startup.c new file mode 100644 index 0000000..87a90a5 --- /dev/null +++ b/platforms/lpc17xx/startup.c @@ -0,0 +1,295 @@ +/**************************************************************************//** + * @file startup.c + * @brief + * @version + * @date + * + * @note + * Copyright (C) 2010 NXP Semiconductors(NXP). All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * products. This software is supplied "AS IS" without any warranties. + * NXP Semiconductors assumes no responsibility or liability for the + * use of the software, conveys no license or title under any patent, + * copyright, or mask work right to the product. NXP Semiconductors + * reserves the right to make changes in the software without + * notification. NXP Semiconductors also make no representation or + * warranty that such application will be suitable for the specified + * use without further testing or modification. + ******************************************************************************/ +#define WEAK __attribute__ ((weak)) +#define ALIAS(f) __attribute__ ((weak, alias (#f))) + + +#include "system_LPC17xx.h" +#include "atomport_private.h" + + + + + void ResetISR(void); +WEAK void NMI_Handler(void); +WEAK void HardFault_Handler(void); +WEAK void MemManage_Handler(void); +WEAK void BusFault_Handler(void); +WEAK void UsageFault_Handler(void); +WEAK void SVC_Handler(void); +WEAK void DebugMon_Handler(void); +WEAK void PendSV_Handler(void); +WEAK void SysTick_Handler(void); +WEAK void IntDefault_Handler(void); + + +//***************************************************************************** +// +// The entry point for the application. +// __main() is the entry point for Redlib based applications +// main() is the entry point for Newlib based applications +// +//***************************************************************************** + +extern int main(void); +//***************************************************************************** +// +// External declaration for the pointer to the stack top from the Linker Script +// +//***************************************************************************** +extern void _vStackTop(void); + + +//***************************************************************************** +// +// The vector table. +// This relies on the linker script to place at correct location in memory. +// +//***************************************************************************** +extern void (* const g_pfnVectors[])(void); +__attribute__ ((section(".isr_vector"))) +void (* const g_pfnVectors[])(void) = { + // Core Level - CM3 + &_vStackTop, // The initial stack pointer + ResetISR, // The reset handler + NMI_Handler, // The NMI handler + HardFault_Handler, // The hard fault handler + MemManage_Handler, // The MPU fault handler + BusFault_Handler, // The bus fault handler + UsageFault_Handler, // The usage fault handler + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + SVC_Handler, // SVCall handler + DebugMon_Handler, // Debug monitor handler + 0, // Reserved + archPendSVHandler, // The PendSV handler + archTickHandler /*SysTick_Handler*/, // The SysTick handler + + // Chip Level - LPC17 + IntDefault_Handler, // 16, 0x40 - WDT + IntDefault_Handler, // 17, 0x44 - TIMER0 + IntDefault_Handler, // 18, 0x48 - TIMER1 + IntDefault_Handler, // 19, 0x4c - TIMER2 + IntDefault_Handler, // 20, 0x50 - TIMER3 + IntDefault_Handler, // 21, 0x54 - UART0 + IntDefault_Handler, // 22, 0x58 - UART1 + IntDefault_Handler, // 23, 0x5c - UART2 + IntDefault_Handler, // 24, 0x60 - UART3 + IntDefault_Handler, // 25, 0x64 - PWM1 + IntDefault_Handler, // 26, 0x68 - I2C0 + IntDefault_Handler, // 27, 0x6c - I2C1 + IntDefault_Handler, // 28, 0x70 - I2C2 + IntDefault_Handler, // 29, 0x74 - SPI + IntDefault_Handler, // 30, 0x78 - SSP0 + IntDefault_Handler, // 31, 0x7c - SSP1 + IntDefault_Handler, // 32, 0x80 - PLL0 (Main PLL) + IntDefault_Handler, // 33, 0x84 - RTC + IntDefault_Handler, // 34, 0x88 - EINT0 + IntDefault_Handler, // 35, 0x8c - EINT1 + IntDefault_Handler, // 36, 0x90 - EINT2 + IntDefault_Handler, // 37, 0x94 - EINT3 + IntDefault_Handler, // 38, 0x98 - ADC + IntDefault_Handler, // 39, 0x9c - BOD + IntDefault_Handler, // 40, 0xA0 - USB + IntDefault_Handler, // 41, 0xa4 - CAN + IntDefault_Handler, // 42, 0xa8 - GP DMA + IntDefault_Handler, // 43, 0xac - I2S + IntDefault_Handler, // 44, 0xb0 - Ethernet + IntDefault_Handler, // 45, 0xb4 - RITINT + IntDefault_Handler, // 46, 0xb8 - Motor Control PWM + IntDefault_Handler, // 47, 0xbc - Quadrature Encoder + IntDefault_Handler, // 48, 0xc0 - PLL1 (USB PLL) + IntDefault_Handler, // 49, 0xc4 - USB Activity interrupt to wakeup + IntDefault_Handler, // 50, 0xc8 - CAN Activity interrupt to wakeup +}; + +//***************************************************************************** +// Functions to carry out the initialization of RW and BSS data sections. These +// are written as separate functions rather than being inlined within the +// ResetISR() function in order to cope with MCUs with multiple banks of +// memory. +//***************************************************************************** +__attribute__ ((section(".after_vectors"))) +void data_init(unsigned int romstart, unsigned int start, unsigned int len) { + unsigned int *pulDest = (unsigned int*) start; + unsigned int *pulSrc = (unsigned int*) romstart; + unsigned int loop; + for (loop = 0; loop < len; loop = loop + 4) + *pulDest++ = *pulSrc++; +} + +__attribute__ ((section(".after_vectors"))) +void bss_init(unsigned int start, unsigned int len) { + unsigned int *pulDest = (unsigned int*) start; + unsigned int loop; + for (loop = 0; loop < len; loop = loop + 4) + *pulDest++ = 0; +} + + +//***************************************************************************** +// The following symbols are constructs generated by the linker, indicating +// the location of various points in the "Global Section Table". This table is +// created by the linker via the Code Red managed linker script mechanism. It +// contains the load address, execution address and length of each RW data +// section and the execution and length of each BSS (zero initialized) section. +//***************************************************************************** +extern unsigned int __data_section_table; +extern unsigned int __data_section_table_end; +extern unsigned int __bss_section_table; +extern unsigned int __bss_section_table_end; + + +//***************************************************************************** +// Reset entry point for your code. +// Sets up a simple runtime environment and initializes the C/C++ +// library. +//***************************************************************************** +__attribute__ ((section(".after_vectors"))) +void +ResetISR(void) { + + // + // Copy the data sections from flash to SRAM. + // + unsigned int LoadAddr, ExeAddr, SectionLen; + unsigned int *SectionTableAddr; + + // Load base address of Global Section Table + SectionTableAddr = &__data_section_table; + + // Copy the data sections from flash to SRAM. + while (SectionTableAddr < &__data_section_table_end) { + LoadAddr = *SectionTableAddr++; + ExeAddr = *SectionTableAddr++; + SectionLen = *SectionTableAddr++; + data_init(LoadAddr, ExeAddr, SectionLen); + } + // At this point, SectionTableAddr = &__bss_section_table; + // Zero fill the bss segment + while (SectionTableAddr < &__bss_section_table_end) { + ExeAddr = *SectionTableAddr++; + SectionLen = *SectionTableAddr++; + bss_init(ExeAddr, SectionLen); + } + + + + low_level_init(); + + + + + main(); + + + // + // main() shouldn't return, but if it does, we'll just enter an infinite loop + // + while (1) ; +} + +//***************************************************************************** +// Default exception handlers. Override the ones here by defining your own +// handler routines in your application code. +//***************************************************************************** +__attribute__ ((section(".after_vectors"))) __attribute__( ( naked ) ) +void NMI_Handler(void) +{ + while(1) ; + +} + +__attribute__ ((section(".after_vectors"))) __attribute__( ( naked ) ) +void HardFault_Handler(void) +{ + + __asm volatile + ( + " tst lr, #4 \n" + " ite eq \n" + " mrseq r0, msp \n" + " mrsne r0, psp \n" + " b dbg_fault_handler \n" + ); + + while(1) ; + +} + +__attribute__ ((section(".after_vectors"))) __attribute__( ( naked ) ) +void MemManage_Handler(void) +{ + while(1) ; + +} + +__attribute__ ((section(".after_vectors"))) __attribute__( ( naked ) ) +void BusFault_Handler(void) +{ + while(1) ; + +} + +__attribute__ ((section(".after_vectors"))) __attribute__( ( naked ) ) +void UsageFault_Handler(void) +{ + while(1) ; + +} + +__attribute__ ((section(".after_vectors"))) __attribute__( ( naked ) ) +void SVC_Handler(void) +{ + while(1) ; + +} + +__attribute__ ((section(".after_vectors"))) __attribute__( ( naked ) ) +void DebugMon_Handler(void) +{ + while(1) ; + +} + +__attribute__ ((section(".after_vectors"))) __attribute__( ( naked ) ) +void PendSV_Handler(void) +{ + while(1) ; + +} + +__attribute__ ((section(".after_vectors"))) __attribute__( ( naked ) ) +void SysTick_Handler(void) +{ + while(1) ; + +} + +__attribute__ ((section(".after_vectors"))) __attribute__( ( naked ) ) +void IntDefault_Handler(void) +{ + while(1) ; + +} diff --git a/platforms/lpc17xx/system.ld b/platforms/lpc17xx/system.ld new file mode 100644 index 0000000..0112192 --- /dev/null +++ b/platforms/lpc17xx/system.ld @@ -0,0 +1,148 @@ +/**************************************************************************//** + * @file system.ld + * @brief + * @version + * @date + * + * @note + * Copyright (C) 2010 NXP Semiconductors(NXP). All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * products. This software is supplied "AS IS" without any warranties. + * NXP Semiconductors assumes no responsibility or liability for the + * use of the software, conveys no license or title under any patent, + * copyright, or mask work right to the product. NXP Semiconductors + * reserves the right to make changes in the software without + * notification. NXP Semiconductors also make no representation or + * warranty that such application will be suitable for the specified + * use without further testing or modification. + ******************************************************************************/ + +MEMORY +{ + /* Define each memory region */ + MFlash512 (rx) : ORIGIN = 0x0, LENGTH = 0x80000 /* 512k */ + RamLoc32 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x8000 /* 32k */ + RamAHB32 (rwx) : ORIGIN = 0x2007c000, LENGTH = 0x8000 /* 32k */ + +} + /* Define a symbol for the top of each memory region */ + __top_MFlash512 = 0x0 + 0x80000; + __top_RamLoc32 = 0x10000000 + 0x8000; + __top_RamAHB32 = 0x2007c000 + 0x8000; + + + +ENTRY(ResetISR) + +SECTIONS +{ + + /* MAIN TEXT SECTION */ + .text : ALIGN(4) + { + FILL(0xff) + KEEP(*(.isr_vector)) + + /* Global Section Table */ + . = ALIGN(4) ; + __section_table_start = .; + __data_section_table = .; + LONG(LOADADDR(.data)); + LONG( ADDR(.data)) ; + LONG( SIZEOF(.data)); + LONG(LOADADDR(.data_RAM2)); + LONG( ADDR(.data_RAM2)) ; + LONG( SIZEOF(.data_RAM2)); + __data_section_table_end = .; + __bss_section_table = .; + LONG( ADDR(.bss)); + LONG( SIZEOF(.bss)); + LONG( ADDR(.bss_RAM2)); + LONG( SIZEOF(.bss_RAM2)); + __bss_section_table_end = .; + __section_table_end = . ; + /* End of Global Section Table */ + + + *(.after_vectors*) + + *(.text*) + *(.rodata .rodata.*) + . = ALIGN(4); + + } > MFlash512 + + /* + * for exception handling/unwind - some Newlib functions (in common + * with C++ and STDC++) use this. + * Use KEEP so not discarded with --gc-sections + */ + .ARM.extab : ALIGN(4) + { + KEEP(*(.ARM.extab* .gnu.linkonce.armextab.*)) + } > MFlash512 + __exidx_start = .; + + .ARM.exidx : ALIGN(4) + { + KEEP(*(.ARM.exidx* .gnu.linkonce.armexidx.*)) + } > MFlash512 + __exidx_end = .; + + _etext = .; + + + .data_RAM2 : ALIGN(4) + { + FILL(0xff) + *(.data.$RAM2*) + *(.data.$RamAHB32*) + . = ALIGN(4) ; + } > RamAHB32 AT>MFlash512 + + /* MAIN DATA SECTION */ + + .uninit_RESERVED : ALIGN(4) + { + KEEP(*(.bss.$RESERVED*)) + . = ALIGN(4) ; + _end_uninit_RESERVED = .; + } > RamLoc32 + + .data : ALIGN(4) + { + FILL(0xff) + _data = .; + *(vtable) + *(.data*) + . = ALIGN(4) ; + _edata = .; + } > RamLoc32 AT>MFlash512 + + + .bss_RAM2 : ALIGN(4) + { + *(.bss.$RAM2*) + *(.bss.$RamAHB32*) + . = ALIGN(4) ; + } > RamAHB32 + + /* MAIN BSS SECTION */ + .bss : ALIGN(4) + { + __bss_start__ = . ; + _bss = .; + *(.bss*) + *(COMMON) + . = ALIGN(4) ; + __bss_end__ = . ; + _ebss = .; + PROVIDE(end = .); + } > RamLoc32 + + PROVIDE(_pvHeapStart = .); + PROVIDE(_vStackTop = __top_RamLoc32 - 0); +} From 8d62300d4144b5059dfa582ed6d479c326ac10e8 Mon Sep 17 00:00:00 2001 From: Natie van Rooyen Date: Tue, 23 Oct 2012 14:45:12 +0200 Subject: [PATCH 23/28] updates --- platforms/lpc17xx/README | 16 +++ platforms/qemu_integratorcp/modules.h | 40 +++--- platforms/qemu_lm3s/Makefile | 1 + platforms/qemu_lm3s/modules.h | 107 ++++++++-------- platforms/rules.mk | 2 + ports/arm/types.h | 4 + ports/cortex_m/atomport_s.S | 4 + ports/cortex_m/types.h | 6 + tests/stress1.c | 176 ++++++++++++++++++++++++++ tests/stress1.h | 18 +++ 10 files changed, 296 insertions(+), 78 deletions(-) create mode 100644 platforms/lpc17xx/README create mode 100644 tests/stress1.c create mode 100644 tests/stress1.h diff --git a/platforms/lpc17xx/README b/platforms/lpc17xx/README new file mode 100644 index 0000000..d23d34f --- /dev/null +++ b/platforms/lpc17xx/README @@ -0,0 +1,16 @@ +--------------------------------------------------------------------------- + +Library: Atomthreads NXP LPC17xx Platform. +Author: Natie van Rooyen +License: BSD Revised + +--------------------------------------------------------------------------- + +NXP LPC17xx Platform + +The "lpc17xx" platform contains sources for building a sample Atomthreads +application for the NXP LPC17xx platform. + +The platform was tested on the mbed NXP LPC1768 (http://www.mbed.org). + + diff --git a/platforms/qemu_integratorcp/modules.h b/platforms/qemu_integratorcp/modules.h index a94140a..538dec6 100644 --- a/platforms/qemu_integratorcp/modules.h +++ b/platforms/qemu_integratorcp/modules.h @@ -36,23 +36,19 @@ #include "atomport.h" -typedef volatile unsigned int REG_DWORD ; -typedef volatile unsigned short REG_WORD ; -typedef volatile unsigned char REG_BYTE ; - // ***************************************************************************** // INTEGRATORCP TIMER // ***************************************************************************** typedef struct ICP_TIMER_S { // offset read/write word size reset Description - REG_DWORD LOAD ; // 0x0000 Read/write 32 0x00000000 Load value for Timer - REG_DWORD VALUE ; // 0x0004 Read 32 0xFFFFFFFF The current value for Timer - REG_BYTE CONTROL ; // 0x0008 Read/write 8 0x20 Timer control register - REG_DWORD INTCLR ; // 0x000C Write - - Timer interrupt clear - REG_DWORD RIS ; // 0x0010 Read 1 0x0 Timer raw interrupt status - REG_DWORD MIS ; // 0x0014 Read 1 0x0 Timer masked interrupt status - REG_DWORD BGLOAD ; // 0x0018 Read/write 32 0x00000000 Background load value for Timer + __IO uint32_t LOAD ; // 0x0000 Read/write 32 0x00000000 Load value for Timer + __I uint32_t VALUE ; // 0x0004 Read 32 0xFFFFFFFF The current value for Timer + __IO uint8_t CONTROL ; // 0x0008 Read/write 8 0x20 Timer control register + __O uint32_t INTCLR ; // 0x000C Write - - Timer interrupt clear + __I uint32_t RIS ; // 0x0010 Read 1 0x0 Timer raw interrupt status + __I uint32_t MIS ; // 0x0014 Read 1 0x0 Timer masked interrupt status + __IO uint32_t BGLOAD ; // 0x0018 Read/write 32 0x00000000 Background load value for Timer } ICP_TIMER_T, *PICP_TIMER_T ; @@ -82,17 +78,17 @@ typedef struct ICP_TIMER_S { // ***************************************************************************** typedef struct ICP_PIC_S { // offset read/write word size reset Description - REG_DWORD IRQ_STATUS ; // 0x0000 Read 22 IRQ gated interrupt status - REG_DWORD IRQ_RAWSTAT ; // 0x0004 Read 22 IRQ raw interrupt status - REG_DWORD IRQ_ENABLESET ; // 0x0008 Read/write 22 IRQ enable set - REG_DWORD IRQ_ENABLECLR ; // 0x000C Write 22 IRQ enable clear - REG_DWORD INT_SOFTSET ; // 0x0010 Read/write 16 Software interrupt set - REG_DWORD INT_SOFTCLR ; // 0x0014 Write 16 Software interrupt clear - REG_DWORD RESERVED[2] ; // 0x0018 - REG_DWORD FIQ_STATUS ; // 0x0020 Read 22 FIQ gated interrupt status - REG_DWORD FIQ_RAWSTAT ; // 0x0024 Read 22 FIQ raw interrupt status - REG_DWORD FIQ_ENABLESET ; // 0x0028 Read/write 22 FIQ enable set - REG_DWORD FIQ_ENABLECLR ; // 0x002C Write-only 22 FIQ enable clear + __I uint32_t IRQ_STATUS ; // 0x0000 Read 22 IRQ gated interrupt status + __I uint32_t IRQ_RAWSTAT ; // 0x0004 Read 22 IRQ raw interrupt status + __IO uint32_t IRQ_ENABLESET ; // 0x0008 Read/write 22 IRQ enable set + __O uint32_t IRQ_ENABLECLR ; // 0x000C Write 22 IRQ enable clear + __IO uint32_t INT_SOFTSET ; // 0x0010 Read/write 16 Software interrupt set + __O uint32_t INT_SOFTCLR ; // 0x0014 Write 16 Software interrupt clear + uint32_t RESERVED[2] ; // 0x0018 + __I uint32_t FIQ_STATUS ; // 0x0020 Read 22 FIQ gated interrupt status + __I uint32_t FIQ_RAWSTAT ; // 0x0024 Read 22 FIQ raw interrupt status + __IO uint32_t FIQ_ENABLESET ; // 0x0028 Read/write 22 FIQ enable set + __O uint32_t FIQ_ENABLECLR ; // 0x002C Write-only 22 FIQ enable clear } ICP_PIC_T, *PICP_PIC_T ; diff --git a/platforms/qemu_lm3s/Makefile b/platforms/qemu_lm3s/Makefile index dc9c117..fbdb94f 100644 --- a/platforms/qemu_lm3s/Makefile +++ b/platforms/qemu_lm3s/Makefile @@ -87,6 +87,7 @@ all_tests: fail_tests: make run_test "TEST_NAME=mutex4" + make run_test "TEST_NAME=timer4" make run_test "TEST_NAME=sem4" diff --git a/platforms/qemu_lm3s/modules.h b/platforms/qemu_lm3s/modules.h index 5a074b4..cc0d5f0 100644 --- a/platforms/qemu_lm3s/modules.h +++ b/platforms/qemu_lm3s/modules.h @@ -36,36 +36,31 @@ #include "atomport.h" -typedef volatile unsigned int REG_DWORD ; -typedef volatile unsigned short REG_WORD ; -typedef volatile unsigned char REG_BYTE ; - - // ***************************************************************************** // The Stellaris General-Purpose Timer Module (GPTM) // ***************************************************************************** typedef struct GPTM_TIMER_S { // offset read/write reset Description - REG_DWORD CFG ; // 0x000 R/W 0x00000000 GPTM Configuration 345 - REG_DWORD TAMR ; // 0x004 R/W 0x00000000 GPTM TimerA Mode 346 - REG_DWORD TBMR ; // 0x008 R/W 0x00000000 GPTM TimerB Mode 348 - REG_DWORD CTL ; // 0x00C R/W 0x00000000 GPTM Control 350 - REG_DWORD Reserved[2] ; // 0x010 - REG_DWORD IMR ; // 0x018 R/W 0x00000000 GPTM Interrupt Mask 353 - REG_DWORD RIS ; // 0x01C RO 0x00000000 GPTM Raw Interrupt Status 355 - REG_DWORD MIS ; // 0x020 RO 0x00000000 GPTM Masked Interrupt Status 356 - REG_DWORD ICR ; // 0x024 W1C 0x00000000 GPTM Interrupt Clear 357 - REG_DWORD TAILR ; // 0x028 R/W 0xFFFFFFFF GPTM TimerA Interval Load 359 - REG_DWORD TBILR ; // 0x02C R/W 0x0000FFFF GPTM TimerB Interval Load 360 - REG_DWORD TAMATCHR ; // 0x030 R/W 0xFFFFFFFF GPTM TimerA Match 361 - REG_DWORD TBMATCHR ; // 0x034 R/W 0x0000FFFF GPTM TimerB Match 362 - REG_DWORD TAPR ; // 0x038 R/W 0x00000000 GPTM TimerA Prescale 363 - REG_DWORD TBPR ; // 0x03C R/W 0x00000000 GPTM TimerB Prescale 364 - REG_DWORD TAPMR ; // 0x040 R/W 0x00000000 GPTM TimerA Prescale Match 365 - REG_DWORD TBPMR ; // 0x044 R/W 0x00000000 GPTM TimerB Prescale Match 366 - REG_DWORD TAR ; // 0x048 RO 0xFFFFFFFF GPTM TimerA 367 - REG_DWORD TBR ; // 0x04C RO 0x0000FFFF GPTM TimerB 368 + __IO uint32_t CFG ; // 0x000 R/W 0x00000000 GPTM Configuration 345 + __IO uint32_t TAMR ; // 0x004 R/W 0x00000000 GPTM TimerA Mode 346 + __IO uint32_t TBMR ; // 0x008 R/W 0x00000000 GPTM TimerB Mode 348 + __IO uint32_t CTL ; // 0x00C R/W 0x00000000 GPTM Control 350 + uint32_t Reserved[2] ; // 0x010 + __IO uint32_t IMR ; // 0x018 R/W 0x00000000 GPTM Interrupt Mask 353 + __I uint32_t RIS ; // 0x01C RO 0x00000000 GPTM Raw Interrupt Status 355 + __I uint32_t MIS ; // 0x020 RO 0x00000000 GPTM Masked Interrupt Status 356 + __O uint32_t ICR ; // 0x024 W1C 0x00000000 GPTM Interrupt Clear 357 + __IO uint32_t TAILR ; // 0x028 R/W 0xFFFFFFFF GPTM TimerA Interval Load 359 + __IO uint32_t TBILR ; // 0x02C R/W 0x0000FFFF GPTM TimerB Interval Load 360 + __IO uint32_t TAMATCHR ; // 0x030 R/W 0xFFFFFFFF GPTM TimerA Match 361 + __IO uint32_t TBMATCHR ; // 0x034 R/W 0x0000FFFF GPTM TimerB Match 362 + __IO uint32_t TAPR ; // 0x038 R/W 0x00000000 GPTM TimerA Prescale 363 + __IO uint32_t TBPR ; // 0x03C R/W 0x00000000 GPTM TimerB Prescale 364 + __IO uint32_t TAPMR ; // 0x040 R/W 0x00000000 GPTM TimerA Prescale Match 365 + __IO uint32_t TBPMR ; // 0x044 R/W 0x00000000 GPTM TimerB Prescale Match 366 + __I uint32_t TAR ; // 0x048 RO 0xFFFFFFFF GPTM TimerA 367 + __I uint32_t TBR ; // 0x04C RO 0x0000FFFF GPTM TimerB 368 } GPTM_TIMER_T, *PGPTM_TIMER_T ; @@ -89,7 +84,7 @@ typedef struct GPTM_TIMER_S { #define GPTM_TIMER_CTL_TBEVENT ((unsigned int)0x03 << 10) // Both edges #define GPTM_TIMER_CTL_TBSTALL ((unsigned int)0x01 << 9) // GPTM Timer B Stall Enable. 0 Timer B continues counting while the processor is halted by the debugger #define GPTM_TIMER_CTL_TBEN ((unsigned int)0x01 << 8) // GPTM TimerB Enable -// -------- // +// -------- #define GPTM_TIMER_CTL_TAPWML ((unsigned int)0x01 << 6) // GPTM TimerA PWM Output Level. 0 Output is unaffected. 1 Output is inverted. #define GPTM_TIMER_CTL_TAOTE ((unsigned int)0x01 << 5) // GPTM TimerA Output Trigger Enable. 0 The output TimerB ADC trigger is disabled. 1 The output TimerB ADC trigger is enabled. #define GPTM_TIMER_CTL_RTCEN ((unsigned int)0x01 << 4) // GPTM RTC Enable @@ -106,7 +101,7 @@ typedef struct GPTM_TIMER_S { #define GPTM_TIMER_INT_CBEIM ((unsigned int)0x01 << 10) // GPTM CaptureB Event Interrupt Mask #define GPTM_TIMER_INT_CBMIM ((unsigned int)0x01 << 9) // GPTM CaptureB Match Interrupt Mask #define GPTM_TIMER_INT_TBTOIM ((unsigned int)0x01 << 8) // GPTM TimerB Time-Out Interrupt Mask -// -------- // +// -------- #define GPTM_TIMER_INT_RTCIM ((unsigned int)0x01 << 3) // GPTM RTC Interrupt Mask #define GPTM_TIMER_INT_CAEIM ((unsigned int)0x01 << 2) // GPTM CaptureA Event Interrupt Mask #define GPTM_TIMER_INT_CAMIM ((unsigned int)0x01 << 1) // GPTM CaptureA Match Interrupt Mask @@ -119,14 +114,14 @@ typedef struct GPTM_TIMER_S { // ***************************************************************************** typedef struct SYSTICK_S { - REG_DWORD Res0[1] ; // 0xE000E000 - REG_DWORD ICT ; // 0xE000E004 - REG_DWORD Res1[2] ; // 0xE000E008 - REG_DWORD STCTRL ; // 0xE000E010 - REG_DWORD STRELOAD ; // 0xE000E014 - REG_DWORD STCURRENT; // 0xE000E018 - REG_DWORD STCALIB ; // 0xE000E01C - REG_DWORD Res2[56] ; // 0xE000E020 + uint32_t Res0[1] ; // 0xE000E000 + __IO uint32_t ICT ; // 0xE000E004 + uint32_t Res1[2] ; // 0xE000E008 + __IO uint32_t STCTRL ; // 0xE000E010 + __IO uint32_t STRELOAD ; // 0xE000E014 + __IO uint32_t STCURRENT; // 0xE000E018 + __IO uint32_t STCALIB ; // 0xE000E01C + uint32_t Res2[56] ; // 0xE000E020 } SYSTICK_T, *PSYSTICK_T ; @@ -145,18 +140,18 @@ typedef struct SYSTICK_S { // ***************************************************************************** typedef struct NVIC_S { - REG_DWORD ISER[2] ; // 0xE000E100 - REG_DWORD Res3[30] ; // 0xE000E120 - REG_DWORD ICER[2] ; // 0xE000E180 - REG_DWORD Res4[30] ; // 0xE000E1A0 - REG_DWORD ISPR[2] ; // 0xE000E200 - REG_DWORD Res5[30] ; // 0xE000E220 - REG_DWORD ICPR[2] ; // 0xE000E280 - REG_DWORD Res6[30] ; // 0xE000E2A0 - REG_DWORD IABR[2] ; // 0xE000E300 - REG_DWORD Res7[64] ; // 0xE000E320 - REG_DWORD IPR[2] ; // 0xE000E400 - // REG_DWORD Res7[515] ; // 0xE000E4F4 + __IO uint32_t ISER[2] ; // 0xE000E100 + uint32_t Res3[30] ; // 0xE000E120 + __IO uint32_t ICER[2] ; // 0xE000E180 + uint32_t Res4[30] ; // 0xE000E1A0 + __IO uint32_t ISPR[2] ; // 0xE000E200 + uint32_t Res5[30] ; // 0xE000E220 + __IO uint32_t ICPR[2] ; // 0xE000E280 + uint32_t Res6[30] ; // 0xE000E2A0 + __IO uint32_t IABR[2] ; // 0xE000E300 + uint32_t Res7[64] ; // 0xE000E320 + __IO uint32_t IPR[2] ; // 0xE000E400 + // uint32_t Res7[515] ; // 0xE000E4F4 } NVIC_T, *PNVIC_T ; @@ -176,17 +171,17 @@ typedef struct NVIC_S { // ***************************************************************************** typedef struct SCB_S { - REG_DWORD CPUID ; // 0xE000ED00 - REG_DWORD ICSR ; // 0xE000ED04 - REG_DWORD VTOR ; // 0xE000ED08 - REG_DWORD AIRCR ; // 0xE000ED0C - REG_DWORD SCR ; // 0xE000ED10 - REG_DWORD CCR ; // 0xE000ED14 + __IO uint32_t CPUID ; // 0xE000ED00 + __IO uint32_t ICSR ; // 0xE000ED04 + __IO uint32_t VTOR ; // 0xE000ED08 + __IO uint32_t AIRCR ; // 0xE000ED0C + __IO uint32_t SCR ; // 0xE000ED10 + __IO uint32_t CCR ; // 0xE000ED14 - REG_DWORD SYS_PRIO[3] ; // 0xE000ED18 - REG_DWORD SYSHNDCTRL ; // 0xE000ED24 - //REG_DWORD FAULTSTAT ; // 0xE000ED28 - //REG_DWORD HFAULTSTAT ; // 0xE000ED2C + __IO uint32_t SYS_PRIO[3] ; // 0xE000ED18 + __IO uint32_t SYSHNDCTRL ; // 0xE000ED24 + //__IO uint32_t FAULTSTAT ; // 0xE000ED28 + //__IO uint32_t HFAULTSTAT ; // 0xE000ED2C } SCB_T, *PSCB_T ; diff --git a/platforms/rules.mk b/platforms/rules.mk index 7f0f767..2d2210d 100644 --- a/platforms/rules.mk +++ b/platforms/rules.mk @@ -20,6 +20,8 @@ all: target target: $(OBJS) $(LN) $(LFLAGS) $(LIBFLAGS) $(OBJS) $(LLIBS) -o $(TARGET_NAME).elf @echo $(TARGET_NAME).elf was compiled + arm-none-eabi-objcopy -O binary $(TARGET_NAME).elf $(TARGET_NAME).bin + arm-none-eabi-objdump -dxS $(TARGET_NAME).elf > $(TARGET_NAME).out clean: rm -f $(OBJS) diff --git a/ports/arm/types.h b/ports/arm/types.h index c07e295..d06e82f 100644 --- a/ports/arm/types.h +++ b/ports/arm/types.h @@ -48,6 +48,10 @@ typedef char int8_t ; #define INLINE __inline #endif +/* IO definitions (access restrictions to peripheral registers) */ +#define __I volatile /*!< defines 'read only' permissions */ +#define __O volatile /*!< defines 'write only' permissions */ +#define __IO volatile /*!< defines 'read / write' permissions */ #endif /* __TYPES_H__ */ diff --git a/ports/cortex_m/atomport_s.S b/ports/cortex_m/atomport_s.S index 2e25d93..0300234 100644 --- a/ports/cortex_m/atomport_s.S +++ b/ports/cortex_m/atomport_s.S @@ -45,7 +45,11 @@ .equ NVIC_INT_CTRL, 0xE000ED04 // Interrupt control state register .equ NVIC_PENDSVSET, 0x10000000 // Value to trigger PendSV exception .equ NVIC_PR_12_15_ADDR, 0xE000ED20 // System Handlers 12-15 Priority Register Address +#ifdef PLATFORM_QEMU_LM3S_HACK .equ NVIC_PENDS_VPRIORITY, 0x00F00000 // PendSV priority is minimal (0xFF -- 0x00FF0000) +#else +.equ NVIC_PENDS_VPRIORITY, 0x00FF0000 // PendSV priority is minimal (0xFF -- 0x00FF0000) +#endif #ifdef PLATFORM_QEMU_LM3S_HACK .equ NVIC_ISER, 0xE000E100 diff --git a/ports/cortex_m/types.h b/ports/cortex_m/types.h index c07e295..e6f927d 100644 --- a/ports/cortex_m/types.h +++ b/ports/cortex_m/types.h @@ -30,6 +30,7 @@ #ifndef __TYPES_H__ #define __TYPES_H__ +#ifndef _STDINT_H typedef unsigned int uintptr_t ; typedef int intptr_t ; typedef unsigned long long uint64_t ; @@ -39,6 +40,7 @@ typedef unsigned char uint8_t ; typedef int int32_t ; typedef short int16_t ; typedef char int8_t ; +#endif #ifndef OFFSETOF #define OFFSETOF(TYPE, MEMBER) ((int) &((TYPE *)0)->MEMBER) @@ -48,6 +50,10 @@ typedef char int8_t ; #define INLINE __inline #endif +/* IO definitions (access restrictions to peripheral registers) */ +#define __I volatile /*!< defines 'read only' permissions */ +#define __O volatile /*!< defines 'write only' permissions */ +#define __IO volatile /*!< defines 'read / write' permissions */ #endif /* __TYPES_H__ */ diff --git a/tests/stress1.c b/tests/stress1.c new file mode 100644 index 0000000..c27b01e --- /dev/null +++ b/tests/stress1.c @@ -0,0 +1,176 @@ +#include +#include "stress1.h" +#include "atom.h" +#include "atommutex.h" +#include "atomsem.h" +#include "atomport.h" +#include "atomport-tests.h" + + +#define MAX_TEST_THREADS 36 + +static unsigned char idle_stack[IDLE_STACK_BYTE_SIZE] ; +static unsigned char monitor_stack[MONITOR_STACK_BYTE_SIZE] ; +static unsigned char stress_test_stack[MAX_TEST_THREADS+1][TEST_STACK_BYTE_SIZE] ; +static unsigned int test_counter[MAX_TEST_THREADS+1] = {0} ; + + +//static unsigned char test_idle_stack[TEST_STACK_BYTE_SIZE] ; + + +static uint8_t test_prio[120] = { + 005,010,100,200,250, 200,200,200,200,200, + 150,150,150,150,150, 250,250,250,250,250, + 101,102,103,104,105, 202,204,206,208,210, + 150,150,150,150,150, 250,250,250,250,250, + 121,122,123,124,125, 061,063,065,067,061, + 150,150,150,150,150, 250,250,250,250,250, + 005,010,100,200,250, 200,200,200,200,200, + 150,150,150,150,150, 250,250,250,250,250, + 101,102,103,104,105, 202,204,206,208,210, + 150,150,150,150,150, 250,250,250,250,250, + 121,122,123,124,125, 061,063,065,067,061, + 150,150,150,150,150, 250,250,250,250,250, + }; + +static uint32_t test_interv[120] = { + 002,001,001,001,001, 002,003,004,005,006, + 015,015,015,015,015, 025,024,023,022,021, + 905,005,005,005,805, 050,051,052,053,054, + 015,015,015,015,015, 025,024,023,022,021, + 030,030,030,030,030, 070,071,072,073,474, + 005,006,007,007,001, 001,001,003,003,005, + 001,001,001,001,001, 002,003,004,005,006, + 015,015,015,015,015, 025,024,023,022,021, + 905,005,005,005,805, 050,051,052,053,054, + 015,015,015,015,015, 025,024,023,022,021, + 030,030,030,030,030, 070,071,072,073,474, + 005,006,007,007,001, 001,001,003,003,005, + }; + + +ATOM_TCB test_tcb[MAX_TEST_THREADS+1] ; +ATOM_TCB monitor_tcb ; +ATOM_TCB test2_tcb ; +ATOM_TCB test3_tcb ; +ATOM_TCB test_idle_tcb ; + +void +monitor_thread (uint32_t parm) +{ + CRITICAL_STORE; + int i ; + unsigned int counter = 0 ; + ATOM_TCB *tcb ; + uint32_t print_lines_count = 0 ; + + tcb = atomCurrentContext() ; + + if (parm) { + print_lines_count = ((parm-1)>>2) + 1; + } + + for (;;counter++) + { + uint32_t time = atomTimeGet() ; + + CRITICAL_START(); + ATOMLOG (_STR("\r\nMonitor %d threads # %d (%08d)\r\n"), parm, counter, (unsigned int)time) ; + ATOMLOG (_STR("------------------------------\r\n")) ; + //CRITICAL_END(); + + for (i=0; i MAX_TEST_THREADS) { + thread_count = MAX_TEST_THREADS ; + } + + ATOMLOG (_STR("\r\natomthreads_stress_test %.3d threads\r\n"), thread_count) ; + ATOMLOG (_STR("-----------------------------------\r\n")) ; + + + atomOSInit(&idle_stack[0], IDLE_STACK_BYTE_SIZE, TRUE) ; + for (i=0; i< thread_count;i++) { + atomThreadCreate ((ATOM_TCB *)&test_tcb[i], test_prio[i], stress_test_thread, i, + &stress_test_stack[i][0], TEST_STACK_BYTE_SIZE, TRUE); + } + + atomThreadCreate ((ATOM_TCB *)&monitor_tcb, 150, monitor_thread, thread_count, + &monitor_stack[0], MONITOR_STACK_BYTE_SIZE, TRUE); + + atomOSStart() ; +} diff --git a/tests/stress1.h b/tests/stress1.h new file mode 100644 index 0000000..303e867 --- /dev/null +++ b/tests/stress1.h @@ -0,0 +1,18 @@ +#ifndef __STRESS1_H__ +#define __STRESS1_H__ + +#include "types.h" + +#define TEST_STACK_BYTE_SIZE 0x200 +#define IDLE_STACK_BYTE_SIZE 0x200 +#define MONITOR_STACK_BYTE_SIZE 0x400 + +#ifndef TEST_THREADS +#define TEST_THREADS 16 +#endif + +extern void atomthreads_stress_test (uint32_t thread_count) ; +extern uint32_t test_start (void) ; + +#endif /* __STRESS1_H__ */ + From d9f1f8389f62171356233d06632da9b25a4a5a55 Mon Sep 17 00:00:00 2001 From: Natie van Rooyen Date: Tue, 23 Oct 2012 14:53:32 +0200 Subject: [PATCH 24/28] atomvm updates --- ports/atomvm/atomvm.c | 23 +++++++++-------------- 1 file changed, 9 insertions(+), 14 deletions(-) diff --git a/ports/atomvm/atomvm.c b/ports/atomvm/atomvm.c index f6ff3a9..b48363f 100644 --- a/ports/atomvm/atomvm.c +++ b/ports/atomvm/atomvm.c @@ -182,12 +182,11 @@ static DWORD WINAPI vm_thread (LPVOID lpParameter) ; * \ingroup atomvm * \b atomvmCtrlCreate * -* This is an atomvm controll function used by a controlling thread -* and must not be called from the atom virtual machine. +* This is an atomvm controll function used by a controlling thread. * * Initializes the virtual machine. * -* @param[out] atomvm Handle to the virtual machine created. +* @param[out] atomvm Handle to the virtual machine to create. * * @return Zero on failure. */ @@ -282,7 +281,8 @@ atomvmCtrlRun (HATOMVM atomvm, uint32_t flags) #if (_WIN32_WINNT >= 0x0600) /* This is used for multi processor machines to ensure the thread - is stopped before executing the next instruction. */ + is stopped before executing the next instruction. Set + _WIN32_WINNT < 0x0600 if you are running Windows XP */ FlushProcessWriteBuffers (); #endif InterlockedExchange (&service_call->result, service_call->callback (patomvm, service_call)) ; @@ -358,7 +358,7 @@ atomvmCtrlRun (HATOMVM atomvm, uint32_t flags) * Closes the virtual machine and release all memory and handles created * in atomvmCtrlCreate. * -* ToDo: this function was never tested. +* ToDo: more testing. * * @param[in] atomvm Handle to the virtual machine created by atomvmCtrlCreate. * @@ -447,7 +447,6 @@ getAtomvm (void) ATOMVM_ASSERT(patomvm , _T("TlsGetValue failed")) ; return patomvm ; - } /** @@ -504,7 +503,6 @@ atomvmCtrlIntRequest (HATOMVM atomvm, uint32_t isr) SwitchToThread() ; } SetEvent (patomvm->atomvm_int) ; - } @@ -558,7 +556,6 @@ atomvmContextCreate (HATOMVM_CONTEXT* atomvm_context, uint32_t stack, uint32_t e ATOMVM_CALLBACK_CONTEXT context_init ; context_init.pcontext = new_context ; - new_context->interrupt_mask = 1 ; res = invokeCallback (patomvm, callbackContextCreate, (PATOMVM_CALLBACK)&context_init) ; @@ -592,16 +589,14 @@ callbackContextSwitch (PATOMVM patomvm, PATOMVM_CALLBACK callback) uint32_t res1 = 1 ; uint32_t res2 ; PATOMVM_CALLBACK_CONTEXT_SWITCH context_switch = (PATOMVM_CALLBACK_CONTEXT_SWITCH)callback ; - CONTEXT* p_old_context = &context_switch->p_old_context->context ; - CONTEXT* p_new_context = &context_switch->p_new_context->context ; - if (p_old_context) { - res1 = GetThreadContext (patomvm->vm_thread, p_old_context) ; + if (context_switch->p_old_context) { + res1 = GetThreadContext (patomvm->vm_thread, &context_switch->p_old_context->context) ; ATOMVM_ASSERT(res1 , _T("GetThreadContext failed")) ; } - InterlockedExchange ((volatile uint32_t*)&patomvm->current_context, (uint32_t)p_new_context) ; - res2 = SetThreadContext (patomvm->vm_thread, &patomvm->current_context->context) ; + patomvm->current_context = context_switch->p_new_context ; + res2 = SetThreadContext (patomvm->vm_thread, &context_switch->p_new_context->context) ; ATOMVM_ASSERT(res2 , _T("SetThreadContext failed")) ; return res1 & res2 ; From 8cdd707b413e4202028049b4c56b86f26cbb5013 Mon Sep 17 00:00:00 2001 From: Natie van Rooyen Date: Tue, 23 Oct 2012 16:58:10 +0200 Subject: [PATCH 25/28] Updated README for lpx17xx --- platforms/lpc17xx/README | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/platforms/lpc17xx/README b/platforms/lpc17xx/README index d23d34f..d8055a3 100644 --- a/platforms/lpc17xx/README +++ b/platforms/lpc17xx/README @@ -8,9 +8,10 @@ License: BSD Revised NXP LPC17xx Platform -The "lpc17xx" platform contains sources for building a sample Atomthreads -application for the NXP LPC17xx platform. - -The platform was tested on the mbed NXP LPC1768 (http://www.mbed.org). +The "lpc17xx" platform contains sources for building the Atomthreads test +suite for the NXP LPC17xx microcontroller. +The build was tested on the "mbed NXP LPC1768" board (http://www.mbed.org) +and the sources were compiled on Ubuntu 12.0.4 with the GNU ARM tool chain +using Newlib. From 9d18dafd72085b5deefd39422312787673a07497 Mon Sep 17 00:00:00 2001 From: Natie van Rooyen Date: Tue, 23 Oct 2012 17:45:25 +0200 Subject: [PATCH 26/28] Atomvm SWI functionality added. --- ports/atomvm/atomport.c | 4 +-- ports/atomvm/atomport.h | 4 +-- ports/atomvm/atomvm.c | 64 ++++++++++++++++++++++++++++++++++++---- ports/atomvm/atomvm.h | 5 ++-- ports/atomvm/msvc/main.c | 6 ++-- 5 files changed, 68 insertions(+), 15 deletions(-) diff --git a/ports/atomvm/atomport.c b/ports/atomvm/atomport.c index a9bc46f..55d6d69 100644 --- a/ports/atomvm/atomport.c +++ b/ports/atomvm/atomport.c @@ -51,7 +51,7 @@ static HANDLE cntrl_thread ; * */ void -atomvmRun () +atomvmRun (void) { atomvmCtrlCreate (&the_atomvm) ; cntrl_thread = CreateThread (NULL, 0, cntrl_thread_proc, (uint32_t*)the_atomvm, CREATE_SUSPENDED, NULL) ; @@ -147,7 +147,7 @@ archContextSwitch (ATOM_TCB * p_sp_old, ATOM_TCB * p_sp_new) * System timer tick interrupt handler. * */ -void archTimerTickIrqHandler () +void archTimerTickIrqHandler (void) { atomIntEnter(); diff --git a/ports/atomvm/atomport.h b/ports/atomvm/atomport.h index 84edb64..0edbf3b 100644 --- a/ports/atomvm/atomport.h +++ b/ports/atomvm/atomport.h @@ -53,8 +53,8 @@ #define ATOM_TLS HATOMVM_CONTEXT context ; /* Function prototypes */ -extern void atomvmRun () ; -extern void archTimerTickIrqHandler () ; +extern void atomvmRun (void) ; +extern void archTimerTickIrqHandler (void) ; /* The instance of the atomvm for this port */ extern HATOMVM the_atomvm ; diff --git a/ports/atomvm/atomvm.c b/ports/atomvm/atomvm.c index b48363f..960b13e 100644 --- a/ports/atomvm/atomvm.c +++ b/ports/atomvm/atomvm.c @@ -119,6 +119,18 @@ typedef struct ATOMVM_CALLBACK_CONTEXT_SWITCH_S { } ATOMVM_CALLBACK_CONTEXT_SWITCH, *PATOMVM_CALLBACK_CONTEXT_SWITCH ; +/* ATOMVM_CALLBACK_INT_REQUEST is the parameter for a ATOMVM_CALLBACK_F call +that take as parameter a pointer to to the function that will be called in +an interrupt context */ +typedef struct ATOMVM_CALLBACK_INT_REQUEST_S { + + ATOMVM_CALLBACK callback ; + + /* Function pointer the callback will call */ + void (*isr) (void) ; + +} ATOMVM_CALLBACK_INT_REQUEST, *PATOMVM_CALLBACK_INT_REQUEST ; + /* ATOMVM_CONTEXT saves the state of a context created by atomvmContextCreate() and sheduled by atomvmContextSwitch(). */ typedef struct ATOMVM_CONTEXT_S { @@ -194,7 +206,6 @@ uint32_t atomvmCtrlCreate (HATOMVM *atomvm) { PATOMVM patomvm = 0 ; - int32_t i ; patomvm = (PATOMVM) malloc (sizeof(struct ATOMVM_S)) ; @@ -494,12 +505,12 @@ atomvmInterruptMask (uint32_t mask) * @return None */ void -atomvmCtrlIntRequest (HATOMVM atomvm, uint32_t isr) +atomvmCtrlIntRequest (HATOMVM atomvm, void (*isr) (void)) { PATOMVM patomvm = (PATOMVM) atomvm ; WaitForSingleObject (patomvm->atomvm_int_complete, INFINITE) ; - while (InterlockedCompareExchange ((volatile uint32_t *)&patomvm->isr, isr, 0) != 0) { + while (InterlockedCompareExchange ((volatile uint32_t *)&patomvm->isr, (uint32_t)isr, 0) != 0) { SwitchToThread() ; } SetEvent (patomvm->atomvm_int) ; @@ -720,7 +731,7 @@ atomvmGetVmId (void) * @return Zero on failure, try to call GetLastError(). */ uint32_t -callbackInterruptWait (PATOMVM patomvm, PATOMVM_CALLBACK callback) +callbackIntWait (PATOMVM patomvm, PATOMVM_CALLBACK callback) { WaitForSingleObject (patomvm->atomvm_int_complete, INFINITE) ; return WaitForSingleObject (patomvm->atomvm_int, INFINITE) == WAIT_OBJECT_0 ; @@ -739,12 +750,53 @@ callbackInterruptWait (PATOMVM patomvm, PATOMVM_CALLBACK callback) * @return void. */ void -atomvmInterruptWait (void) +atomvmIntWait (void) { PATOMVM patomvm = getAtomvm () ; ATOMVM_CALLBACK callback ; - invokeCallback (patomvm, callbackInterruptWait, (PATOMVM_CALLBACK)&callback) ; + invokeCallback (patomvm, callbackIntWait, (PATOMVM_CALLBACK)&callback) ; +} + +/** +* \b callbackIntRequest +* +* This function is invoked from the controll thread after a call to atomvmIntRequest(). +* +* The atom virtual machine is suspended while this function is called. +* +* @param[in] patomvm Pointer to the virtual machine created by atomvmCtrlCreate. +* @param[in] callback Callback parameter. +* +* @return Zero on failure, try to call GetLastError(). +*/ +uint32_t +callbackIntRequest (PATOMVM patomvm, PATOMVM_CALLBACK callback) +{ + PATOMVM_CALLBACK_INT_REQUEST int_request = (PATOMVM_CALLBACK_INT_REQUEST)callback ; + + int_request->isr () ; + return 1 ; +} + +/** +* \ingroup atomvm +* \b atomvmIntRequest +* +* This function is to be used by the atom virtual machine. +* +* @param[in] isr Function that will be called from the controll thread. +* +* @return void. +*/ +void +atomvmIntRequest (void (*isr) (void)) +{ + PATOMVM patomvm = getAtomvm () ; + ATOMVM_CALLBACK_INT_REQUEST callback ; + + callback.isr = isr ; + invokeCallback (patomvm, callbackIntRequest, (PATOMVM_CALLBACK)&callback) ; } diff --git a/ports/atomvm/atomvm.h b/ports/atomvm/atomvm.h index 24e2a99..b4ae55d 100644 --- a/ports/atomvm/atomvm.h +++ b/ports/atomvm/atomvm.h @@ -80,7 +80,7 @@ typedef struct ATOMVM_CONTEXT* HATOMVM_CONTEXT ; /* Function prototypes used for controlling the atom virtual machine */ extern uint32_t atomvmCtrlCreate (HATOMVM* atomvm) ; extern void atomvmCtrlRun (HATOMVM atomvm, uint32_t flags) ; -extern void atomvmCtrlIntRequest (HATOMVM atomvm, uintptr_t isr) ; +extern void atomvmCtrlIntRequest (HATOMVM atomvm, void (*isr) (void)) ; extern void atomvmCtrlClose (HATOMVM atomvm) ; /* Function prototypes for use by the atom virtual machine from within the @@ -91,7 +91,8 @@ extern uint32_t atomvmContextSwitch (HATOMVM_CONTEXT old_context, HATOMV extern void atomvmContextDesrtroy (HATOMVM_CONTEXT context) ; extern void atomvmWriteThreadId (uint32_t thread_id) ; extern uint32_t atomvmReadThreadId (void) ; -extern void atomvmInterruptWait (void) ; +extern void atomvmIntWait (void) ; +extern void atomvmIntRequest (void (*isr) (void)) ; extern uint32_t atomvmGetVmId (void) ; diff --git a/ports/atomvm/msvc/main.c b/ports/atomvm/msvc/main.c index 28f78a8..7d0b4bf 100644 --- a/ports/atomvm/msvc/main.c +++ b/ports/atomvm/msvc/main.c @@ -213,7 +213,7 @@ __atomvmClose () void -test_isr () +test_isr (void) { static int i = 0 ; test_isr_count++ ; @@ -232,7 +232,7 @@ isr_thread_proc (LPVOID lpParameter) int x ; int y = rand() % 100 ; while (1) { - atomvmCtrlIntRequest (the_atomvm, (uintptr_t)test_isr) ; + atomvmCtrlIntRequest (the_atomvm, test_isr) ; if (i++==y) { x = rand() % 50 ; Sleep (x) ; @@ -264,7 +264,7 @@ main () while (1) { Sleep(1) ; - atomvmCtrlIntRequest (the_atomvm, (uintptr_t)archTimerTickIrqHandler) ; + atomvmCtrlIntRequest (the_atomvm, archTimerTickIrqHandler) ; } } From 356685005a86aa97bb57e4fb5e015a4b6451d823 Mon Sep 17 00:00:00 2001 From: Natie van Rooyen Date: Thu, 25 Oct 2012 10:41:23 +0200 Subject: [PATCH 27/28] LPC17xx platform for Cortex M port --- platforms/lpc17xx/Makefile | 7 ++- platforms/lpc17xx/README | 13 +++-- platforms/lpc17xx/drivers/lpc17xx_uart.c | 13 +++++ platforms/lpc17xx/drivers/lpc17xx_uart.h | 2 +- platforms/lpc17xx/main.c | 66 +++++++++++++----------- platforms/lpc17xx/modules.c | 3 +- platforms/lpc17xx/startup.c | 2 + ports/cortex_m/atomport.h | 4 ++ ports/cortex_m/types.h | 6 +++ 9 files changed, 77 insertions(+), 39 deletions(-) diff --git a/platforms/lpc17xx/Makefile b/platforms/lpc17xx/Makefile index 172df5a..8975de9 100644 --- a/platforms/lpc17xx/Makefile +++ b/platforms/lpc17xx/Makefile @@ -8,8 +8,6 @@ ifeq ($(TEST_NAME),) TEST_NAME = kern1 endif - - CC = arm-none-eabi-gcc LN = arm-none-eabi-gcc AS = arm-none-eabi-gcc @@ -18,7 +16,7 @@ CFLAGS := $(CFLAGS) -O3 -Os -g3 -Wall -c -mcpu=cortex-m3 -mthumb AFLAGS := $(AFLAGS) -O3 -Os -g3 -Wall -c -fmessage-length=0 -fno-builtin -ffunction-sections -fdata-sections -mcpu=cortex-m3 -mthumb LFLAGS := $(LFLAGS) -O3 -Os -Wall -mcpu=cortex-m3 -mthumb -Wl,-Map=system.map -Tsystem.ld -CDEFS := $(CDEFS) -DATOMTHREADS_TEST='"$(TEST_NAME)"' +CDEFS := $(CDEFS) -DATOMTHREADS_TEST='"$(TEST_NAME)"' -DBOARD_MBED_LP1768 ADEFS := $(ADEFS) -D__thumb2__ -DARM_RDI_MONITOR LLIBS := $(LLIBS) @@ -39,7 +37,8 @@ ASMS := $(ASMS) \ INCLUDES := $(INCLUDES) \ - -I./CMSISv2p00_LPC17xx/inc \ + -I$(ATOMTHREADS)/platforms/lpc17xx/CMSISv2p00_LPC17xx/inc \ + -I$(ATOMTHREADS)/platforms/lpc17xx \ -I$(ATOMTHREADS) include $(ATOMTHREADS)/ports/cortex_m/Makefile diff --git a/platforms/lpc17xx/README b/platforms/lpc17xx/README index d8055a3..8f69ee8 100644 --- a/platforms/lpc17xx/README +++ b/platforms/lpc17xx/README @@ -11,7 +11,14 @@ NXP LPC17xx Platform The "lpc17xx" platform contains sources for building the Atomthreads test suite for the NXP LPC17xx microcontroller. -The build was tested on the "mbed NXP LPC1768" board (http://www.mbed.org) -and the sources were compiled on Ubuntu 12.0.4 with the GNU ARM tool chain -using Newlib. +The build was tested on the "mbed NXP LPC1768" board (http://www.mbed.org) +but it should work on any LPC17xx development board where UART0 can be used +to monitor the output of the test. + +The NXP LPC17xx microcontrollers use the ARM Cortex M3 processor core. The +source code in this example uses the ARM CMSIS Cortex-M Access Library V2.01 +to initialize the platform and Newlib as the runtime library. Also it uses a +driver provided by NXP for the UART. The CMSIS library and the UART driver +are provided as source with the sample and Newlib is expected to be installed +together with the GNU ARM tool chain. diff --git a/platforms/lpc17xx/drivers/lpc17xx_uart.c b/platforms/lpc17xx/drivers/lpc17xx_uart.c index 3a0202f..fca71ec 100644 --- a/platforms/lpc17xx/drivers/lpc17xx_uart.c +++ b/platforms/lpc17xx/drivers/lpc17xx_uart.c @@ -143,6 +143,19 @@ void LPC17xx_UART_PutString (uint8_t *str) #endif } +/** + * @brief Write a buffer to UART0. + * + * @param buffer: buffer to be written + * @retval None + */ +void LPC17xx_UART_WriteBuffer (uint8_t *buffer, uint32_t len) +{ + while (len-- != 0) { + LPC17xx_UART_PutChar(*buffer++); + } + +} /** * @brief Print formatted string. This function takes variable length arguments. * diff --git a/platforms/lpc17xx/drivers/lpc17xx_uart.h b/platforms/lpc17xx/drivers/lpc17xx_uart.h index 9e7f045..400a089 100644 --- a/platforms/lpc17xx/drivers/lpc17xx_uart.h +++ b/platforms/lpc17xx/drivers/lpc17xx_uart.h @@ -29,8 +29,8 @@ void LPC17xx_UART_PutChar (uint8_t); uint8_t LPC17xx_UART_GetChar (void); void LPC17xx_UART_Init(uint32_t baudrate); -//void LPC17xx_UART_Printf (const uint8_t *format, ...); void LPC17xx_UART_PutString (uint8_t *str) ; +void LPC17xx_UART_WriteBuffer (uint8_t *buffer, uint32_t len) ; #endif // __LPC17xx_UART_H_ diff --git a/platforms/lpc17xx/main.c b/platforms/lpc17xx/main.c index 755f965..04d053f 100644 --- a/platforms/lpc17xx/main.c +++ b/platforms/lpc17xx/main.c @@ -27,31 +27,34 @@ * POSSIBILITY OF SUCH DAMAGE. */ - +#include #include "LPC17xx.h" #include "drivers/lpc17xx_uart.h" -#include #include "modules.h" #include "atom.h" #include "tests/atomtests.h" -// for mbed board -#define LED1_GPIO (1 << 18) -#define LED2_GPIO (1 << 20) -#define LED3_GPIO (1 << 21) -#define LED4_GPIO (1 << 23) - -#define LED_GET(led) (LPC_GPIO1->FIOSET & led) -#define LED_SET(led, on) { if (on) LPC_GPIO1->FIOSET = led ; else LPC_GPIO1->FIOCLR = led ; } -#define LED_TOGGLE(led) LED_SET(led, !LED_GET(led)) #ifndef ATOMTHREADS_TEST #define ATOMTHREADS_TEST "kern1" #endif -#define TEST_STACK_BYTE_SIZE 1024 -#define IDLE_STACK_BYTE_SIZE 512 +// for mbed board +#define MBED_LED1_GPIO (1 << 18) +#define MBED_LED2_GPIO (1 << 20) +#define MBED_LED3_GPIO (1 << 21) +#define MBED_LED4_GPIO (1 << 23) + +#define MBED_LED_GET(led) (LPC_GPIO1->FIOSET & led) +#define MBED_LED_SET(led, on) { if (on) LPC_GPIO1->FIOSET = led ; else LPC_GPIO1->FIOCLR = led ; } +#define MBED_LED_TOGGLE(led) MBED_LED_SET(led, !MBED_LED_GET(led)) +#define MBED_LED_COUNT(count) MBED_LED_SET(MBED_LED1_GPIO, count & 1) ; MBED_LED_SET(MBED_LED2_GPIO, count & 2) ; \ + MBED_LED_SET(MBED_LED3_GPIO, count & 4) ; MBED_LED_SET(MBED_LED4_GPIO, count & 8) ; + + +#define TEST_STACK_BYTE_SIZE 512 +#define IDLE_STACK_BYTE_SIZE 128 static unsigned char test_stack[TEST_STACK_BYTE_SIZE] ; static unsigned char idle_stack[IDLE_STACK_BYTE_SIZE] ; @@ -68,7 +71,6 @@ void test_thread (uint32_t param) { uint32_t failures ; - static volatile unsigned int i ; CRITICAL_STORE ; failures = test_start () ; @@ -79,18 +81,28 @@ test_thread (uint32_t param) CRITICAL_END() ; while(1) { - LED_TOGGLE(LED1_GPIO) ; - for (i=0; i<1000000; i++) ; +#ifdef BOARD_MBED_LP1768 + MBED_LED_TOGGLE(MBED_LED1_GPIO) ; +#endif + atomTimerDelay (65) ; } } -int main(void) { +/** + * \b main + * + * Initialize atomthreads and start a test_thread to run the Atomthreads test suite. + * + */ +int +main(void) +{ - static volatile unsigned int i ; - - // mbed board - LPC_GPIO1->FIODIR |= LED1_GPIO | LED2_GPIO | LED3_GPIO | LED4_GPIO ; +#ifdef BOARD_MBED_LP1768 + LPC_GPIO1->FIODIR |= MBED_LED1_GPIO | MBED_LED2_GPIO | MBED_LED3_GPIO | MBED_LED4_GPIO ; + MBED_LED_SET(MBED_LED1_GPIO | MBED_LED2_GPIO | MBED_LED3_GPIO | MBED_LED4_GPIO, 1); +#endif dbg_format_msg ("\r\nLPC17xx SystemCoreClock = %d\r\n",SystemCoreClock) ; @@ -99,18 +111,12 @@ int main(void) { dbg_format_msg ("Atomthreads starting %s... \r\n", ATOMTHREADS_TEST) ; atomOSInit(&idle_stack[0], IDLE_STACK_BYTE_SIZE, TRUE) ; - atomThreadCreate ((ATOM_TCB *)&test_tcb, TEST_THREAD_PRIO, test_thread, 0, &test_stack[0], TEST_STACK_BYTE_SIZE, TRUE); + atomThreadCreate ((ATOM_TCB *)&test_tcb, TEST_THREAD_PRIO, test_thread, 0, + &test_stack[0], TEST_STACK_BYTE_SIZE, TRUE); atomOSStart() ; + while(1) ; - - while(1) { - - LED_TOGGLE(LED1_GPIO) ; - for (i=0; i<1000000; i++) ; - - - } return 0 ; } diff --git a/platforms/lpc17xx/modules.c b/platforms/lpc17xx/modules.c index 7901bcd..95b55cf 100644 --- a/platforms/lpc17xx/modules.c +++ b/platforms/lpc17xx/modules.c @@ -50,7 +50,8 @@ dbg_format_msg (char *format, ...) va_start (args, format) ; //CRITICAL_START() ; - vsnprintf ((char*)msg, 256, (char*)format, args) ; + + vsniprintf ((char*)msg, 256, (char*)format, args) ; LPC17xx_UART_PutString (msg) ; //CRITICAL_END() ; diff --git a/platforms/lpc17xx/startup.c b/platforms/lpc17xx/startup.c index 87a90a5..14d104f 100644 --- a/platforms/lpc17xx/startup.c +++ b/platforms/lpc17xx/startup.c @@ -51,6 +51,8 @@ WEAK void IntDefault_Handler(void); //***************************************************************************** extern int main(void); +extern void low_level_init(void); + //***************************************************************************** // // External declaration for the pointer to the stack top from the Linker Script diff --git a/ports/cortex_m/atomport.h b/ports/cortex_m/atomport.h index 1a4cfd9..bc77588 100644 --- a/ports/cortex_m/atomport.h +++ b/ports/cortex_m/atomport.h @@ -39,7 +39,9 @@ * If stddef.h is available on the platform it is simplest to include it * from this header, otherwise define below. */ +#ifndef NULL #define NULL ((void *)(0)) +#endif /* Size of each stack entry / stack alignment size (e.g. 32 bits) */ #define STACK_ALIGN_SIZE sizeof(unsigned int) @@ -56,7 +58,9 @@ * Most of these are available from types.h on this platform, which is * included above. */ +#ifndef POINTER #define POINTER void * +#endif /* * * diff --git a/ports/cortex_m/types.h b/ports/cortex_m/types.h index e6f927d..ba0b9ee 100644 --- a/ports/cortex_m/types.h +++ b/ports/cortex_m/types.h @@ -51,9 +51,15 @@ typedef char int8_t ; #endif /* IO definitions (access restrictions to peripheral registers) */ +#ifndef __I #define __I volatile /*!< defines 'read only' permissions */ +#endif +#ifndef __O #define __O volatile /*!< defines 'write only' permissions */ +#endif +#ifndef __IO #define __IO volatile /*!< defines 'read / write' permissions */ +#endif #endif /* __TYPES_H__ */ From b19004817c68da56a757bc5f68dbbd3e8d96ab39 Mon Sep 17 00:00:00 2001 From: Natie van Rooyen Date: Sun, 18 Nov 2012 11:29:32 +0100 Subject: [PATCH 28/28] Added thread exit routine. --- ports/atomvm/atomport.c | 6 ++--- ports/atomvm/atomvm.c | 59 +++++++++++++++++++++++++++++++---------- ports/atomvm/atomvm.h | 4 ++- 3 files changed, 51 insertions(+), 18 deletions(-) diff --git a/ports/atomvm/atomport.c b/ports/atomvm/atomport.c index 55d6d69..8daac41 100644 --- a/ports/atomvm/atomport.c +++ b/ports/atomvm/atomport.c @@ -32,7 +32,6 @@ #include "windows.h" /** Forward declarations */ -static void thread_shell (void); DWORD WINAPI cntrl_thread_proc (LPVOID lpParameter) ; /* Global data */ @@ -73,7 +72,7 @@ cntrl_thread_proc (LPVOID lpParameter) * */ void -thread_shell (void) +thread_shell (uint32_t arg) { ATOM_TCB *curr_tcb; @@ -111,7 +110,8 @@ archThreadContextInit (ATOM_TCB *tcb_ptr, void *stack_top, void (*entry_point)(u tcb_ptr->entry_param = entry_param ; tcb_ptr->entry_point = entry_point ; - atomvmContextCreate (&tcb_ptr->context, (unsigned int )stack_top, (unsigned int )thread_shell) ; + tcb_ptr->context = atomvmContextCreate (1) ; + atomvmContextInit (tcb_ptr->context, (unsigned int *)stack_top, thread_shell, entry_param, 0) ; } diff --git a/ports/atomvm/atomvm.c b/ports/atomvm/atomvm.c index 960b13e..3785212 100644 --- a/ports/atomvm/atomvm.c +++ b/ports/atomvm/atomvm.c @@ -550,15 +550,12 @@ callbackContextCreate (PATOMVM patomvm, PATOMVM_CALLBACK callback) * This function creates a atomvm thread context that can be scheduled * by atomvmContextSwitch. * -* @param[out] context Handle to the context of the thread that are allocated -* by the caller. -* @param[in] stack Stack top. -* @param[in] entry Entry point using the default caling convention of the compiler. +* @param[in] interrupt_mask initial interrupt mask of the thread. * -* @return Zero on failure, try to call GetLastError(). +* @return Handle to the context of the thread created. */ -uint32_t -atomvmContextCreate (HATOMVM_CONTEXT* atomvm_context, uint32_t stack, uint32_t entry) +HATOMVM_CONTEXT +atomvmContextCreate (uint32_t interrupt_mask) { uint32_t res ; PATOMVM patomvm = getAtomvm () ; @@ -567,21 +564,55 @@ atomvmContextCreate (HATOMVM_CONTEXT* atomvm_context, uint32_t stack, uint32_t e ATOMVM_CALLBACK_CONTEXT context_init ; context_init.pcontext = new_context ; - new_context->interrupt_mask = 1 ; - + new_context->interrupt_mask = interrupt_mask ; + new_context->thread_id = (uint32_t) -1 ; res = invokeCallback (patomvm, callbackContextCreate, (PATOMVM_CALLBACK)&context_init) ; if (res) { - pcontext->Ebp = stack ; - pcontext->Esp = stack ; - pcontext->Eip = entry ; - *atomvm_context = (HATOMVM_CONTEXT)new_context ; + return (HATOMVM_CONTEXT)new_context ; + } else { + free (new_context) ; } + return 0 ; +} + +/** +* \ingroup atomvm +* \b atomvmContextInit +* +* This function is to be used by the atom virtual machine. +* +* This function initialize a atomvm thread context that can be scheduled +* by atomvmContextSwitch. +* +* @param[out] context Handle to the context of the thread that are allocated +* by the caller. +* @param[in] stack Stack top. +* @param[in] entry Entry point of the thread. +* @param[in] arg argument passed on the stack as first parameter. +* @param[in] exit exit function to return to. +* @param[in] status status for exit function. +* +* @return Zero on failure, try to call GetLastError(). +*/ +uint32_t +atomvmContextInit (HATOMVM_CONTEXT context, uint32_t* stack, void (*entry)(uint32_t), uint32_t arg, void (*exit)(uint32_t)) +{ + uint32_t res = 0 ; + PATOMVM_CONTEXT new_context = (PATOMVM_CONTEXT)context ; + CONTEXT* pcontext = &new_context->context ; + + *stack-- = arg; + *stack = (uint32_t)exit ; + + pcontext->Ebp = (uint32_t)stack ; + pcontext->Esp = (uint32_t)stack ; + pcontext->Eip = (uint32_t)entry ; + return res ; } - /** * \b callbackContextSwitch * diff --git a/ports/atomvm/atomvm.h b/ports/atomvm/atomvm.h index b4ae55d..6d69058 100644 --- a/ports/atomvm/atomvm.h +++ b/ports/atomvm/atomvm.h @@ -86,7 +86,9 @@ extern void atomvmCtrlClose (HATOMVM atomvm) ; /* Function prototypes for use by the atom virtual machine from within the call to __atomvmReset(). */ extern int32_t atomvmInterruptMask (uint32_t mask) ; -extern uint32_t atomvmContextCreate (HATOMVM_CONTEXT* context, uint32_t stack, uint32_t entry) ; +extern HATOMVM_CONTEXT atomvmContextCreate (uint32_t interrupt_mask) ; +extern uint32_t atomvmContextInit (HATOMVM_CONTEXT context, uint32_t* stack, + void (*entry)(uint32_t), uint32_t arg, void (*exit)(uint32_t)) ; extern uint32_t atomvmContextSwitch (HATOMVM_CONTEXT old_context, HATOMVM_CONTEXT new_context) ; extern void atomvmContextDesrtroy (HATOMVM_CONTEXT context) ; extern void atomvmWriteThreadId (uint32_t thread_id) ;