From daa748332b55f4f590a2edb421b6a0121582f1ba Mon Sep 17 00:00:00 2001 From: Natie van Rooyen Date: Mon, 24 Sep 2012 23:16:03 +0200 Subject: [PATCH] cortex m port qemu_lm3s platform --- platforms/qemu_integratorcp/Makefile | 2 +- platforms/qemu_integratorcp/system.ld | 4 - platforms/qemu_lm3s/Makefile | 96 ++++++++++++ platforms/qemu_lm3s/main.c | 89 +++++++++++ platforms/qemu_lm3s/modules.c | 161 +++++++++++++++++++ platforms/qemu_lm3s/modules.h | 213 +++++++++++++++++++++++++ platforms/qemu_lm3s/startup.S | 215 ++++++++++++++++++++++++++ platforms/qemu_lm3s/system.ld | 100 ++++++++++++ ports/arm/types.h | 10 -- ports/cortex_m/atomport.c | 53 ++++--- ports/cortex_m/atomport.h | 1 + ports/cortex_m/atomport_s.S | 64 +++++++- ports/cortex_m/types.h | 9 ++ 13 files changed, 973 insertions(+), 44 deletions(-) create mode 100644 platforms/qemu_lm3s/Makefile create mode 100644 platforms/qemu_lm3s/main.c create mode 100644 platforms/qemu_lm3s/modules.c create mode 100644 platforms/qemu_lm3s/modules.h create mode 100644 platforms/qemu_lm3s/startup.S create mode 100644 platforms/qemu_lm3s/system.ld diff --git a/platforms/qemu_integratorcp/Makefile b/platforms/qemu_integratorcp/Makefile index 551529f..e88e47d 100644 --- a/platforms/qemu_integratorcp/Makefile +++ b/platforms/qemu_integratorcp/Makefile @@ -15,7 +15,7 @@ LN = arm-none-eabi-gcc AS = arm-none-eabi-gcc CFLAGS := $(CFLAGS) -Wall -g -c -mcpu=arm926ej-s -ffreestanding -AFLAGS := $(CFLAGS) -Wall -g -c -mcpu=arm926ej-s -ffreestanding +AFLAGS := $(AFLAGS) -Wall -g -c -mcpu=arm926ej-s -ffreestanding LFLAGS := $(LFLAGS) -Wall -mcpu=arm926ej-s -Wl,-Map=system.map,--verbose -Tsystem.ld CDEFS := $(CDEFS) -DATOMTHREADS_TEST='"$(TEST_NAME)"' diff --git a/platforms/qemu_integratorcp/system.ld b/platforms/qemu_integratorcp/system.ld index 4d4fc2c..40682db 100644 --- a/platforms/qemu_integratorcp/system.ld +++ b/platforms/qemu_integratorcp/system.ld @@ -84,10 +84,6 @@ SECTIONS } >sram - /*DISCARD : - { - *(.eh_*) - }*/ } _end = .; diff --git a/platforms/qemu_lm3s/Makefile b/platforms/qemu_lm3s/Makefile new file mode 100644 index 0000000..5b86d1f --- /dev/null +++ b/platforms/qemu_lm3s/Makefile @@ -0,0 +1,96 @@ +ifeq ($(TARGET_NAME),) +TARGET_NAME=boot +endif +ifeq ($(ATOMTHREADS),) +ATOMTHREADS = $(shell pwd)/../../ +endif +ifeq ($(TEST_NAME),) +TEST_NAME = mutex1 +endif + + + +CC = arm-none-eabi-gcc +LN = arm-none-eabi-gcc +AS = arm-none-eabi-gcc + +CFLAGS := $(CFLAGS) -Wall -g -c -mcpu=cortex-m3 -mthumb -mthumb-interwork -ffreestanding +AFLAGS := $(AFLAGS) -Wall -g -c -mcpu=cortex-m3 -mthumb -mthumb-interwork -ffreestanding +LFLAGS := $(LFLAGS) -Wall -mcpu=cortex-m3 -mthumb -Wl,-Map=system.map -Tsystem.ld + +CDEFS := $(CDEFS) -DATOMTHREADS_TEST='"$(TEST_NAME)"' -DPLATFORM_QEMU_LM3S_HACK +ADEFS := $(ADEFS) -D__thumb2__ -DARM_RDI_MONITOR -DPLATFORM_QEMU_LM3S_HACK + +LLIBS := $(LLIBS) + + +SRCS := $(SRCS) \ + modules.c \ + main.c \ + $(ATOMTHREADS)/tests/$(TEST_NAME).c \ + +# startup_c.c \ + +ASMS := $(ASMS) \ + startup.S \ + +INCLUDES := $(INCLUDES) \ + -I$(ATOMTHREADS) + +include $(ATOMTHREADS)/ports/cortex_m/Makefile + +OBJS = $(SRCS:.c=.o) $(ASMS:.S=.o) + +include ../rules.mk + + +run_test: clean all + echo "START TEST $(TEST_NAME)" + qemu-system-arm -M lm3s6965evb -kernel boot.elf -semihosting >> atomthreads_test.out + +all_tests: + echo "Starting atomthreads test suite" > atomthreads_test.out + make run_test "TEST_NAME=mutex1" + make run_test "TEST_NAME=mutex2" + make run_test "TEST_NAME=mutex3" + make run_test "TEST_NAME=mutex5" + make run_test "TEST_NAME=mutex6" + make run_test "TEST_NAME=mutex7" + make run_test "TEST_NAME=mutex8" + make run_test "TEST_NAME=mutex9" + make run_test "TEST_NAME=kern1" + make run_test "TEST_NAME=kern2" + make run_test "TEST_NAME=kern3" + make run_test "TEST_NAME=kern4" + make run_test "TEST_NAME=timer1" + make run_test "TEST_NAME=timer2" + make run_test "TEST_NAME=timer3" + make run_test "TEST_NAME=timer5" + make run_test "TEST_NAME=timer6" + make run_test "TEST_NAME=timer7" + make run_test "TEST_NAME=queue1" + make run_test "TEST_NAME=queue2" + make run_test "TEST_NAME=queue3" + make run_test "TEST_NAME=queue4" + make run_test "TEST_NAME=queue5" + make run_test "TEST_NAME=queue6" + make run_test "TEST_NAME=queue7" + make run_test "TEST_NAME=queue8" + make run_test "TEST_NAME=queue9" + make run_test "TEST_NAME=sem1" + make run_test "TEST_NAME=sem2" + make run_test "TEST_NAME=sem3" + make run_test "TEST_NAME=sem5" + make run_test "TEST_NAME=sem6" + make run_test "TEST_NAME=sem7" + make run_test "TEST_NAME=sem8" + make run_test "TEST_NAME=sem9" + +all_fail: + make run_test "TEST_NAME=mutex4" + make run_test "TEST_NAME=sem4" + + +run_last: + qemu-system-arm -M lm3s6965evb -kernel boot.elf -monitor stdio -semihosting + diff --git a/platforms/qemu_lm3s/main.c b/platforms/qemu_lm3s/main.c new file mode 100644 index 0000000..3f68d6c --- /dev/null +++ b/platforms/qemu_lm3s/main.c @@ -0,0 +1,89 @@ +/* + * Copyright (c) 2012, Natie van Rooyen. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. No personal names or organizations' names associated with the + * Atomthreads project may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include "modules.h" +#include "atom.h" +#include "tests/atomtests.h" + +#ifndef ATOMTHREADS_TEST +#define ATOMTHREADS_TEST "kern1" +#endif + +#define TEST_STACK_BYTE_SIZE 1024 +#define IDLE_STACK_BYTE_SIZE 512 + +static unsigned char test_stack[TEST_STACK_BYTE_SIZE] ; +static unsigned char idle_stack[IDLE_STACK_BYTE_SIZE] ; +ATOM_TCB test_tcb ; + + + +/** + * \b test_thread + * + * Function calling the test function of the Atomthreads test suite. + * + */ +void +test_thread (uint32_t param) +{ + uint32_t failures ; + CRITICAL_STORE ; + + failures = test_start () ; + + atomTimerDelay (10) ; + CRITICAL_START() ; + printf ("%s %s\r\n", ATOMTHREADS_TEST, failures ? "FAIL" : "PASS") ; + exit (failures) ; + CRITICAL_END() ; +} + + +/** + * \b main + * + * Initialize atomthreads and start a test_thread to run the Atomthreads test suite. + * + */ +int +main (void) +{ + int i = 0 ; + + uint32_t failures ; + printf ("atomthreads starting %s... \r\n", ATOMTHREADS_TEST) ; + + atomOSInit(&idle_stack[IDLE_STACK_BYTE_SIZE - sizeof(unsigned int)], IDLE_STACK_BYTE_SIZE - sizeof(unsigned int)) ; + atomThreadCreate ((ATOM_TCB *)&test_tcb, TEST_THREAD_PRIO, test_thread, 0, &test_stack[(TEST_STACK_BYTE_SIZE) - sizeof(unsigned int)], TEST_STACK_BYTE_SIZE - sizeof(unsigned int)); + atomOSStart() ; + + return 0 ; +} + diff --git a/platforms/qemu_lm3s/modules.c b/platforms/qemu_lm3s/modules.c new file mode 100644 index 0000000..fc7cbc8 --- /dev/null +++ b/platforms/qemu_lm3s/modules.c @@ -0,0 +1,161 @@ +/* + * Copyright (c) 2012, Natie van Rooyen. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. No personal names or organizations' names associated with the + * Atomthreads project may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include "modules.h" +#include +#include +#include "atomport_private.h" +#include "atom.h" +#include "atomport.h" +#include "types.h" + +SYSTICK_T* const board_systick = (SYSTICK_T*) BOARD_BASE_ADDRESS_SYSTICK ; +NVIC_T* const board_nvic = (NVIC_T*) BOARD_BASE_ADDRESS_NVIC ; +SCB_T * const board_scb = (SCB_T*) BOARD_BASE_ADDRESS_SCB ; +GPTM_TIMER_T * const board_gptm0 = (GPTM_TIMER_T*) BOARD_BASE_ADDRESS_GPTIMER0 ; + + +/** + * \b dbg_format_msg + * + * Same as printf. + * + */ +void +dbg_format_msg (char *format, ...) +{ + va_list args; + static char msg[256] ; + CRITICAL_STORE ; + + va_start (args, format) ; + CRITICAL_START() ; + vsnprintf ((char*)msg, 256, (char*)format, args) ; + printf (msg) ; + CRITICAL_END() ; + +} + + +/** + * \b low_level_init + * + * Initializes the PIC and start the system timer tick intrerupt. + * + */ +int +low_level_init (void) +{ + contextInit () ; + + //board_systick->STRELOAD = 0x010000 ; + //board_systick->STCTRL = NVIC_STCTRL_CLK | + // NVIC_STCTRL_INTEN | + // NVIC_STCTRL_ENABLE ; + + board_gptm0->CTL &= ~GPTM_TIMER_CTL_TAEN ; + board_gptm0->CFG = 0 ; + board_gptm0->TAMR = GPTM_TIMER_TMR_TMR_PERIODIC ; + board_gptm0->TAILR = 0x10000 ; + board_gptm0->IMR |= GPTM_TIMER_INT_TATOIM ; + board_gptm0->CTL |= GPTM_TIMER_CTL_TAEN ; + + // board_nvic->ISER[0] = 0x80000 ; + + return 0 ; +} + + +/** + * \b __context_preempt_handler + * + * System timer tic interupt handler. + * + */ +void +__context_tick_handler (void) +{ + + if (1) { + atomIntEnter(); + + /* Call the OS system tick handler */ + atomTimerTick(); + + board_gptm0->ICR |= GPTM_TIMER_INT_TATOIM ; + + /* Call the interrupt exit routine */ + atomIntExit(TRUE); + + } + +} + +void +dbg_hard_fault_handler_c (unsigned int * hardfault_args) +{ + unsigned int stacked_r0; + unsigned int stacked_r1; + unsigned int stacked_r2; + unsigned int stacked_r3; + unsigned int stacked_r12; + unsigned int stacked_lr; + unsigned int stacked_pc; + unsigned int stacked_psr; + + stacked_r0 = ((unsigned long) hardfault_args[0]); + stacked_r1 = ((unsigned long) hardfault_args[1]); + stacked_r2 = ((unsigned long) hardfault_args[2]); + stacked_r3 = ((unsigned long) hardfault_args[3]); + + stacked_r12 = ((unsigned long) hardfault_args[4]); + stacked_lr = ((unsigned long) hardfault_args[5]); + stacked_pc = ((unsigned long) hardfault_args[6]); + stacked_psr = ((unsigned long) hardfault_args[7]); + + printf ("\r\n\r\n[Hard fault handler - all numbers in hex]\r\n"); + printf ("SP = 0x%x\r\n", hardfault_args); + printf ("R0 = 0x%x\r\n", stacked_r0); + printf ("R1 = 0x%x\r\n", stacked_r1); + printf ("R2 = 0x%x\r\n", stacked_r2); + printf ("R3 = 0x%x\r\n", stacked_r3); + printf ("R12 = 0x%x\r\n", stacked_r12); + printf ("LR [R14] = 0x%x subroutine call return address\r\n", stacked_lr); + printf ("PC [R15] = 0x%x program counter\r\n", stacked_pc); + printf ("PSR = 0x%x\r\n", stacked_psr); + //printf ("BFAR = 0x%x\r\n", (*((volatile unsigned long *)(0xE000ED38)))); + //printf ("CFSR = 0x%x\r\n", (*((volatile unsigned long *)(0xE000ED28)))); + //printf ("HFSR = 0x%x\r\n", (*((volatile unsigned long *)(0xE000ED2C)))); + //printf ("DFSR = 0x%x\r\n", (*((volatile unsigned long *)(0xE000ED30)))); + //printf ("AFSR = 0x%x\r\n", (*((volatile unsigned long *)(0xE000ED3C)))); + // printf ("SCB_SHCSR = %x\n", SCB->SHCSR); + + while (1); + +} + diff --git a/platforms/qemu_lm3s/modules.h b/platforms/qemu_lm3s/modules.h new file mode 100644 index 0000000..3a341e0 --- /dev/null +++ b/platforms/qemu_lm3s/modules.h @@ -0,0 +1,213 @@ +/* + * Copyright (c) 2012, Natie van Rooyen. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. No personal names or organizations' names associated with the + * Atomthreads project may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __MODULES_H__ +#define __MODULES_H__ + +/* + * Module definitions to use with the Stellaris LM3S6965 Microcontroller + */ + +#include "atomport.h" + + +typedef volatile unsigned int REG_DWORD ; +typedef volatile unsigned short REG_WORD ; +typedef volatile unsigned char REG_BYTE ; + + +// ***************************************************************************** +// The Stellaris General-Purpose Timer Module (GPTM) +// ***************************************************************************** +typedef struct GPTM_TIMER_S { + + // offset read/write reset Description + REG_DWORD CFG ; // 0x000 R/W 0x00000000 GPTM Configuration 345 + REG_DWORD TAMR ; // 0x004 R/W 0x00000000 GPTM TimerA Mode 346 + REG_DWORD TBMR ; // 0x008 R/W 0x00000000 GPTM TimerB Mode 348 + REG_DWORD CTL ; // 0x00C R/W 0x00000000 GPTM Control 350 + REG_DWORD Reserved[2] ; // 0x010 + REG_DWORD IMR ; // 0x018 R/W 0x00000000 GPTM Interrupt Mask 353 + REG_DWORD RIS ; // 0x01C RO 0x00000000 GPTM Raw Interrupt Status 355 + REG_DWORD MIS ; // 0x020 RO 0x00000000 GPTM Masked Interrupt Status 356 + REG_DWORD ICR ; // 0x024 W1C 0x00000000 GPTM Interrupt Clear 357 + REG_DWORD TAILR ; // 0x028 R/W 0xFFFFFFFF GPTM TimerA Interval Load 359 + REG_DWORD TBILR ; // 0x02C R/W 0x0000FFFF GPTM TimerB Interval Load 360 + REG_DWORD TAMATCHR ; // 0x030 R/W 0xFFFFFFFF GPTM TimerA Match 361 + REG_DWORD TBMATCHR ; // 0x034 R/W 0x0000FFFF GPTM TimerB Match 362 + REG_DWORD TAPR ; // 0x038 R/W 0x00000000 GPTM TimerA Prescale 363 + REG_DWORD TBPR ; // 0x03C R/W 0x00000000 GPTM TimerB Prescale 364 + REG_DWORD TAPMR ; // 0x040 R/W 0x00000000 GPTM TimerA Prescale Match 365 + REG_DWORD TBPMR ; // 0x044 R/W 0x00000000 GPTM TimerB Prescale Match 366 + REG_DWORD TAR ; // 0x048 RO 0xFFFFFFFF GPTM TimerA 367 + REG_DWORD TBR ; // 0x04C RO 0x0000FFFF GPTM TimerB 368 + +} GPTM_TIMER_T, *PGPTM_TIMER_T ; + +// -------- GPTM_TIMER_CFG : (CFG Offset: 0x00) This register configures the global operation of the GPTM module -------- +#define GPTM_TIMER_CFG_MASK ((unsigned int)0x07 << 0) // + #define GPTM_TIMER_CFG_32BIT ((unsigned int)0x00 << 0) // 32-bit timer configuration + #define GPTM_TIMER_CFG_32BIT_RT ((unsigned int)0x01 << 0) // 32-bit real-time clock (RTC) counter configuration +// -------- GPTM_TIMER_TAMR : (TAMR Offset: 0x04) This register configures the GPTM based on the configuration selected in the GPTMCFG register -------- +// -------- GPTM_TIMER_TBMR : (TBMR Offset: 0x08) This register configures the GPTM based on the configuration selected in the GPTMCFG register -------- +#define GPTM_TIMER_TMR_TAMS ((unsigned int)0x01 << 3) // GPTM TimerA Alternate Mode Select. 0 Capture mode is enabled. 1 PWM mode is enabled +#define GPTM_TIMER_TMR_TCMR ((unsigned int)0x01 << 2) // GPTM TimerA Capture Mode. 0 Edge-Count mode. 1 Edge-Time mode. +#define GPTM_TIMER_TMR_TMR_ONE_SHOT ((unsigned int)0x01 << 0) // One-Shot Timer mode +#define GPTM_TIMER_TMR_TMR_PERIODIC ((unsigned int)0x02 << 0) // Periodic Timer mode +#define GPTM_TIMER_TMR_TMR_CAPTURE ((unsigned int)0x03 << 0) // Capture mode +// -------- GPTM_TIMER_CTL : (CTL Offset: 0x0C) This register is used alongside the GPTMCFG and GMTMTnMR registers to fine-tune the timer configuration -------- +#define GPTM_TIMER_CTL_TBPWML ((unsigned int)0x01 << 14) // GPTM TimerB PWM Output Level. 0 Output is unaffected. 1 Output is inverted. +#define GPTM_TIMER_CTL_TBOTE ((unsigned int)0x01 << 13) // GPTM TimerB Output Trigger Enable. 0 The output TimerB ADC trigger is disabled. 1 The output TimerB ADC trigger is enabled. +#define GPTM_TIMER_CTL_TBEVENT_MASK ((unsigned int)0x03 << 10) // GPTM TimerB Event Mode + #define GPTM_TIMER_CTL_TBEVENT_PE ((unsigned int)0x00 << 10) // Positive edge + #define GPTM_TIMER_CTL_TBEVENT_NE ((unsigned int)0x01 << 10) // Negative edge + #define GPTM_TIMER_CTL_TBEVENT_NE ((unsigned int)0x03 << 10) // Both edges +#define GPTM_TIMER_CTL_TBSTALL ((unsigned int)0x01 << 9) // GPTM Timer B Stall Enable. 0 Timer B continues counting while the processor is halted by the debugger +#define GPTM_TIMER_CTL_TBEN ((unsigned int)0x01 << 8) // GPTM TimerB Enable +// -------- +#define GPTM_TIMER_CTL_TAPWML ((unsigned int)0x01 << 6) // GPTM TimerA PWM Output Level. 0 Output is unaffected. 1 Output is inverted. +#define GPTM_TIMER_CTL_TAOTE ((unsigned int)0x01 << 5) // GPTM TimerA Output Trigger Enable. 0 The output TimerB ADC trigger is disabled. 1 The output TimerB ADC trigger is enabled. +#define GPTM_TIMER_CTL_RTCEN ((unsigned int)0x01 << 4) // GPTM RTC Enable +#define GPTM_TIMER_CTL_TAEVENT_MASK ((unsigned int)0x03 << 2) // GPTM TimerA Event Mode + #define GPTM_TIMER_CTL_TAEVENT_PE ((unsigned int)0x00 << 2) // Positive edge + #define GPTM_TIMER_CTL_TAEVENT_NE ((unsigned int)0x01 << 2) // Negative edge + #define GPTM_TIMER_CTL_TAEVENT_NE ((unsigned int)0x03 << 2) // Both edges +#define GPTM_TIMER_CTL_TASTALL ((unsigned int)0x01 << 1) // GPTM Timer A Stall Enable. 0 Timer B continues counting while the processor is halted by the debugger +#define GPTM_TIMER_CTL_TAEN ((unsigned int)0x01 << 0) // GPTM TimerA Enable +// -------- GPTM_TIMER_IMR : (IMR Offset: 0x18) This register allows software to enable/disable GPTM controller-level interrupts. -------- +// -------- GPTM_TIMER_RIS : (RIS Offset: 0x1C) This register shows the state of the GPTM's internal interrupt signal. -------- +// -------- GPTM_TIMER_MIS : (MIS Offset: 0x20) This register show the state of the GPTM's controller-level interrupt. -------- +// -------- GPTM_TIMER_ICR : (ICR Offset: 0x24) This register is used to clear the status bits in the GPTMRIS and GPTMMIS registers. -------- +#define GPTM_TIMER_INT_CBEIM ((unsigned int)0x01 << 10) // GPTM CaptureB Event Interrupt Mask +#define GPTM_TIMER_INT_CBMIM ((unsigned int)0x01 << 9) // GPTM CaptureB Match Interrupt Mask +#define GPTM_TIMER_INT_TBTOIM ((unsigned int)0x01 << 8) // GPTM TimerB Time-Out Interrupt Mask +// -------- +#define GPTM_TIMER_INT_RTCIM ((unsigned int)0x01 << 3) // GPTM RTC Interrupt Mask +#define GPTM_TIMER_INT_CAEIM ((unsigned int)0x01 << 2) // GPTM CaptureA Event Interrupt Mask +#define GPTM_TIMER_INT_CAMIM ((unsigned int)0x01 << 1) // GPTM CaptureA Match Interrupt Mask +#define GPTM_TIMER_INT_TATOIM ((unsigned int)0x01 << 0) // GPTM TimerA Time-Out Interrupt Mask + + + +// ***************************************************************************** +// Cortex M System Timer (SysTick) +// ***************************************************************************** +typedef struct SYSTICK_S { + + REG_DWORD Res0[1] ; // 0xE000E000 + REG_DWORD ICT ; // 0xE000E004 + REG_DWORD Res1[2] ; // 0xE000E008 + REG_DWORD STCTRL ; // 0xE000E010 + REG_DWORD STRELOAD ; // 0xE000E014 + REG_DWORD STCURRENT; // 0xE000E018 + REG_DWORD STCALIB ; // 0xE000E01C + REG_DWORD Res2[56] ; // 0xE000E020 + +} SYSTICK_T, *PSYSTICK_T ; + +// -------- SYSTICK_STCTRL : (STCTRL Offset: 0xE000E010) SysTick Control and Status Register -------- +#define SYSTICK_STCTRL_COUNT ((unsigned int)0x1 << 16) // 0 - The SysTick timer has not counted to 0 since the last time this bit was read. +#define SYSTICK_STCTRL_CLK ((unsigned int)0x1 << 2) // 1 - System clock +#define SYSTICK_STCTRL_INTEN ((unsigned int)0x1 << 1) // 1 - An interrupt is generated to the NVIC when SysTick counts to 0. +#define SYSTICK_STCTRL_ENABLE ((unsigned int)0x1 << 1) // Enables SysTick to operate in a multi-shot way. +// -------- SYSTICK_STRELOAD : (STRELOAD Offset: 0xE000E014) Reload Value -------- +#define SYSTICK_STRELOAD_MASK ((unsigned int)0xFFFFFF << 0) // IRQ mask +// -------- SYSTICK_STCURRENT : (STCURRENT Offset: 0xE000E018) SysTick Current Value Register -------- + + +// ***************************************************************************** +// Cortex M Nested Vectored Interrupt Controller +// ***************************************************************************** +typedef struct NVIC_S { + + REG_DWORD ISER[2] ; // 0xE000E100 + REG_DWORD Res3[30] ; // 0xE000E120 + REG_DWORD ICER[2] ; // 0xE000E180 + REG_DWORD Res4[30] ; // 0xE000E1A0 + REG_DWORD ISPR[2] ; // 0xE000E200 + REG_DWORD Res5[30] ; // 0xE000E220 + REG_DWORD ICPR[2] ; // 0xE000E280 + REG_DWORD Res6[30] ; // 0xE000E2A0 + REG_DWORD IABR[2] ; // 0xE000E300 + REG_DWORD Res7[64] ; // 0xE000E320 + REG_DWORD IPR[2] ; // 0xE000E400 + // REG_DWORD Res7[515] ; // 0xE000E4F4 + +} NVIC_T, *PNVIC_T ; + +#define NVIC_EXCEPTION_RESET 1 +#define NVIC_EXCEPTION_NMI 2 +#define NVIC_EXCEPTION_HARD_FAULT 3 +#define NVIC_EXCEPTION_MEM_MANAGEMENT 4 +#define NVIC_EXCEPTION_BUS_FAULT 5 +#define NVIC_EXCEPTION_USAGE_FAULT 6 +#define NVIC_EXCEPTION_SVCALL 11 +#define NVIC_EXCEPTION_DEBUG_MON 12 +#define NVIC_EXCEPTION_PEND_SV 14 +#define NVIC_EXCEPTION_SYS_TICK 15 + +// ***************************************************************************** +// System Control Block (SCB) Registers +// ***************************************************************************** +typedef struct SCB_S { + + REG_DWORD CPUID ; // 0xE000ED00 + REG_DWORD ICSR ; // 0xE000ED04 + REG_DWORD VTOR ; // 0xE000ED08 + REG_DWORD AIRCR ; // 0xE000ED0C + REG_DWORD SCR ; // 0xE000ED10 + REG_DWORD CCR ; // 0xE000ED14 + + REG_DWORD SYS_PRIO[3] ; // 0xE000ED18 + REG_DWORD SYSHNDCTRL ; // 0xE000ED24 + //REG_DWORD FAULTSTAT ; // 0xE000ED28 + //REG_DWORD HFAULTSTAT ; // 0xE000ED2C + +} SCB_T, *PSCB_T ; + + + +#define BOARD_BASE_ADDRESS_SYSTICK 0xE000E000 +#define BOARD_BASE_ADDRESS_NVIC 0xE000E100 +#define BOARD_BASE_ADDRESS_SCB 0xE000ED00 +#define BOARD_BASE_ADDRESS_GPTIMER0 0x40030000 + +extern SYSTICK_T* const board_systick ; +extern NVIC_T* const board_nvic ; +extern SCB_T* const board_scb ; +extern GPTM_TIMER_T* const board_gptm0 ; + + + +extern int low_level_init (void) ; +extern void dbg_format_msg (char *format, ...) ; +extern void dbg_hard_fault_handler_c (unsigned int * hardfault_args) ; + +#define DBG_MESSAGE(fmt_str) { dbg_format_msg fmt_str ; } + +#endif /* __MODULES_H__ */ diff --git a/platforms/qemu_lm3s/startup.S b/platforms/qemu_lm3s/startup.S new file mode 100644 index 0000000..da5823b --- /dev/null +++ b/platforms/qemu_lm3s/startup.S @@ -0,0 +1,215 @@ +/* + Copyright (c) 2012, Natie van Rooyen. All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + 1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + 3. No personal names or organizations' names associated with the + Atomthreads project may be used to endorse or promote products + derived from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS + "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. +*/ + +/* lm3s Startup Script */ + +.section .vectors,"x",%progbits +.syntax unified +.thumb + + +.global __interrupt_vector_table +.global tick_Handler +.global pendSV_Handler +.global dbg_hard_fault_handler_c + +/** + * \b __interrupt_vector_table + * + */ +__interrupt_vector_table: +.long __c_stack_top__ +.long reset_Handler +.long fault_Handler +.long fault_Handler +.long fault_Handler +.long fault_Handler +.long fault_Handler +.long 0 +.long 0 +.long 0 +.long 0 +.long sys_Handler +.long sys_Handler +.long 0 +.long pendSV_Handler +.long sys_Handler + +/* External interrupts */ +.long default_Handler // GPIO Port A +.long default_Handler // GPIO Port B +.long default_Handler // GPIO Port C +.long default_Handler // GPIO Port D +.long default_Handler // GPIO Port E +.long default_Handler // UART0 Rx and Tx +.long default_Handler // UART1 Rx and Tx +.long default_Handler // SSI0 Rx and Tx +.long default_Handler // I2C0 Master and Slave +.long default_Handler // PWM Fault +.long default_Handler // PWM Generator 0 +.long default_Handler // PWM Generator 1 +.long default_Handler // PWM Generator 2 +.long default_Handler // Quadrature Encoder 0 +.long default_Handler // ADC Sequence 0 +.long default_Handler // ADC Sequence 1 +.long default_Handler // ADC Sequence 2 +.long default_Handler // ADC Sequence 3 +.long default_Handler // Watchdog timer +.long tick_Handler // Timer 0 subtimer A +.long default_Handler // Timer 0 subtimer B +.long default_Handler // Timer 1 subtimer A +.long default_Handler // Timer 1 subtimer B +.long default_Handler // Timer 2 subtimer A +.long default_Handler // Timer 2 subtimer B +.long default_Handler // Analog Comparator 0 +.long default_Handler // Analog Comparator 1 +.long default_Handler // Analog Comparator 2 +.long default_Handler // System Control (PLL, OSC, BO) +.long default_Handler // FLASH Control +.long default_Handler // GPIO Port F +.long default_Handler // GPIO Port G +.long default_Handler // GPIO Port H +.long default_Handler // UART2 Rx and Tx +.long default_Handler // SSI1 Rx and Tx +.long default_Handler // Timer 3 subtimer A +.long default_Handler // Timer 3 subtimer B +.long default_Handler // I2C1 Master and Slave +.long default_Handler // Quadrature Encoder 1 +.long default_Handler // CAN0 +.long default_Handler // CAN1 +.long default_Handler // CAN2 +.long default_Handler // Ethernet +.long default_Handler // Hibernate + +/** + * \b sys_Handler + * + * @return None + */ +.thumb_func +sys_Handler: + B . + +/** + * \b default_Handler + * + * @return None + */ +.thumb_func +default_Handler: + B . + +/** + * \b fault_Handler + * + * @return None + */ + .thumb_func +fault_Handler: + tst lr, #4 + ite eq + mrseq r0, MSP + mrsne r0, PSP + b dbg_hard_fault_handler_c + + +.section .startup,"x",%progbits +.syntax unified +.thumb + +.global reset_Handler +.global initialise_monitor_handles +.global low_level_init +.global main + + +/** + * \b reset_Handler + * + * + * + * @return None + */ +.thumb_func +reset_Handler: + +/* + * Initialize the data and bss sections. + */ +init_data: + ldr r0, .ETEXT + ldr r1, .DATA + ldr r2, .EDATA + sub r2, r2, r1 + cmp r2, #0 + beq init_bss +init_data_copy: + ldrb r4, [r0], #1 + strb r4, [r1], #1 + subs r2, r2, #1 + bne init_data_copy +init_bss: + mov r0, #0 + ldr r1, = .BSS + ldr r2, = .EBSS + sub r2, r2, r1 + cmp r2, #0 + beq init_done +init_bss_zero: + strb r0, [r1], #1 + subs r2, r2, #1 + bne init_bss_zero +init_done: + + /* + * The following call initializes the function pointers for stdio etc. + * These are used by the semihosting interface. + * + * This function is implemented in newlib. + */ + bl initialise_monitor_handles + + /* + * Platform specific low level initialization. + */ + bl low_level_init + + /* + * Call the application's entry point. + */ + bl main + + +.BSS: .long _bss +.EBSS: .long _ebss +.ETEXT: .long _etext +.DATA: .long _data +.EDATA: .long _edata + +.end \ No newline at end of file diff --git a/platforms/qemu_lm3s/system.ld b/platforms/qemu_lm3s/system.ld new file mode 100644 index 0000000..de5ffc8 --- /dev/null +++ b/platforms/qemu_lm3s/system.ld @@ -0,0 +1,100 @@ +/****************************************************************************** + * + * hello_codered.ld - Code Red linker configuration file for hello. + * + * Copyright (c) 2006-2012 Texas Instruments Incorporated. All rights reserved. + * Software License Agreement + * + * Texas Instruments (TI) is supplying this software for use solely and + * exclusively on TI's microcontroller products. The software is owned by + * TI and/or its suppliers, and is protected under applicable copyright + * laws. You may not combine this software with "viral" open-source + * software in order to form a larger program. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. + * NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT + * NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY + * CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL + * DAMAGES, FOR ANY REASON WHATSOEVER. + * + * This is part of revision 9107 of the EK-LM3S6965 Firmware Package. + * + *****************************************************************************/ + +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000 + SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00010000 +} + +SECTIONS +{ + _vRamTop = 0x20000000 + 0x00010000; + .text : + { + *(.vectors) + *(.startup) + *(.text*) + *(.rodata*) + } > FLASH + + /* + * for exception handling/unwind - some Newlib functions (in common with + * C++ and STDC++) use this. + */ + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + _etext = .; + + .data : AT (__exidx_end) + { + _data = .; + *(vtable) + *(.data*) + _edata = .; + } > SRAM + + /* zero initialized data */ + + .bss : + { + __bss_start__ = . ; + _bss = .; + *(.bss*) + *(COMMON) + __bss_end__ = . ; + _ebss = .; + } > SRAM + + /* Where we put the heap with cr_clib */ + + .cr_heap : + { + end = .; + _pvHeapStart = .; + } > SRAM + + /* + * Note: (ref: M0000066) + * Moving the stack down by 16 is to work around a GDB bug. + * This space can be reclaimed for Production Builds. + */ + + _vStackTop = _vRamTop - 16; + .stack _vStackTop : + { + __c_stack_top__ = . ; + } +} diff --git a/ports/arm/types.h b/ports/arm/types.h index d383d84..c07e295 100644 --- a/ports/arm/types.h +++ b/ports/arm/types.h @@ -40,16 +40,6 @@ typedef int int32_t ; typedef short int16_t ; typedef char int8_t ; -// typedef volatile unsigned int REG_DWORD ;// Hardware register definition - -#define UWORD64 unsigned long long -#define UWORD32 unsigned int -#define UWORD16 unsigned short -#define UWORD8 unsigned char -#define WORD32 int -#define WORD16 short -#define WORD8 char - #ifndef OFFSETOF #define OFFSETOF(TYPE, MEMBER) ((int) &((TYPE *)0)->MEMBER) #endif diff --git a/ports/cortex_m/atomport.c b/ports/cortex_m/atomport.c index 6d6fc6a..d41359d 100644 --- a/ports/cortex_m/atomport.c +++ b/ports/cortex_m/atomport.c @@ -38,7 +38,6 @@ */ typedef void * SYSCONTEXT ; -extern void contextInit (void) ; extern void contextSwitch (SYSCONTEXT* save_context, SYSCONTEXT* new_context) ; extern void contextStart (SYSCONTEXT* context) ; extern void contextEnableInterrupts (void) ; @@ -93,7 +92,11 @@ archThreadContextInit (ATOM_TCB *tcb_ptr, void *stack_top, void (*entry_point)(u *stack_ptr = 0x01000000L; //-- xPSR stack_ptr--; - *stack_ptr = ((uint32_t)thread_shell) | 1; //-- Entry Point (1 for THUMB mode) +#ifndef PLATFORM_QEMU_LM3S_HACK + *stack_ptr = ((uint32_t)thread_shell) | 1 ; //-- Entry Point (1 for THUMB mode) +#else + *stack_ptr = ((uint32_t)thread_shell) & ~1 ; //-- Entry Point (1 for THUMB mode) +#endif stack_ptr--; *stack_ptr = ((uint32_t)/*exit*/0) | 1; //-- R14 (LR) (1 for THUMB mode) stack_ptr--; @@ -159,20 +162,20 @@ archContextSwitch (ATOM_TCB * p_sp_old, ATOM_TCB * p_sp_new) * System timer tick interrupt handler. * */ -void -archTickHandler (void) -{ - atomIntEnter(); - - /* Call the OS system tick handler */ - atomTimerTick(); - - /* ack the interrupt if needed */ - /* ... */ - - /* Call the interrupt exit routine */ - atomIntExit(TRUE); -} +//void +//archTickHandler (void) +//{ +// atomIntEnter(); +// +// /* Call the OS system tick handler */ +// atomTimerTick(); +// +// /* ack the interrupt if needed */ +// /* ... */ +// +// /* Call the interrupt exit routine */ +// atomIntExit(TRUE); +//} /** * \b archTickInit @@ -180,14 +183,14 @@ archTickHandler (void) * System timer initialization. * */ -void -archTickInit (void) -{ - /* Initialize NVIC PendSV */ - contextInit () ; - - /* Initializa Timer Hardware */ - /* ... */ -} +//void +//archTickInit (void) +//{ +// /* Initialize NVIC PendSV */ +// contextInit () ; +// +// /* Initializa Timer Hardware */ +// /* ... */ +//} diff --git a/ports/cortex_m/atomport.h b/ports/cortex_m/atomport.h index 39bd0c0..f7ac10d 100644 --- a/ports/cortex_m/atomport.h +++ b/ports/cortex_m/atomport.h @@ -47,6 +47,7 @@ * Functions defined in atomport_arm.asm * */ +extern void contextInit (void) ; extern uint32_t contextEnterCritical (void) ; extern void contextExitCritical (uint32_t posture) ; diff --git a/ports/cortex_m/atomport_s.S b/ports/cortex_m/atomport_s.S index 46c3138..0ae97c4 100644 --- a/ports/cortex_m/atomport_s.S +++ b/ports/cortex_m/atomport_s.S @@ -37,20 +37,28 @@ .global pendSV_Handler .global tick_Handler -.global archTickHandler +.global __context_tick_handler /**/ .equ NVIC_INT_CTRL, 0xE000ED04 // Interrupt control state register .equ NVIC_PENDSVSET, 0x10000000 // Value to trigger PendSV exception .equ NVIC_PR_12_15_ADDR, 0xE000ED20 // System Handlers 12-15 Priority Register Address -.equ NVIC_PENDS_VPRIORITY, 0x00FF0000 // PendSV priority is minimal (0xFF) +.equ NVIC_PENDS_VPRIORITY, 0x00F00000 // PendSV priority is minimal (0xFF -- 0x00FF0000) + +#ifdef PLATFORM_QEMU_LM3S_HACK +.equ NVIC_ISER, 0xE000E100 +.equ NVIC_ICER, 0xE000E180 +.equ NVIC_I_TIMER0, 0x80000 +#endif + .syntax unified .text .thumb + /** * \b contextInit * @@ -128,7 +136,13 @@ contextStart: * @return None */ contextEnableInterrupts: +#ifndef PLATFORM_QEMU_LM3S_HACK CPSIE i +#else + LDR r1, =NVIC_ISER + LDR r0, =NVIC_I_TIMER0 + STR r0, [r1] +#endif BX lr @@ -142,10 +156,14 @@ contextEnableInterrupts: * @return None */ contextExitCritical: +#ifndef PLATFORM_QEMU_LM3S_HACK MSR PRIMASK, r0 +#else + LDR r1, =NVIC_ISER + STR r0, [r1] +#endif BX lr - /** * \b contextEnterCritical * @@ -154,8 +172,15 @@ contextExitCritical: * @return Current interrupt posture */ contextEnterCritical: +#ifndef PLATFORM_QEMU_LM3S_HACK MRS r0, PRIMASK CPSID i +#else + LDR r1, =NVIC_ISER + LDR r0, [r1] + LDR r1, =NVIC_ICER + STR r0, [r1] +#endif BX lr /** @@ -165,8 +190,15 @@ contextEnterCritical: * * @return None */ + .thumb_func pendSV_Handler: +#ifndef PLATFORM_QEMU_LM3S_HACK CPSID i // Disable core int +#else + LDR r0, =NVIC_ICER + LDR r1, =NVIC_I_TIMER0 + STR r1, [r0] +#endif LDR r1, =context_save_stack_ptr LDR r0, [r1] // Load old (current) stack pointer address @@ -192,7 +224,13 @@ pendsv_handler_new_stack: MSR PSP, r2 // Mov new stack point to PSP pendsv_handler_exit: +#ifndef PLATFORM_QEMU_LM3S_HACK CPSIE i // Enable core int +#else + LDR r0, =NVIC_ISER + LDR r1, =NVIC_I_TIMER0 + STR r1, [r0] +#endif ORR lr, lr, #0x04 // Ensure exception return uses process stack BX lr // Exit interrupt @@ -205,15 +243,33 @@ pendsv_handler_exit: * * @return None */ + .thumb_func tick_Handler: PUSH {r4-r11, lr} + +#ifndef PLATFORM_QEMU_LM3S_HACK cpsid I // Disable core int - BL archTickHandler +#else + LDR r0, =NVIC_ICER + LDR r1, =NVIC_I_TIMER0 + STR r1, [r0] +#endif + + BL __context_tick_handler + +#ifndef PLATFORM_QEMU_LM3S_HACK cpsie I // Enable core int +#else + LDR r0, =NVIC_ISER + LDR r1, =NVIC_I_TIMER0 + STR r1, [r0] +#endif + POP {r4-r11, pc} /**/ +.data context_new_stack_ptr: .long 0x00000000 context_save_stack_ptr: .long 0x00000000 diff --git a/ports/cortex_m/types.h b/ports/cortex_m/types.h index 82317f7..c07e295 100644 --- a/ports/cortex_m/types.h +++ b/ports/cortex_m/types.h @@ -40,5 +40,14 @@ typedef int int32_t ; typedef short int16_t ; typedef char int8_t ; +#ifndef OFFSETOF +#define OFFSETOF(TYPE, MEMBER) ((int) &((TYPE *)0)->MEMBER) +#endif + +#ifndef INLINE +#define INLINE __inline +#endif + + #endif /* __TYPES_H__ */