Added “arm” port .

Added platforms directory.
Added QEMU qemu_integratorcp platform in platforms.
Modified test cases to make stack top DWORD aligned.
This commit is contained in:
Natie van Rooyen
2012-09-17 13:02:09 +02:00
parent a2646ec695
commit dfb831fa63
48 changed files with 1062 additions and 293 deletions

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ifeq ($(TARGET_NAME),)
TARGET_NAME=boot
endif
ifeq ($(ATOMTHREADS),)
ATOMTHREADS = $(shell pwd)/../../
endif
ifeq ($(TEST_NAME),)
TEST_NAME = kern1
endif
CC = arm-none-eabi-gcc
LN = arm-none-eabi-gcc
AS = arm-none-eabi-gcc
CFLAGS := $(CFLAGS) -Wall -g -c -mcpu=arm926ej-s -ffreestanding
AFLAGS := $(CFLAGS) -Wall -g -c -mcpu=arm926ej-s -ffreestanding
LFLAGS := $(LFLAGS) -Wall -mcpu=arm926ej-s -Wl,-Map=system.map,--verbose -Tsystem.ld
CDEFS := $(CDEFS) -DATOMTHREADS_TEST='"$(TEST_NAME)"'
ADEFS := $(ADEFS)
LLIBS := $(LLIBS)
SRCS := $(SRCS) \
modules.c \
main.c \
$(ATOMTHREADS)/tests/$(TEST_NAME).c
ASMS := $(ASMS) \
startup.S \
INCLUDES := $(INCLUDES) \
-I$(ATOMTHREADS)
include $(ATOMTHREADS)/ports/arm/Makefile
OBJS = $(SRCS:.c=.o) $(ASMS:.S=.o)
include ../rules.mk
run_test: clean all
echo "START TEST $(TEST_NAME)"
qemu-system-arm -M integratorcp -kernel boot.elf -semihosting | tee atomthreads_test.out
all_tests:
echo "Starting atomthreads test suite" > atomthreads_test.out
make run_test "TEST_NAME=mutex1"
make run_test "TEST_NAME=mutex2"
make run_test "TEST_NAME=mutex3"
make run_test "TEST_NAME=mutex4"
make run_test "TEST_NAME=mutex5"
make run_test "TEST_NAME=mutex6"
make run_test "TEST_NAME=mutex7"
make run_test "TEST_NAME=mutex8"
make run_test "TEST_NAME=mutex9"
make run_test "TEST_NAME=kern1"
make run_test "TEST_NAME=kern2"
make run_test "TEST_NAME=kern3"
make run_test "TEST_NAME=kern4"
make run_test "TEST_NAME=timer1"
make run_test "TEST_NAME=timer2"
make run_test "TEST_NAME=timer3"
make run_test "TEST_NAME=timer5"
make run_test "TEST_NAME=timer6"
make run_test "TEST_NAME=timer7"
make run_test "TEST_NAME=queue1"
make run_test "TEST_NAME=queue2"
make run_test "TEST_NAME=queue3"
make run_test "TEST_NAME=queue4"
make run_test "TEST_NAME=queue5"
make run_test "TEST_NAME=queue6"
make run_test "TEST_NAME=queue7"
make run_test "TEST_NAME=queue8"
make run_test "TEST_NAME=queue9"
make run_test "TEST_NAME=sem1"
make run_test "TEST_NAME=sem2"
make run_test "TEST_NAME=sem3"
make run_test "TEST_NAME=sem4"
make run_test "TEST_NAME=sem5"
make run_test "TEST_NAME=sem6"
make run_test "TEST_NAME=sem7"
make run_test "TEST_NAME=sem8"
make run_test "TEST_NAME=sem9"
run_last:
qemu-system-arm -M integratorcp -kernel boot.elf -monitor stdio -semihosting

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Starting atomthreads test suite
VNC server running on `127.0.0.1:5900'
atomthreads starting mutex1... mutex1 PASS
VNC server running on `127.0.0.1:5900'
atomthreads starting mutex2... mutex2 PASS
VNC server running on `127.0.0.1:5900'
atomthreads starting mutex3... mutex3 PASS
VNC server running on `127.0.0.1:5900'
atomthreads starting mutex4... mutex4 PASS
VNC server running on `127.0.0.1:5900'
atomthreads starting mutex5... mutex5 PASS
VNC server running on `127.0.0.1:5900'
atomthreads starting mutex6... mutex6 PASS
VNC server running on `127.0.0.1:5900'
atomthreads starting mutex7... mutex7 PASS
VNC server running on `127.0.0.1:5900'
atomthreads starting mutex8... mutex8 PASS
VNC server running on `127.0.0.1:5900'
atomthreads starting mutex9... mutex9 PASS
VNC server running on `127.0.0.1:5900'
atomthreads starting kern1... kern1 PASS
VNC server running on `127.0.0.1:5900'
atomthreads starting kern2... kern2 PASS
VNC server running on `127.0.0.1:5900'
atomthreads starting kern3... kern3 PASS
VNC server running on `127.0.0.1:5900'
atomthreads starting kern4... kern4 PASS
VNC server running on `127.0.0.1:5900'
atomthreads starting timer1... timer1 PASS
VNC server running on `127.0.0.1:5900'
atomthreads starting timer2... timer2 FAIL
VNC server running on `127.0.0.1:5900'
atomthreads starting timer3... timer3 PASS
VNC server running on `127.0.0.1:5900'
atomthreads starting timer5... timer5 PASS
VNC server running on `127.0.0.1:5900'
atomthreads starting timer6... timer6 PASS
VNC server running on `127.0.0.1:5900'
atomthreads starting timer7... timer7 PASS
VNC server running on `127.0.0.1:5900'
atomthreads starting queue1... queue1 PASS
VNC server running on `127.0.0.1:5900'
atomthreads starting queue2... queue2 PASS
VNC server running on `127.0.0.1:5900'
atomthreads starting queue3... queue3 PASS
VNC server running on `127.0.0.1:5900'
atomthreads starting queue4... queue4 PASS
VNC server running on `127.0.0.1:5900'
atomthreads starting queue5... queue5 PASS
VNC server running on `127.0.0.1:5900'
atomthreads starting queue6... queue6 PASS
VNC server running on `127.0.0.1:5900'
atomthreads starting queue7... queue7 PASS
VNC server running on `127.0.0.1:5900'
atomthreads starting queue8... queue8 PASS
VNC server running on `127.0.0.1:5900'
atomthreads starting queue9... queue9 PASS
VNC server running on `127.0.0.1:5900'
atomthreads starting sem1... sem1 PASS
VNC server running on `127.0.0.1:5900'
atomthreads starting sem2... sem2 PASS
VNC server running on `127.0.0.1:5900'
atomthreads starting sem3... sem3 PASS
VNC server running on `127.0.0.1:5900'
atomthreads starting sem4... sem4 PASS
VNC server running on `127.0.0.1:5900'
atomthreads starting sem5... sem5 PASS
VNC server running on `127.0.0.1:5900'
atomthreads starting sem6... sem6 PASS
VNC server running on `127.0.0.1:5900'
atomthreads starting sem7... sem7 PASS
VNC server running on `127.0.0.1:5900'
atomthreads starting sem8... sem8 PASS
VNC server running on `127.0.0.1:5900'
atomthreads starting sem9... sem9 PASS

Binary file not shown.

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/*
* Copyright (c) 2012, Natie van Rooyen. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. No personal names or organizations' names associated with the
* Atomthreads project may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <stdio.h>
#include "modules.h"
#include "atom.h"
#include "tests/atomtests.h"
#ifndef ATOMTHREADS_TEST
#define ATOMTHREADS_TEST "kern1"
#endif
#define TEST_STACK_BYTE_SIZE 1024
#define IDLE_STACK_BYTE_SIZE 512
static unsigned char test_stack[TEST_STACK_BYTE_SIZE] ;
static unsigned char idle_stack[IDLE_STACK_BYTE_SIZE] ;
ATOM_TCB test_tcb ;
/**
* \b test_thread
*
* Function calling the test function of the Atomthreads test suite.
*
*/
void
test_thread (uint32_t param)
{
uint32_t failures ;
CRITICAL_STORE ;
failures = test_start () ;
atomTimerDelay (10) ;
CRITICAL_START() ;
printf ("%s %s\r\n", ATOMTHREADS_TEST, failures ? "FAIL" : "PASS") ;
exit (failures) ;
CRITICAL_END() ;
}
/**
* \b main
*
* Initialize atomthreads and start a test_thread to run the Atomthreads test suite.
*
*/
int
main (void)
{
uint32_t failures ;
printf ("atomthreads starting %s... ", ATOMTHREADS_TEST) ;
atomOSInit(&idle_stack[IDLE_STACK_BYTE_SIZE - sizeof(unsigned int)], IDLE_STACK_BYTE_SIZE - sizeof(unsigned int)) ;
atomThreadCreate ((ATOM_TCB *)&test_tcb, TEST_THREAD_PRIO, test_thread, 0, &test_stack[(TEST_STACK_BYTE_SIZE) - sizeof(unsigned int)], TEST_STACK_BYTE_SIZE - sizeof(unsigned int));
atomOSStart() ;
return 0 ;
}

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/*
* Copyright (c) 2012, Natie van Rooyen. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. No personal names or organizations' names associated with the
* Atomthreads project may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include "modules.h"
#include <stdio.h>
#include <stdarg.h>
#include "atomport_private.h"
#include "atom.h"
#include "atomport.h"
#include "types.h"
ICP_TIMER_T* const board_timer_0 = (ICP_TIMER_T*) BOARD_BASE_ADDRESS_TIMER_0 ;
ICP_PIC_T * const board_pic = (ICP_PIC_T*) BOARD_BASE_ADDRESS_PIC ;
/**
* \b dbg_format_msg
*
* Same as printf.
*
*/
void
dbg_format_msg (char *format, ...)
{
va_list args;
static char msg[256] ;
CRITICAL_STORE ;
va_start (args, format) ;
CRITICAL_START() ;
vsnprintf ((char*)msg, 256, (char*)format, args) ;
CRITICAL_END() ;
printf (msg) ;
}
/**
* \b low_level_init
*
* Initializes the PIC and start the system timer tick intrerupt.
*
*/
int
low_level_init (void)
{
board_pic->IRQ_ENABLECLR = ICP_PIC_IRQ_TIMERINT0 ;
board_timer_0->INTCLR = 1 ;
board_pic->IRQ_ENABLESET |= ICP_PIC_IRQ_TIMERINT0 ;
board_timer_0->LOAD = 0x2000 ;
board_timer_0->BGLOAD = 0x2000 ;
board_timer_0->CONTROL = ICP_TIMER_CONTROL_ENABLE |
ICP_TIMER_CONTROL_MODE |
ICP_TIMER_CONTROL_IE |
/*ICP_TIMER_CONTROL_PRESCALE_256 |*/
ICP_TIMER_CONTROL_TIMER_SIZE ;
return 0 ;
}
/**
* \b __context_preempt_handler
*
* System timer tic interupt handler.
*
*/
void
__context_preempt_handler (void)
{
unsigned int status = board_pic->IRQ_STATUS ;
if (status | ICP_PIC_IRQ_TIMERINT0) {
atomIntEnter();
/* Call the OS system tick handler */
atomTimerTick();
/* ack the interrupt */
board_timer_0->INTCLR = 0x1 ;
/* Call the interrupt exit routine */
atomIntExit(TRUE);
}
}

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/*
* Copyright (c) 2012, Natie van Rooyen. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. No personal names or organizations' names associated with the
* Atomthreads project may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __MODULES_H__
#define __MODULES_H__
#include "atomport.h"
extern void dbg_format_msg (char *format, ...) ;
#define DBG_MESSAGE(fmt_str) { dbg_format_msg fmt_str ; }
typedef volatile unsigned int REG_DWORD ;// Hardware register definition
typedef volatile unsigned short REG_WORD ;
typedef volatile unsigned char REG_BYTE ;
// *****************************************************************************
// INTEGRATORCP TIMER
// *****************************************************************************
typedef struct ICP_TIMER_S {
// offset read/write word size reset Description
REG_DWORD LOAD ; // 0x0000 Read/write 32 0x00000000 Load value for Timer
REG_DWORD VALUE ; // 0x0004 Read 32 0xFFFFFFFF The current value for Timer
REG_BYTE CONTROL ; // 0x0008 Read/write 8 0x20 Timer control register
REG_DWORD INTCLR ; // 0x000C Write - - Timer interrupt clear
REG_DWORD RIS ; // 0x0010 Read 1 0x0 Timer raw interrupt status
REG_DWORD MIS ; // 0x0014 Read 1 0x0 Timer masked interrupt status
REG_DWORD BGLOAD ; // 0x0018 Read/write 32 0x00000000 Background load value for Timer
} ICP_TIMER_T, *PICP_TIMER_T ;
// -------- ICP_TIMER_LOAD : (LOAD Offset: 0x00) Load value for Timer --------
// -------- ICP_TIMER_VALUE : (LOAD Offset: 0x04) The current value for Timer --------
// -------- ICP_TIMER_CONTROL : (CONTROL Offset: 0x04) Timer control register --------
#define ICP_TIMER_CONTROL_MASK ((unsigned int)0x0F << 0) // Timer control mask
#define ICP_TIMER_CONTROL_ENABLE ((unsigned int)0x01 << 7) // Timer enable: 0 = disabled 1 = enabled.
#define ICP_TIMER_CONTROL_MODE ((unsigned int)0x01 << 6) // Timer mode: 0 = free running, counts once and then wraps to 0xFFFF 1 = periodic, reloads from load register at the end of each count..
#define ICP_TIMER_CONTROL_IE ((unsigned int)0x01 << 5) // Interrupt enable.
#define ICP_TIMER_CONTROL_R ((unsigned int)0x01 << 4) // Unused, always write as 0s.
#define ICP_TIMER_CONTROL_PRESCALE_MASK ((unsigned int)0x03 << 2) // Prescale divisor
#define ICP_TIMER_CONTROL_PRESCALE_NONE ((unsigned int)0x00 << 2) //
#define ICP_TIMER_CONTROL_PRESCALE_16 ((unsigned int)0x01 << 2) //
#define ICP_TIMER_CONTROL_PRESCALE_256 ((unsigned int)0x02 << 2) //
#define ICP_TIMER_CONTROL_TIMER_SIZE ((unsigned int)0x01 << 1) // Selects 16/32 bit counter operation: 0 = 16-bit counter (default) 1 = 32-bit counter For 16-bit mode, write the high 16 bits of the 32-bit value as 0.
#define ICP_TIMER_CONTROL_ONE_SHOT ((unsigned int)0x01 << 0) // Selects one-shot or wrapping counter mode: 0 = wrapping mode (default) 1 = one-shot mode
// -------- ICP_TIMER_INTCLR : (INTCLR Offset: 0x0C) Timer interrupt clear --------
// -------- ICP_TIMER_RIS : (RIS Offset: 0x10) Timer raw interrupt status --------
// -------- ICP_TIMER_MIS : (MIS Offset: 0x14) Timer masked interrupt status --------
#define ICP_TIMER_INT ((unsigned int)0x01 << 0) // Interrupt
// -------- ICP_TIMER_BGLOAD : (BGLOAD Offset: 0x18) Timer masked interrupt status --------
// *****************************************************************************
// INTEGRATORCP PIC
// *****************************************************************************
typedef struct ICP_PIC_S {
// offset read/write word size reset Description
REG_DWORD IRQ_STATUS ; // 0x0000 Read 22 IRQ gated interrupt status
REG_DWORD IRQ_RAWSTAT ; // 0x0004 Read 22 IRQ raw interrupt status
REG_DWORD IRQ_ENABLESET ; // 0x0008 Read/write 22 IRQ enable set
REG_DWORD IRQ_ENABLECLR ; // 0x000C Write 22 IRQ enable clear
REG_DWORD INT_SOFTSET ; // 0x0010 Read/write 16 Software interrupt set
REG_DWORD INT_SOFTCLR ; // 0x0014 Write 16 Software interrupt clear
REG_DWORD RESERVED[2] ; // 0x0018
REG_DWORD FIQ_STATUS ; // 0x0020 Read 22 FIQ gated interrupt status
REG_DWORD FIQ_RAWSTAT ; // 0x0024 Read 22 FIQ raw interrupt status
REG_DWORD FIQ_ENABLESET ; // 0x0028 Read/write 22 FIQ enable set
REG_DWORD FIQ_ENABLECLR ; // 0x002C Write-only 22 FIQ enable clear
} ICP_PIC_T, *PICP_PIC_T ;
// -------- ICP_PIC_IRQ_STATUS : (IRQ_STATUS Offset: 0x00) IRQ gated interrupt status --------
// -------- ICP_PIC_IRQ_RAWSTAT : (IRQ_RAWSTAT Offset: 0x04) IRQ raw interrupt status --------
// -------- ICP_PIC_IRQ_ENABLESET : (IRQ_ENABLESET Offset: 0x08) IRQ enable set --------
// -------- ICP_PIC_IRQ_ENABLECLR : (IRQ_ENABLECLR Offset: 0x0C) IRQ enable clear --------
#define ICP_PIC_IRQ_MASK ((unsigned int)0x3FFFFF << 0) // IRQ mask
#define ICP_PIC_IRQ_TIMERINT2 ((unsigned int)0x01 << 7) // TIMERINT2 Counter-timer 2 interrupt
#define ICP_PIC_IRQ_TIMERINT1 ((unsigned int)0x01 << 6) // TIMERINT1 Counter-timer 1 interrupt
#define ICP_PIC_IRQ_TIMERINT0 ((unsigned int)0x01 << 5) // TIMERINT0 Counter-timer 0 interrupt
#define ICP_PIC_IRQ_SOFTINT ((unsigned int)0x01 << 0) // OFTINT Software interrupt
// -------- ICP_PIC_INT_SOFTSET : (INT_SOFTSET Offset: 0x10) Software interrupt set --------
// -------- ICP_PIC_INT_SOFTCLR : (INT_SOFTCLR Offset: 0x14) Software interrupt clear --------
#define BOARD_BASE_ADDRESS_TIMER_0 0x13000000
#define BOARD_BASE_ADDRESS_PIC 0x14000000
extern ICP_TIMER_T* const board_timer_0 ;
extern ICP_PIC_T* const board_pic ;
extern int low_level_init (void) ;
#endif /* __MODULES_H__ */

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.section .vectors, "x"
.global __interrupt_vector_table
.global __irq_stack_top__
.global __fiq_stack_top__
.global __svc_stack_top__
.global bsp_ints_enable
.global bsp_ints_disable
.global bsp_ints_restore
.equ USR_MODE, 0x10
.equ FIQ_MODE, 0x11
.equ IRQ_MODE, 0x12
.equ SVC_MODE, 0x13
.equ ABT_MODE, 0x17
.equ UND_MODE, 0x1B
.equ SYS_MODE, 0x1F
.equ I_BIT, 0x80 /* when I bit is set, IRQ is disabled */
.equ F_BIT, 0x40 /* when F bit is set, FIQ is disabled */
__interrupt_vector_table:
B Reset_Handler /* Reset */
B . /* Undefined */
B . /* SWI */
B . /* Prefetch Abort */
B . /* Data Abort */
B . /* reserved */
B IRQ_Handler /* IRQ */
B . /* FIQ */
Reset_Handler:
MSR CPSR_c,#(IRQ_MODE | I_BIT | F_BIT)
LDR sp,=__irq_stack_top__ /* set the IRQ stack pointer */
MSR CPSR_c,#(FIQ_MODE | I_BIT | F_BIT)
LDR sp,=__fiq_stack_top__ /* set the FIQ stack pointer */
MSR CPSR_c,#(SVC_MODE | I_BIT | F_BIT)
LDR sp,=__svc_stack_top__ /* set the SVC stack pointer */
BL low_level_init
BL _mainCRTStartup
B .
IRQ_Handler:
B archIRQHandler

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ENTRY(__interrupt_vector_table)
MEMORY
{
flash (rx) : ORIGIN = 0x00000000, LENGTH = 0x00020000
sram (rwx) : ORIGIN = 0x00020000, LENGTH = 0x00020000
}
EXTERN(__interrupt_vector_table);
C_STACK_SIZE = 512;
IRQ_STACK_SIZE = 256;
FIQ_STACK_SIZE = 256;
SVC_STACK_SIZE = 512;
ABT_STACK_SIZE = 256;
UND_STACK_SIZE = 256;
SECTIONS
{
.text :
{
*(.vectors)
/* Startup assembly */
*(.startup)
*(.init)
/* Rest of the code (C) */
*(.text)
*(.rodata)
*(.rodata*)
_end_text = .;
} >flash
.data :
{
_start_data = .;
*(.data)
_end_data = .;
} >sram
.bss :
{
_start_bss = .;
__bss_start__ = . ;
*(.bss)
*(.eh_*)
} >sram
. = ALIGN(4);
_end_bss = .;
__bss_end__ = . ;
. = ALIGN(256);
.stack : {
__stack_start__ = . ;
. += IRQ_STACK_SIZE;
. = ALIGN (4);
__irq_stack_top__ = . ;
. += FIQ_STACK_SIZE;
. = ALIGN (4);
__fiq_stack_top__ = . ;
. += SVC_STACK_SIZE;
. = ALIGN (4);
__svc_stack_top__ = . ;
. += ABT_STACK_SIZE;
. = ALIGN (4);
__abt_stack_top__ = . ;
. += UND_STACK_SIZE;
. = ALIGN (4);
__und_stack_top__ = . ;
. += C_STACK_SIZE;
. = ALIGN (4);
__c_stack_top__ = . ;
__stack_end__ = .;
} >sram
/*DISCARD :
{
*(.eh_*)
}*/
}
_end = .;
PROVIDE(end = .);

60
platforms/rules.mk Normal file
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#
# The following part of the makefile is generic; it can be used to
# build any executable just by changing the definitions above and by
# deleting dependencies appended to the file from 'make depend'
#
.SUFFIXES: .asm .elf .hex .lst .o .S .s .c .cpp
.PHONY: depend clean
dump:
@echo "Target: "
@echo $(TARGET_NAME)
@echo "Source files: "
@echo $(SRCS)
@echo $(ASMS)
@echo "Object files: "
@echo $(OBJS)
all: target
target: $(OBJS)
$(LN) $(LFLAGS) $(LIBFLAGS) $(OBJS) $(LLIBS) -o $(TARGET_NAME).elf
@echo $(TARGET_NAME).elf was compiled
clean:
rm -f $(OBJS)
# this is a suffix replacement rule for building .o's from .c's
# it uses automatic variables $<: the name of the prerequisite of
# the rule(a .c file) and $@: the name of the target of the rule (a .o file)
# (see the gnu make manual section about automatic variables)
.c.o:
$(CC) $(CDEFS) $(CFLAGS) $(INCLUDES) -c $< -o $@
.cpp.o:
$(CC) $(CDEFS) $(CFLAGS) $(INCLUDES) -c $< -o $@
.S.o:
$(AS) $(ADEFS) $(AFLAGS) $(INCLUDES) -c $< -o $@
.s.o:
$(AS) $(ADEFS) $(AFLAGS) $(INCLUDES) -c $< -o $@
DEPFILE=.depends
DEPTOKEN='\# MAKEDEPENDS'
DEPFLAGS=-Y -f $(DEPFILE) -s $(DEPTOKEN) -p $(OUTDIR)/
depend:
rm -f $(DEPFILE)
make $(DEPFILE)
$(DEPFILE):
@echo $(DEPTOKEN) > $(DEPFILE)
makedepend $(DEPFLAGS) -- $(CFLAGS) -- $(SRCS) >&/dev/null
# put this file in the last line of your Makefile
sinclude $(DEPFILE)