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62 lines
1.5 KiB
Makefile
62 lines
1.5 KiB
Makefile
#
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# The following part of the makefile is generic; it can be used to
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# build any executable just by changing the definitions above and by
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# deleting dependencies appended to the file from 'make depend'
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#
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.SUFFIXES: .asm .elf .hex .lst .o .S .s .c .cpp
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.PHONY: depend clean
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dump:
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@echo "Target: "
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@echo $(TARGET_NAME)
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@echo "Source files: "
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@echo $(SRCS)
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@echo $(ASMS)
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@echo "Object files: "
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@echo $(OBJS)
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all: target
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target: $(OBJS)
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$(LN) $(LFLAGS) $(LIBFLAGS) $(OBJS) $(LLIBS) -o $(TARGET_NAME).elf
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@echo $(TARGET_NAME).elf was compiled
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arm-none-eabi-objcopy -O binary $(TARGET_NAME).elf $(TARGET_NAME).bin
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arm-none-eabi-objdump -dxS $(TARGET_NAME).elf > $(TARGET_NAME).out
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clean:
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rm -f $(OBJS)
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# this is a suffix replacement rule for building .o's from .c's
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# it uses automatic variables $<: the name of the prerequisite of
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# the rule(a .c file) and $@: the name of the target of the rule (a .o file)
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# (see the gnu make manual section about automatic variables)
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.c.o:
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$(CC) $(CDEFS) $(CFLAGS) $(INCLUDES) -c $< -o $@
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.cpp.o:
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$(CC) $(CDEFS) $(CFLAGS) $(INCLUDES) -c $< -o $@
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.S.o:
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$(AS) $(ADEFS) $(AFLAGS) $(INCLUDES) -c $< -o $@
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.s.o:
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$(AS) $(ADEFS) $(AFLAGS) $(INCLUDES) -c $< -o $@
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DEPFILE=.depends
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DEPTOKEN='\# MAKEDEPENDS'
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DEPFLAGS=-Y -f $(DEPFILE) -s $(DEPTOKEN) -p $(OUTDIR)/
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depend:
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rm -f $(DEPFILE)
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make $(DEPFILE)
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$(DEPFILE):
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@echo $(DEPTOKEN) > $(DEPFILE)
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makedepend $(DEPFLAGS) -- $(CFLAGS) -- $(SRCS) >&/dev/null
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# put this file in the last line of your Makefile
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sinclude $(DEPFILE)
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