mirror of
https://github.com/kelvinlawson/atomthreads.git
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332 lines
9.0 KiB
C
332 lines
9.0 KiB
C
/**
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******************************************************************************
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* @file stm8s_itc.c
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* @brief This file contains all the functions for the ITC peripheral.
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* @author STMicroelectronics - MCD Application Team
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* @version V1.1.1
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* @date 06/05/2009
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******************************************************************************
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*
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* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
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* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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*
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* <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>
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* @image html logo.bmp
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******************************************************************************
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "stm8s_itc.h"
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/* Private typedef -----------------------------------------------------------*/
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/* Private define ------------------------------------------------------------*/
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/* Private macro -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private function prototypes -----------------------------------------------*/
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/* Private functions ---------------------------------------------------------*/
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/** @addtogroup ITC_Private_Functions
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* @{
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*/
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/**
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* @brief Utility function used to read CC register.
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* @par Parameters:
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* None
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* @retval u8 Content of CC register (in A register).
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*/
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#ifdef __SDCC_stm8
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uint8_t get_cc(void);
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#endif
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u8 ITC_GetCPUCC(void)
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{
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#ifdef _COSMIC_
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_asm("push cc");
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_asm("pop a");
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return; /* Ignore compiler warning, the returned value is in A register */
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#endif
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#ifdef __SDCC_stm8
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return get_cc();
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#endif
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#ifdef _RAISONANCE_
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return _getCC_();
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#endif
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#ifdef _IAR_SYSTEMS_
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__asm("push cc");
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__asm("pop a");
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#endif
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}
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/**
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* @}
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*/
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/* Public functions ----------------------------------------------------------*/
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/** @addtogroup ITC_Public_Functions
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* @{
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*/
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/**
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* @brief Deinitializes the ITC registers to their default reset value.
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* @par Parameters:
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* None
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* @retval
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* None
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*/
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void ITC_DeInit(void)
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{
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ITC->ISPR1 = ITC_SPRX_RESET_VALUE;
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ITC->ISPR2 = ITC_SPRX_RESET_VALUE;
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ITC->ISPR3 = ITC_SPRX_RESET_VALUE;
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ITC->ISPR4 = ITC_SPRX_RESET_VALUE;
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ITC->ISPR5 = ITC_SPRX_RESET_VALUE;
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ITC->ISPR6 = ITC_SPRX_RESET_VALUE;
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ITC->ISPR7 = ITC_SPRX_RESET_VALUE;
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ITC->ISPR8 = ITC_SPRX_RESET_VALUE;
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}
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/**
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* @brief Get the software interrupt priority bits (I1, I0) value from CPU CC register.
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* @par Parameters:
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* None
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* @retval u8 The software interrupt priority bits value.
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*/
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u8 ITC_GetSoftIntStatus(void)
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{
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return (u8)(ITC_GetCPUCC() & CPU_CC_I1I0);
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}
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/**
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* @brief Get the software priority of the specified interrupt source.
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* @param[in] IrqNum The IRQ number to access.
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* @retval ITC_PriorityLevel_TypeDef The software priority of the interrupt source.
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*/
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ITC_PriorityLevel_TypeDef ITC_GetSoftwarePriority(ITC_Irq_TypeDef IrqNum)
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{
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u8 Value = 0;
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u8 Mask;
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/* Check function parameters */
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assert_param(IS_ITC_IRQ_OK((u8)IrqNum));
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/* Define the mask corresponding to the bits position in the SPR register */
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Mask = (u8)(0x03U << (((u8)IrqNum % 4U) * 2U));
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switch (IrqNum)
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{
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case ITC_IRQ_TLI: /* TLI software priority can be read but has no meaning */
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case ITC_IRQ_AWU:
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case ITC_IRQ_CLK:
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case ITC_IRQ_PORTA:
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Value = (u8)(ITC->ISPR1 & Mask); /* Read software priority */
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break;
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case ITC_IRQ_PORTB:
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case ITC_IRQ_PORTC:
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case ITC_IRQ_PORTD:
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case ITC_IRQ_PORTE:
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Value = (u8)(ITC->ISPR2 & Mask); /* Read software priority */
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break;
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#ifdef STM8S208
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case ITC_IRQ_CAN_RX:
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case ITC_IRQ_CAN_TX:
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#endif /*STM8S208*/
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#ifdef STM8S903
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case ITC_IRQ_PORTF:
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#endif /*STM8S903*/
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case ITC_IRQ_SPI:
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case ITC_IRQ_TIM1_OVF:
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Value = (u8)(ITC->ISPR3 & Mask); /* Read software priority */
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break;
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case ITC_IRQ_TIM1_CAPCOM:
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#ifdef STM8S903
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case ITC_IRQ_TIM5_OVFTRI:
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case ITC_IRQ_TIM5_CAPCOM:
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#else
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case ITC_IRQ_TIM2_OVF:
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case ITC_IRQ_TIM2_CAPCOM:
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#endif /*STM8S903*/
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case ITC_IRQ_TIM3_OVF:
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Value = (u8)(ITC->ISPR4 & Mask); /* Read software priority */
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break;
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case ITC_IRQ_TIM3_CAPCOM:
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case ITC_IRQ_UART1_TX:
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case ITC_IRQ_UART1_RX:
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case ITC_IRQ_I2C:
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Value = (u8)(ITC->ISPR5 & Mask); /* Read software priority */
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break;
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#ifdef STM8S105
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case ITC_IRQ_UART2_TX:
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case ITC_IRQ_UART2_RX:
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#endif /*STM8S105*/
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#if defined(STM8S208) ||defined(STM8S207)
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case ITC_IRQ_UART3_TX:
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case ITC_IRQ_UART3_RX:
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case ITC_IRQ_ADC2:
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#endif /*STM8S208 or STM8S207*/
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#if defined(STM8S105) ||defined(STM8S103) ||defined(STM8S905)
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case ITC_IRQ_ADC1:
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#endif /*STM8S105, STM8S103 or STM8S905 */
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#ifdef STM8S903
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case ITC_IRQ_TIM6_OVFTRI:
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#else
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case ITC_IRQ_TIM4_OVF:
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#endif /*STM8S903*/
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Value = (u8)(ITC->ISPR6 & Mask); /* Read software priority */
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break;
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case ITC_IRQ_EEPROM_EEC:
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Value = (u8)(ITC->ISPR7 & Mask); /* Read software priority */
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break;
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default:
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break;
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}
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Value >>= (u8)(((u8)IrqNum % 4u) * 2u);
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return((ITC_PriorityLevel_TypeDef)Value);
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}
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/**
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* @brief Set the software priority of the specified interrupt source.
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* @param[in] IrqNum The interrupt source to access.
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* @param[in] PriorityValue The software priority value to set.
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* @retval ITC_PriorityLevel_TypeDef The software priority of the interrupt source.
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* @par Required preconditions:
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* - The modification of the software priority is only possible when the interrupts are disabled.
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* - The normal behavior is to disable the interrupts before calling this function, and re-enable it after.
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* - The priority level 0 cannot be set (see product specification for more details).
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*/
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void ITC_SetSoftwarePriority(ITC_Irq_TypeDef IrqNum, ITC_PriorityLevel_TypeDef PriorityValue)
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{
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u8 Mask;
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u8 NewPriority;
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/* Check function parameters */
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assert_param(IS_ITC_IRQ_OK((u8)IrqNum));
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assert_param(IS_ITC_PRIORITY_OK(PriorityValue));
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/* Check if interrupts are disabled */
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assert_param(IS_ITC_INTERRUPTS_DISABLED);
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/* Define the mask corresponding to the bits position in the SPR register */
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/* The mask is reversed in order to clear the 2 bits after more easily */
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Mask = (u8)(~(u8)(0x03U << (((u8)IrqNum % 4U) * 2U)));
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/* Define the new priority to write */
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NewPriority = (u8)((u8)(PriorityValue) << (((u8)IrqNum % 4U) * 2U));
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switch (IrqNum)
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{
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case ITC_IRQ_TLI: /* TLI software priority can be written but has no meaning */
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case ITC_IRQ_AWU:
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case ITC_IRQ_CLK:
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case ITC_IRQ_PORTA:
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ITC->ISPR1 &= Mask;
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ITC->ISPR1 |= NewPriority;
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break;
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case ITC_IRQ_PORTB:
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case ITC_IRQ_PORTC:
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case ITC_IRQ_PORTD:
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case ITC_IRQ_PORTE:
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ITC->ISPR2 &= Mask;
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ITC->ISPR2 |= NewPriority;
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break;
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#ifdef STM8S208
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case ITC_IRQ_CAN_RX:
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case ITC_IRQ_CAN_TX:
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#endif /*STM8S208*/
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#ifdef STM8S903
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case ITC_IRQ_PORTF:
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#endif /*STM8S903*/
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case ITC_IRQ_SPI:
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case ITC_IRQ_TIM1_OVF:
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ITC->ISPR3 &= Mask;
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ITC->ISPR3 |= NewPriority;
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break;
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case ITC_IRQ_TIM1_CAPCOM:
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#ifdef STM8S903
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case ITC_IRQ_TIM5_OVFTRI:
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case ITC_IRQ_TIM5_CAPCOM:
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#else
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case ITC_IRQ_TIM2_OVF:
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case ITC_IRQ_TIM2_CAPCOM:
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#endif /*STM8S903*/
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case ITC_IRQ_TIM3_OVF:
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ITC->ISPR4 &= Mask;
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ITC->ISPR4 |= NewPriority;
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break;
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case ITC_IRQ_TIM3_CAPCOM:
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case ITC_IRQ_UART1_TX:
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case ITC_IRQ_UART1_RX:
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case ITC_IRQ_I2C:
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ITC->ISPR5 &= Mask;
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ITC->ISPR5 |= NewPriority;
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break;
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#ifdef STM8S105
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case ITC_IRQ_UART2_TX:
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case ITC_IRQ_UART2_RX:
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#endif /*STM8S105*/
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#if defined(STM8S208) ||defined(STM8S207)
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case ITC_IRQ_UART3_TX:
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case ITC_IRQ_UART3_RX:
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case ITC_IRQ_ADC2:
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#endif /*STM8S208 or STM8S207*/
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#if defined(STM8S105) ||defined(STM8S103) ||defined(STM8S905)
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case ITC_IRQ_ADC1:
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#endif /*STM8S105, STM8S103 or STM8S905 */
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#ifdef STM8S903
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case ITC_IRQ_TIM6_OVFTRI:
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#else
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case ITC_IRQ_TIM4_OVF:
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#endif /*STM8S903*/
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ITC->ISPR6 &= Mask;
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ITC->ISPR6 |= NewPriority;
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break;
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case ITC_IRQ_EEPROM_EEC:
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ITC->ISPR7 &= Mask;
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ITC->ISPR7 |= NewPriority;
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break;
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default:
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break;
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}
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}
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/**
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* @}
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*/
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/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
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