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130 lines
3.8 KiB
ArmAsm
130 lines
3.8 KiB
ArmAsm
/*
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* Copyright (c) 2011, Himanshu Chauhan. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. No personal names or organizations' names associated with the
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* Atomthreads project may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "atomport-asm-macros.h"
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.extern _stack_start
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.section .start.text,"ax",@progbits
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EXCEPTION_VECTOR(_tlbmiss, 0x00, _handle_tlbmiss)
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EXCEPTION_VECTOR(_cache_error, 0x100, _handle_cache_error)
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EXCEPTION_VECTOR(_general_exception, 0x180, _handle_general_exception)
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/* FIXME: We don't need this when in EIC mode. */
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EXCEPTION_VECTOR(_interrupts, 0x200, _handle_interrupt)
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LEAF(_start)
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mtc0 zero, CP0_CONTEXT
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nop
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nop
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nop
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/* globally disable interrupts until we are prepared. */
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disable_global_interrupts
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/* clear CPU timer counters. We don't want surprises. */
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mtc0 zero, CP0_COMPARE
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mtc0 zero, CP0_COUNT
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la sp, _stack_start /* setup the stack (bss segment) */
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la t0, main
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j t0 /* Call the C- code now */
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nop
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1: b 1b /* we should not come here whatsoever */
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END(_start)
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.extern vmm_cpu_handle_pagefault
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LEAF(_handle_tlbmiss)
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//disable_global_interrupts
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//move k0, sp
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//SAVE_INT_CONTEXT(_int_stack)
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//move a0, sp
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//bal vmm_cpu_handle_pagefault
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//nop
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//enable_global_interrupts
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//eret
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END(_handle_tlbmiss)
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.extern generic_int_handler
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.extern _int_stack
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.extern vmm_regs_dump
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LEAF(_handle_interrupt)
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//disable_global_interrupts
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//SAVE_INT_CONTEXT(_int_stack)
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//move a0, sp
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//bal generic_int_handler
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//nop
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//RESTORE_INT_CONTEXT(sp)
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//enable_global_interrupts
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//eret
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END(_handle_interrupt)
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LEAF(_handle_cache_error)
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b _handle_cache_error
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nop
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END(_handle_cache_error)
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LEAF(_handle_general_exception)
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b _handle_general_exception
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nop
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END(_handle_general_exception)
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/**
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* a0 -> Contains virtual address.
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* a1 -> Contains physical address.
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* a2 -> TLB index: If -1 select automatically.
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*/
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.globl create_tlb_entry
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LEAF(create_tlb_entry)
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mtc0 a2, CP0_INDEX /* load the tlb index to be programmed. */
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srl a0, a0, 12 /* get the VPN */
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sll a0, a0, 12
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nop
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mtc0 a0, CP0_ENTRYHI /* load VPN in entry hi */
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addi t0, a1, 0x1000 /* next PFN for entry lo1 in T0 */
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srl a1, a1, 12 /* get the PFN */
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sll a1, a1, 6 /* get the PFN */
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srl t0, t0, 12
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sll t0, t0, 6
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ori a1, a1, 0x7 /* mark the page writable, global and valid */
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mtc0 a1, CP0_ENTRYLO0
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ori t0, t0, 0x7 /* mark the next physical page writable, global and valid */
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nop
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nop
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mtc0 t0, CP0_ENTRYLO1
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nop
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nop
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nop
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tlbwi
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ehb
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j ra
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nop
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END(create_tlb_entry)
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