mirror of
https://github.com/drasko/codezero.git
synced 2026-02-15 11:23:16 +01:00
1. Old pending files cleaned from public repo. 2. Thread_create routines removed from timer_service and kmi_service. 3. Sconstruct of libdev updated.
This commit is contained in:
Amit Mahajan
@@ -46,6 +46,12 @@ objects += SConscript('uart/pl011/SConscript', duplicate=0, \
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exports = {'platform' : platform, 'env' : env})
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objects += SConscript('timer/sp804/SConscript', duplicate=0, \
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exports = {'platform' : platform, 'env' : env})
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objects += SConscript('kmi/pl050/SConscript', duplicate=0, \
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exports = {'platform' : platform, 'env' : env})
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objects += SConscript('uart/omap/SConscript', duplicate=0, \
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exports = {'platform' : platform, 'env' : env})
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objects += SConscript('timer/omap/SConscript', duplicate=0, \
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exports = {'platform' : platform, 'env' : env})
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library = env.StaticLibrary('libdev-' + variant, objects)
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@@ -1,104 +0,0 @@
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#ifndef __PL110_CLCD_H__
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#define __PL110_CLCD_H__
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/* Register offsets */
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#define PL110_CLCD_TIMING0 0x000 /* Horizontal Axis Panel Control*/
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#define PL110_CLCD_TIMING1 0x004 /* Vertical Axis Panel Control */
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#define PL110_CLCD_TIMING2 0x008 /* Clock and Polarity Signal Control*/
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#define PL110_CLCD_TIMING3 0x00c /* Line End Control */
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#define PL110_CLCD_UPBASE 0x010 /* Upper Panel Frame Base Address*/
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#define PL110_CLCD_LPBASE 0x014 /* Lower Panel Frame Base Address */
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#define PL110_CLCD_IMSC 0x018 /* Interrupt Mast Set Clear */
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#define PL110_CLCD_CONTROL 0x01c /* CLCD Control */
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#define PL110_CLCD_RIS 0x020 /* Raw Interrupt Status */
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#define PL110_CLCD_MIS 0x024 /* Masked Interrupt Status */
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#define PL110_CLCD_ICR 0x028 /* Interrupt Clear */
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#define PL110_CLCD_UPCURR 0x02c /* Upper Panel Current Address Value */
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#define PL110_CLCD_LPCURR 0x030 /* Lower Panel Current Address Value */
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//#define PL110_LCD_PALETTE
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#define PL110_CLCD_PERIPHID0 0xfe0 /* Peripheral Identification */
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#define PL110_CLCD_PERIPHID1 0xfe4 /* Peripheral Identification */
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#define PL110_CLCD_PERIPHID2 0xfe8 /* Peripheral Identification */
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#define PL110_CLCD_PERIPHID3 0xfec /* Peripheral Identification */
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#define PL110_CLCD_PCELLID0 0xff0 /* Peripheral Identification */
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#define PL110_CLCD_PCELLID1 0xff4 /* PrimeCell Identification */
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#define PL110_CLCD_PCELLID2 0xff8 /* PrimeCell Identification */
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#define PL110_CLCD_PCELLID3 0xffc /* PrimeCell Identification */
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/* Scan mode */
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#define SCAN_VMODE_NONINTERLACED 0 /* non interlaced */
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#define SCAN_VMODE_INTERLACED 1 /* interlaced */
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#define SCAN_VMODE_DOUBLE 2 /* double scan */
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#define SCAN_VMODE_ODD_FLD_FIRST 4 /* interlaced: top line first */
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#define SCAN_VMODE_MASK 255
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/* Control Register Bits */
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#define PL110_CNTL_LCDEN (1 << 0)
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#define PL110_CNTL_LCDBPP1 (0 << 1)
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#define PL110_CNTL_LCDBPP2 (1 << 1)
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#define PL110_CNTL_LCDBPP4 (2 << 1)
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#define PL110_CNTL_LCDBPP8 (3 << 1)
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#define PL110_CNTL_LCDBPP16 (4 << 1)
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#define PL110_CNTL_LCDBPP16_565 (6 << 1)
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#define PL110_CNTL_LCDBPP24 (5 << 1)
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#define PL110_CNTL_LCDBW (1 << 4)
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#define PL110_CNTL_LCDTFT (1 << 5)
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#define PL110_CNTL_LCDMONO8 (1 << 6)
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#define PL110_CNTL_LCDDUAL (1 << 7)
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#define PL110_CNTL_BGR (1 << 8)
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#define PL110_CNTL_BEBO (1 << 9)
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#define PL110_CNTL_BEPO (1 << 10)
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#define PL110_CNTL_LCDPWR (1 << 11)
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#define PL110_CNTL_LCDVCOMP(x) ((x) << 12)
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#define PL110_CNTL_LDMAFIFOTIME (1 << 15)
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#define PL110_CNTL_WATERMARK (1 << 16)
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#define PL110_TIM2_CLKSEL (1 << 5)
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#define PL110_TIM2_IVS (1 << 11)
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#define PL110_TIM2_IHS (1 << 12)
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#define PL110_TIM2_IPC (1 << 13)
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#define PL110_TIM2_IOE (1 << 14)
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#define PL110_TIM2_BCD (1 << 26)
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struct videomode {
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const char *name; /* optional */
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unsigned int refresh; /* optional */
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unsigned int xres;
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unsigned int yres;
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unsigned int pixclock;
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unsigned int left_margin;
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unsigned int right_margin;
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unsigned int upper_margin;
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unsigned int lower_margin;
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unsigned int hsync_len;
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unsigned int vsync_len;
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unsigned int sync;
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unsigned int vmode;
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unsigned int flag;
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};
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struct pl110_clcd_panel {
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struct videomode mode;
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signed short width; /* width in mm */
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signed short height; /* height in mm */
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unsigned int tim2;
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unsigned int tim3;
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unsigned int cntl;
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unsigned int bpp:8,
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fixedtimings:1,
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grayscale:1;
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unsigned int connector;
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};
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struct pl110_clcd {
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unsigned int virt_base;
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struct pl110_clcd_panel *panel;
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char *frame_buffer;
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};
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void pl110_initialise(struct pl110_clcd *clcd, char *buf);
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#endif /* __PL110_CLCD_H__ */
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@@ -1,68 +0,0 @@
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#include <pl110_clcd.h>
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#define read(a) *((volatile unsigned int *)(a))
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#define write(v, a) (*((volatile unsigned int *)(a)) = v)
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#define setbit(bit, a) write(read(a) | bit, a)
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#define clrbit(bit, a) write(read(a) & ~bit, a)
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/*
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* Default panel, we will use this for now
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* Seems like qemu has support for this
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*/
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static struct pl110_clcd_panel vga = {
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.mode = {
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.name = "VGA",
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.refresh = 60,
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.xres = 640,
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.yres = 480,
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.pixclock = 39721,
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.left_margin = 40,
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.right_margin = 24,
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.upper_margin = 32,
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.lower_margin = 11,
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.hsync_len = 96,
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.vsync_len = 2,
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.sync = 0,
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.vmode = SCAN_VMODE_NONINTERLACED,
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},
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.width = -1,
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.height = -1,
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.tim2 = PL110_TIM2_BCD | PL110_TIM2_IPC,
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.cntl = PL110_CNTL_LCDTFT | PL110_CNTL_LCDVCOMP(1),
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.bpp = 16,
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};
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static void pl110_clcd_set_uppanel_fb(unsigned int clcd_base,
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unsigned int fb_base)
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{
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write(fb_base, (clcd_base + PL110_CLCD_UPBASE));
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}
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#if 0
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static void pl110_clcd_set_lwrpanel_fb(unsigned int clcd_base, unsigned int fb_base)
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{
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write(fb_base, (clcd_base +PL110_CLCD_LPBASE));
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}
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static unsigned int pl110_clcd_get_uppanel_fb(unsigned int clcd_base)
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{
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return read((clcd_base +PL110_CLCD_UPBASE));
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}
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static unsigned int pl110_clcd_get_lwrpanel_fb(unsigned int clcd_base)
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{
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return read((clcd_base +PL110_CLCD_LPBASE));
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}
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#endif
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void pl110_initialise(struct pl110_clcd *clcd, char *buf)
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{
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clcd->panel = &vga;
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clcd->frame_buffer = buf;
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pl110_clcd_set_uppanel_fb(clcd->virt_base, (unsigned int)(buf));
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}
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@@ -1,67 +0,0 @@
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/*
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* SP804 Primecell Timer offsets
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*
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* Copyright (C) 2007 Bahadir Balban
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*
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*/
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#ifndef __SP804_TIMER_H__
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#define __SP804_TIMER_H__
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#define SP804_TIMER2_OFFSET 0x20
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/* Base address of Timers for differen platforms */
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#if defined(PLATFORM_PB926)
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#define TIMER0_PHYS_BASE 0x101E2000
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#define TIMER1_PHYS_BASE (TIMER0_PHYS_BASE + SP804_TIMER2_OFFSET)
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#define TIMER2_PHYS_BASE 0x101E3000
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#define TIMER3_PHYS_BASE (TIMER2_PHYS_BASE + SP804_TIMER2_OFFSET)
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#elif defined(PLATFORM_EB)
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#define TIMER0_PHYS_BASE 0x10011000
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#define TIMER1_PHYS_BASE (TIMER0_PHYS_BASE + SP804_TIMER2_OFFSET)
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#define TIMER2_PHYS_BASE 0x10012000
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#define TIMER3_PHYS_BASE (TIMER2_PHYS_BASE + SP804_TIMER2_OFFSET)
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#elif defined(PLATFORM_PB11MPCORE)
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#define TIMER0_PHYS_BASE 0x10011000
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#define TIMER1_PHYS_BASE (TIMER0_PHYS_BASE + SP804_TIMER2_OFFSET)
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#define TIMER2_PHYS_BASE 0x10012000
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#define TIMER3_PHYS_BASE (TIMER2_PHYS_BASE + SP804_TIMER2_OFFSET)
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#define TIMER4_PHYS_BASE 0x10018000
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#define TIMER5_PHYS_BASE (TIMER4_PHYS_BASE + SP804_TIMER2_OFFSET)
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#define TIMER6_PHYS_BASE 0x10019000
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#define TIMER7_PHYS_BASE (TIMER6_PHYS_BASE + SP804_TIMER2_OFFSET)
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#endif
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/* Run mode of timers */
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#define SP804_TIMER_RUNMODE_FREERUN 0
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#define SP804_TIMER_RUNMODE_PERIODIC 1
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/* Wrap mode of timers */
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#define SP804_TIMER_WRAPMODE_WRAPPING 0
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#define SP804_TIMER_WRAPMODE_ONESHOT 1
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/* Operational width of timer */
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#define SP804_TIMER_WIDTH16BIT 0
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#define SP804_TIMER_WIDTH32BIT 1
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/* Enable/disable irq on timer */
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#define SP804_TIMER_IRQDISABLE 0
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#define SP804_TIMER_IRQENABLE 1
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/* Register offsets */
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#define SP804_TIMERLOAD 0x0
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#define SP804_TIMERVALUE 0x4
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#define SP804_TIMERCONTROL 0x8
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#define SP804_TIMERINTCLR 0xC
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#define SP804_TIMERRIS 0x10
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#define SP804_TIMERMIS 0x14
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#define SP804_TIMERBGLOAD 0x18
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void sp804_init(unsigned int timer_base, int runmode, int wrapmode, \
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int width, int irq_enable);
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void sp804_irq_handler(unsigned int timer_base);
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void sp804_enable(unsigned int timer_base, int enable);
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void sp804_set_irq(unsigned int timer_base, int enable);
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unsigned int sp804_read_value(unsigned int timer_base);
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#endif /* __SP804_TIMER_H__ */
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@@ -1,107 +0,0 @@
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/*
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* SP804 Primecell Timer driver
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*
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* Copyright (C) 2007 Bahadir Balban
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*/
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#include <sp804_timer.h>
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#define read(a) *((volatile unsigned int *)(a))
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#define write(v, a) (*((volatile unsigned int *)(a)) = v)
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#define setbit(bit, a) write(read(a) | bit, a)
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#define clrbit(bit, a) write(read(a) & ~bit, a)
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extern void timer_irq_handler(void);
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void sp804_irq_handler(unsigned int timer_base)
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{
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/*
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* Timer enabled as Periodic/Wrapper only needs irq clearing
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* as it automatically reloads and wraps
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*/
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write(1, (timer_base + SP804_TIMERINTCLR));
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timer_irq_handler();
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}
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static inline void sp804_control(unsigned int timer_base, int bit, int setclr)
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{
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unsigned long addr = (timer_base + SP804_TIMERCONTROL);
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setclr ? setbit(bit, addr) : clrbit(bit, addr);
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}
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/*
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* Sets timer's run mode:
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* @periodic: periodic mode = 1, free-running = 0.
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*/
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#define SP804_PEREN (1 << 6)
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static inline void sp804_set_runmode(unsigned int timer_base, int periodic)
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{
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sp804_control(timer_base, SP804_PEREN, periodic);
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}
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/*
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* Sets timer's wrapping mode:
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* @oneshot: oneshot = 1, wrapping = 0.
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*/
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#define SP804_ONESHOT (1 << 0)
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static inline void sp804_set_wrapmode(unsigned int timer_base, int oneshot)
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{
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sp804_control(timer_base, SP804_ONESHOT, oneshot);
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}
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/*
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* Sets the operational width of timers.
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* In 16bit mode, top halfword is ignored.
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* @width: 32bit mode = 1; 16bit mode = 0
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*/
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#define SP804_32BIT (1 << 1)
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static inline void sp804_set_widthmode(unsigned int timer_base, int width)
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{
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sp804_control(timer_base, SP804_32BIT, width);
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}
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/*
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* Enable/disable timer:
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* @enable: enable = 1, disable = 0;
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*/
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#define SP804_ENABLE (1 << 7)
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void sp804_enable(unsigned int timer_base, int enable)
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{
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sp804_control(timer_base, SP804_ENABLE, enable);
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}
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/*
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* Enable/disable local irq register:
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* @enable: enable = 1, disable = 0
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*/
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#define SP804_IRQEN (1 << 5)
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void sp804_set_irq(unsigned int timer_base, int enable)
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{
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sp804_control(timer_base, SP804_IRQEN, enable);
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}
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/* Loads timer with value in val */
|
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static inline void sp804_load_value(unsigned int timer_base, unsigned int val)
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{
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write(val, (timer_base + SP804_TIMERLOAD));
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}
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|
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/* Returns current timer value */
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unsigned int sp804_read_value(unsigned int timer_base)
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{
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return read(timer_base + SP804_TIMERVALUE);
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}
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/* TODO: Define macro values for duration */
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void sp804_init(unsigned int timer_base, int run_mode, int wrap_mode, \
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int width, int irq_enable)
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{
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||||
/* 1 tick per usec */
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const int duration = 250;
|
||||
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sp804_set_runmode(timer_base, run_mode); /* Periodic */
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sp804_set_wrapmode(timer_base, wrap_mode); /* Wrapping */
|
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sp804_set_widthmode(timer_base, width); /* 32 bit */
|
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sp804_set_irq(timer_base, irq_enable); /* Enable */
|
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sp804_load_value(timer_base, duration);
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}
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@@ -1,379 +0,0 @@
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#ifndef __PL011__UART__H__
|
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#define __PL011__UART__H__
|
||||
|
||||
/*
|
||||
* PL011 UART Generic driver implementation.
|
||||
* Copyright Bahadir Balban (C) 2009
|
||||
*
|
||||
* The particular intention of this code is that it has been carefully
|
||||
* written as decoupled from os-specific code and in a verbose way such
|
||||
* that it clearly demonstrates how the device operates, reducing the
|
||||
* amount of time to be spent for understanding the operational model
|
||||
* and implementing a driver from scratch. This is the very first to be
|
||||
* such a driver so far, hopefully it will turn out to be useful.
|
||||
*/
|
||||
|
||||
#if defined(VARIANT_USERSPACE)
|
||||
/* FIXME: Take this value in agreement from kernel, or from kernel only */
|
||||
#define PL011_BASE 0x500000
|
||||
#endif
|
||||
|
||||
#if defined(VARIANT_BAREMETAL)
|
||||
#if defined(PLATFORM_PB926)
|
||||
#define PL011_BASE 0x101F1000
|
||||
#elif defined(PLATFORM_EB)
|
||||
#define PL011_BASE 0x10009000
|
||||
#elif defined(PLATFORM_PB11MPCORE)
|
||||
#define PL011_BASE 0x10009000
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* Architecture specific memory access macros */
|
||||
#define read(val, address) val = *((volatile unsigned int *) address)
|
||||
#define write(val, address) *((volatile unsigned int *) address) = val
|
||||
|
||||
/* Register offsets */
|
||||
#define PL011_UARTDR 0x00
|
||||
#define PL011_UARTRSR 0x04
|
||||
#define PL011_UARTECR 0x04
|
||||
#define PL011_UARTFR 0x18
|
||||
#define PL011_UARTILPR 0x20
|
||||
#define PL011_UARTIBRD 0x24
|
||||
#define PL011_UARTFBRD 0x28
|
||||
#define PL011_UARTLCR_H 0x2C
|
||||
#define PL011_UARTCR 0x30
|
||||
#define PL011_UARTIFLS 0x34
|
||||
#define PL011_UARTIMSC 0x38
|
||||
#define PL011_UARTRIS 0x3C
|
||||
#define PL011_UARTMIS 0x40
|
||||
#define PL011_UARTICR 0x44
|
||||
#define PL011_UARTDMACR 0x48
|
||||
|
||||
/* IRQ bits for each uart irq event */
|
||||
#define PL011_RXIRQ (1 << 4)
|
||||
#define PL011_TXIRQ (1 << 5)
|
||||
#define PL011_RXTIMEOUTIRQ (1 << 6)
|
||||
#define PL011_FEIRQ (1 << 7)
|
||||
#define PL011_PEIRQ (1 << 8)
|
||||
#define PL011_BEIRQ (1 << 9)
|
||||
#define PL011_OEIRQ (1 << 10)
|
||||
|
||||
struct pl011_uart {
|
||||
unsigned long base;
|
||||
unsigned int frame_errors;
|
||||
unsigned int parity_errors;
|
||||
unsigned int break_errors;
|
||||
unsigned int overrun_errors;
|
||||
unsigned int rx_timeout_errors;
|
||||
};
|
||||
|
||||
int pl011_tx_char(unsigned int base, char c);
|
||||
int pl011_rx_char(unsigned int base, char *c);
|
||||
|
||||
void pl011_set_baudrate(unsigned int base, unsigned int baud,
|
||||
unsigned int clkrate);
|
||||
void pl011_set_irq_mask(unsigned int base, unsigned int flags);
|
||||
void pl011_clr_irq_mask(unsigned int base, unsigned int flags);
|
||||
|
||||
void pl011_irq_handler(struct pl011_uart *);
|
||||
void pl011_tx_irq_handler(struct pl011_uart *uart, unsigned int);
|
||||
void pl011_rx_irq_handler(struct pl011_uart *uart, unsigned int);
|
||||
void pl011_error_irq_handler(struct pl011_uart *uart, unsigned int);
|
||||
|
||||
static inline void pl011_uart_enable(unsigned int base);
|
||||
static inline void pl011_uart_disable(unsigned int base);
|
||||
static inline void pl011_tx_enable(unsigned int base);
|
||||
static inline void pl011_tx_disable(unsigned int base);
|
||||
static inline void pl011_rx_enable(unsigned int base);
|
||||
static inline void pl011_rx_disable(unsigned int base);
|
||||
static inline void pl011_irq_clear(unsigned int base, unsigned int flags);
|
||||
static inline unsigned int pl011_read_irqstat(unsigned int base);
|
||||
static inline unsigned int pl011_read_irqmask(unsigned int base);
|
||||
static inline void pl011_rx_dma_disable(unsigned int base);
|
||||
static inline void pl011_rx_dma_enable(unsigned int base);
|
||||
static inline void pl011_tx_dma_enable(unsigned int base);
|
||||
static inline void pl011_tx_dma_disable(unsigned int base);
|
||||
static inline void pl011_set_irq_fifolevel(unsigned int base,
|
||||
unsigned int xfer, unsigned int level);
|
||||
static inline void pl011_set_word_width(unsigned int base, int size);
|
||||
static inline void pl011_disable_fifos(unsigned int base);
|
||||
static inline void pl011_set_parity_even(unsigned int base);
|
||||
static inline void pl011_parity_enable(unsigned int base);
|
||||
static inline void pl011_set_stopbits(unsigned int base, int stopbits);
|
||||
|
||||
static inline void pl011_set_parity_odd(unsigned int base);
|
||||
static inline void pl011_enable_fifos(unsigned int base);
|
||||
static inline void pl011_parity_disable(unsigned int base);
|
||||
|
||||
#define PL011_UARTEN (1 << 0)
|
||||
static inline void pl011_uart_enable(unsigned int base)
|
||||
{
|
||||
unsigned int val = 0;
|
||||
|
||||
read(val, (base + PL011_UARTCR));
|
||||
val |= PL011_UARTEN;
|
||||
write(val, (base + PL011_UARTCR));
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
static inline void pl011_uart_disable(unsigned int base)
|
||||
{
|
||||
unsigned int val = 0;
|
||||
|
||||
read(val, (base + PL011_UARTCR));
|
||||
val &= ~PL011_UARTEN;
|
||||
write(val, (base + PL011_UARTCR));
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
#define PL011_TXE (1 << 8)
|
||||
static inline void pl011_tx_enable(unsigned int base)
|
||||
{
|
||||
unsigned int val = 0;
|
||||
|
||||
read(val, (base + PL011_UARTCR));
|
||||
val |= PL011_TXE;
|
||||
write(val, (base + PL011_UARTCR));
|
||||
return;
|
||||
}
|
||||
|
||||
static inline void pl011_tx_disable(unsigned int base)
|
||||
{
|
||||
unsigned int val = 0;
|
||||
|
||||
read(val, (base + PL011_UARTCR));
|
||||
val &= ~PL011_TXE;
|
||||
write(val, (base + PL011_UARTCR));
|
||||
return;
|
||||
}
|
||||
|
||||
#define PL011_RXE (1 << 9)
|
||||
static inline void pl011_rx_enable(unsigned int base)
|
||||
{
|
||||
unsigned int val = 0;
|
||||
|
||||
read(val, (base + PL011_UARTCR));
|
||||
val |= PL011_RXE;
|
||||
write(val, (base + PL011_UARTCR));
|
||||
return;
|
||||
}
|
||||
|
||||
static inline void pl011_rx_disable(unsigned int base)
|
||||
{
|
||||
unsigned int val = 0;
|
||||
|
||||
read(val, (base + PL011_UARTCR));
|
||||
val &= ~PL011_RXE;
|
||||
write(val, (base + PL011_UARTCR));
|
||||
return;
|
||||
}
|
||||
|
||||
#define PL011_TWO_STOPBITS_SELECT (1 << 3)
|
||||
static inline void pl011_set_stopbits(unsigned int base, int stopbits)
|
||||
{
|
||||
unsigned int val = 0;
|
||||
read(val, (base + PL011_UARTLCR_H));
|
||||
|
||||
if(stopbits == 2) { /* Set to two bits */
|
||||
val |= PL011_TWO_STOPBITS_SELECT;
|
||||
} else { /* Default is 1 */
|
||||
val &= ~PL011_TWO_STOPBITS_SELECT;
|
||||
}
|
||||
write(val, (base + PL011_UARTLCR_H));
|
||||
return;
|
||||
}
|
||||
|
||||
#define PL011_PARITY_ENABLE (1 << 1)
|
||||
static inline void pl011_parity_enable(unsigned int base)
|
||||
{
|
||||
unsigned int val = 0;
|
||||
|
||||
read(val, (base +PL011_UARTLCR_H));
|
||||
val |= PL011_PARITY_ENABLE;
|
||||
write(val, (base + PL011_UARTLCR_H));
|
||||
return;
|
||||
}
|
||||
|
||||
static inline void pl011_parity_disable(unsigned int base)
|
||||
{
|
||||
unsigned int val = 0;
|
||||
|
||||
read(val, (base + PL011_UARTLCR_H));
|
||||
val &= ~PL011_PARITY_ENABLE;
|
||||
write(val, (base + PL011_UARTLCR_H));
|
||||
return;
|
||||
}
|
||||
|
||||
#define PL011_PARITY_EVEN (1 << 2)
|
||||
static inline void pl011_set_parity_even(unsigned int base)
|
||||
{
|
||||
unsigned int val = 0;
|
||||
|
||||
read(val, (base + PL011_UARTLCR_H));
|
||||
val |= PL011_PARITY_EVEN;
|
||||
write(val, (base + PL011_UARTLCR_H));
|
||||
return;
|
||||
}
|
||||
|
||||
static inline void pl011_set_parity_odd(unsigned int base)
|
||||
{
|
||||
unsigned int val = 0;
|
||||
|
||||
read(val, (base + PL011_UARTLCR_H));
|
||||
val &= ~PL011_PARITY_EVEN;
|
||||
write(val, (base + PL011_UARTLCR_H));
|
||||
return;
|
||||
}
|
||||
|
||||
#define PL011_ENABLE_FIFOS (1 << 4)
|
||||
static inline void pl011_enable_fifos(unsigned int base)
|
||||
{
|
||||
unsigned int val = 0;
|
||||
|
||||
read(val, (base + PL011_UARTLCR_H));
|
||||
val |= PL011_ENABLE_FIFOS;
|
||||
write(val, (base + PL011_UARTLCR_H));
|
||||
return;
|
||||
}
|
||||
|
||||
static inline void pl011_disable_fifos(unsigned int base)
|
||||
{
|
||||
unsigned int val = 0;
|
||||
|
||||
read(val, (base + PL011_UARTLCR_H));
|
||||
val &= ~PL011_ENABLE_FIFOS;
|
||||
write(val, (base + PL011_UARTLCR_H));
|
||||
return;
|
||||
}
|
||||
|
||||
#define PL011_WORD_WIDTH_SHIFT (5)
|
||||
/* Sets the transfer word width for the data register. */
|
||||
static inline void pl011_set_word_width(unsigned int base, int size)
|
||||
{
|
||||
unsigned int val = 0;
|
||||
if(size < 5 || size > 8) /* Default is 8 */
|
||||
size = 8;
|
||||
|
||||
/* Clear size field */
|
||||
read(val, (base + PL011_UARTLCR_H));
|
||||
val &= ~(0x3 << PL011_WORD_WIDTH_SHIFT);
|
||||
write(val, (base + PL011_UARTLCR_H));
|
||||
|
||||
/*
|
||||
* The formula is to write 5 less of size given:
|
||||
* 11 = 8 bits
|
||||
* 10 = 7 bits
|
||||
* 01 = 6 bits
|
||||
* 00 = 5 bits
|
||||
*/
|
||||
read(val, (base + PL011_UARTLCR_H));
|
||||
val |= (size - 5) << PL011_WORD_WIDTH_SHIFT;
|
||||
write(val, (base + PL011_UARTLCR_H));
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
/*
|
||||
* Defines at which level of fifo fullness an irq will be generated.
|
||||
* @xfer: tx fifo = 0, rx fifo = 1
|
||||
* @level: Generate irq if:
|
||||
* 0 rxfifo >= 1/8 full txfifo <= 1/8 full
|
||||
* 1 rxfifo >= 1/4 full txfifo <= 1/4 full
|
||||
* 2 rxfifo >= 1/2 full txfifo <= 1/2 full
|
||||
* 3 rxfifo >= 3/4 full txfifo <= 3/4 full
|
||||
* 4 rxfifo >= 7/8 full txfifo <= 7/8 full
|
||||
* 5-7 reserved reserved
|
||||
*/
|
||||
static inline void pl011_set_irq_fifolevel(unsigned int base, \
|
||||
unsigned int xfer, unsigned int level)
|
||||
{
|
||||
if(xfer != 1 && xfer != 0) /* Invalid fifo */
|
||||
return;
|
||||
if(level > 4) /* Invalid level */
|
||||
return;
|
||||
|
||||
write(level << (xfer * 3), (base + PL011_UARTIFLS));
|
||||
return;
|
||||
}
|
||||
|
||||
/* returns which irqs are masked */
|
||||
static inline unsigned int pl011_read_irqmask(unsigned int base)
|
||||
{
|
||||
unsigned int flags;
|
||||
read(flags, (base + PL011_UARTIMSC));
|
||||
return flags;
|
||||
}
|
||||
|
||||
/* returns masked irq status */
|
||||
static inline unsigned int pl011_read_irqstat(unsigned int base)
|
||||
{
|
||||
unsigned int irqstatus;
|
||||
read(irqstatus, (base + PL011_UARTMIS));
|
||||
return irqstatus;
|
||||
}
|
||||
|
||||
/* Clears the given asserted irqs */
|
||||
static inline void pl011_irq_clear(unsigned int base, unsigned int flags)
|
||||
{
|
||||
if(flags > 0x3FF) {
|
||||
/* Invalid irq clearing bitvector */
|
||||
return;
|
||||
}
|
||||
/* Simply write the flags since it's a write-only register */
|
||||
write(flags, (base + PL011_UARTICR));
|
||||
return;
|
||||
}
|
||||
|
||||
#define PL011_TXDMAEN (1 << 1)
|
||||
#define PL011_RXDMAEN (1 << 0)
|
||||
/*
|
||||
* Enables dma transfers for uart. The dma controller
|
||||
* must be initialised, set-up and enabled separately.
|
||||
*/
|
||||
static inline void pl011_tx_dma_enable(unsigned int base)
|
||||
{
|
||||
unsigned int val = 0;
|
||||
|
||||
read(val, (base + PL011_UARTDMACR));
|
||||
val |= PL011_TXDMAEN;
|
||||
write(val, (base + PL011_UARTDMACR));
|
||||
return;
|
||||
}
|
||||
|
||||
/* Disables dma transfers for uart */
|
||||
static inline void pl011_tx_dma_disable(unsigned int base)
|
||||
{
|
||||
unsigned int val = 0;
|
||||
|
||||
read(val, (base + PL011_UARTDMACR));
|
||||
val &= ~PL011_TXDMAEN;
|
||||
write(val, (base + PL011_UARTDMACR));
|
||||
return;
|
||||
}
|
||||
|
||||
static inline void pl011_rx_dma_enable(unsigned int base)
|
||||
{
|
||||
unsigned int val = 0;
|
||||
|
||||
read(val, (base + PL011_UARTDMACR));
|
||||
val |= PL011_RXDMAEN;
|
||||
write(val, (base + PL011_UARTDMACR));
|
||||
return;
|
||||
}
|
||||
|
||||
static inline void pl011_rx_dma_disable(unsigned int base)
|
||||
{
|
||||
unsigned int val = 0;
|
||||
|
||||
read(val, (base + PL011_UARTDMACR));
|
||||
val &= ~PL011_RXDMAEN;
|
||||
write(val, (base +PL011_UARTDMACR));
|
||||
return;
|
||||
}
|
||||
int pl011_initialise(struct pl011_uart *uart);
|
||||
|
||||
#endif /* __PL011__UART__ */
|
||||
|
||||
@@ -1,123 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2009 B Labs Ltd.
|
||||
*/
|
||||
#include <pl011_uart.h>
|
||||
|
||||
/* UART-specific internal error codes */
|
||||
#define PL011_ERROR 1
|
||||
#define PL011_EAGAIN 2
|
||||
|
||||
/* Error status bits in receive status register */
|
||||
#define PL011_FE (1 << 0)
|
||||
#define PL011_PE (1 << 1)
|
||||
#define PL011_BE (1 << 2)
|
||||
#define PL011_OE (1 << 3)
|
||||
|
||||
/* Status bits in flag register */
|
||||
#define PL011_TXFE (1 << 7)
|
||||
#define PL011_RXFF (1 << 6)
|
||||
#define PL011_TXFF (1 << 5)
|
||||
#define PL011_RXFE (1 << 4)
|
||||
#define PL011_BUSY (1 << 3)
|
||||
#define PL011_DCD (1 << 2)
|
||||
#define PL011_DSR (1 << 1)
|
||||
#define PL011_CTS (1 << 0)
|
||||
|
||||
int pl011_tx_char(unsigned int base, char c)
|
||||
{
|
||||
unsigned int val = 0;
|
||||
|
||||
read(val, (base + PL011_UARTFR));
|
||||
if(val & PL011_TXFF) { /* TX FIFO Full */
|
||||
return -PL011_EAGAIN;
|
||||
}
|
||||
write(c, (base + PL011_UARTDR));
|
||||
return 0;
|
||||
}
|
||||
|
||||
int pl011_rx_char(unsigned int base, char * c)
|
||||
{
|
||||
unsigned int data;
|
||||
unsigned int val = 0;
|
||||
|
||||
read(val, (base + PL011_UARTFR));
|
||||
if(val & PL011_RXFE) { /* RX FIFO Empty */
|
||||
return -PL011_EAGAIN;
|
||||
}
|
||||
|
||||
read(data, (base + PL011_UARTDR));
|
||||
*c = (char) data;
|
||||
|
||||
if((data >> 8) & 0xF) { /* There were errors */
|
||||
return -1; /* Signal error in xfer */
|
||||
}
|
||||
return 0; /* No error return */
|
||||
}
|
||||
|
||||
/*
|
||||
* Sets the baud rate in kbps. It is recommended to use
|
||||
* standard rates such as: 1200, 2400, 3600, 4800, 7200,
|
||||
* 9600, 14400, 19200, 28800, 38400, 57600 76800, 115200.
|
||||
*/
|
||||
void pl011_set_baudrate(unsigned int base, unsigned int baud,
|
||||
unsigned int clkrate)
|
||||
{
|
||||
const unsigned int uartclk = 24000000; /* 24Mhz clock fixed on pb926 */
|
||||
unsigned int val = 0, ipart = 0, fpart = 0;
|
||||
|
||||
/* Use default pb926 rate if no rate is supplied */
|
||||
if(clkrate == 0) {
|
||||
clkrate = uartclk;
|
||||
}
|
||||
if(baud > 115200 || baud < 1200) {
|
||||
baud = 38400; /* Default rate. */
|
||||
}
|
||||
/* 24000000 / (38400 * 16) */
|
||||
ipart = 39;
|
||||
|
||||
write(ipart, (base + PL011_UARTIBRD));
|
||||
write(fpart, (base + PL011_UARTFBRD));
|
||||
|
||||
/*
|
||||
* For the IBAUD and FBAUD to update, we need to
|
||||
* write to UARTLCR_H because the 3 registers are
|
||||
* actually part of a single register in hardware
|
||||
* which only updates by a write to UARTLCR_H
|
||||
*/
|
||||
read(val, (base + PL011_UARTLCR_H));
|
||||
write(val, (base + PL011_UARTLCR_H));
|
||||
return;
|
||||
|
||||
}
|
||||
|
||||
/* Masks the irqs given in the flags bitvector. */
|
||||
void pl011_set_irq_mask(unsigned int base, unsigned int flags)
|
||||
{
|
||||
unsigned int val = 0;
|
||||
|
||||
if(flags > 0x3FF) { /* Invalid irqmask bitvector */
|
||||
return;
|
||||
}
|
||||
|
||||
read(val, (base + PL011_UARTIMSC));
|
||||
val |= flags;
|
||||
write(val, (base + PL011_UARTIMSC));
|
||||
return;
|
||||
}
|
||||
|
||||
/* Clears the irqs given in flags from masking */
|
||||
void pl011_clr_irq_mask(unsigned int base, unsigned int flags)
|
||||
{
|
||||
unsigned int val = 0;
|
||||
|
||||
if(flags > 0x3FF) {
|
||||
/* Invalid irqmask bitvector */
|
||||
return;
|
||||
}
|
||||
|
||||
read(val, (base + PL011_UARTIMSC));
|
||||
val &= ~flags;
|
||||
write(val, (base + PL011_UARTIMSC));
|
||||
return;
|
||||
}
|
||||
|
||||
@@ -1,60 +0,0 @@
|
||||
/*
|
||||
* User space uart driver.
|
||||
*
|
||||
* Copyright (C) 2009, B Labs Ltd.
|
||||
*/
|
||||
|
||||
#include <pl011_uart.h>
|
||||
|
||||
/*
|
||||
* Every task who wants to use this uart needs
|
||||
* to initialize an instance of this
|
||||
*/
|
||||
struct pl011_uart uart;
|
||||
|
||||
/*
|
||||
* Initialises the uart class data structures, and the device.
|
||||
* Terminal-like operation is assumed for default settings.
|
||||
*/
|
||||
int pl011_initialise(struct pl011_uart *uart)
|
||||
{
|
||||
uart->frame_errors = 0;
|
||||
uart->parity_errors = 0;
|
||||
uart->break_errors = 0;
|
||||
uart->overrun_errors = 0;
|
||||
|
||||
/* Initialise data register for 8 bit data read/writes */
|
||||
pl011_set_word_width(uart->base, 8);
|
||||
|
||||
/*
|
||||
* Fifos are disabled because by default it is assumed the port
|
||||
* will be used as a user terminal, and in that case the typed
|
||||
* characters will only show up when fifos are flushed, rather than
|
||||
* when each character is typed. We avoid this by not using fifos.
|
||||
*/
|
||||
pl011_disable_fifos(uart->base);
|
||||
|
||||
/* Set default baud rate of 38400 */
|
||||
pl011_set_baudrate(uart->base, 38400, 24000000);
|
||||
|
||||
/* Set default settings of 1 stop bit, no parity, no hw flow ctrl */
|
||||
pl011_set_stopbits(uart->base, 1);
|
||||
pl011_parity_disable(uart->base);
|
||||
|
||||
/* Disable all irqs */
|
||||
pl011_set_irq_mask(uart->base, 0x3FF);
|
||||
|
||||
/* Enable rx, tx, and uart chip */
|
||||
pl011_tx_enable(uart->base);
|
||||
pl011_rx_enable(uart->base);
|
||||
pl011_uart_enable(uart->base);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void platform_init(void)
|
||||
{
|
||||
uart.base = PL011_BASE;
|
||||
pl011_initialise(&uart);
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user