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CLCD added as new capability, code note added yet

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This commit is contained in:
Amit Mahajan
2009-12-04 00:54:23 +05:30
parent fcc1e52bea
commit 3d2b87d488
14 changed files with 604 additions and 5 deletions
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9
conts/libdev/SConscript
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@@ -24,13 +24,18 @@ LIBDEV_UART_PATH = join(PROJROOT, 'conts/libdev/uart')
# Path for timer files
LIBDEV_TIEMR_PATH = join(PROJROOT, 'conts/libdev/timer/sp804')
# Path for clcd files
LIBDEV_CLCD_PATH = join(PROJROOT, 'conts/libdev/clcd/pl110')
e = env.Clone()
e.Append(CPPPATH = [LIBDEV_UART_PATH + '/include', LIBDEV_TIEMR_PATH + '/include'],
e.Append(CPPPATH = [LIBDEV_UART_PATH + '/include', LIBDEV_TIEMR_PATH + '/include',
LIBDEV_CLCD_PATH + '/include',],
CCFLAGS = ['-nostdinc', '-DVARIANT_' + variant.upper(),
'-DPLATFORM_' + platform.upper()])
source = Glob('uart/src' + '/*.c') + \
Glob('timer/sp804/src' + '/*.c')
Glob('timer/sp804/src' + '/*.c') + \
Glob('clcd/pl110/src' + '/*.c')
objects = e.StaticObject(source)
library = e.StaticLibrary('libdev-' + variant, objects)

104
conts/libdev/clcd/pl110/include/pl110_clcd.h Normal file
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@@ -0,0 +1,104 @@
#ifndef __PL110_CLCD_H__
#define __PL110_CLCD_H__
/* Register offsets */
#define PL110_CLCD_TIMING0 0x000 /* Horizontal Axis Panel Control*/
#define PL110_CLCD_TIMING1 0x004 /* Vertical Axis Panel Control */
#define PL110_CLCD_TIMING2 0x008 /* Clock and Polarity Signal Control*/
#define PL110_CLCD_TIMING3 0x00c /* Line End Control */
#define PL110_CLCD_UPBASE 0x010 /* Upper Panel Frame Base Address*/
#define PL110_CLCD_LPBASE 0x014 /* Lower Panel Frame Base Address */
#define PL110_CLCD_IMSC 0x018 /* Interrupt Mast Set Clear */
#define PL110_CLCD_CONTROL 0x01c /* CLCD Control */
#define PL110_CLCD_RIS 0x020 /* Raw Interrupt Status */
#define PL110_CLCD_MIS 0x024 /* Masked Interrupt Status */
#define PL110_CLCD_ICR 0x028 /* Interrupt Clear */
#define PL110_CLCD_UPCURR 0x02c /* Upper Panel Current Address Value */
#define PL110_CLCD_LPCURR 0x030 /* Lower Panel Current Address Value */
//#define PL110_LCD_PALETTE
#define PL110_CLCD_PERIPHID0 0xfe0 /* Peripheral Identification */
#define PL110_CLCD_PERIPHID1 0xfe4 /* Peripheral Identification */
#define PL110_CLCD_PERIPHID2 0xfe8 /* Peripheral Identification */
#define PL110_CLCD_PERIPHID3 0xfec /* Peripheral Identification */
#define PL110_CLCD_PCELLID0 0xff0 /* Peripheral Identification */
#define PL110_CLCD_PCELLID1 0xff4 /* PrimeCell Identification */
#define PL110_CLCD_PCELLID2 0xff8 /* PrimeCell Identification */
#define PL110_CLCD_PCELLID3 0xffc /* PrimeCell Identification */
/* Scan mode */
#define SCAN_VMODE_NONINTERLACED 0 /* non interlaced */
#define SCAN_VMODE_INTERLACED 1 /* interlaced */
#define SCAN_VMODE_DOUBLE 2 /* double scan */
#define SCAN_VMODE_ODD_FLD_FIRST 4 /* interlaced: top line first */
#define SCAN_VMODE_MASK 255
/* Control Register Bits */
#define PL110_CNTL_LCDEN (1 << 0)
#define PL110_CNTL_LCDBPP1 (0 << 1)
#define PL110_CNTL_LCDBPP2 (1 << 1)
#define PL110_CNTL_LCDBPP4 (2 << 1)
#define PL110_CNTL_LCDBPP8 (3 << 1)
#define PL110_CNTL_LCDBPP16 (4 << 1)
#define PL110_CNTL_LCDBPP16_565 (6 << 1)
#define PL110_CNTL_LCDBPP24 (5 << 1)
#define PL110_CNTL_LCDBW (1 << 4)
#define PL110_CNTL_LCDTFT (1 << 5)
#define PL110_CNTL_LCDMONO8 (1 << 6)
#define PL110_CNTL_LCDDUAL (1 << 7)
#define PL110_CNTL_BGR (1 << 8)
#define PL110_CNTL_BEBO (1 << 9)
#define PL110_CNTL_BEPO (1 << 10)
#define PL110_CNTL_LCDPWR (1 << 11)
#define PL110_CNTL_LCDVCOMP(x) ((x) << 12)
#define PL110_CNTL_LDMAFIFOTIME (1 << 15)
#define PL110_CNTL_WATERMARK (1 << 16)
#define PL110_TIM2_CLKSEL (1 << 5)
#define PL110_TIM2_IVS (1 << 11)
#define PL110_TIM2_IHS (1 << 12)
#define PL110_TIM2_IPC (1 << 13)
#define PL110_TIM2_IOE (1 << 14)
#define PL110_TIM2_BCD (1 << 26)
struct videomode {
const char *name; /* optional */
unsigned int refresh; /* optional */
unsigned int xres;
unsigned int yres;
unsigned int pixclock;
unsigned int left_margin;
unsigned int right_margin;
unsigned int upper_margin;
unsigned int lower_margin;
unsigned int hsync_len;
unsigned int vsync_len;
unsigned int sync;
unsigned int vmode;
unsigned int flag;
};
struct pl110_clcd_panel {
struct videomode mode;
signed short width; /* width in mm */
signed short height; /* height in mm */
unsigned int tim2;
unsigned int tim3;
unsigned int cntl;
unsigned int bpp:8,
fixedtimings:1,
grayscale:1;
unsigned int connector;
};
struct pl110_clcd {
unsigned int virt_base;
struct pl110_clcd_panel *panel;
char *frame_buffer;
};
void pl110_initialise(struct pl110_clcd *clcd, char *buf);
#endif /* __PL110_CLCD_H__ */

68
conts/libdev/clcd/pl110/src/pl110_clcd.c Normal file
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@@ -0,0 +1,68 @@
#include <pl110_clcd.h>
#define read(a) *((volatile unsigned int *)(a))
#define write(v, a) (*((volatile unsigned int *)(a)) = v)
#define setbit(bit, a) write(read(a) | bit, a)
#define clrbit(bit, a) write(read(a) & ~bit, a)
/*
* Default panel, we will use this for now
* Seems like qemu has support for this
*/
static struct pl110_clcd_panel vga = {
.mode = {
.name = "VGA",
.refresh = 60,
.xres = 640,
.yres = 480,
.pixclock = 39721,
.left_margin = 40,
.right_margin = 24,
.upper_margin = 32,
.lower_margin = 11,
.hsync_len = 96,
.vsync_len = 2,
.sync = 0,
.vmode = SCAN_VMODE_NONINTERLACED,
},
.width = -1,
.height = -1,
.tim2 = PL110_TIM2_BCD | PL110_TIM2_IPC,
.cntl = PL110_CNTL_LCDTFT | PL110_CNTL_LCDVCOMP(1),
.bpp = 16,
};
static void pl110_clcd_set_uppanel_fb(unsigned int clcd_base,
unsigned int fb_base)
{
write(fb_base, (clcd_base + PL110_CLCD_UPBASE));
}
#if 0
static void pl110_clcd_set_lwrpanel_fb(unsigned int clcd_base, unsigned int fb_base)
{
write(fb_base, (clcd_base +PL110_CLCD_LPBASE));
}
static unsigned int pl110_clcd_get_uppanel_fb(unsigned int clcd_base)
{
return read((clcd_base +PL110_CLCD_UPBASE));
}
static unsigned int pl110_clcd_get_lwrpanel_fb(unsigned int clcd_base)
{
return read((clcd_base +PL110_CLCD_LPBASE));
}
#endif
void pl110_initialise(struct pl110_clcd *clcd, char *buf)
{
clcd->panel = &vga;
clcd->frame_buffer = buf;
pl110_clcd_set_uppanel_fb(clcd->virt_base, (unsigned int)(buf));
}