Kernel updates since December 2009

conts/libdev/timer/omap/SConscript

@@ -0,0 +1,15 @@
+Import('env', 'platform')
+
+#Platforms using omap_uart
+plat_list = 'beagle'
+
+# The set of source files associated with this SConscript file.
+src_local = []
+
+#for plat_supported in plat_list:
+#if plat_supported == platform:
+if plat_list == platform:
+    src_local += ['timer.c']
+
+obj = env.StaticObject(src_local)
+Return('obj')

conts/libdev/timer/omap/timer.c

@@ -0,0 +1,97 @@
+/*
+ * omap GP timer driver honoring generic
+ * timer library API
+ *
+ * Copyright (C) 2010 B Labs Ltd.
+ *
+ * Author: Bahadir Balban
+ */
+
+#include <libdev/io.h>
+#include <l4lib/types.h>
+#include "timer.h"
+
+#define OMAP_TIMER_MAT_IT_FLAG  (1 << 0)
+#define OMAP_TIMER_OVR_IT_FLAG  (1 << 1)
+#define OMAP_TIMER_TCAR_IT_FLAG (1 << 2)
+u32 timer_periodic_intr_status(unsigned long timer_base)
+{
+	volatile u32 reg = read(timer_base + OMAP_TIMER_TISR);
+	return (reg & OMAP_TIMER_OVR_IT_FLAG);
+}
+
+#define OMAP_TIMER_SOFT_RESET	(1 << 1)
+void timer_reset(unsigned long timer_base)
+{
+	/* Reset Timer */
+	write(OMAP_TIMER_SOFT_RESET, timer_base + OMAP_TIMER_TIOCP);
+
+	/* Wait for reset completion */
+	while (!read(timer_base + OMAP_TIMER_TSTAT));
+}
+
+void timer_load(unsigned long timer_base, u32 value)
+{
+	write(value, timer_base + OMAP_TIMER_TLDR);
+	write(value, timer_base + OMAP_TIMER_TCRR);
+}
+
+u32 timer_read(unsigned long timer_base)
+{
+	return read(timer_base + OMAP_TIMER_TCRR);
+}
+
+#define OMAP_TIMER_START	(1 << 0)
+void timer_start(unsigned long timer_base)
+{
+	volatile u32 reg = read(timer_base + OMAP_TIMER_TCLR);
+	reg |= OMAP_TIMER_START;
+	write(reg, timer_base + OMAP_TIMER_TCLR);
+}
+
+void timer_stop(unsigned long timer_base)
+{
+	volatile u32 reg = read(timer_base + OMAP_TIMER_TCLR);
+	reg &= (~OMAP_TIMER_START);
+	write(reg, timer_base + OMAP_TIMER_TCLR);
+}
+
+void timer_init_periodic(unsigned long timer_base)
+{
+	volatile u32 reg;
+
+	/* Reset the timer */
+	timer_reset(timer_base);
+
+	/* Set timer to autoreload mode */
+	reg = read(timer_base + OMAP_TIMER_TCLR);
+	reg |= (1 << OMAP_TIMER_MODE_AUTORELAOD);
+	write(reg, timer_base + OMAP_TIMER_TCLR);
+
+	/*
+	* Beagle Board RevC manual:
+	* overflow period = (0xffffffff - TLDR + 1)*PS*(1/TIMER_FCLK)
+	* where,
+	* PS: Prescaler divisor (we are not using this)
+	*
+	* Beagle board manual says, 26MHz oscillator present on board.
+	* U-Boot divides the sys_clock by 2 if sys_clk is >19MHz,
+	* so,we have sys_clk frequency = 13MHz
+	*
+	* TIMER_FCLK = 13MHz
+	* So, for 1ms period, TLDR = 0xffffcd38
+	*
+	*/
+	timer_load(timer_base, 0xffffcd38);
+
+	/* Clear pending Interrupts, if any */
+	write(7, timer_base + OMAP_TIMER_TISR);
+
+	/* Enable inteerupts */
+	write((1 << OMAP_TIMER_INTR_OVERFLOW), timer_base + OMAP_TIMER_TIER);
+}
+
+void timer_init(unsigned long timer_base)
+{
+	timer_init_periodic(timer_base);
+}

conts/libdev/timer/omap/timer.h

@@ -0,0 +1,51 @@
+/*
+ * OMAP GP Timer offsets
+ *
+ * Copyright (C) 2007 Bahadir Balban
+ *
+ */
+#ifndef __OMAP_GPTIMER_H__
+#define __OMAP_GPTIMER_H__
+
+/* Register offsets */
+#define OMAP_TIMER_TIOCP		0x10
+#define OMAP_TIMER_TSTAT		0x14
+#define OMAP_TIMER_TISR                 0x18
+#define OMAP_TIMER_TIER			0x1C
+#define OMAP_TIMER_TCLR			0x24
+#define OMAP_TIMER_TCRR			0x28
+#define OMAP_TIMER_TLDR                 0x2C
+#define OMAP_TIMER_TPIR			0x48
+#define OMAP_TIMER_TNIR			0x4C
+#define OMAP_TIMER_TCVR			0x50
+
+/* Enable/Disable IRQ */
+#define OMAP_TIMER_IRQENABLE		1
+#define OMAP_TIMER_IRQDISABLE		0
+
+/* Timer modes supported */
+#define OMAP_TIMER_MODE_AUTORELAOD	1
+#define OMAP_TIMER_MODE_COMPARE		6
+#define OMAP_TIMER_MODE_CAPTURE		13
+
+/* Interrupt types */
+#define OMAP_TIMER_INTR_MATCH           0x0
+#define OMAP_TIMER_INTR_OVERFLOW        0x1
+#define OMAP_TIMER_INTR_CAPTURE         0x2
+
+/* Clock source for timer */
+#define OMAP_TIMER_CLKSRC_SYS_CLK	0x1
+#define OMAP_TIMER_CLKSRC_32KHZ_CLK	0x0
+
+u32 timer_periodic_intr_status(unsigned long timer_base);
+void timer_start(unsigned long base);
+void timer_set_mode(unsigned long base, int mode);
+void timer_reset(unsigned long timer_base);
+void timer_load(unsigned long timer_base, u32 value);
+u32 timer_read(unsigned long timer_base);
+void timer_start(unsigned long timer_base);
+void timer_stop(unsigned long timer_base);
+void timer_init_periodic(unsigned long timer_base);
+void timer_init(unsigned long timer_base);
+
+#endif /* __OMAP_GPTIMER_H__*/

conts/libdev/timer/sp804/SConscript

@@ -0,0 +1,14 @@
+Import('env', 'platform')
+
+#Platforms using sp804
+plat_list = ('eb', 'pba8', 'pba9', 'pb11mpcore', 'pb926')
+
+# The set of source files associated with this SConscript file.
+src_local = []
+
+for plat_supported in plat_list:
+    if plat_supported == platform:
+        src_local += Glob('*.c')
+
+obj = env.StaticObject(src_local)
+Return('obj')

conts/libdev/timer/sp804/timer.c

@@ -0,0 +1,65 @@
+/*
+ * SP804 primecell driver honoring generic
+ * timer library API
+ *
+ * Copyright (C) 2010 B Labs Ltd.
+ *
+ * Author: Bahadir Balban
+ */
+#include <l4lib/types.h>
+#include "timer.h"
+
+/* Enable timer with its current configuration */
+void timer_start(unsigned long timer_base)
+{
+	volatile u32 reg = read(timer_base + SP804_CTRL);
+
+	reg |= SP804_ENABLE;
+
+	write(reg, timer_base + SP804_CTRL);
+
+}
+
+/* Load the timer with ticks value */
+void timer_load(u32 loadval, unsigned long timer_base)
+{
+	write(loadval, timer_base + SP804_LOAD);
+}
+
+u32 timer_read(unsigned long timer_base)
+{
+	return read(timer_base + SP804_VALUE);
+}
+
+void timer_stop(unsigned long timer_base)
+{
+	write(0, timer_base + SP804_CTRL);
+}
+
+void timer_init_periodic(unsigned long timer_base)
+{
+	volatile u32 reg = read(timer_base + SP804_CTRL);
+
+	reg |= SP804_PERIODIC | SP804_32BIT | SP804_IRQEN;
+
+	write(reg, timer_base + SP804_CTRL);
+
+	/* 1 tick per usec, 1 irq per msec */
+	timer_load(1000, timer_base);
+}
+
+void timer_init_oneshot(unsigned long timer_base)
+{
+	volatile u32 reg = read(timer_base + SP804_CTRL);
+
+	/* One shot, 32 bits, no irqs */
+	reg |= SP804_32BIT | SP804_ONESHOT;
+
+	write(reg, timer_base + SP804_CTRL);
+}
+
+void timer_init(unsigned long timer_base)
+{
+	timer_stop(timer_base);
+	timer_init_periodic(timer_base);
+}

conts/libdev/timer/sp804/timer.h

@@ -0,0 +1,63 @@
+/*
+ * SP804 Primecell Timer offsets
+ *
+ * Copyright (C) 2007 Bahadir Balban
+ *
+ */
+#ifndef __SP804_TIMER_H__
+#define __SP804_TIMER_H__
+
+#include <libdev/io.h>
+
+/* Register offsets */
+#define SP804_LOAD			0x0
+#define SP804_VALUE			0x4
+#define SP804_CTRL			0x8
+#define SP804_INTCLR			0xC
+#define SP804_RIS			0x10
+#define SP804_MIS			0x14
+#define SP804_BGLOAD			0x18
+
+#define SP804_ENABLE			(1 << 7)
+#define SP804_PERIODIC			(1 << 6)
+#define SP804_IRQEN			(1 << 5)
+#define SP804_32BIT			(1 << 1)
+#define SP804_ONESHOT			(1 << 0)
+
+/* Timer prescaling */
+#define SP804_SCALE_SHIFT		2
+#define SP804_SCALE_DIV16		1
+#define SP804_SCALE_DIV256		2
+
+/* Wrapping = 0, Oneshot = 1 */
+#define SP804_ONESHOT			(1 << 0)
+
+static inline __attribute__ ((always_inline))
+void sp804_load(unsigned long timer_base, u32 val)
+{
+	write(val, timer_base + SP804_LOAD);
+}
+
+static inline __attribute__ ((always_inline))
+void sp804_irq_clear(unsigned long timer_base)
+{
+	write(1, timer_base + SP804_INTCLR);
+}
+
+static inline __attribute__ ((always_inline))
+void sp804_enable(unsigned long timer_base)
+{
+	volatile u32 reg = read(timer_base + SP804_CTRL);
+
+	write(reg | SP804_ENABLE, timer_base + SP804_CTRL);
+}
+
+void timer_start(unsigned long timer_base);
+void timer_load(u32 loadval, unsigned long timer_base);
+u32 timer_read(unsigned long timer_base);
+void timer_stop(unsigned long timer_base);
+void timer_init_periodic(unsigned long timer_base);
+void timer_init_oneshot(unsigned long timer_base);
+void timer_init(unsigned long timer_base);
+
+#endif /* __SP804_TIMER_H__ */