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Kernel updates since December 2009

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This commit is contained in:
Bahadir Balban
2010-03-25 01:12:40 +02:00
parent 16818191b3
commit 74b5963fcb
487 changed files with 22477 additions and 3857 deletions
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17
include/l4/api/cache.h Normal file
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@@ -0,0 +1,17 @@
/*
* Generic macros for cache operations
*
* Copyright (C) 2009 B Labs Ltd.
*/
#ifndef __CACHE_CONTROL_H__
#define __CACHE_CONTROL_H__
#include INC_GLUE(cache.h)
#define L4_INVALIDATE_ICACHE ARCH_INVALIDATE_ICACHE
#define L4_INVALIDATE_DCACHE ARCH_INVALIDATE_DCACHE
#define L4_CLEAN_DCACHE ARCH_CLEAN_DCACHE
#define L4_CLEAN_INVALIDATE_DCACHE ARCH_CLEAN_INVALIDATE_DCACHE
#define L4_INVALIDATE_TLB ARCH_INVALIDATE_TLB
#endif /* __CACHE_CONTROL_H__ */

2
include/l4/api/errno.h
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@@ -142,5 +142,7 @@
#define ENOUTCB 135 /* Task has no utcb set up */
#define ENOMAP 136 /* The memory area has unmapped regions */
#define ENOIRQ 137 /* Irq cannot be registered */
#define EABORT 138 /* Abort cannot be handled */
#define ENOCHILD 139 /* Task is not paged by caller */
#endif /* __ERRNO_H__ */

3
include/l4/api/kip.h
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@@ -61,7 +61,8 @@ struct kip {
u32 schedule;
u32 getid;
u32 mutex_control;
u32 cache_control;
u32 arch_syscall0;
u32 arch_syscall1;
u32 arch_syscall2;

5
include/l4/api/syscall.h
View File

@@ -26,7 +26,8 @@
#define sys_container_control_offset 0x2C
#define sys_time_offset 0x30
#define sys_mutex_control_offset 0x34
#define syscalls_end_offset sys_mutex_control_offset
#define sys_cache_control_offset 0x38
#define syscalls_end_offset sys_cache_control_offset
#define SYSCALLS_TOTAL ((syscalls_end_offset >> 2) + 1)
void print_syscall_context(struct ktcb *t);
@@ -46,5 +47,7 @@ int sys_capability_control(unsigned int req, unsigned int flags, void *addr);
int sys_container_control(unsigned int req, unsigned int flags, void *addr);
int sys_time(struct timeval *tv, int set);
int sys_mutex_control(unsigned long mutex_address, int mutex_op);
int sys_cache_control(unsigned long start, unsigned long end,
unsigned int flags);
#endif /* __SYSCALL_H__ */

14
include/l4/api/thread.h
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@@ -9,15 +9,17 @@
#define THREAD_RECYCLE 0x40000000
#define THREAD_WAIT 0x50000000
#define THREAD_CREATE_MASK 0x0FF00000
#define THREAD_SHARE_MASK 0x00F00000
#define THREAD_SPACE_MASK 0x0F000000
#define THREAD_CREATE_MASK (THREAD_SHARE_MASK | THREAD_SPACE_MASK)
#define TC_SHARE_CAPS 0x00100000 /* Share all thread capabilities */
#define TC_SHARE_UTCB 0x00200000 /* Share utcb location (same space */
#define TC_SHARE_GROUP 0x00400000 /* Share thread group id */
#define TC_SHARE_SPACE 0x00800000 /* New thread, use given space */
#define TC_COPY_SPACE 0x01000000 /* New thread, copy given space */
#define TC_NEW_SPACE 0x02000000 /* New thread, new space */
#define TC_SHARE_PAGER 0x04000000 /* New thread, shared pager */
#define TC_AS_PAGER 0x08000000 /* Set new thread as child */
#define TC_SHARE_SPACE 0x01000000 /* New thread, use given space */
#define TC_COPY_SPACE 0x02000000 /* New thread, copy given space */
#define TC_NEW_SPACE 0x04000000 /* New thread, new space */
/* #define THREAD_USER_MASK 0x000F0000 Reserved for userspace */
#define THREAD_EXIT_MASK 0x0000FFFF /* Thread exit code */
#endif /* __API_THREAD_H__ */

16
include/l4/arch/arm/asm-macros.S Normal file
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@@ -0,0 +1,16 @@
/*
* Copyright (C) 2010 B Labs Ltd.
*
* Common assembler macros
*
* Prem Mallappa, Bahadir Balban
*/
#ifndef __ASM_MACROS_S__
#define __ASM_MACROS_S__
.macro get_cpuid cpuid
mrc p15, 0, \cpuid, c0, c0, 5 @ Read MPIDR
and \cpuid, \cpuid, #0xF @ Mask lower cpuid bits
.endm
#endif /* __ASM_MACROS_S__ */

6
include/l4/arch/arm/asm.h
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@@ -20,9 +20,11 @@
#define ARM_NOIRQ_FIQ 0xD1
#define ARM_NOIRQ_USR 0xD0
#define ARM_NOIRQ_SYS 0xDF
/* For enabling *clear* these bits */
#define ARM_IRQ_BIT 0x80
#define ARM_FIQ_BIT 0x40
#define ARM_IRQ_BIT 0x080
#define ARM_FIQ_BIT 0x040
#define ARM_A_BIT 0x100 /* Asynchronous abort */
/* Notes about ARM instructions:
*

100
include/l4/arch/arm/exception.h
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@@ -1,78 +1,57 @@
/*
* Definitions for exception support on ARM
* Common definitions for exceptions
* across ARM sub-architectures.
*
* Copyright (C) 2007 Bahadir Balban
* Copyright (C) 2010 B Labs Ltd.
*/
#ifndef __ARCH_EXCEPTIONS_H__
#define __ARCH_EXCEPTIONS_H__
#ifndef __EXCEPTION_H__
#define __EXCEPTION_H__
#include INC_SUBARCH(exception.h)
#include INC_ARCH(asm.h)
static inline void enable_irqs()
{
__asm__ __volatile__(
"mrs r0, cpsr_fc\n"
"bic r0, r0, #0x80\n" /* ARM_IRQ_BIT */
"msr cpsr_fc, r0\n"
);
}
static inline void disable_irqs()
{
__asm__ __volatile__(
"mrs r0, cpsr_fc\n"
"orr r0, r0, #0x80\n" /* ARM_IRQ_BIT */
"msr cpsr_fc, r0\n"
);
}
int irqs_enabled();
/* Disable the irqs unconditionally, but also keep the previous state such that
* if it was already disabled before the call, the restore call would retain
* this state. */
void irq_local_disable_save(unsigned long *state);
#if 0
{
unsigned long temp;
__asm__ __volatile__ (
"mrs %0, cpsr_fc\n"
"orr %2, %0, #0x80\n"
"msr cpsr_fc, %2\n"
: "=r" (*state)
: "r" (*state),"r" (temp)
);
}
/* Abort debugging conditions */
//#define DEBUG_ABORTS
#if defined (DEBUG_ABORTS)
#define dbg_abort(...) printk(__VA_ARGS__)
#else
#define dbg_abort(...)
#endif
/* Simply change it back to original state supplied in @flags. This might enable
* or retain disabled state of the irqs for example. Useful for nested calls. */
void irq_local_restore(unsigned long state);
/* Codezero-specific abort type */
#define ABORT_TYPE_PREFETCH 1
#define ABORT_TYPE_DATA 0
static inline void irq_local_enable()
{
enable_irqs();
}
/* If abort is handled and resolved in check_aborts */
#define ABORT_HANDLED 1
/* Codezero makes use of bit 8 (Always Zero) of FSR to define which type of abort */
#define set_abort_type(fsr, x) { fsr &= ~(1 << 8); fsr |= ((x & 1) << 8); }
#define is_prefetch_abort(fsr) ((fsr >> 8) & 0x1)
#define is_data_abort(fsr) (!is_prefetch_abort(fsr))
/* Kernel's data about the fault */
typedef struct fault_kdata {
u32 faulty_pc; /* In DABT: Aborting PC, In PABT: Same as FAR */
u32 fsr; /* In DABT: DFSR, In PABT: IFSR */
u32 far; /* In DABT: DFAR, in PABT: IFAR */
pte_t pte; /* Faulty page table entry */
} __attribute__ ((__packed__)) fault_kdata_t;
static inline void irq_local_disable()
{
disable_irqs();
}
/* This is filled on entry to irq handler, only if a process was interrupted.*/
extern unsigned int preempted_psr;
/*
* FIXME: TASK_IN_KERNEL works for non-current tasks, in_kernel() works for current task?
* in_kernel() is for irq, since normally in process context you know if you are in kernel or not :-)
*/
/* Implementing these as functions cause circular include dependency for tcb.h */
#define TASK_IN_KERNEL(tcb) (((tcb)->context.spsr & ARM_MODE_MASK) == ARM_MODE_SVC)
#define TASK_IN_USER(tcb) (!TASK_IN_KERNEL(tcb))
static inline int is_user_mode(u32 spsr)
{
return ((spsr & ARM_MODE_MASK) == ARM_MODE_USR);
}
static inline int in_kernel()
{
return (((preempted_psr & ARM_MODE_MASK) == ARM_MODE_SVC)) ? 1 : 0;
@@ -86,4 +65,9 @@ static inline int in_user()
int pager_pagein_request(unsigned long vaddr, unsigned long size,
unsigned int flags);
#endif
int fault_ipc_to_pager(u32 faulty_pc, u32 fsr, u32 far, u32 ipc_tag);
int is_kernel_abort(u32 faulted_pc, u32 fsr, u32 far, u32 spsr);
int check_abort_type(u32 faulted_pc, u32 fsr, u32 far, u32 spsr);
#endif /* __EXCEPTION_H__ */

17
include/l4/arch/arm/io.h
View File

@@ -6,7 +6,20 @@
* Copyright (C) 2007 Bahadir Balban
*/
#define read(val, address) val = *((volatile unsigned int *) address)
#define write(val, address) *((volatile unsigned int *) address) = val
#if defined (__KERNEL__)
#include INC_GLUE(memlayout.h)
#define read(address) *((volatile unsigned int *) (address))
#define write(val, address) *((volatile unsigned int *) (address)) = val
#endif /* ends __KERNEL__ */
/*
* Generic uart virtual address until a file-based console access
* is available for userspace
*/
#define USERSPACE_CONSOLE_VBASE 0xF9800000
#endif /* __ARM_IO_H__ */

29
include/l4/arch/arm/irq.h Normal file
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@@ -0,0 +1,29 @@
#ifndef __ARM_IRQ_H__
#define __ARM_IRQ_H__
#include INC_SUBARCH(irq.h)
void irq_local_restore(unsigned long state);
void irq_local_disable_save(unsigned long *state);
int irqs_enabled();
static inline void irq_local_enable()
{
enable_irqs();
}
static inline void irq_local_disable()
{
disable_irqs();
}
/*
* Destructive atomic-read.
*
* Write 0 to byte at @location as its contents are read back.
*/
char l4_atomic_dest_readb(void *location);
#endif /* __ARM_IRQ_H__ */

8
include/l4/arch/arm/linker.h
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@@ -16,9 +16,15 @@ extern unsigned long arm_high_vector[];
extern unsigned long _end_vectors[];
extern unsigned long _start_kip[];
extern unsigned long _end_kip[];
extern unsigned long _start_syscalls[];
extern unsigned long _end_syscalls[];
extern unsigned long _start_init[];
extern unsigned long _end_init[];
extern unsigned long _bootstack[];
extern unsigned long _start_bootstack[];
extern unsigned long _end_bootstack[];
extern unsigned long _start_init_pgd[];
extern unsigned long _end_init_pgd[];
extern unsigned long _end_kernel[];
extern unsigned long _end[];

89
include/l4/arch/arm/linker.lds.in Normal file
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@@ -0,0 +1,89 @@
/*
* Simple linker script
*
* Copyright (C) 2007 Bahadir Balban
*/
#if !defined (CONFIG_NCPU)
#define CONFIG_NCPU 1
#endif
phys_ram_start = PLATFORM_PHYS_MEM_START;
kernel_offset = KERNEL_AREA_START - phys_ram_start;
kernel_physical = 0x8000 + phys_ram_start;
kernel_virtual = kernel_physical + kernel_offset;
/* A temporary boot stack is used before a proper kernel stack is set up */
_bootstack_physical = _end_bootstack - kernel_offset;
/* The symbols are linked at virtual addresses. So is _start.
* We must set the entry point to a physical address, so that
* when the image is loaded, it doesn't jump to a non existing
* virtual address.
*/
ENTRY(kernel_physical)
SECTIONS
{
. = kernel_virtual;
_start_kernel = .;
.text : AT (ADDR(.text) - kernel_offset)
{
_start_text = .;
/* Make sure head.S comes first */
/* *head.o(.text) This only works when given its full path. Bad limitation. */
*(.text.head)
*(.text)
_end_text = .;
}
. = ALIGN(4);
/* rodata is needed else your strings will link at physical! */
.rodata : AT (ADDR(.rodata) - kernel_offset) { *(.rodata) }
.rodata1 : AT (ADDR(.rodata1) - kernel_offset) { *(.rodata1) }
.data : AT (ADDR(.data) - kernel_offset)
{
_start_data = .;
*(.data)
/* Best alignment because we need 4 x (4K) and 1 x 16K block */
. = ALIGN(16K);
_start_vectors = .;
*(.data.vectors)
_end_vectors = .;
. = ALIGN(4K);
_start_kip = .;
*(.data.kip)
. = ALIGN(4K);
_end_kip = .;
_start_syscalls = .;
*(.data.syscalls)
. = ALIGN(4K);
_end_syscalls = .;
_start_init_pgd = .;
*(.data.pgd);
_end_init_pgd = .;
_start_bootstack = .;
. = ALIGN(4K);
. += PAGE_SIZE * CONFIG_NCPU;
_end_bootstack = .;
_end_data = .;
}
.bss : AT (ADDR(.bss) - kernel_offset)
{
*(.bss)
}
. = ALIGN(4K);
. += PAGE_SIZE * 2; /* This is required as the link counter does not seem
* to increment for the bss section
* TODO: Change this with PAGE_SIZE */
/* Below part is to be discarded after boot */
_start_init = .;
.init : AT (ADDR(.init) - kernel_offset)
{
*(.init.task.pgd) /* Non-global task table on split tables, otherwise nil */
*(.init.bootmem)
*(.init.data)
}
_end_init = .;
_end_kernel = .;
_end = .;
}

7
include/l4/arch/arm/mutex.h
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@@ -1,15 +1,16 @@
#ifndef __ARCH_MUTEX_H__
#define __ARCH_MUTEX_H__
/*
* ARM specific low-level mutex interfaces
*
* Copyright (C) 2007 Bahadir Balban
*/
#ifndef __ARCH_MUTEX_H__
#define __ARCH_MUTEX_H__
/* TODO: The return types could be improved for debug checking */
void __spin_lock(unsigned int *s);
void __spin_unlock(unsigned int *s);
unsigned int __mutex_lock(unsigned int *m);
void __mutex_unlock(unsigned int *m);
#endif
#endif /* __ARCH_MUTEX_H__ */

34
include/l4/arch/arm/scu.h Normal file
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@@ -0,0 +1,34 @@
/*
* SCU registers
*
* Copyright (C) 2010 B Labs Ltd.
*
* Author: Prem Mallappa
*/
#ifndef __SCU_H__
#define __SCU_H__
/* Following defines may well go into realview/scu.h */
#define SCU_CTRL_REG 0x00 /* Control Register */
#define SCU_CFG_REG 0x04 /* Configuration Register */
#define SCU_CPU_PWR_REG 0x08 /* SCU CPU Power state register */
#define SCU_INV_ALL_S 0x0C /* SCU Invalidate all Secure Registers */
#define SCU_ACCESS_REG_S 0x50 /* SCU Access Control Secure */
#define SCU_ACCESS_REG_NS 0x54 /* SCU Access Control Non-Secure */
/* The contents of CONTROL AND CONFIG are Implementation Defined. so they may go into platform specific scu.h */
#define SCU_CTRL_EN (1 << 0)
#define SCU_CTRL_ADDR_FLTR_EN (1 << 1)
#define SCU_CTRL_PARITY_ON (1 << 2)
#define SCU_CTRL_STBY_EN (1 << 5) /* SCU StandBy Enable */
#define SCU_CTRL_GIC_STBY_EN (1 << 6) /* GIC Standby enable */
/* Config register */
#define SCU_CFG_SMP_MASK 0x000000f0
#define SCU_CFG_TAG_RAM_MASK 0x0000ff00
#define SCU_CFG_NCPU_MASK 0x7
#define SCU_CFG_SMP_NCPU_SHIFT 4
#endif /* __SCU_H__ */

0
include/l4/arch/arm/v7/mutex.h → include/l4/arch/arm/v5/cache.h
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24
include/l4/arch/arm/v5/cpu.h Normal file
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@@ -0,0 +1,24 @@
/*
* Cpu specific features
* defined upon the base architecture.
*
* Copyright (C) 2010 B Labs Ltd.
* Written by Bahadir Balban
*/
#ifndef __V5_CPU_H__
#define __V5_CPU_H__
#include INC_SUBARCH(mmu_ops.h)
static inline void cpu_startup(void)
{
}
static inline int smp_get_cpuid()
{
return 0;
}
#endif /* __V5_CPU_H__ */

0
include/l4/arch/arm/v5/debug.h Normal file
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33
include/l4/arch/arm/v5/exception.h Normal file
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@@ -0,0 +1,33 @@
/*
* Definitions for exception support on ARMv5
*
* Copyright (C) 2007 Bahadir Balban
*/
#ifndef __ARCH_V5_EXCEPTION_H__
#define __ARCH_V5_EXCEPTION_H__
#include INC_ARCH(asm.h)
/*
* v5 Architecture-defined data abort values for FSR ordered
* in highest to lowest priority.
*/
#define DABT_TERMINAL 0x2
#define DABT_VECTOR 0x0 /* Obsolete */
#define DABT_ALIGN 0x1
#define DABT_EXT_XLATE_LEVEL1 0xC
#define DABT_EXT_XLATE_LEVEL2 0xE
#define DABT_XLATE_SECT 0x5
#define DABT_XLATE_PAGE 0x7
#define DABT_DOMAIN_SECT 0x9
#define DABT_DOMAIN_PAGE 0xB
#define DABT_PERM_SECT 0xD
#define DABT_PERM_PAGE 0xF
#define DABT_EXT_LFETCH_SECT 0x4
#define DABT_EXT_LFETCH_PAGE 0x6
#define DABT_EXT_NON_LFETCH_SECT 0x8
#define DABT_EXT_NON_LFETCH_PAGE 0xA
#define FSR_FS_MASK 0xF
#endif /* __ARCH_V5_EXCEPTION_H__ */

29
include/l4/arch/arm/v5/irq.h
View File

@@ -1,11 +1,28 @@
#ifndef __ARM_V5_IRQ_H__
#define __ARM_V5_IRQ_H__
/*
* Destructive atomic-read.
*
* Write 0 to byte at @location as its contents are read back.
*/
char l4_atomic_dest_readb(void *location);
static inline void enable_irqs()
{
__asm__ __volatile__(
"mrs r0, cpsr_fc\n"
"bic r0, r0, #0x80\n" /* ARM_IRQ_BIT */
"msr cpsr_fc, r0\n"
);
}
static inline void disable_irqs()
{
__asm__ __volatile__(
"mrs r0, cpsr_fc\n"
"orr r0, r0, #0x80\n" /* ARM_IRQ_BIT */
"msr cpsr_fc, r0\n"
);
}
/* Disable the irqs unconditionally, but also keep the previous state such that
* if it was already disabled before the call, the restore call would retain
* this state. */
void irq_local_disable_save(unsigned long *state);
void irq_local_restore(unsigned long state);
#endif

158
include/l4/arch/arm/v5/mm.h
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@@ -9,53 +9,65 @@
/* ARM specific definitions */
#define VIRT_MEM_START 0
#define VIRT_MEM_END 0xFFFFFFFF
#define ARM_SECTION_SIZE SZ_1MB
#define ARM_SECTION_MASK (ARM_SECTION_SIZE - 1)
#define ARM_SECTION_BITS 20
#define SECTION_SIZE SZ_1MB
#define SECTION_MASK (SECTION_SIZE - 1)
#define SECTION_ALIGN_MASK (~SECTION_MASK)
#define SECTION_BITS 20
#define ARM_PAGE_SIZE SZ_4K
#define ARM_PAGE_MASK 0xFFF
#define ARM_PAGE_BITS 12
#define PGD_SIZE SZ_4K * 4
#define PGD_ENTRY_TOTAL SZ_4K
#define PGD_TYPE_MASK 0x3
#define PGD_COARSE_ALIGN_MASK 0xFFFFFC00
#define PGD_SECTION_ALIGN_MASK 0xFFF00000
#define PGD_FINE_ALIGN_MASK 0xFFFFF000
#define PGD_TYPE_FAULT 0
#define PGD_TYPE_COARSE 1
#define PGD_TYPE_SECTION 2
#define PGD_TYPE_FINE 3
#define PMD_TYPE_MASK 0x3
#define PMD_TYPE_FAULT 0
#define PMD_TYPE_LARGE 1
#define PMD_TYPE_SMALL 2
#define PMD_TYPE_TINY 3
/* Permission field offsets */
#define SECTION_AP0 10
#define PMD_SIZE SZ_1K
#define PMD_ENTRY_TOTAL 256
#define PMD_MAP_SIZE SZ_1MB
#define PMD_ALIGN_MASK (~(PMD_SIZE - 1))
#define PMD_TYPE_MASK 0x3
#define PMD_TYPE_FAULT 0
#define PMD_TYPE_PMD 1
#define PMD_TYPE_SECTION 2
/* We need this as printascii.S is including this file */
#define PTE_TYPE_MASK 0x3
#define PTE_TYPE_FAULT 0
#define PTE_TYPE_LARGE 1
#define PTE_TYPE_SMALL 2
#define PTE_TYPE_TINY 3
/* Permission field offsets */
#define SECTION_AP0 10
/*
* These are indices into arrays with pgd_t or pmd_t sized elements,
* therefore the index must be divided by appropriate element size
*/
#define PGD_INDEX(x) (((((unsigned long)(x)) >> 18) \
& 0x3FFC) / sizeof(pmd_t))
/*
* Strip out the page offset in this
* megabyte from a total of 256 pages.
*/
#define PMD_INDEX(x) (((((unsigned long)(x)) >> 10) \
& 0x3FC) / sizeof (pte_t))
/* We need this as print-early.S is including this file */
#ifndef __ASSEMBLY__
/* Type-checkable page table elements */
typedef u32 pgd_t;
typedef u32 pmd_t;
typedef u32 pte_t;
/* Page global directory made up of pgd_t entries */
typedef struct pgd_table {
pgd_t entry[PGD_ENTRY_TOTAL];
pmd_t entry[PGD_ENTRY_TOTAL];
} pgd_table_t;
/* Page middle directory made up of pmd_t entries */
typedef struct pmd_table {
pmd_t entry[PMD_ENTRY_TOTAL];
pte_t entry[PMD_ENTRY_TOTAL];
} pmd_table_t;
/* Applies for both small and large pages */
@@ -79,86 +91,38 @@ typedef struct pmd_table {
#define unbufferable 0
/* Helper macros for common cases */
#define __MAP_USR_RW_FLAGS (cacheable | bufferable | (SVC_RW_USR_RW << PAGE_AP0) \
| (SVC_RW_USR_RW << PAGE_AP1) | (SVC_RW_USR_RW << PAGE_AP2) \
| (SVC_RW_USR_RW << PAGE_AP3))
#define __MAP_USR_RO_FLAGS (cacheable | bufferable | (SVC_RW_USR_RO << PAGE_AP0) \
| (SVC_RW_USR_RO << PAGE_AP1) | (SVC_RW_USR_RO << PAGE_AP2) \
| (SVC_RW_USR_RO << PAGE_AP3))
#define __MAP_SVC_RW_FLAGS (cacheable | bufferable | (SVC_RW_USR_NONE << PAGE_AP0) \
| (SVC_RW_USR_NONE << PAGE_AP1) | (SVC_RW_USR_NONE << PAGE_AP2) \
| (SVC_RW_USR_NONE << PAGE_AP3))
#define __MAP_SVC_IO_FLAGS (uncacheable | unbufferable | (SVC_RW_USR_NONE << PAGE_AP0) \
| (SVC_RW_USR_NONE << PAGE_AP1) | (SVC_RW_USR_NONE << PAGE_AP2) \
| (SVC_RW_USR_NONE << PAGE_AP3))
#define __MAP_USR_IO_FLAGS (uncacheable | unbufferable | (SVC_RW_USR_RW << PAGE_AP0) \
| (SVC_RW_USR_RW << PAGE_AP1) | (SVC_RW_USR_RW << PAGE_AP2) \
| (SVC_RW_USR_RW << PAGE_AP3))
#define __MAP_USR_RW (cacheable | bufferable | (SVC_RW_USR_RW << PAGE_AP0) \
| (SVC_RW_USR_RW << PAGE_AP1) | (SVC_RW_USR_RW << PAGE_AP2) \
| (SVC_RW_USR_RW << PAGE_AP3))
#define __MAP_USR_RO (cacheable | bufferable | (SVC_RW_USR_RO << PAGE_AP0) \
| (SVC_RW_USR_RO << PAGE_AP1) | (SVC_RW_USR_RO << PAGE_AP2) \
| (SVC_RW_USR_RO << PAGE_AP3))
#define __MAP_KERN_RW (cacheable | bufferable | (SVC_RW_USR_NONE << PAGE_AP0) \
| (SVC_RW_USR_NONE << PAGE_AP1) | (SVC_RW_USR_NONE << PAGE_AP2) \
| (SVC_RW_USR_NONE << PAGE_AP3))
#define __MAP_KERN_IO (uncacheable | unbufferable | (SVC_RW_USR_NONE << PAGE_AP0) \
| (SVC_RW_USR_NONE << PAGE_AP1) | (SVC_RW_USR_NONE << PAGE_AP2) \
| (SVC_RW_USR_NONE << PAGE_AP3))
#define __MAP_USR_IO (uncacheable | unbufferable | (SVC_RW_USR_RW << PAGE_AP0) \
| (SVC_RW_USR_RW << PAGE_AP1) | (SVC_RW_USR_RW << PAGE_AP2) \
| (SVC_RW_USR_RW << PAGE_AP3))
/* Abort information */
/* There is no execute bit in ARMv5, so we ignore it */
#define __MAP_USR_RWX __MAP_USR_RW
#define __MAP_USR_RX __MAP_USR_RO
#define __MAP_KERN_RWX __MAP_KERN_RW
#define __MAP_KERN_RX __MAP_KERN_RW /* We always have kernel RW */
#define __MAP_FAULT 0
/*FIXME: Carry all these definitions to an abort.h, Also carry all abort code to abort.c. Much neater!!! */
/* Abort type */
#define ARM_PABT 1
#define ARM_DABT 0
/* The kernel makes use of bit 8 (Always Zero) of FSR to define which type of abort */
#define set_abort_type(fsr, x) { fsr &= ~(1 << 8); fsr |= ((x & 1) << 8); }
#define ARM_FSR_MASK 0xF
#define is_prefetch_abort(fsr) ((fsr >> 8) & 0x1)
#define is_data_abort(fsr) (!is_prefetch_abort(fsr))
/*
* v5 Architecture-defined data abort values for FSR ordered
* in highest to lowest priority.
*/
#define DABT_TERMINAL 0x2
#define DABT_VECTOR 0x0 /* Obsolete */
#define DABT_ALIGN 0x1
#define DABT_EXT_XLATE_LEVEL1 0xC
#define DABT_EXT_XLATE_LEVEL2 0xE
#define DABT_XLATE_SECT 0x5
#define DABT_XLATE_PAGE 0x7
#define DABT_DOMAIN_SECT 0x9
#define DABT_DOMAIN_PAGE 0xB
#define DABT_PERM_SECT 0xD
#define DABT_PERM_PAGE 0xF
#define DABT_EXT_LFETCH_SECT 0x4
#define DABT_EXT_LFETCH_PAGE 0x6
#define DABT_EXT_NON_LFETCH_SECT 0x8
#define DABT_EXT_NON_LFETCH_PAGE 0xA
#define TASK_PGD(x) (x)->space->pgd
#define STACK_ALIGNMENT 8
/* Kernel's data about the fault */
typedef struct fault_kdata {
u32 faulty_pc;
u32 fsr;
u32 far;
pte_t pte;
} __attribute__ ((__packed__)) fault_kdata_t;
void arch_hardware_flush(pgd_table_t *pgd);
void add_section_mapping_init(unsigned int paddr, unsigned int vaddr,
unsigned int size, unsigned int flags);
void add_boot_mapping(unsigned int paddr, unsigned int vaddr,
unsigned int size, unsigned int flags);
struct address_space;
int delete_page_tables(struct address_space *space);
int copy_user_tables(struct address_space *new, struct address_space *orig);
pgd_table_t *copy_page_tables(pgd_table_t *from);
void remap_as_pages(void *vstart, void *vend);
int pgd_count_pmds(pgd_table_t *pgd);
pgd_table_t *realloc_page_tables(void);
void remove_section_mapping(unsigned long vaddr);
void copy_pgds_by_vrange(pgd_table_t *to, pgd_table_t *from,
unsigned long start, unsigned long end);
extern pgd_table_t init_pgd;
void arch_update_utcb(unsigned long utcb_address);
void system_identify(void);
#endif /* __ASSEMBLY__ */
#endif /* __V5_MM_H__ */

19
include/l4/arch/arm/v5/mmu_ops.h
View File

@@ -18,6 +18,7 @@ void arm_enable_high_vectors(void);
void arm_invalidate_cache(void);
void arm_invalidate_icache(void);
void arm_invalidate_dcache(void);
void arm_clean_dcache(void);
void arm_clean_invalidate_dcache(void);
void arm_clean_invalidate_cache(void);
void arm_drain_writebuffer(void);
@@ -31,4 +32,22 @@ static inline void arm_enable_caches(void)
arm_enable_dcache();
}
static inline void dmb(void)
{
/* This is the closest to its meaning */
arm_drain_writebuffer();
}
static inline void dsb(void)
{
/* No op */
}
static inline void isb(void)
{
/* No op */
}
#endif /* __MMU__OPS__H__ */

6
include/l4/arch/arm/v5/perfmon.h Normal file
View File

@@ -0,0 +1,6 @@
#ifndef __PERFMON_H__
#define __PERFMON_H__
static inline void perfmon_init(void) { }
#endif

1
include/l4/arch/arm/v6/abort.h Normal file
View File

@@ -0,0 +1 @@

43
include/l4/arch/arm/v6/cpu.h Normal file
View File

@@ -0,0 +1,43 @@
/*
* Cpu specific features
* defined upon the base architecture.
*
* Copyright (C) 2010 B Labs Ltd.
* Written by Bahadir Balban
*/
#ifndef __V6_CPU_H__
#define __V6_CPU_H__
#include INC_SUBARCH(mmu_ops.h)
#define MPIDR_CPUID_MASK 0x7
/* Read multi-processor affinity register */
static inline unsigned int __attribute__((always_inline))
cp15_read_mpidr(void)
{
unsigned int val;
__asm__ __volatile__ (
"mrc p15, 0, %0, c0, c0, 5\n"
: "=r" (val)
:
);
return val;
}
static inline int smp_get_cpuid()
{
volatile u32 mpidr = cp15_read_mpidr();
return mpidr & MPIDR_CPUID_MASK;
}
static inline void cpu_startup(void)
{
}
#endif /* __V6_CPU_H__ */

33
include/l4/arch/arm/v6/exception.h Normal file
View File

@@ -0,0 +1,33 @@
/*
* Definitions for exception support on ARMv5
*
* Copyright (C) 2007 Bahadir Balban
*/
#ifndef __ARCH_V5_EXCEPTION_H__
#define __ARCH_V5_EXCEPTION_H__
#include INC_ARCH(asm.h)
/*
* v5 Architecture-defined data abort values for FSR ordered
* in highest to lowest priority.
*/
#define DABT_TERMINAL 0x2
#define DABT_VECTOR 0x0 /* Obsolete */
#define DABT_ALIGN 0x1
#define DABT_EXT_XLATE_LEVEL1 0xC
#define DABT_EXT_XLATE_LEVEL2 0xE
#define DABT_XLATE_SECT 0x5
#define DABT_XLATE_PAGE 0x7
#define DABT_DOMAIN_SECT 0x9
#define DABT_DOMAIN_PAGE 0xB
#define DABT_PERM_SECT 0xD
#define DABT_PERM_PAGE 0xF
#define DABT_EXT_LFETCH_SECT 0x4
#define DABT_EXT_LFETCH_PAGE 0x6
#define DABT_EXT_NON_LFETCH_SECT 0x8
#define DABT_EXT_NON_LFETCH_PAGE 0xA
#define FSR_FS_MASK 0xF
#endif /* __ARCH_V5_EXCEPTION_H__ */

26
include/l4/arch/arm/v6/irq.h Normal file
View File

@@ -0,0 +1,26 @@
#ifndef __ARM_V5_IRQ_H__
#define __ARM_V5_IRQ_H__
static inline void enable_irqs()
{
__asm__ __volatile__(
"mrs r0, cpsr_fc\n"
"bic r0, r0, #0x80\n" /* ARM_IRQ_BIT */
"msr cpsr_fc, r0\n"
);
}
static inline void disable_irqs()
{
__asm__ __volatile__(
"mrs r0, cpsr_fc\n"
"orr r0, r0, #0x80\n" /* ARM_IRQ_BIT */
"msr cpsr_fc, r0\n"
);
}
/* Disable the irqs unconditionally, but also keep the previous state such that
* if it was already disabled before the call, the restore call would retain
* this state. */
void irq_local_disable_save(unsigned long *state);
#endif

157
include/l4/arch/arm/v6/mm.h
View File

@@ -9,53 +9,65 @@
/* ARM specific definitions */
#define VIRT_MEM_START 0
#define VIRT_MEM_END 0xFFFFFFFF
#define ARM_SECTION_SIZE SZ_1MB
#define ARM_SECTION_MASK (ARM_SECTION_SIZE - 1)
#define ARM_SECTION_BITS 20
#define SECTION_SIZE SZ_1MB
#define SECTION_MASK (SECTION_SIZE - 1)
#define SECTION_ALIGN_MASK (~SECTION_MASK)
#define SECTION_BITS 20
#define ARM_PAGE_SIZE SZ_4K
#define ARM_PAGE_MASK 0xFFF
#define ARM_PAGE_BITS 12
#define PGD_SIZE SZ_4K * 4
#define PGD_ENTRY_TOTAL SZ_4K
#define PGD_TYPE_MASK 0x3
#define PGD_COARSE_ALIGN_MASK 0xFFFFFC00
#define PGD_SECTION_ALIGN_MASK 0xFFF00000
#define PGD_FINE_ALIGN_MASK 0xFFFFF000
#define PGD_TYPE_FAULT 0
#define PGD_TYPE_COARSE 1
#define PGD_TYPE_SECTION 2
#define PGD_TYPE_FINE 3
#define PMD_TYPE_MASK 0x3
#define PMD_TYPE_FAULT 0
#define PMD_TYPE_LARGE 1
#define PMD_TYPE_SMALL 2
#define PMD_TYPE_TINY 3
/* Permission field offsets */
#define SECTION_AP0 10
#define PMD_SIZE SZ_1K
#define PMD_ENTRY_TOTAL 256
#define PMD_MAP_SIZE SZ_1MB
#define PMD_ALIGN_MASK (~(PMD_SIZE - 1))
#define PMD_TYPE_MASK 0x3
#define PMD_TYPE_FAULT 0
#define PMD_TYPE_PMD 1
#define PMD_TYPE_SECTION 2
/* We need this as printascii.S is including this file */
#define PTE_TYPE_MASK 0x3
#define PTE_TYPE_FAULT 0
#define PTE_TYPE_LARGE 1
#define PTE_TYPE_SMALL 2
#define PTE_TYPE_TINY 3
/* Permission field offsets */
#define SECTION_AP0 10
/*
* These are indices into arrays with pgd_t or pmd_t sized elements,
* therefore the index must be divided by appropriate element size
*/
#define PGD_INDEX(x) (((((unsigned long)(x)) >> 18) \
& 0x3FFC) / sizeof(pmd_t))
/*
* Strip out the page offset in this
* megabyte from a total of 256 pages.
*/
#define PMD_INDEX(x) (((((unsigned long)(x)) >> 10) \
& 0x3FC) / sizeof (pte_t))
/* We need this as print-early.S is including this file */
#ifndef __ASSEMBLY__
/* Type-checkable page table elements */
typedef u32 pgd_t;
typedef u32 pmd_t;
typedef u32 pte_t;
/* Page global directory made up of pgd_t entries */
typedef struct pgd_table {
pgd_t entry[PGD_ENTRY_TOTAL];
pmd_t entry[PGD_ENTRY_TOTAL];
} pgd_table_t;
/* Page middle directory made up of pmd_t entries */
typedef struct pmd_table {
pmd_t entry[PMD_ENTRY_TOTAL];
pte_t entry[PMD_ENTRY_TOTAL];
} pmd_table_t;
/* Applies for both small and large pages */
@@ -79,86 +91,35 @@ typedef struct pmd_table {
#define unbufferable 0
/* Helper macros for common cases */
#define __MAP_USR_RW_FLAGS (cacheable | bufferable | (SVC_RW_USR_RW << PAGE_AP0) \
| (SVC_RW_USR_RW << PAGE_AP1) | (SVC_RW_USR_RW << PAGE_AP2) \
| (SVC_RW_USR_RW << PAGE_AP3))
#define __MAP_USR_RO_FLAGS (cacheable | bufferable | (SVC_RW_USR_RO << PAGE_AP0) \
| (SVC_RW_USR_RO << PAGE_AP1) | (SVC_RW_USR_RO << PAGE_AP2) \
| (SVC_RW_USR_RO << PAGE_AP3))
#define __MAP_SVC_RW_FLAGS (cacheable | bufferable | (SVC_RW_USR_NONE << PAGE_AP0) \
| (SVC_RW_USR_NONE << PAGE_AP1) | (SVC_RW_USR_NONE << PAGE_AP2) \
| (SVC_RW_USR_NONE << PAGE_AP3))
#define __MAP_SVC_IO_FLAGS (uncacheable | unbufferable | (SVC_RW_USR_NONE << PAGE_AP0) \
| (SVC_RW_USR_NONE << PAGE_AP1) | (SVC_RW_USR_NONE << PAGE_AP2) \
| (SVC_RW_USR_NONE << PAGE_AP3))
#define __MAP_USR_IO_FLAGS (uncacheable | unbufferable | (SVC_RW_USR_RW << PAGE_AP0) \
| (SVC_RW_USR_RW << PAGE_AP1) | (SVC_RW_USR_RW << PAGE_AP2) \
| (SVC_RW_USR_RW << PAGE_AP3))
#define __MAP_USR_RW (cacheable | bufferable | (SVC_RW_USR_RW << PAGE_AP0) \
| (SVC_RW_USR_RW << PAGE_AP1) | (SVC_RW_USR_RW << PAGE_AP2) \
| (SVC_RW_USR_RW << PAGE_AP3))
#define __MAP_USR_RO (cacheable | bufferable | (SVC_RW_USR_RO << PAGE_AP0) \
| (SVC_RW_USR_RO << PAGE_AP1) | (SVC_RW_USR_RO << PAGE_AP2) \
| (SVC_RW_USR_RO << PAGE_AP3))
#define __MAP_KERN_RW (cacheable | bufferable | (SVC_RW_USR_NONE << PAGE_AP0) \
| (SVC_RW_USR_NONE << PAGE_AP1) | (SVC_RW_USR_NONE << PAGE_AP2) \
| (SVC_RW_USR_NONE << PAGE_AP3))
#define __MAP_KERN_IO (uncacheable | unbufferable | (SVC_RW_USR_NONE << PAGE_AP0) \
| (SVC_RW_USR_NONE << PAGE_AP1) | (SVC_RW_USR_NONE << PAGE_AP2) \
| (SVC_RW_USR_NONE << PAGE_AP3))
#define __MAP_USR_IO (uncacheable | unbufferable | (SVC_RW_USR_RW << PAGE_AP0) \
| (SVC_RW_USR_RW << PAGE_AP1) | (SVC_RW_USR_RW << PAGE_AP2) \
| (SVC_RW_USR_RW << PAGE_AP3))
/* Abort information */
/* There is no execute bit in ARMv5, so we ignore it */
#define __MAP_USR_RWX __MAP_USR_RW
#define __MAP_USR_RX __MAP_USR_RO
#define __MAP_KERN_RWX __MAP_KERN_RW
#define __MAP_KERN_RX __MAP_KERN_RW /* We always have kernel RW */
#define __MAP_FAULT 0
/*FIXME: Carry all these definitions to an abort.h, Also carry all abort code to abort.c. Much neater!!! */
/* Abort type */
#define ARM_PABT 1
#define ARM_DABT 0
/* The kernel makes use of bit 8 (Always Zero) of FSR to define which type of abort */
#define set_abort_type(fsr, x) { fsr &= ~(1 << 8); fsr |= ((x & 1) << 8); }
#define ARM_FSR_MASK 0xF
#define is_prefetch_abort(fsr) ((fsr >> 8) & 0x1)
#define is_data_abort(fsr) (!is_prefetch_abort(fsr))
/*
* v5 Architecture-defined data abort values for FSR ordered
* in highest to lowest priority.
*/
#define DABT_TERMINAL 0x2
#define DABT_VECTOR 0x0 /* Obsolete */
#define DABT_ALIGN 0x1
#define DABT_EXT_XLATE_LEVEL1 0xC
#define DABT_EXT_XLATE_LEVEL2 0xE
#define DABT_XLATE_SECT 0x5
#define DABT_XLATE_PAGE 0x7
#define DABT_DOMAIN_SECT 0x9
#define DABT_DOMAIN_PAGE 0xB
#define DABT_PERM_SECT 0xD
#define DABT_PERM_PAGE 0xF
#define DABT_EXT_LFETCH_SECT 0x4
#define DABT_EXT_LFETCH_PAGE 0x6
#define DABT_EXT_NON_LFETCH_SECT 0x8
#define DABT_EXT_NON_LFETCH_PAGE 0xA
#define TASK_PGD(x) (x)->space->pgd
#define STACK_ALIGNMENT 8
/* Kernel's data about the fault */
typedef struct fault_kdata {
u32 faulty_pc;
u32 fsr;
u32 far;
pte_t pte;
} __attribute__ ((__packed__)) fault_kdata_t;
void arch_hardware_flush(pgd_table_t *pgd);
void add_section_mapping_init(unsigned int paddr, unsigned int vaddr,
unsigned int size, unsigned int flags);
void add_boot_mapping(unsigned int paddr, unsigned int vaddr,
unsigned int size, unsigned int flags);
struct address_space;
int delete_page_tables(struct address_space *space);
int copy_user_tables(struct address_space *new, struct address_space *orig);
pgd_table_t *copy_page_tables(pgd_table_t *from);
void remap_as_pages(void *vstart, void *vend);
int pgd_count_pmds(pgd_table_t *pgd);
pgd_table_t *realloc_page_tables(void);
void remove_section_mapping(unsigned long vaddr);
void copy_pgds_by_vrange(pgd_table_t *to, pgd_table_t *from,
unsigned long start, unsigned long end);
extern pgd_table_t init_pgd;
#endif /* __ASSEMBLY__*/
#endif /* __ASSEMBLY__ */
#endif /* __V5_MM_H__ */

20
include/l4/arch/arm/v6/mmu_ops.h
View File

@@ -6,7 +6,6 @@
* Copyright (C) 2005 Bahadir Balban
*
*/
void arm_set_ttb(unsigned int);
void arm_set_domain(unsigned int);
unsigned int arm_get_domain(void);
@@ -18,6 +17,7 @@ void arm_enable_high_vectors(void);
void arm_invalidate_cache(void);
void arm_invalidate_icache(void);
void arm_invalidate_dcache(void);
void arm_clean_dcache(void);
void arm_clean_invalidate_dcache(void);
void arm_clean_invalidate_cache(void);
void arm_drain_writebuffer(void);
@@ -31,4 +31,22 @@ static inline void arm_enable_caches(void)
arm_enable_dcache();
}
static inline void dmb(void)
{
/* This is the closest to its meaning */
arm_drain_writebuffer();
}
static inline void dsb(void)
{
/* No op */
}
static inline void isb(void)
{
/* No op */
}
#endif /* __MMU__OPS__H__ */

13
include/l4/arch/arm/v7/cortexa8/cpu.h
View File

@@ -1,13 +0,0 @@
/*
*
* Copyright (C) 2005 Bahadir Balban
*
*/
#ifndef __ARM926EJS__H__
#define __ARM926EJS__H__
#endif /* __ARM926EJS__H__ */

164
include/l4/arch/arm/v7/mm.h
View File

@@ -1,164 +0,0 @@
/*
* ARM v5-specific virtual memory details
*
* Copyright (C) 2007 Bahadir Balban
*/
#ifndef __V5_MM_H__
#define __V5_MM_H__
/* ARM specific definitions */
#define VIRT_MEM_START 0
#define VIRT_MEM_END 0xFFFFFFFF
#define ARM_SECTION_SIZE SZ_1MB
#define ARM_SECTION_MASK (ARM_SECTION_SIZE - 1)
#define ARM_SECTION_BITS 20
#define ARM_PAGE_SIZE SZ_4K
#define ARM_PAGE_MASK 0xFFF
#define ARM_PAGE_BITS 12
#define PGD_SIZE SZ_4K * 4
#define PGD_ENTRY_TOTAL SZ_4K
#define PGD_TYPE_MASK 0x3
#define PGD_COARSE_ALIGN_MASK 0xFFFFFC00
#define PGD_SECTION_ALIGN_MASK 0xFFF00000
#define PGD_FINE_ALIGN_MASK 0xFFFFF000
#define PGD_TYPE_FAULT 0
#define PGD_TYPE_COARSE 1
#define PGD_TYPE_SECTION 2
#define PGD_TYPE_FINE 3
#define PMD_TYPE_MASK 0x3
#define PMD_TYPE_FAULT 0
#define PMD_TYPE_LARGE 1
#define PMD_TYPE_SMALL 2
#define PMD_TYPE_TINY 3
/* Permission field offsets */
#define SECTION_AP0 10
#define PMD_SIZE SZ_1K
#define PMD_ENTRY_TOTAL 256
#define PMD_MAP_SIZE SZ_1MB
/* We need this as printascii.S is including this file */
#ifndef __ASSEMBLY__
/* Type-checkable page table elements */
typedef u32 pgd_t;
typedef u32 pmd_t;
typedef u32 pte_t;
/* Page global directory made up of pgd_t entries */
typedef struct pgd_table {
pgd_t entry[PGD_ENTRY_TOTAL];
} pgd_table_t;
/* Page middle directory made up of pmd_t entries */
typedef struct pmd_table {
pmd_t entry[PMD_ENTRY_TOTAL];
} pmd_table_t;
/* Applies for both small and large pages */
#define PAGE_AP0 4
#define PAGE_AP1 6
#define PAGE_AP2 8
#define PAGE_AP3 10
/* Permission values with rom and sys bits ignored */
#define SVC_RW_USR_NONE 1
#define SVC_RW_USR_RO 2
#define SVC_RW_USR_RW 3
#define PTE_PROT_MASK (0xFF << 4)
#define CACHEABILITY 3
#define BUFFERABILITY 2
#define cacheable (1 << CACHEABILITY)
#define bufferable (1 << BUFFERABILITY)
#define uncacheable 0
#define unbufferable 0
/* Helper macros for common cases */
#define __MAP_USR_RW_FLAGS (cacheable | bufferable | (SVC_RW_USR_RW << PAGE_AP0) \
| (SVC_RW_USR_RW << PAGE_AP1) | (SVC_RW_USR_RW << PAGE_AP2) \
| (SVC_RW_USR_RW << PAGE_AP3))
#define __MAP_USR_RO_FLAGS (cacheable | bufferable | (SVC_RW_USR_RO << PAGE_AP0) \
| (SVC_RW_USR_RO << PAGE_AP1) | (SVC_RW_USR_RO << PAGE_AP2) \
| (SVC_RW_USR_RO << PAGE_AP3))
#define __MAP_SVC_RW_FLAGS (cacheable | bufferable | (SVC_RW_USR_NONE << PAGE_AP0) \
| (SVC_RW_USR_NONE << PAGE_AP1) | (SVC_RW_USR_NONE << PAGE_AP2) \
| (SVC_RW_USR_NONE << PAGE_AP3))
#define __MAP_SVC_IO_FLAGS (uncacheable | unbufferable | (SVC_RW_USR_NONE << PAGE_AP0) \
| (SVC_RW_USR_NONE << PAGE_AP1) | (SVC_RW_USR_NONE << PAGE_AP2) \
| (SVC_RW_USR_NONE << PAGE_AP3))
#define __MAP_USR_IO_FLAGS (uncacheable | unbufferable | (SVC_RW_USR_RW << PAGE_AP0) \
| (SVC_RW_USR_RW << PAGE_AP1) | (SVC_RW_USR_RW << PAGE_AP2) \
| (SVC_RW_USR_RW << PAGE_AP3))
/* Abort information */
/*FIXME: Carry all these definitions to an abort.h, Also carry all abort code to abort.c. Much neater!!! */
/* Abort type */
#define ARM_PABT 1
#define ARM_DABT 0
/* The kernel makes use of bit 8 (Always Zero) of FSR to define which type of abort */
#define set_abort_type(fsr, x) { fsr &= ~(1 << 8); fsr |= ((x & 1) << 8); }
#define ARM_FSR_MASK 0xF
#define is_prefetch_abort(fsr) ((fsr >> 8) & 0x1)
#define is_data_abort(fsr) (!is_prefetch_abort(fsr))
/*
* v5 Architecture-defined data abort values for FSR ordered
* in highest to lowest priority.
*/
#define DABT_TERMINAL 0x2
#define DABT_VECTOR 0x0 /* Obsolete */
#define DABT_ALIGN 0x1
#define DABT_EXT_XLATE_LEVEL1 0xC
#define DABT_EXT_XLATE_LEVEL2 0xE
#define DABT_XLATE_SECT 0x5
#define DABT_XLATE_PAGE 0x7
#define DABT_DOMAIN_SECT 0x9
#define DABT_DOMAIN_PAGE 0xB
#define DABT_PERM_SECT 0xD
#define DABT_PERM_PAGE 0xF
#define DABT_EXT_LFETCH_SECT 0x4
#define DABT_EXT_LFETCH_PAGE 0x6
#define DABT_EXT_NON_LFETCH_SECT 0x8
#define DABT_EXT_NON_LFETCH_PAGE 0xA
#define TASK_PGD(x) (x)->space->pgd
#define STACK_ALIGNMENT 8
/* Kernel's data about the fault */
typedef struct fault_kdata {
u32 faulty_pc;
u32 fsr;
u32 far;
pte_t pte;
} __attribute__ ((__packed__)) fault_kdata_t;
void arch_hardware_flush(pgd_table_t *pgd);
void add_section_mapping_init(unsigned int paddr, unsigned int vaddr,
unsigned int size, unsigned int flags);
void add_boot_mapping(unsigned int paddr, unsigned int vaddr,
unsigned int size, unsigned int flags);
struct address_space;
int delete_page_tables(struct address_space *space);
int copy_user_tables(struct address_space *new, struct address_space *orig);
pgd_table_t *copy_page_tables(pgd_table_t *from);
void remap_as_pages(void *vstart, void *vend);
int pgd_count_pmds(pgd_table_t *pgd);
pgd_table_t *realloc_page_tables(void);
void remove_section_mapping(unsigned long vaddr);
void copy_pgds_by_vrange(pgd_table_t *to, pgd_table_t *from,
unsigned long start, unsigned long end);
#endif /* __ASSEMBLY__*/
#endif /* __V5_MM_H__ */

34
include/l4/arch/arm/v7/mmu_ops.h
View File

@@ -1,34 +0,0 @@
#ifndef __MMU__OPS__H__
#define __MMU__OPS__H__
/*
* Prototypes for low level mmu operations
*
* Copyright (C) 2005 Bahadir Balban
*
*/
void arm_set_ttb(unsigned int);
void arm_set_domain(unsigned int);
unsigned int arm_get_domain(void);
void arm_enable_mmu(void);
void arm_enable_icache(void);
void arm_enable_dcache(void);
void arm_enable_wbuffer(void);
void arm_enable_high_vectors(void);
void arm_invalidate_cache(void);
void arm_invalidate_icache(void);
void arm_invalidate_dcache(void);
void arm_clean_invalidate_dcache(void);
void arm_clean_invalidate_cache(void);
void arm_drain_writebuffer(void);
void arm_invalidate_tlb(void);
void arm_invalidate_itlb(void);
void arm_invalidate_dtlb(void);
static inline void arm_enable_caches(void)
{
arm_enable_icache();
arm_enable_dcache();
}
#endif /* __MMU__OPS__H__ */

100
include/l4/drivers/irq/gic/gic.h
View File

@@ -1,35 +1,91 @@
/*
* Generic Interrupt Controller offsets
*
* Copyright (C) 2007 Bahadir Balban
* Copyright (C) 2009 B Labs Ltd.
*
*/
#ifndef __ARM_GIC_H__
#define __ARM_GIC_H__
#include <l4/types.h>
#include INC_PLAT(platform.h)
#include INC_PLAT(offsets.h)
/* GIC CPU register offsets */
#define ARM_GIC_CPU_IC 0x00 /* Interface Control */
#define ARM_GIC_CPUPM 0x04 /* Interrupt Priority Mask */
#define ARM_GIC_CPU_BP 0x08 /* Binary Point */
#define ARM_GIC_CPU_IA 0x0c /* Interrupt Acknowledge */
#define ARM_GIC_CPU_EOI 0x10 /* End of Interrupt */
#define ARM_GIC_CPU_RPI 0x14 /* Running Priority */
#define ARM_GIC_CPU_HPI 0x18 /* Highest Priority Interrupt*/
/* CPU registers */
struct gic_cpu
{
u32 control; /* Control Register */
u32 prio_mask; /* Priority Mask */
u32 bin_point; /* Binary Point Register */
u32 ack; /* Interrupt */
u32 eoi; /* End of Interrupt */
u32 running; /* Running Priority register */
u32 high_pending; /* Highest Pending Register */
};
/* Distributor register map */
#define ARM_GIC_DIST_CNTRL 0x000 /* Control Register */
#define ARM_GIC_DIST_ICT 0x004 /* Interface Controller Type */
#define ARM_GIC_DIST_ISE 0x100 /* Interrupt Set Enable */
#define ARM_GIC_DIST_ICE 0x180 /* Interrupt Clear Enable */
#define ARM_GIC_DIST_ISP 0x200 /* Interrupt Set Pending */
#define ARM_GIC_DIST_ICP 0x280 /* Interrupt Clear Pending*/
#define ARM_GIC_DIST_AB 0x300 /* Active Bit */
#define ARM_GIC_DIST_IP 0x400 /* Interrupt Priority */
#define ARM_GIC_DIST_IPT 0x800 /* Interrupt Processor Target */
#define ARM_GIC_DIST_IC 0xc00 /* Interrupt Configuration */
#define ARM_GIC_DIST_SGI 0xf00 /* Software Generated Interrupt */
#define NIRQ 1024
#define NREGS_1_BIT_PER_INT 32 /* when 1 bit per interrupt */
#define NREGS_4_BIT_PER_INT 256
#define NREGS_4_BIT_PER_INT 256
#define NREGS_2_BIT_PER_INT 64
#define NID 4
#endif /* __ARM_GIC_H__ */
/* Distributor registers */
/* -r- -- reserved */
struct gic_dist{
u32 control; /* Control Register */
u32 const type; /* Type Register */
u32 dummy1[62]; /* -r- */
u32 set_en[NREGS_1_BIT_PER_INT]; /* Enable Set */
u32 clr_en[NREGS_1_BIT_PER_INT]; /* Enable Clear */
u32 set_pending[NREGS_1_BIT_PER_INT]; /* Set Pending */
u32 clr_pending[NREGS_1_BIT_PER_INT]; /* Clear Pending */
u32 active[NREGS_1_BIT_PER_INT]; /* Active Bit registers */
u32 dummy2[32]; /* -r- */
u32 priority[NREGS_4_BIT_PER_INT]; /* Interrupt Priority */
u32 target[NREGS_4_BIT_PER_INT]; /* CPU Target Registers */
u32 config[NREGS_2_BIT_PER_INT]; /* Interrupt Config */
u32 level[NREGS_2_BIT_PER_INT]; /* Interrupt Line Level */
u32 dummy3[64]; /* -r- */
u32 soft_int; /* Software Interrupts */
u32 dummy4[55]; /* -r- */
u32 id[NID]; /* Primecell ID registers */
};
struct gic_data {
struct gic_cpu *cpu;
struct gic_dist *dist;
};
l4id_t gic_read_irq(void *data);
void gic_mask_irq(l4id_t irq);
void gic_unmask_irq(l4id_t irq);
void gic_ack_irq(l4id_t irq);
void gic_ack_and_mask(l4id_t irq);
void gic_clear_pending(l4id_t irq);
void gic_cpu_init(int idx, unsigned long base);
void gic_dist_init(int idx, unsigned long base);
void gic_send_ipi(int cpu, int ipi_cmd);
void gic_set_target(u32 irq, u32 cpu);
u32 gic_get_target(u32 irq);
void gic_set_priority(u32 irq, u32 prio);
u32 gic_get_priority(u32 irq);
void gic_dummy_init(void);
#endif /* __GIC_H__ */

73
include/l4/drivers/irq/omap3/omap3_intc.h Normal file
View File

@@ -0,0 +1,73 @@
/*
* OMAP3XXX Interrupt Controller Defines
*
* Copyright 2010 B Labs Ltd.
*/
#ifndef __OMAP3_INTC_H__
#define __OMAP3_INTC_H__
#include INC_ARCH(io.h)
#define OMAP3_INTC_SYSCONFIG (0x00000010) /* RW */
#define OMAP3_INTC_SYSSTATUS (0x00000014) /* RO */
#define OMAP3_INTC_SIR_IRQ (0x00000040) /* RO */
#define OMAP3_INTC_SIR_FIQ (0x00000044) /* RO */
#define OMAP3_INTC_CONTROL (0x00000048) /* RW */
#define OMAP3_INTC_PROT (0x0000004C) /* RW - Protection */
#define OMAP3_INTC_IDLE (0x00000050) /* RW */
#define OMAP3_INTC_IRQ_PRIO (0x00000060) /* RW - IRQ Priority */
#define OMAP3_INTC_FIQ_PRIO (0x00000064) /* RW - FIQ Priority */
#define OMAP3_INTC_THREASHOLD (0x00000068) /* RW */
#define OMAP3_INTC_ITR (0x00000080) /* RO - Raw Interrupt Status*/
#define OMAP3_INTC_MIR (0x00000084) /* RW - Masked Int Status */
#define OMAP3_INTC_MIR_CLR (0x00000088) /* WO - Clear Mask*/
#define OMAP3_INTC_MIR_SET (0x0000008C) /* WO - Set Mask*/
#define OMAP3_INTC_ISR_SET (0x00000090) /* RW - Software Int Set */
#define OMAP3_INTC_ISR_CLR (0x00000094) /* WO */
#define OMAP3_INTC_IRQ_PEND (0x00000098) /* RO */
#define OMAP3_INTC_FIQ_PEND (0x0000009C) /* RO */
#define OMAP3_INTC_ILR (0x00000100) /* RW */
/* Reset Bits */
#define OMAP_INTC_SOFTRESET (1 << 1)
static inline unsigned int omap3_intc_get_ilr(unsigned long base,
unsigned int irq)
{
return read((base + OMAP3_INTC_ILR + (irq * 4)));
}
static inline void omap3_intc_set_ilr(unsigned long base, unsigned int irq,
unsigned int val)
{
write(val, (base + OMAP3_INTC_ILR + (irq * 4)));
}
/* Set clear Interrupt masks */
static inline
void omap3_intc_set_irq_status(unsigned long base, unsigned int reg,
unsigned int irq)
{
unsigned int val = 0;
unsigned int offset = (irq >> 5); /* Same as dividing by 32 */
irq -= (offset * 32);
val = read((base + reg + (0x20 * offset)));
val |= (1 << irq);
write(val, (base + reg + (0x20 * offset)));
}
void omap3_intc_reset(unsigned long base);
void omap3_intc_init(void);
void omap3_intc_eoi_irq(l4id_t irq);
void omap3_intc_mask_irq(l4id_t irq);
void omap3_intc_unmask_irq(l4id_t irq);
void omap3_intc_ack_irq(l4id_t irq);
void omap3_intc_ack_and_mask(l4id_t irq);
l4id_t omap3_intc_read_irq(void *data);
#endif /* !__OMAP3_INTC_H__ */

9
include/l4/drivers/irq/pl190/pl190_vic.h
View File

@@ -10,9 +10,10 @@
#include INC_PLAT(platform.h)
#include INC_ARCH(types.h)
#include INC_ARCH(io.h)
#define PL190_BASE PLATFORM_IRQCTRL0_VIRTUAL
#define PL190_SIC_BASE PLATFORM_IRQCTRL1_VIRTUAL
#define PL190_BASE PLATFORM_IRQCTRL0_VBASE
#define PL190_SIC_BASE PLATFORM_IRQCTRL1_VBASE
#define PL190_IRQS_MAX 32
@@ -49,9 +50,9 @@ void pl190_vic_init(void);
void pl190_ack_irq(l4id_t irq);
void pl190_mask_irq(l4id_t irq);
void pl190_unmask_irq(l4id_t irq);
l4id_t pl190_read_irq(void);
l4id_t pl190_read_irq(void *irq_chip_data);
l4id_t pl190_sic_read_irq(void);
l4id_t pl190_sic_read_irq(void *irq_chip_data);
void pl190_sic_mask_irq(l4id_t irq);
void pl190_sic_mask_irq(l4id_t irq);
void pl190_sic_ack_irq(l4id_t irq);

52
include/l4/drivers/timer/omap/timer.h Normal file
View File

@@ -0,0 +1,52 @@
/*
* OMAP GP Timer offsets
*
* Copyright (C) 2007 Bahadir Balban
*
*/
#ifndef __OMAP_GPTIMER_H__
#define __OMAP_GPTIMER_H__
/* Register offsets */
#define OMAP_TIMER_TIOCP 0x10
#define OMAP_TIMER_TSTAT 0x14
#define OMAP_TIMER_TISR 0x18
#define OMAP_TIMER_TIER 0x1C
#define OMAP_TIMER_TCLR 0x24
#define OMAP_TIMER_TCRR 0x28
#define OMAP_TIMER_TLDR 0x2C
#define OMAP_TIMER_TMAR 0x38
#define OMAP_TIMER_TPIR 0x48
#define OMAP_TIMER_TNIR 0x4C
#define OMAP_TIMER_TCVR 0x50
/* Enable/Disable IRQ */
#define OMAP_TIMER_IRQENABLE 1
#define OMAP_TIMER_IRQDISABLE 0
/* Timer modes supported */
#define OMAP_TIMER_MODE_AUTORELAOD 1
#define OMAP_TIMER_MODE_COMPARE 6
#define OMAP_TIMER_MODE_CAPTURE 13
/* Interrupt types */
#define OMAP_TIMER_INTR_MATCH 0x0
#define OMAP_TIMER_INTR_OVERFLOW 0x1
#define OMAP_TIMER_INTR_CAPTURE 0x2
/* Clock source for timer */
#define OMAP_TIMER_CLKSRC_SYS_CLK 0x1
#define OMAP_TIMER_CLKSRC_32KHZ_CLK 0x0
void timer_init_oneshot(unsigned long timer_base);
u32 timer_periodic_intr_status(unsigned long timer_base);
void timer_reset(unsigned long timer_base);
void timer_load(unsigned long timer_base, u32 value);
u32 timer_read(unsigned long timer_base);
void timer_start(unsigned long timer_base);
void timer_stop(unsigned long timer_base);
void timer_init_periodic(unsigned long timer_base);
void timer_irq_clear(unsigned long timer_base);
void timer_init(unsigned long timer_base);
#endif /* __OMAP_GPTIMER_H__*/

46
include/l4/drivers/timer/sp804/timer.h Normal file
View File

@@ -0,0 +1,46 @@
/*
* SP804 Primecell Timer offsets
*
* Copyright (C) 2007 Bahadir Balban
*
*/
#ifndef __SP804_TIMER_H__
#define __SP804_TIMER_H__
#include INC_ARCH(io.h)
/* Register offsets */
#define SP804_LOAD 0x0
#define SP804_VALUE 0x4
#define SP804_CTRL 0x8
#define SP804_INTCLR 0xC
#define SP804_RIS 0x10
#define SP804_MIS 0x14
#define SP804_BGLOAD 0x18
#define SP804_ENABLE (1 << 7)
#define SP804_PERIODIC (1 << 6)
#define SP804_IRQEN (1 << 5)
#define SP804_32BIT (1 << 1)
#define SP804_ONESHOT (1 << 0)
#define SP804_SECONDARY_OFFSET 0x20
/* Timer prescaling */
#define SP804_SCALE_SHIFT 2
#define SP804_SCALE_DIV16 1
#define SP804_SCALE_DIV256 2
/* Wrapping = 0, Oneshot = 1 */
#define SP804_ONESHOT (1 << 0)
unsigned long timer_secondary_base(unsigned long timer_base);
void timer_irq_clear(unsigned long timer_base);
void timer_start(unsigned long timer_base);
void timer_load(u32 loadval, unsigned long timer_base);
u32 timer_read(unsigned long timer_base);
void timer_stop(unsigned long timer_base);
void timer_init_periodic(unsigned long timer_base, unsigned int load_value);
void timer_init_oneshot(unsigned long timer_base);
void timer_init(unsigned long timer_base, unsigned int load_value);
#endif /* __SP804_TIMER_H__ */

62
include/l4/drivers/uart/omap/uart.h Normal file
View File

@@ -0,0 +1,62 @@
/*
* OMAP UART Generic driver implementation.
*
* Copyright (C) 2007 Bahadir Balban
*
* The particular intention of this code is that it has been carefully written
* as decoupled from os-specific code and in a verbose way such that it clearly
* demonstrates how the device operates, reducing the amount of time to be spent
* for understanding the operational model and implementing a driver from
* scratch. This is the very first to be such a driver so far, hopefully it will
* turn out to be useful.
*/
#ifndef __OMAP_UART_H__
#define __OMAP_UART_H__
#include INC_PLAT(uart.h)
#include INC_ARCH(io.h)
/* Register offsets */
#define OMAP_UART_DLL 0x00
#define OMAP_UART_THR 0x00
#define OMAP_UART_RHR 0x00
#define OMAP_UART_DLH 0x04
#define OMAP_UART_IER 0x04
#define OMAP_UART_FCR 0x08
#define OMAP_UART_MCR 0x10
#define OMAP_UART_LSR 0x14
#define OMAP_UART_MDR1 0x20
#define OMAP_UART_LCR 0x0C
/* Modes supported by OMAP UART/IRDA/CIR IP */
#define OMAP_UART_MODE_UART16X 0x0
#define OMAP_UART_MODE_SIR 0x1
#define OMAP_UART_MODE_UART16X_AUTO_BAUD 0x2
#define OMAP_UART_MODE_UART13X 0x3
#define OMAP_UART_MODE_MIR 0x4
#define OMAP_UART_MODE_FIR 0x5
#define OMAP_UART_MODE_CIR 0x6
#define OMAP_UART_MODE_DEFAULT 0x7 /* Disable */
/* Number of data bits for UART */
#define OMAP_UART_DATA_BITS_5 0x0
#define OMAP_UART_DATA_BITS_6 0x1
#define OMAP_UART_DATA_BITS_7 0x2
#define OMAP_UART_DATA_BITS_8 0x3
/* Stop bits to be used for UART data */
#define OMAP_UART_STOP_BITS_1 0x0
#define OMAP_UART_STOP_BITS_1_5 0x1
/* Banked Register modes- ConfigA, ConfigB, Operational */
#define OMAP_UART_BANKED_MODE_OPERATIONAL 0x00
#define OMAP_UART_BANKED_MODE_CONFIG_A 0x80
#define OMAP_UART_BANKED_MODE_CONFIG_B 0xBF
void uart_tx_char(unsigned long base, char c);
char uart_rx_char(unsigned long uart_base);
void uart_set_baudrate(unsigned long uart_base, u32 baudrate, u32 clkrate);
void uart_init(unsigned long uart_base);
#endif /* __OMAP_UART_H__ */

35
include/l4/drivers/uart/pl011/uart.h Normal file
View File

@@ -0,0 +1,35 @@
/*
* PL011 UART Generic driver implementation.
* Copyright Bahadir Balban (C) 2009
*/
#ifndef __PL011_H__
#define __PL011_H__
#include INC_ARCH(io.h)
#include INC_PLAT(offsets.h)
/* Register offsets */
#define PL011_UARTDR 0x00
#define PL011_UARTRSR 0x04
#define PL011_UARTECR 0x04
#define PL011_UARTFR 0x18
#define PL011_UARTILPR 0x20
#define PL011_UARTIBRD 0x24
#define PL011_UARTFBRD 0x28
#define PL011_UARTLCR_H 0x2C
#define PL011_UARTCR 0x30
#define PL011_UARTIFLS 0x34
#define PL011_UARTIMSC 0x38
#define PL011_UARTRIS 0x3C
#define PL011_UARTMIS 0x40
#define PL011_UARTICR 0x44
#define PL011_UARTDMACR 0x48
void uart_tx_char(unsigned long uart_base, char c);
char uart_rx_char(unsigned long uart_base);
void uart_init(unsigned long base);
#endif /* __PL011__UART__ */

2
include/l4/generic/bootmem.h
View File

@@ -9,6 +9,4 @@ unsigned long bootmem_free_pages(void);
void *alloc_bootmem(int size, int alignment);
pmd_table_t *alloc_boot_pmd(void);
extern pgd_table_t init_pgd;
#endif /* __BOOTMEM_H__ */

7
include/l4/generic/cap-types.h
View File

@@ -46,7 +46,6 @@
*/
#define CAP_DEVTYPE_TIMER 1
#define CAP_DEVTYPE_UART 2
#define CAP_DEVTYPE_CLCD 3
#define CAP_DEVTYPE_OTHER 0xF
#define CAP_DEVTYPE_MASK 0xFFFF
#define CAP_DEVNUM_MASK 0xFFFF0000
@@ -102,6 +101,10 @@
#define CAP_MAP_UNMAP (1 << 5)
#define CAP_MAP_UTCB (1 << 6)
/* Cache operations, applicable to (virtual) memory regions */
#define CAP_CACHE_INVALIDATE (1 << 7)
#define CAP_CACHE_CLEAN (1 << 8)
/*
* IRQ Control capability
*/
@@ -137,4 +140,6 @@
#define CAP_CAP_DESTROY (1 << 6)
#define CAP_CAP_MODIFY (CAP_CAP_DEDUCE | CAP_CAP_SPLIT \
| CAP_CAP_DESTROY)
#endif /* __CAP_TYPES_H__ */

4
include/l4/generic/capability.h
View File

@@ -104,6 +104,8 @@ struct capability *cap_find_by_capid(l4id_t capid, struct cap_list **clist);
/* Capability checking on system calls */
int cap_map_check(struct ktcb *task, unsigned long phys, unsigned long virt,
unsigned long npages, unsigned int flags);
int cap_unmap_check(struct ktcb *task, unsigned long virt,
unsigned long npages);
int cap_thread_check(struct ktcb *task, unsigned int flags,
struct task_ids *ids);
int cap_exregs_check(struct ktcb *task, struct exregs_data *exregs);
@@ -114,5 +116,7 @@ int cap_mutex_check(unsigned long mutex_address, int mutex_op);
int cap_irq_check(struct ktcb *registrant, unsigned int req,
unsigned int flags, l4id_t irq);
int cap_cache_check(unsigned long start, unsigned long end,
unsigned int flags);
#endif /* __GENERIC_CAPABILITY_H__ */

3
include/l4/generic/container.h
View File

@@ -106,8 +106,7 @@ void kres_insert_container(struct container *c,
struct container *container_create(void);
int container_init_pagers(struct kernel_resources *kres,
pgd_table_t *current_pgd);
int container_init_pagers(struct kernel_resources *kres);
int init_containers(struct kernel_resources *kres);
struct container *container_find(struct kernel_resources *kres, l4id_t cid);

162
include/l4/generic/debug.h Normal file
View File

@@ -0,0 +1,162 @@
/*
* Definitions for kernel entry accounting.
*
* Copyright (C) 2010 B Labs Ltd.
*
* Written by Bahadir Balban
*/
#ifndef __GENERIC_DEBUG_H__
#define __GENERIC_DEBUG_H__
#include INC_ARCH(types.h)
#include INC_SUBARCH(cache.h)
#include <l4/lib/printk.h>
#if defined(CONFIG_DEBUG_ACCOUNTING)
struct exception_count {
u64 syscall;
u64 data_abort;
u64 prefetch_abort;
u64 irq;
u64 undefined_abort;
};
/*
* Note these are packed to match systable offsets
* so that they're incremented with an auccess
*/
struct syscall_count {
u64 ipc;
u64 tswitch;
u64 tctrl;
u64 exregs;
u64 emtpy;
u64 unmap;
u64 irqctrl;
u64 empty1;
u64 map;
u64 getid;
u64 capctrl;
u64 empty2;
u64 time;
u64 mutexctrl;
u64 cachectrl;
} __attribute__ ((__packed__));
struct task_op_count {
u64 context_switch;
u64 space_switch;
};
struct cache_op_count {
u64 dcache_clean_mva;
u64 dcache_inval_mva;
u64 icache_clean_mva;
u64 icache_inval_mva;
u64 dcache_clean_setway;
u64 dcache_inval_setway;
u64 tlb_mva;
};
#if defined(CONFIG_DEBUG_PERFMON_KERNEL)
/* Minimum, maximum and average timings for the call */
struct syscall_timing {
u64 total;
u32 min;
u32 max;
u32 avg;
};
struct syscall_timings {
struct syscall_timing ipc;
struct syscall_timing tswitch;
struct syscall_timing tctrl;
struct syscall_timing exregs;
struct syscall_timing emtpy;
struct syscall_timing unmap;
struct syscall_timing irqctrl;
struct syscall_timing empty1;
struct syscall_timing map;
struct syscall_timing getid;
struct syscall_timing capctrl;
struct syscall_timing empty2;
struct syscall_timing time;
struct syscall_timing mutexctrl;
struct syscall_timing cachectrl;
u64 all_total;
} __attribute__ ((__packed__));
extern struct syscall_timings syscall_timings;
#endif /* End of CONFIG_DEBUG_PERFMON_KERNEL */
struct system_accounting {
struct syscall_count syscalls;
#if defined(CONFIG_DEBUG_PERFMON_KERNEL)
struct syscall_timings syscall_timings;
#endif
struct exception_count exceptions;
struct cache_op_count cache_ops;
struct task_op_count task_ops;
} __attribute__ ((__packed__));
extern struct system_accounting system_accounting;
static inline void system_account_dabort(void)
{
system_accounting.exceptions.data_abort++;
}
static inline void system_account_pabort(void)
{
system_accounting.exceptions.prefetch_abort++;
}
static inline void system_account_undef_abort(void)
{
system_accounting.exceptions.undefined_abort++;
}
static inline void system_account_irq(void)
{
system_accounting.exceptions.irq++;
}
static inline void system_account_syscall(void)
{
system_accounting.exceptions.syscall++;
}
static inline void system_account_context_switch(void)
{
system_accounting.task_ops.context_switch++;
}
static inline void system_account_space_switch(void)
{
system_accounting.task_ops.space_switch++;
}
#include INC_SUBARCH(debug.h)
#else /* End of CONFIG_DEBUG_ACCOUNTING */
static inline void system_account_cache_op(int op) { }
static inline void system_account_irq(void) { }
static inline void system_account_syscall(void) { }
static inline void system_account_dabort(void) { }
static inline void system_account_pabort(void) { }
static inline void system_account_undef_abort(void) { }
static inline void system_account_space_switch(void) { }
static inline void system_account_context_switch(void) { }
#endif /* End of !CONFIG_DEBUG_ACCOUNTING */
#endif /* __GENERIC_DEBUG_H__ */

5
include/l4/generic/irq.h
View File

@@ -19,8 +19,8 @@
typedef void (*irq_op_t)(l4id_t irq);
struct irq_chip_ops {
void (*init)(void);
l4id_t (*read_irq)(void);
void (*init)();
l4id_t (*read_irq)(void *data);
irq_op_t ack_and_mask;
irq_op_t unmask;
};
@@ -31,6 +31,7 @@ struct irq_chip {
int cascade; /* The irq that lower chip uses on this chip */
int start; /* The global irq offset for this chip */
int end; /* End of this chip's irqs */
void *data; /* Anything that a of interest to a driver */
struct irq_chip_ops ops;
};

27
include/l4/generic/platform.h
View File

@@ -2,21 +2,32 @@
#define __PLATFORM_H__
/*
* Generic functions to be provided by every platform.
*
* Include only those API's that are needed by sources
* outside the src/platform code.
*/
#include <l4/generic/resource.h>
void platform_init(void);
/* Uart APIs */
void uart_init(void);
void uart_putc(char c);
/* Timer APIs */
void timer_init(void);
void timer_start(void);
/* IRQ controller */
void irq_controller_init(void);
void platform_irq_enable(int irq);
void platform_irq_disable(int irq);
#define dprintk(str, val) \
{ \
print_early(str); \
printhex8((val)); \
print_early("\n"); \
}
void print_early(char *str);
void printhex8(unsigned int);
int platform_setup_device_caps(struct kernel_resources *kres);
void platform_test_cpucycles(void);
#endif /* __PLATFORM_H__ */

1
include/l4/generic/preempt.h
View File

@@ -12,4 +12,5 @@ int preempt_count(void);
int in_nested_irq_context(void);
int in_irq_context(void);
int in_task_context(void);
#endif /* __PREEMPT_H__ */

13
include/l4/generic/resource.h
View File

@@ -92,15 +92,20 @@ struct kernel_resources {
struct mem_cache *cont_cache;
/* Zombie thread list */
struct ktcb_list zombie_list;
DECLARE_PERCPU(struct ktcb_list, zombie_list);
#if defined(CONFIG_SUBARCH_V7)
/* Global page tables on split page tables */
pgd_global_table_t *pgd_global;
#endif
};
extern struct kernel_resources kernel_resources;
void free_pgd(void *addr);
void free_pmd(void *addr);
void free_space(void *addr);
void free_ktcb(void *addr);
void free_space(void *addr, struct ktcb *task);
void free_ktcb(void *addr, struct ktcb *task);
void free_capability(void *addr);
void free_container(void *addr);
void free_user_mutex(void *addr);
@@ -118,4 +123,6 @@ int free_boot_memory(struct kernel_resources *kres);
int init_system_resources(struct kernel_resources *kres);
void setup_idle_caps(); /*TODO: Delete this when done with it */
#endif /* __RESOURCES_H__ */

28
include/l4/generic/scheduler.h
View File

@@ -7,8 +7,11 @@
#define __SCHEDULER_H__
#include <l4/generic/tcb.h>
#include <l4/generic/smp.h>
#include INC_SUBARCH(cpu.h)
#include INC_SUBARCH(mm.h)
#include INC_GLUE(memory.h)
#include INC_GLUE(smp.h)
/* Task priorities */
#define TASK_PRIO_MAX 10
@@ -19,14 +22,16 @@
#define TASK_PRIO_LOW 2
#define TASK_PRIO_TOTAL 30
/* Ticks per second, try ticks = 1000 + timeslice = 1 for regressed preemption test. */
#define SCHED_TICKS 100
/*
* CONFIG_SCHED_TICKS gives ticks per second.
* try ticks = 1000, and timeslice = 1 for regressed preemption test.
*/
/*
* A task can run continuously at this granularity,
* even if it has a greater total time slice.
*/
#define SCHED_GRANULARITY SCHED_TICKS/50
#define SCHED_GRANULARITY CONFIG_SCHED_TICKS/10
static inline struct ktcb *current_task(void)
{
@@ -37,13 +42,13 @@ static inline struct ktcb *current_task(void)
#define current current_task()
#define need_resched (current->ts_need_resched)
#define SCHED_RQ_TOTAL 2
#define SCHED_RQ_TOTAL 2
/* A basic runqueue */
struct runqueue {
struct scheduler *sched;
struct spinlock lock; /* Lock */
struct link task_list; /* List of tasks in rq */
struct link task_list; /* List of tasks in rq */
unsigned int total; /* Total tasks */
};
@@ -52,22 +57,25 @@ struct scheduler {
struct runqueue sched_rq[SCHED_RQ_TOTAL];
struct runqueue *rq_runnable;
struct runqueue *rq_expired;
struct ktcb *idle_task;
/* Total priority of all tasks in container */
int prio_total;
};
extern struct scheduler scheduler;
void sched_init_runqueue(struct runqueue *rq);
DECLARE_PERCPU(extern struct scheduler, scheduler);
void sched_init_runqueue(struct scheduler *sched, struct runqueue *rq);
void sched_init_task(struct ktcb *task, int priority);
void sched_prepare_sleep(void);
void sched_exit_sync(void);
void sched_suspend_sync(void);
void sched_suspend_async(void);
void sched_resume_sync(struct ktcb *task);
void sched_resume_async(struct ktcb *task);
void sched_enqueue_task(struct ktcb *first_time_runner, int sync);
void scheduler_start(void);
void schedule(void);
void sched_init(struct scheduler *scheduler);
void sched_init(void);
void idle_task(void);
#endif /* __SCHEDULER_H__ */

23
include/l4/generic/smp.h Normal file
View File

@@ -0,0 +1,23 @@
/*
* Copyright 2010 B Labs Ltd.
*
* Author: Prem Mallappa <prem.mallappa@b-labs.co.uk>
*/
#ifndef __GENERIC_SMP_H__
#define __GENERIC_SMP_H__
#include INC_SUBARCH(cpu.h)
/* IPIs, we define more as we go */
/* we have limited IPI's on ARM, exactly 15 */
#define IPI_TLB_FLUSH 0x00000001
#define IPI_SCHEDULE 0x00000002
#define IPI_CACH_FLUSH 0x00000003
#if !defined (CONFIG_NCPU)
#define CONFIG_NCPU 1
#define smp_get_cpuid() 0
#endif
#endif /* __GENERIC_SMP_H__ */

36
include/l4/generic/space.h
View File

@@ -1,22 +1,31 @@
/*
* Generic address space related information.
*
* Copyright (C) 2007 Bahadir Balban
* Copyright (C) 2007-2010 Bahadir Balban
*/
#ifndef __SPACE_H__
#define __SPACE_H__
/* The flags not embedded in the name behave as expected. E.g USR_RW is also */
#define MAP_USR_RW_FLAGS 0 /* CB as one would expect */
#define MAP_USR_RO_FLAGS 1 /* CB as one would expect */
#define MAP_SVC_RW_FLAGS 2 /* CB as one would expect */
#define MAP_USR_IO_FLAGS 3 /* Non-CB, RW TODO: How about RO one? */
#define MAP_SVC_IO_FLAGS 4 /* Non-CB, RW */
/*
* Generic mapping flags.
*/
#define MAP_FAULT 0
#define MAP_USR_RW 1
#define MAP_USR_RO 2
#define MAP_KERN_RW 3
#define MAP_USR_IO 4
#define MAP_KERN_IO 5
#define MAP_USR_RWX 6
#define MAP_KERN_RWX 7
#define MAP_USR_RX 8
#define MAP_KERN_RX 9
#define MAP_UNMAP 10 /* For unmap syscall */
#define MAP_INVALID_FLAGS (1 << 31)
/* Some default aliases */
#define MAP_USR_DEFAULT_FLAGS MAP_USR_RW_FLAGS
#define MAP_SVC_DEFAULT_FLAGS MAP_SVC_RW_FLAGS
#define MAP_IO_DEFAULT_FLAGS MAP_SVC_IO_FLAGS
#define MAP_USR_DEFAULT MAP_USR_RW
#define MAP_KERN_DEFAULT MAP_KERN_RW
#define MAP_IO_DEFAULT MAP_KERN_IO
#if defined (__KERNEL__)
@@ -46,11 +55,14 @@ struct address_space_list {
};
struct address_space *address_space_create(struct address_space *orig);
void address_space_delete(struct address_space *space);
void address_space_delete(struct address_space *space,
struct ktcb *task_accounted);
void address_space_attach(struct ktcb *tcb, struct address_space *space);
struct address_space *address_space_find(l4id_t spid);
void address_space_add(struct address_space *space);
void address_space_remove(struct address_space *space);
struct container;
void address_space_remove(struct address_space *space, struct container *cont);
void init_address_space_list(struct address_space_list *space_list);
int check_access(unsigned long vaddr, unsigned long size,
unsigned int flags, int page_in);

20
include/l4/generic/tcb.h
View File

@@ -28,15 +28,20 @@
#define TASK_INTERRUPTED (1 << 0)
#define TASK_SUSPENDING (1 << 1)
#define TASK_RESUMING (1 << 2)
#define TASK_EXITING (1 << 3)
#define TASK_PENDING_SIGNAL (TASK_SUSPENDING | TASK_EXITING)
#define TASK_PENDING_SIGNAL (TASK_SUSPENDING)
/*
* This is to indicate a task (either current or one of
* its children) exit has occured and cleanup needs to be
* called
*/
#define TASK_EXITED (1 << 3)
/* Task states */
enum task_state {
TASK_INACTIVE = 0,
TASK_SLEEPING = 1,
TASK_RUNNABLE = 2,
TASK_DEAD = 3,
};
#define TASK_CID_MASK 0xFF000000
@@ -82,6 +87,9 @@ struct ktcb {
l4id_t tid; /* Global thread id */
l4id_t tgid; /* Global thread group id */
/* CPU affinity */
int affinity;
/* Other related threads */
l4id_t pagerid;
@@ -94,6 +102,9 @@ struct ktcb {
/* Lock for blocking thread state modifications via a syscall */
struct mutex thread_control_lock;
/* To protect against thread deletion/modification */
struct spinlock thread_lock;
u32 ts_need_resched; /* Scheduling flag */
enum task_state state;
@@ -171,13 +182,14 @@ static inline void set_task_ids(struct ktcb *task, struct task_ids *ids)
}
struct ktcb *tcb_find(l4id_t tid);
struct ktcb *tcb_find_lock(l4id_t tid);
void tcb_add(struct ktcb *tcb);
void tcb_remove(struct ktcb *tcb);
void tcb_init(struct ktcb *tcb);
struct ktcb *tcb_alloc_init(l4id_t cid);
void tcb_delete(struct ktcb *tcb);
void tcb_delete_zombies(void);
void ktcb_list_remove(struct ktcb *task, struct ktcb_list *ktcb_list);
void ktcb_list_add(struct ktcb *new, struct ktcb_list *ktcb_list);

1
include/l4/generic/thread.h
View File

@@ -11,6 +11,7 @@ void thread_id_pool_init(void);
int thread_id_new(void);
int thread_id_del(int tid);
void thread_setup_affinity(struct ktcb *task);
void thread_destroy(struct ktcb *);
#endif /* __GENERIC_THREAD_H__ */

6
include/l4/generic/time.h
View File

@@ -4,8 +4,8 @@
* Copyright (C) 2007 Bahadir Balban
*/
#ifndef __GENERIC_TIMER_H__
#define __GENERIC_TIMER_H__
#ifndef __GENERIC_TIME_H__
#define __GENERIC_TIME_H__
/* Used by posix systems */
struct timeval {
@@ -17,4 +17,4 @@ extern volatile u32 jiffies;
int do_timer_irq(void);
#endif /* __GENERIC_TIMER_H__ */
#endif /* __GENERIC_TIME_H__ */

26
include/l4/glue/arm/cache.h Normal file
View File

@@ -0,0 +1,26 @@
/*
* Generic cache api calls
*
* Copyright (C) 2010 B Labs Ltd.
*
* Author: Bahadir Balban
*/
#ifndef __GLUE_CACHE_H__
#define __GLUE_CACHE_H__
#include INC_SUBARCH(mmu_ops.h)
/* Lowest byte is reserved for and used by capability permissions */
#define ARCH_INVALIDATE_ICACHE 0x10
#define ARCH_INVALIDATE_DCACHE 0x20
#define ARCH_CLEAN_DCACHE 0x30
#define ARCH_CLEAN_INVALIDATE_DCACHE 0x40
#define ARCH_INVALIDATE_TLB 0x50
void arch_invalidate_dcache(unsigned long start, unsigned long end);
void arch_clean_invalidate_dcache(unsigned long start, unsigned long end);
void arch_invalidate_icache(unsigned long start, unsigned long end);
void arch_invalidate_tlb(unsigned long start, unsigned long end);
void arch_clean_dcache(unsigned long start, unsigned long end);
#endif /* __GLUE_CACHE_H__ */

51
include/l4/glue/arm/debug.h Normal file
View File

@@ -0,0 +1,51 @@
/*
* ARM-specific syscall type accounting.
*
* Copyright (C) 2010 B Labs Ltd.
*
* Author: Bahadir Balban
*/
#ifndef __ARM_DEBUG_H__
#define __ARM_DEBUG_H__
#include INC_SUBARCH(perfmon.h)
#if defined (CONFIG_DEBUG_ACCOUNTING)
extern struct system_accounting system_accounting;
static inline void
system_account_syscall_type(unsigned long swi_address)
{
*(((u64 *)&system_accounting.syscalls) +
((swi_address & 0xFF) >> 2)) += 1;
}
#else /* End of CONFIG_DEBUG_ACCOUNTING */
static inline void system_account_syscall_type(unsigned long swi_address) { }
#endif /* End of !CONFIG_DEBUG_ACCOUNTING */
#if defined (CONFIG_DEBUG_PERFMON_KERNEL)
static inline void
system_measure_syscall_start(void)
{
/* To avoid non-voluntary rescheduling during call */
perfmon_reset_start_cyccnt();
}
/* Defined in arm/glue/debug.c */
void system_measure_syscall_end(unsigned long swi_address);
#else /* End of CONFIG_DEBUG_PERFMON_KERNEL */
static inline void system_measure_syscall_start(void) { }
static inline void system_measure_syscall_end(unsigned long swi_address) { }
#endif /* End of !CONFIG_DEBUG_PERFMON_KERNEL */
#endif /* __ARM_DEBUG_H__ */

14
include/l4/glue/arm/init.h
View File

@@ -1,3 +1,8 @@
/*
* Copyright (C) 2010 B Labs Ltd.
* Author: Prem Mallappa <prem.mallappa@b-labs.co.uk>
*/
#ifndef __ARM_GLUE_INIT_H__
#define __ARM_GLUE_INIT_H__
@@ -8,5 +13,14 @@ void switch_to_user(struct ktcb *inittask);
void timer_start(void);
extern struct address_space init_space;
void init_kernel_mappings(void);
void start_virtual_memory(void);
void finalize_virtual_memory(void);
void init_finalize(void);
void remove_section_mapping(unsigned long vaddr);
void vectors_init(void);
void setup_idle_caps(void);
void setup_idle_task(void);
#endif /* __ARM_GLUE_INIT_H__ */

18
include/l4/glue/arm/ipi.h Normal file
View File

@@ -0,0 +1,18 @@
#ifndef __IPI_H__
#define __IPI_H__
/*
* Copyright 2010 B Labs.Ltd.
*
* Author: Prem Mallappa <prem.mallappa@b-labs.co.uk>
*
* Description:
*/
#include <l4/generic/irq.h>
int ipi_handler(struct irq_desc *desc);
#endif /* __IPI_H__ */

89
include/l4/glue/arm/mapping.h Normal file
View File

@@ -0,0 +1,89 @@
/*
* Generic mapping operations
*
* Operations on address space mappings that
* all subarchitectures support generically.
*
* Copyright (C) 2008 - 2010 B Labs Ltd.
* Written by Bahadir Balban
*/
#ifndef __ARM_GLUE_MAPPING_H__
#define __ARM_GLUE_MAPPING_H__
#include INC_SUBARCH(mm.h)
#define TASK_PGD(x) (x)->space->pgd
unsigned int space_flags_to_ptflags(unsigned int flags);
void add_mapping_pgd(unsigned long paddr, unsigned long vaddr,
unsigned int size, unsigned int flags,
pgd_table_t *pgd);
void add_mapping(unsigned long paddr, unsigned long vaddr,
unsigned int size, unsigned int flags);
void add_boot_mapping(unsigned long paddr, unsigned long vaddr,
unsigned int size, unsigned int flags);
int remove_mapping(unsigned long vaddr);
int remove_mapping_pgd(pgd_table_t *pgd, unsigned long vaddr);
void remove_mapping_pgd_all_user(pgd_table_t *pgd);
int check_mapping_pgd(unsigned long vaddr, unsigned long size,
unsigned int flags, pgd_table_t *pgd);
int check_mapping(unsigned long vaddr, unsigned long size,
unsigned int flags);
void copy_pgd_kern_all(pgd_table_t *);
struct address_space;
int delete_page_tables(struct address_space *space);
int copy_user_tables(struct address_space *new, struct address_space *orig);
void remap_as_pages(void *vstart, void *vend);
void copy_pgds_by_vrange(pgd_table_t *to, pgd_table_t *from,
unsigned long start, unsigned long end);
/*
* TODO: Some of these may be made inline by
* removing their signature from here completely
* and creating an arch-specific mapping.h which
* has inline definitions or just signatures.
*/
pte_t virt_to_pte(unsigned long vaddr);
pte_t *virt_to_ptep(unsigned long vaddr);
pte_t virt_to_pte_from_pgd(pgd_table_t *pgd, unsigned long vaddr);
unsigned long virt_to_phys_by_pgd(pgd_table_t *pgd, unsigned long vaddr);
void arch_prepare_pte(u32 paddr, u32 vaddr, unsigned int flags,
pte_t *ptep);
void arch_write_pte(pte_t *ptep, pte_t pte, u32 vaddr);
void arch_prepare_write_pte(u32 paddr, u32 vaddr,
unsigned int flags, pte_t *ptep);
pmd_t *arch_pick_pmd(pgd_table_t *pgd, unsigned long vaddr);
void arch_write_pmd(pmd_t *pmd_entry, u32 pmd_phys, u32 vaddr);
int arch_check_pte_access_perms(pte_t pte, unsigned int flags);
pgd_table_t *arch_realloc_page_tables(void);
void arch_copy_pgd_kernel_entries(pgd_table_t *to);
int is_global_pgdi(int i);
struct ktcb;
void arch_space_switch(struct ktcb *task);
int pgd_count_boot_pmds();
void idle_task(void);
#endif /* __ARM_GLUE_MAPPING_H__ */

25
include/l4/glue/arm/memlayout.h
View File

@@ -27,19 +27,24 @@
/* ARM-specific offset in KIP that tells the address of UTCB page */
#define UTCB_KIP_OFFSET 0x50
#define IO_AREA0_VADDR (IO_AREA_START + (ARM_SECTION_SIZE*0))
#define IO_AREA1_VADDR (IO_AREA_START + (ARM_SECTION_SIZE*1))
#define IO_AREA2_VADDR (IO_AREA_START + (ARM_SECTION_SIZE*2))
#define IO_AREA3_VADDR (IO_AREA_START + (ARM_SECTION_SIZE*3))
#define IO_AREA4_VADDR (IO_AREA_START + (ARM_SECTION_SIZE*4))
#define IO_AREA5_VADDR (IO_AREA_START + (ARM_SECTION_SIZE*5))
#define IO_AREA6_VADDR (IO_AREA_START + (ARM_SECTION_SIZE*6))
#define IO_AREA7_VADDR (IO_AREA_START + (ARM_SECTION_SIZE*7))
#define IO_AREA0_VADDR IO_AREA_START
#define IO_AREA1_VADDR (IO_AREA_START + (SZ_1MB*1))
#define IO_AREA2_VADDR (IO_AREA_START + (SZ_1MB*2))
#define IO_AREA3_VADDR (IO_AREA_START + (SZ_1MB*3))
#define IO_AREA4_VADDR (IO_AREA_START + (SZ_1MB*4))
#define IO_AREA5_VADDR (IO_AREA_START + (SZ_1MB*5))
#define IO_AREA6_VADDR (IO_AREA_START + (SZ_1MB*6))
#define IO_AREA7_VADDR (IO_AREA_START + (SZ_1MB*7))
/*
* IO_AREA8_VADDR
* The beginning page in this slot is used for userspace uart mapping
*/
#define ARM_HIGH_VECTOR 0xFFFF0000
#define ARM_SYSCALL_VECTOR 0xFFFFFF00
#define KERNEL_OFFSET (KERNEL_AREA_START - PHYS_MEM_START)
#define KERNEL_OFFSET (KERNEL_AREA_START - PLATFORM_PHYS_MEM_START)
/* User tasks define them differently */
#if defined (__KERNEL__)
@@ -49,7 +54,7 @@
#define KERN_ADDR(x) ((x >= KERNEL_AREA_START) && (x < KERNEL_AREA_END))
#define UTCB_ADDR(x) ((x >= UTCB_AREA_START) && (x < UTCB_AREA_END))
#define PRIVILEGED_ADDR(x) (KERN_ADDR(x) || (x >= ARM_HIGH_VECTOR) || \
#define is_kernel_address(x) (KERN_ADDR(x) || (x >= ARM_HIGH_VECTOR) || \
(x >= IO_AREA_START && x < IO_AREA_END))
#endif /* __MEMLAYOUT_H__ */

66
include/l4/glue/arm/memory.h
View File

@@ -11,35 +11,32 @@
#include INC_SUBARCH(mm.h)
/* Generic definitions */
#define PAGE_SIZE ARM_PAGE_SIZE
#define PAGE_MASK ARM_PAGE_MASK
#define PAGE_BITS ARM_PAGE_BITS
/*
* This defines the largest size defined by this architecture that is
* easily mappable. ARM supports 1MB mappings so it fits well. If it's
* unsupported by the arch then a reasonable size could be 1MB.
*/
#define SECTION_SIZE ARM_SECTION_SIZE
#define SECTION_MASK ARM_SECTION_MASK
#define SECTION_BITS ARM_SECTION_BITS
#define PFN_SHIFT 12
#define PAGE_BITS PFN_SHIFT
#define PAGE_SIZE SZ_4K
#define PAGE_MASK (PAGE_SIZE - 1)
/* Aligns to the upper page (ceiling) FIXME: Must add a wraparound checker. */
#define page_align_up(addr) ((((unsigned int)(addr)) + \
(PAGE_SIZE - 1)) & \
(~PAGE_MASK))
/* Aligns to the lower page (floor) */
#define page_align(addr) (((unsigned int)(addr)) & \
#define page_align_up(addr) ((((unsigned long)(addr)) + PAGE_MASK) & \
(~PAGE_MASK))
#define is_aligned(val, size) (!(((unsigned long)(val)) & ((size) - 1)))
/* Aligns to the lower page (floor) */
#define page_align(addr) (((unsigned long)(addr)) & \
(~PAGE_MASK))
#define is_aligned(val, size) (!(((unsigned long)(val)) & (((unsigned long)size) - 1)))
#define is_page_aligned(val) (!(((unsigned long)(val)) & PAGE_MASK))
#define page_boundary(x) is_page_aligned(x)
/* Align to given size */
#define align(addr, size) (((unsigned int)(addr)) & (~(size-1)))
/*
* Align to given size.
*
* Note it must be an alignable size i.e. one that is a power of two.
* E.g. 0x1000 would work but 0x1010 would not.
*/
#define align(addr, size) (((unsigned int)(addr)) & (~((unsigned long)size-1)))
#define align_up(addr, size) ((((unsigned long)(addr)) + \
((size) - 1)) & (~((size) - 1)))
((size) - 1)) & (~(((unsigned long)size) - 1)))
/* The bytes left until the end of the page that x is in */
#define TILL_PAGE_ENDS(x) (PAGE_SIZE - ((unsigned long)(x) & PAGE_MASK))
@@ -58,6 +55,8 @@
#define BITWISE_GETWORD(x) ((x) >> WORD_BITS_LOG2) /* Divide by 32 */
#define BITWISE_GETBIT(x) (1 << ((x) % WORD_BITS))
/* Minimum stack alignment restriction across functions, exceptions */
#define STACK_ALIGNMENT 8
/* Endianness conversion */
static inline void be32_to_cpu(unsigned int x)
@@ -75,31 +74,6 @@ static inline void be32_to_cpu(unsigned int x)
p[2] = tmp;
}
void paging_init(void);
unsigned int space_flags_to_ptflags(unsigned int flags);
void add_mapping_pgd(unsigned int paddr, unsigned int vaddr,
unsigned int size, unsigned int flags,
pgd_table_t *pgd);
void add_mapping(unsigned int paddr, unsigned int vaddr,
unsigned int size, unsigned int flags);
int remove_mapping(unsigned long vaddr);
int remove_mapping_pgd(unsigned long vaddr, pgd_table_t *pgd);
int remove_mapping_pgd_all_user(pgd_table_t *pgd);
void prealloc_phys_pagedesc(void);
int check_mapping_pgd(unsigned long vaddr, unsigned long size,
unsigned int flags, pgd_table_t *pgd);
int check_mapping(unsigned long vaddr, unsigned long size,
unsigned int flags);
void copy_pgd_kern_all(pgd_table_t *);
pte_t virt_to_pte(unsigned long virtual);
pte_t virt_to_pte_from_pgd(unsigned long virtual, pgd_table_t *pgd);
unsigned long virt_to_phys_by_pgd(unsigned long vaddr, pgd_table_t *pgd);
struct ktcb;
void task_init_registers(struct ktcb *task, unsigned long pc);

46
include/l4/glue/arm/smp.h Normal file
View File

@@ -0,0 +1,46 @@
/*
* Copyright 2010 B Labs Ltd.
*
* Authors: Prem Mallappa, Bahadir Balban
*
* SMP support
*/
#ifndef __GLUE_ARM_SMP_H__
#define __GLUE_ARM_SMP_H__
#include INC_ARCH(scu.h)
struct cpuinfo {
u32 ncpus;
u32 flags;
volatile u32 cpu_spinning;
void (*send_ipi)(int cpu, int ipi_cmd);
void (*smp_spin)(void);
void (*smp_finish)(void);
} __attribute__ ((__packed__));
extern struct cpuinfo cpuinfo;
#if defined(CONFIG_SMP)
void smp_attach(void);
void smp_start_cores(void);
#else
static inline void smp_attach(void) {}
static inline void smp_start_cores(void) {}
#endif
void init_smp(void);
void arch_smp_spin(void);
void arch_send_ipi(u32 cpu, int ipi);
void platform_smp_init(int ncpus);
int platform_smp_start(int cpu, void (*start)(int));
void secondary_init_platform(void);
extern unsigned long secondary_run_signal;
#define CPUID_TO_MASK(cpu) (1 << (cpu))
#endif

21
include/l4/lib/list.h
View File

@@ -68,6 +68,7 @@ static inline void list_remove_init(struct link *link)
struct link *prev = link->prev;
struct link *next = link->next;
//BUG_ON(prev == NULL || next == NULL || link == NULL);
prev->next = next;
next->prev = prev;
@@ -87,6 +88,26 @@ static inline struct link *list_detach(struct link *head)
return next;
}
/* append new_list to list given by head/end pair */
static inline void list_attach(struct link *new_list, struct link *head, struct link *end)
{
/* attach new list at the end of original list */
end->next = new_list;
new_list->prev = end;
/* go to the end of list to be attached */
while (new_list->next != end->next)
new_list = new_list->next;
/* set end nodes properly */
new_list->next = head;
head->prev = new_list;
/* set end to new end */
end = new_list;
}
static inline int list_empty(struct link *list)
{
return list->prev == list && list->next == list;

10
include/l4/lib/math.h
View File

@@ -1,6 +1,16 @@
#ifndef __LIB_MATH_H__
#define __LIB_MATH_H__
/* Take the power */
static inline int pow(int val, int exp)
{
int res = 1;
for (int i = 0; i < exp; i++)
res *= val;
return res;
}
static inline int min(int x, int y)
{
return x < y ? x : y;

7
include/l4/lib/printk.h
View File

@@ -4,15 +4,12 @@
#include <stdarg.h>
#if defined(ARCH_TEST)
/* For host tests all printks mean printf using the host C library */
#include <stdio.h>
#define printk printf
#elif !defined(__KERNEL__)
#if !defined(__KERNEL__)
#define printk printf
#else
int printk(char *format, ...) __attribute__((format (printf, 1, 2)));
extern void putc(char c);
void init_printk_lock(void);
#endif
#endif /* __PRINTK_H__ */

28
include/l4/lib/spinlock.h
View File

@@ -3,12 +3,21 @@
#include <l4/lib/string.h>
#include <l4/generic/preempt.h>
#include INC_ARCH(exception.h)
#include INC_ARCH(irq.h)
#include INC_ARCH(mutex.h)
struct spinlock {
unsigned int lock;
};
#define DECLARE_SPINLOCK(lockname) \
struct spinlock lockname = { \
.lock = 0, \
}
void spin_lock_record_check(void *lock_addr);
void spin_unlock_delete_check(void *lock_addr);
static inline void spin_lock_init(struct spinlock *s)
{
memset(s, 0, sizeof(struct spinlock));
@@ -22,6 +31,10 @@ static inline void spin_lock(struct spinlock *s)
{
preempt_disable(); /* This must disable local preempt */
#if defined(CONFIG_SMP)
#if defined (CONFIG_DEBUG_SPINLOCKS)
spin_lock_record_check(s);
#endif
__spin_lock(&s->lock);
#endif
}
@@ -29,6 +42,10 @@ static inline void spin_lock(struct spinlock *s)
static inline void spin_unlock(struct spinlock *s)
{
#if defined(CONFIG_SMP)
#if defined (CONFIG_DEBUG_SPINLOCKS)
spin_unlock_delete_check(s);
#endif
__spin_unlock(&s->lock);
#endif
preempt_enable();
@@ -44,6 +61,10 @@ static inline void spin_lock_irq(struct spinlock *s,
{
irq_local_disable_save(state);
#if defined(CONFIG_SMP)
#if defined (CONFIG_DEBUG_SPINLOCKS)
spin_lock_record_check(s);
#endif
__spin_lock(&s->lock);
#endif
}
@@ -52,6 +73,11 @@ static inline void spin_unlock_irq(struct spinlock *s,
unsigned long state)
{
#if defined(CONFIG_SMP)
#if defined (CONFIG_DEBUG_SPINLOCKS)
spin_unlock_delete_check(s);
#endif
__spin_unlock(&s->lock);
#endif
irq_local_restore(state);

29
include/l4/macros.h
View File

@@ -9,7 +9,6 @@
* source file, using gcc's -imacro command line option. Only macro
* definitions will be extracted.
*/
#define INC_ARCH(x) <l4/arch/__ARCH__/x>
#define INC_SUBARCH(x) <l4/arch/__ARCH__/__SUBARCH__/x>
#define INC_CPU(x) <l4/arch/__ARCH__/__SUBARCH__/__CPU__/x>
@@ -19,9 +18,16 @@
#define __initdata SECTION(".init.data")
/*
* FIXME: Remove __CPP__
* This is defined in kernel linker.lds.in,
* find some better way.
*/
#if !defined(__CPP__)
/* use this to place code/data in a certain section */
#define SECTION(x) __attribute__((section(x)))
#define ALIGN(x) __attribute__((aligned (x)))
#endif
/* Functions for critical path optimizations */
#if (__GNUC__ >= 3)
@@ -40,11 +46,13 @@
#endif
/* Convenience functions for memory sizes. */
#define SZ_1K 1024
#define SZ_2K 2048
#define SZ_4K 0x1000
#define SZ_16K 0x4000
#define SZ_32K 0x8000
#define SZ_64K 0x10000
#define SZ_1MB 0x100000
#define SZ_2MB 0x200000
#define SZ_4MB (4*SZ_1MB)
#define SZ_8MB (8*SZ_1MB)
#define SZ_16MB (16*SZ_1MB)
@@ -53,6 +61,25 @@
#define SZ_16K_BITS 14
#define SZ_1MB_BITS 20
/* Per-cpu variables */
#if defined CONFIG_SMP
#define DECLARE_PERCPU(type, name) \
type name[CONFIG_NCPU]
#define per_cpu(val) (val)[smp_get_cpuid()]
#define per_cpu_byid(val, cpu) (val)[(cpu)]
#else /* Not CONFIG_SMP */
#define DECLARE_PERCPU(type, name) \
type name
#define per_cpu(val) (val)
#define per_cpu_byid(val, cpu) val
#endif /* End of Not CONFIG_SMP */
#ifndef __ASSEMBLY__
#include <stddef.h> /* offsetof macro, defined in the `standard' way. */
#endif

25
include/l4/platform/beagle/cm.h Normal file
View File

@@ -0,0 +1,25 @@
/*
* Clock mangaer module of the beagleboard.
*
* Copyright (C) 2007 Bahadir Balban
*
*/
#ifndef __PLATFORM_BEAGLE_CM_H__
#define __PLATFORM_BEAGLE_CM_H__
/*
* Register offsets for Clock Manager(CM)
* PER_CM, WKUP_CM etc all have same offsets
* for registers
*/
#define CM_FCLKEN_OFFSET 0x00
#define CM_ICLKEN_OFFSET 0x10
#define CM_CLKSEL_OFFSET 0x40
void omap_cm_enable_iclk(unsigned long cm_base, int bit);
void omap_cm_enable_fclk(unsigned long cm_base, int bit);
void omap_cm_clk_select(unsigned long cm_base, int bit, int src);
#endif /* __PLATFORM_BEAGLE_CM_H__ */

35
include/l4/platform/beagle/irq.h Normal file
View File

@@ -0,0 +1,35 @@
#ifndef __PLATFORM_IRQ_H__
#define __PLATFORM_IRQ_H__
/*
* Support for generic irq handling using platform irq controller (GIC)
*
* Copyright (C) 2007 Bahadir Balban
*/
/* TODO: Not sure about this, need to check */
#define IRQ_CHIPS_MAX 1
#define IRQS_MAX 96
/* IRQ indices. */
#define IRQ_UART0 72
#define IRQ_UART1 73
#define IRQ_UART2 74
/* General Purpose Timers */
#define IRQ_TIMER0 37
#define IRQ_TIMER1 38
#define IRQ_TIMER2 39
#define IRQ_TIMER3 40
#define IRQ_TIMER4 41
#define IRQ_TIMER5 42
#define IRQ_TIMER6 43
#define IRQ_TIMER7 44
#define IRQ_TIMER8 45
#define IRQ_TIMER9 46
#define IRQ_TIMER10 47
#define IRQ_TIMER11 95
#endif /* __PLATFORM_IRQ_H__ */

66
include/l4/platform/beagle/offsets.h Normal file
View File

@@ -0,0 +1,66 @@
/*
*
* Describes physical memory layout of Beagle Boards.
* We have rev3 boards.
*
* Copyright (C) 2007 Bahadir Balban
*/
#ifndef __PLATFORM_BEAGLE_OFFSETS_H__
#define __PLATFORM_BEAGLE_OFFSETS_H__
/*
* Physical memory base
* FIXME: Somewhere its written: Rev 1 and 2
* of Beagleboard has 128MB SDRAM while Rev 3 has 256MB
* SDRAM which is detected automatically on intiliazation,
* we have Rev3 boards, so hardcoding this only.
*/
#define PLATFORM_PHYS_MEM_START 0x80000000 /* inclusive */
#define PLATFORM_PHYS_MEM_END 0x90000000 /* 256MB, exclusive */
/*
* Device offsets in physical memory
* Naming of devices done starting with 0 subscript,
* as we use these names for device capability
*/
#define PLATFORM_WKUP_CM_BASE 0x48004C00 /* Wake up clock manager */
#define PLATFORM_PERCM_BASE 0x48005000 /* Peripheral Clock Manager */
#define PLATFORM_UART0_BASE 0x4806A000 /* UART 0 */
#define PLATFORM_UART1_BASE 0x4806C000 /* UART 1 */
#define PLATFORM_UART2_BASE 0x49020000 /* UART 2 */
#define PLATFORM_TIMER0_BASE 0x48318000 /* GPTIMER1 */
#define PLATFORM_TIMER1_BASE 0x49032000 /* GPTIMER2 */
#define PLATFORM_TIMER2_BASE 0x49034000 /* GPTIMER3 */
#define PLATFORM_TIMER3_BASE 0x49036000 /* GPTIMER4 */
#define PLATFORM_TIMER4_BASE 0x49038000 /* GPTIMER5 */
#define PLATFORM_TIMER5_BASE 0x4903A000 /* GPTIMER6 */
#define PLATFORM_TIMER6_BASE 0x4903C000 /* GPTIMER7 */
#define PLATFORM_TIMER7_BASE 0x4903E000 /* GPTIMER8 */
#define PLATFORM_TIMER8_BASE 0x49040000 /* GPTIMER9 */
#define PLATFORM_TIMER9_BASE 0x48086000 /* GPTIMER10 */
#define PLATFORM_TIMER10_BASE 0x48088000 /* GPTIMER11 */
#define PLATFORM_TIMER11_BASE 0x48304000 /* GPTIMER12 */
#define PLATFORM_INTC_BASE 0x48200000 /* Interrupt controller */
/*
* Virtual Memory base address, where devices will be mapped.
* Each Device will take one page in virtual memory.
* Nice and smooth.
*/
#define DEVICE_PAGE 0x1000
#define PLATFORM_WKUP_CM_VBASE (IO_AREA0_VADDR + (0 * DEVICE_PAGE))
#define PLATFORM_CONSOLE_VBASE (IO_AREA0_VADDR + (1 * DEVICE_PAGE))
#define PLATFORM_TIMER0_VBASE (IO_AREA0_VADDR + (2 * DEVICE_PAGE))
#define PLATFORM_INTC_VBASE (IO_AREA0_VADDR + (3 * DEVICE_PAGE))
#define PLATFORM_PERCM_VBASE (IO_AREA0_VADDR + (4 * DEVICE_PAGE))
/* Add userspace devices here as they become necessary for irqs */
#define PLATFORM_TIMER1_VBASE (IO_AREA0_VADDR + (5 * DEVICE_PAGE))
/* Add size of various user space devices, to be used in capability generation */
#define PLATFORM_TIMER1_SIZE DEVICE_PAGE
#endif /* __PLATFORM_BEAGLE_OFFSETS_H__ */

18
include/l4/platform/beagle/platform.h Normal file
View File

@@ -0,0 +1,18 @@
#ifndef __BEAGLE_PLATFORM_H__
#define __BEAGLE_PLATFORM_H__
/*
* Platform specific ties between drivers and generic APIs used by the kernel.
* E.g. system timer and console.
*
* Copyright (C) Bahadir Balban 2007
*/
#include INC_PLAT(offsets.h)
#include INC_GLUE(memlayout.h)
#include <l4/generic/capability.h>
#include <l4/generic/cap-types.h>
void platform_timer_start(void);
void platform_test_cpucycles(void);
#endif /* __BEAGLE_PLATFORM_H__ */

13
include/l4/platform/beagle/timer.h Normal file
View File

@@ -0,0 +1,13 @@
/*
* Platform encapsulation over timer driver.
*
* Copyright (C) 2007 Bahadir Balban
*
*/
#ifndef __PLATFORM_BEAGLE_TIMER_H__
#define __PLATFORM_BEAGLE_TIMER_H__
#include <l4/drivers/timer/omap/timer.h>
#endif /* __PLATFORM_BEAGLE_TIMER_H__ */

13
include/l4/platform/beagle/uart.h Normal file
View File

@@ -0,0 +1,13 @@
/*
* Platform specific ties to generic uart functions that putc expects.
*
* Copyright (C) 2007 Bahadir Balban
*
*/
#ifndef __PLATFORM_BEAGLE_UART_H__
#define __PLATFORM_BEAGLE_UART_H__
#include <l4/drivers/uart/omap/uart.h>
#endif /* __PLATFORM_BEAGLE_UART_H__ */

83
include/l4/platform/eb/irq.h
View File

@@ -1,26 +1,20 @@
/*
* Copyright (C) 2009 B Labs Ltd.
*/
#ifndef __PLATFORM_IRQ_H__
#define __PLATFORM_IRQ_H__
/* TODO: Not sure about this, need to check */
#define IRQ_CHIPS_MAX 4
#define IRQS_MAX 96
/* Actually there are 4 GIC's on the EB, only 2 are used for tile site 1 */
#define IRQ_CHIPS_MAX 2
#if defined(CONFIG_CPU_ARM11MPCORE) || defined (CONFIG_CPU_CORTEXA9)
#define IRQS_MAX 64
#else
#define IRQS_MAX 96
#endif
/*
* IRQ indices,
* GIC 0 and 1 are for logic tile 1
* GIC 2 and 3 are for logic tile 2
*/
#define IRQ_TIMER01 4
#define IRQ_TIMER23 5
#define IRQ_RTC 10
#define IRQ_UART0 12
#define IRQ_UART1 13
#define IRQ_UART2 14
#define IRQ_UART3 15
/*
* TODO: Seems like GIC0 and GIC1 are cascaded for logic tile1
* and GIC2 and GIC3 are cascaded for logic tile 2.
* Interrupt Distribution:
* 0-31: Used as SI provided by distributed interrupt controller
* 32-63: Externel Peripheral Interrupts
@@ -28,4 +22,57 @@
* 72-79: Interrupts from tile site 2
* 80-95: PCI and reserved Interrupts
*/
#define EB_GIC_IRQ_OFFSET 32
#define EB_IRQ_WATCHDOG (EB_GIC_IRQ_OFFSET + 0)
#define EB_IRQ_SOFTINT (EB_GIC_IRQ_OFFSET + 1)
#define EB_IRQ_COMRX (EB_GIC_IRQ_OFFSET + 2)
#define EB_IRQ_COMTX (EB_GIC_IRQ_OFFSET + 3)
#define EB_IRQ_TIMER01 (EB_GIC_IRQ_OFFSET + 4)
#define EB_IRQ_TIMER23 (EB_GIC_IRQ_OFFSET + 5)
#define EB_IRQ_GPIO0 (EB_GIC_IRQ_OFFSET + 6)
#define EB_IRQ_GPIO1 (EB_GIC_IRQ_OFFSET + 7)
#define EB_IRQ_GPIO2 (EB_GIC_IRQ_OFFSET + 8)
#define EB_IRQ_RTC (EB_GIC_IRQ_OFFSET + 10)
#define EB_IRQ_UART0 (EB_GIC_IRQ_OFFSET + 12)
#define EB_IRQ_UART1 (EB_GIC_IRQ_OFFSET + 13)
#define EB_IRQ_UART2 (EB_GIC_IRQ_OFFSET + 14)
#define EB_IRQ_UART3 (EB_GIC_IRQ_OFFSET + 15)
#define EB_IRQ_SCI (EB_GIC_IRQ_OFFSET + 16) /* Smart Card Interface */
#define EB_IRQ_MCI0 (EB_GIC_IRQ_OFFSET + 17)
#define EB_IRQ_MCI1 (EB_GIC_IRQ_OFFSET + 18)
#define EB_IRQ_AACI (EB_GIC_IRQ_OFFSET + 19) /* Advanced Audio codec */
#define EB_IRQ_KMI0 (EB_GIC_IRQ_OFFSET + 20) /* Keyboard */
#define EB_IRQ_KMI1 (EB_GIC_IRQ_OFFSET + 21) /* Mouse */
#define EB_IRQ_LCD (EB_GIC_IRQ_OFFSET + 20) /* Character LCD */
#define EB_IRQ_DMAC (EB_GIC_IRQ_OFFSET + 20) /* DMA Controller */
/* Interrupt Sources to ARM 11 MPCore or EB+A9 MPCore GIC */
#define MPCORE_GIC_IRQ_AACI (EB_GIC_IRQ_OFFSET + 0)
#define MPCORE_GIC_IRQ_TIMER01 (EB_GIC_IRQ_OFFSET + 1)
#define MPCORE_GIC_IRQ_TIMER23 (EB_GIC_IRQ_OFFSET + 2)
#define MPCORE_GIC_IRQ_USB (EB_GIC_IRQ_OFFSET + 3)
#define MPCORE_GIC_IRQ_UART0 (EB_GIC_IRQ_OFFSET + 4)
#define MPCORE_GIC_IRQ_UART1 (EB_GIC_IRQ_OFFSET + 5)
#define MPCORE_GIC_IRQ_RTC (EB_GIC_IRQ_OFFSET + 6)
#define MPCORE_GIC_IRQ_KMI0 (EB_GIC_IRQ_OFFSET + 7)
#define MPCORE_GIC_IRQ_KMI1 (EB_GIC_IRQ_OFFSET + 8)
#define MPCORE_GIC_IRQ_ETH (EB_GIC_IRQ_OFFSET + 9)
/* Interrupt from GIC1 on Base board */
#define MPCORE_GIC_IRQ_EB_GIC1 (EB_GIC_IRQ_OFFSET + 10)
#define MPCORE_GIC_IRQ_EB_GIC2 (EB_GIC_IRQ_OFFSET + 11)
#define MPCORE_GIC_IRQ_EB_GIC3 (EB_GIC_IRQ_OFFSET + 12)
#define MPCORE_GIC_IRQ_EB_GIC4 (EB_GIC_IRQ_OFFSET + 13)
#if defined (CONFIG_CPU_ARM11MPCORE) || defined (CONFIG_CPU_CORTEXA9)
#define IRQ_TIMER0 MPCORE_GIC_IRQ_TIMER01
#define IRQ_TIMER1 MPCORE_GIC_IRQ_TIMER23
#else
#define IRQ_TIMER0 EB_IRQ_TIMER01
#define IRQ_TIMER1 EB_IRQ_TIMER23
#endif
#endif /* __PLATFORM_IRQ_H__ */

100
include/l4/platform/eb/offsets.h
View File

@@ -1,71 +1,61 @@
/*
* Describes physical memory layout of EB platform.
*
* Copyright (C) 2007 Bahadir Balban
* This only include physical and memory offsets that
* are not included in realview/offsets.h
*
* Copyright (C) 2009 B Labs Ltd.
* Author: Prem Mallappa <prem.mallappa@b-labs.co.uk>
*/
#ifndef __PLATFORM_EB_OFFSETS_H__
#define __PLATFORM_EB_OFFSETS_H__
/* Physical memory base */
#define PHYS_MEM_START 0x00000000 /* inclusive */
#define PHYS_MEM_END 0x10000000 /* 256 MB, exclusive */
/*
* These bases taken from where kernel is `physically' linked at,
* also used to calculate virtual-to-physical translation offset.
* See the linker script for their sources. PHYS_ADDR_BASE can't
* use a linker variable because it's referred from assembler.
*/
#define PHYS_ADDR_BASE 0x100000
/* Device memory base */
#define EB_DEV_PHYS 0x10000000
#include <l4/platform/realview/offsets.h>
/* Device offsets in physical memory */
#define EB_SYSTEM_REGISTERS 0x10000000 /* System registers */
#define EB_SYSCTRL_BASE 0x10001000 /* System controller */
#define EB_UART0_BASE 0x10009000 /* UART 0 */
#define EB_UART1_BASE 0x1000A000 /* UART 1 */
#define EB_UART2_BASE 0x1000B000 /* UART 2 */
#define EB_UART3_BASE 0x1000C000 /* UART 3 */
#define EB_WATCHDOG0_BASE 0x10010000 /* WATCHDOG */
#define EB_TIMER01_BASE 0x10011000 /* TIMER 0-1 */
#define EB_TIMER23_BASE 0x10012000 /* TIMER 2-3 */
#define EB_RTC_BASE 0x10017000 /* RTC interface */
#define EB_GIC0_BASE 0x10040000 /* GIC 0 */
#define EB_GIC1_BASE 0x10050000 /* GIC 1 */
#define EB_GIC2_BASE 0x10060000 /* GIC 2 */
#define EB_GIC3_BASE 0x10070000 /* GIC 3 */
#define PLATFORM_GIC1_BASE 0x10040000 /* GIC 1 */
#define PLATFORM_GIC2_BASE 0x10050000 /* GIC 2 */
#define PLATFORM_GIC3_BASE 0x10060000 /* GIC 3 */
#define PLATFORM_GIC4_BASE 0x10070000 /* GIC 4 */
/*
* Uart virtual address until a file-based console access
* is available for userspace
*/
#define USERSPACE_UART_BASE 0x500000
#define MPCORE_PRIVATE_VBASE (IO_AREA0_VADDR + (13 * DEVICE_PAGE))
/*
* Device offsets in virtual memory. They offset to some virtual
* device base address. Each page on this virtual base is consecutively
* allocated to devices. Nice and smooth.
*/
#define EB_SYSREGS_VOFFSET 0x00000000
#define EB_SYSCTRL_VOFFSET 0x00001000
#define EB_UART0_VOFFSET 0x00002000
#define EB_TIMER01_VOFFSET 0x00003000
#define EB_GIC0_VOFFSET 0x00004000
#define EB_GIC1_VOFFSET 0x00005000
#define EB_GIC2_VOFFSET 0x00006000
#define EB_GIC3_VOFFSET 0x00007000
#if defined (CONFIG_CPU_CORTEXA9)
#define MPCORE_PRIVATE_BASE 0x1F000000
#endif /* End CORTEXA9 */
#define EB_SYSREGS_VBASE (IO_AREA0_VADDR + EB_SYSREGS_VOFFSET)
#define EB_SYSCTRL_VBASE (IO_AREA0_VADDR + EB_SYSCTRL_VOFFSET)
#define EB_UART0_VBASE (IO_AREA0_VADDR + EB_UART0_VOFFSET)
#define EB_TIMER01_VBASE (IO_AREA0_VADDR + EB_TIMER01_VOFFSET)
#define EB_GIC0_VBASE (IO_AREA0_VADDR + EB_GIC0_VOFFSET)
#define EB_GIC1_VBASE (IO_AREA0_VADDR + EB_GIC1_VOFFSET)
#define EB_GIC2_VBASE (IO_AREA0_VADDR + EB_GIC2_VOFFSET)
#define EB_GIC3_VBASE (IO_AREA0_VADDR + EB_GIC3_VOFFSET)
#if defined (CONFIG_CPU_ARM11MPCORE)
#if defined REV_C || defined REV_D
#define MPCORE_PRIVATE_BASE 0x1F000000
#else /* REV_B and QEMU */
#define MPCORE_PRIVATE_BASE 0x10100000
#endif /* End REV_B and QEMU */
#endif /* End ARM11MPCORE */
#if defined (CONFIG_CPU_CORTEXA9) || defined (CONFIG_CPU_ARM11MPCORE)
/* MPCore private memory region */
#define SCU_BASE MPCORE_PRIVATE_BASE
#define SCU_VBASE MPCORE_PRIVATE_VBASE
#define GIC0_CPU_VBASE (MPCORE_PRIVATE_VBASE + 0x100)
#define GIC0_DIST_VBASE (MPCORE_PRIVATE_VBASE + 0x1000)
#endif /* End CORTEXA9 || ARM11MPCORE */
#define GIC1_CPU_VBASE (PLATFORM_GIC1_VBASE + 0x0)
#define GIC2_CPU_VBASE (PLATFORM_GIC2_VBASE + 0x0)
#define GIC3_CPU_VBASE (PLATFORM_GIC3_VBASE + 0x0)
#define GIC4_CPU_VBASE (PLATFORM_GIC4_VBASE + 0x0)
#define GIC1_DIST_VBASE (PLATFORM_GIC1_VBASE + 0x1000)
#define GIC2_DIST_VBASE (PLATFORM_GIC2_VBASE + 0x1000)
#define GIC3_DIST_VBASE (PLATFORM_GIC3_VBASE + 0x1000)
#define GIC4_DIST_VBASE (PLATFORM_GIC4_VBASE + 0x1000)
#if defined (CONFIG_CPU_ARM11MPCORE) || defined (CONFIG_CPU_CORTEXA9)
#define PLATFORM_IRQCTRL0_VIRTUAL EB_GIC0_VBASE
#endif
#define PLATFORM_IRQCTRL1_VIRTUAL EB_GIC1_VBASE
#endif /* __PLATFORM_EB_OFFSETS_H__ */

28
include/l4/platform/eb/platform.h
View File

@@ -1,28 +1,18 @@
#ifndef __EB_PLATFORM_H__
#define __EB_PLATFORM_H__
/*
* Platform specific ties between drivers and generic APIs used by the kernel.
* E.g. system timer and console.
*
* Copyright (C) Bahadir Balban 2007
* Copyright (C) 2009 B Labs Ltd.
*/
#ifndef __EB_PLATFORM_H__
#define __EB_PLATFORM_H__
#include INC_PLAT(offsets.h)
#include INC_GLUE(memlayout.h)
#include INC_PLAT(sysctrl.h)
#include <l4/drivers/irq/gic/gic.h>
#include <l4/platform/realview/platform.h>
#define PLATFORM_CONSOLE0_BASE EB_UART0_VBASE
#define PLATFORM_TIMER0_BASE EB_TIMER01_VBASE
#define PLATFORM_SP810_BASE EB_SYSCTRL_VBASE
void cpu_extra_init(void);
void init_platform_irq_controller();
void init_platform_devices();
/* Total number of timers present in this platform */
#define TOTAL_TIMERS 4
#define PLATFORM_TIMER0 0
#define PLATFORM_TIMER1 1
#define PLATFORM_TIMER2 2
#define PLATFORM_TIMER3 3
void platform_irq_enable(int irq);
void platform_irq_disable(int irq);
void timer_start(void);
#endif /* __EB_PLATFORM_H__ */

95
include/l4/platform/eb/sysctrl.h Normal file
View File

@@ -0,0 +1,95 @@
#ifndef __EB_SYSCTRL_H__
#define __EB_SYSCTRL_H__
/* TODO: Better to stick this file in a ARM specific folder as most realview boards
* tend to have this component
*/
#define SYS_ID 0x0000
#define SYS_SW 0x0004
#define SYS_LED 0x0008
#define SYS_OSC0 0x000C
#define SYS_OSC1 0x0010
#define SYS_OSC2 0x0014
#define SYS_OSC3 0x0018
#define SYS_OSC4 0x001C
#define SYS_LOCK 0x0020
#define SYS_100HZ 0x0024
#define SYS_CFGDATA0 0x0028
#define SYS_CFGDATA1 0x002C
#define SYS_FLAGS 0x0030
#define SYS_FLAGS_SET 0x0030
#define SYS_FLAGS_CLR 0x0034
#define SYS_NVFLAGS 0x0038
#define SYS_NVFLAGS_SET 0x0038
#define SYS_NVFLAGS_CLR 0x003C
#define SYS_PCICTL 0x0044
#define SYS_MCI 0x0048
#define SYS_FLASH 0x004C
#define SYS_CLCD 0x0050
#define SYS_CLCDSER 0x0054
#define SYS_BOOTCS 0x0058
#define SYS_24MHZ 0x005C
#define SYS_MISC 0x0060
#define SYS_DMAPSR0 0x0064
#define SYS_DMAPSR1 0x0068
#define SYS_DMAPSR2 0x006C
#define SYS_IOSEL 0x0070
#define SYS_PLDCTL1 0x0074
#define SYS_PLDCTL2 0x0078
#define SYS_BUSID 0x0080
#define SYS_PROCID1 0x0084
#define SYS_PROCID0 0x0088
#define SYS_OSCRESET0 0x008C
#define SYS_OSCRESET1 0x0090
#define SYS_OSCRESET2 0x0094
#define SYS_OSCRESET3 0x0098
#define SYS_OSCRESET4 0x009C
/* System Controller Lock/Unlock */
#define SYSCTRL_LOCK 0xFF
#define SYSCTRL_UNLOCK 0xA05F
#define ID_MASK_REV 0xF0000000
#define ID_MASK_HBI 0x0FFF0000
#define ID_MASK_BUILD 0x0000F000
#define ID_MASK_ARCH 0x00000F00
#define ID_MASK_FPGA 0x000000FF
#define SW_MASK_BOOTSEL 0x0000FF00
#define SW_MASK_GP 0x000000FF
#define LED_MASK_LED 0x000000FF
#define FLASH_WRITE_EN 0x1
#define FLASH_WRITE_DIS 0x0
#define CLCD_QVGA (0 << 8) /* 320x240 */
#define CLDE_VGA (1 << 8) /* 640x480 */
#define CLCD_SMALL (2 << 8) /* 220x176 */
#define CLCD_SSP_CS (1 << 7) /* SSP Chip Select */
#define CLCD_TS_EN (1 << 6) /* Touch Screen Enable */
/* Different Voltages */
#define CLCD_NEG_EN (1 << 5)
#define CLCD_3V5V_EN (1 << 4)
#define CLCD_POS_EN (1 << 3)
#define CLCD_IO_ON (1 << 2)
/* Normal without DCC, no FIQ, recommended for SMP */
#define PLD_CTRL1_INTMOD_WITHOUT_DCC (1 << 22)
/* Not Recommended */
#define PLD_CTRL1_INTMOD_WITH_DCC (2 << 22)
/* For single cpu such as 1136 */
#define PLD_CTRL1_INTMOD_LEGACY (4 << 22)
#endif /* __EB_SYSCTRL_H__ */

22
include/l4/platform/eb/uart.h
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@@ -1,20 +1,6 @@
/*
* Platform specific ties to generic uart functions that putc expects.
*
* Copyright (C) 2007 Bahadir Balban
*
*/
#ifndef __EB_UART_H__
#define __EB_UART_H__
#ifndef __PLATFORM_EB_UART_H__
#define __PLATFORM_EB_UART_H__
#include <l4/platform/realview/uart.h>
#include INC_PLAT(offsets.h)
#include INC_GLUE(memlayout.h)
#define PLATFORM_CONSOLE_BASE EB_UART0_VBASE
#include <l4/drivers/uart/pl011/pl011_uart.h>
void uart_init(void);
void uart_putc(char c);
#endif /* __PLATFORM_EB_UART_H__ */
#endif /* __EB_UART_H__ */

8
include/l4/platform/pb11mpcore/irq.h
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@@ -6,10 +6,10 @@
#define IRQS_MAX 96
/* IRQ indices. */
#define IRQ_TIMER01 36
#define IRQ_TIMER23 37
#define IRQ_TIMER45 73
#define IRQ_TIMER67 74
#define IRQ_TIMER0 36
#define IRQ_TIMER1 37
#define IRQ_TIMER2 73
#define IRQ_TIMER3 74
#define IRQ_RTC 42
#define IRQ_UART0 44
#define IRQ_UART1 45

70
include/l4/platform/pb11mpcore/offsets.h
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@@ -1,77 +1,35 @@
/*
* Describes physical memory layout of PB11MPCORE platform.
*
* This only include physical and memory offsets that
* are not included in realview/offsets.h
*
* Copyright (C) 2007 Bahadir Balban
*/
#ifndef __PLATFORM_PB11MPCORE_OFFSETS_H__
#define __PLATFORM_PB11MPCORE_OFFSETS_H__
/* Physical memory base */
#define PHYS_MEM_START 0x00000000 /* inclusive */
#define PHYS_MEM_END 0x10000000 /* 256 MB, exclusive */
/*
* These bases taken from where kernel is `physically' linked at,
* also used to calculate virtual-to-physical translation offset.
* See the linker script for their sources. PHYS_ADDR_BASE can't
* use a linker variable because it's referred from assembler.
*/
#define PHYS_ADDR_BASE 0x100000
/* Device memory base */
#define PB11MPCORE_DEV_PHYS 0x10000000
#include <l4/platform/realview/offsets.h>
/* Device offsets in physical memory */
#define PB11MPCORE_SYSTEM_REGISTERS 0x10000000 /* System registers */
#define PB11MPCORE_SYSCTRL0_BASE 0x10001000 /* System controller 0 */
#define PB11MPCORE_UART0_BASE 0x10009000 /* UART 0 */
#define PB11MPCORE_UART1_BASE 0x1000A000 /* UART 1 */
#define PB11MPCORE_UART2_BASE 0x1000B000 /* UART 2 */
#define PB11MPCORE_UART3_BASE 0x1000C000 /* UART 3 */
#define PB11MPCORE_WATCHDOG0_BASE 0x1000F000 /* WATCHDOG 0 */
#define PB11MPCORE_WATCHDOG1_BASE 0x10010000 /* WATCHDOG 1 */
#define PB11MPCORE_TIMER01_BASE 0x10011000 /* TIMER 0-1 */
#define PB11MPCORE_TIMER23_BASE 0x10012000 /* TIMER 2-3 */
#define PB11MPCORE_RTC_BASE 0x10017000 /* RTC interface */
#define PB11MPCORE_TIMER45_BASE 0x10018000 /* TIMER 4-5 */
#define PB11MPCORE_TIMER67_BASE 0x10019000 /* TIMER 6-7 */
#define PB11MPCORE_SYSCTRL1_BASE 0x1001A000 /* System controller 1 */
#define PB11MPCORE_GIC0_BASE 0x1E000000 /* GIC 0 */
#define PB11MPCORE_GIC1_BASE 0x1E010000 /* GIC 1 */
#define PB11MPCORE_GIC2_BASE 0x1E020000 /* GIC 2 */
#define PB11MPCORE_GIC3_BASE 0x1E030000 /* GIC 3 */
/*
* Uart virtual address until a file-based console access
* is available for userspace
*/
#define USERSPACE_UART_BASE 0x500000
#define PLATFORM_TIMER2_BASE 0x10018000 /* TIMER 4-5 */
#define PLATFORM_TIMER3_BASE 0x10019000 /* TIMER 6-7 */
#define PLATFORM_SYSCTRL1_BASE 0x1001A000 /* System controller 1 */
#define PLATFORM_GIC0_BASE 0x1E000000 /* GIC 0 */
#define PLATFORM_GIC1_BASE 0x1E010000 /* GIC 1 */
#define PLATFORM_GIC2_BASE 0x1E020000 /* GIC 2 */
#define PLATFORM_GIC3_BASE 0x1E030000 /* GIC 3 */
/*
* Device offsets in virtual memory. They offset to some virtual
* device base address. Each page on this virtual base is consecutively
* allocated to devices. Nice and smooth.
*/
#define PB11MPCORE_SYSREGS_VOFFSET 0x00000000
#define PB11MPCORE_SYSCTRL0_VOFFSET 0x00001000
#define PB11MPCORE_SYSCTRL1_VOFFSET 0x00002000
#define PB11MPCORE_UART0_VOFFSET 0x00003000
#define PB11MPCORE_TIMER01_VOFFSET 0x00004000
#define PB11MPCORE_GIC0_VOFFSET 0x00005000
#define PB11MPCORE_GIC1_VOFFSET 0x00006000
#define PB11MPCORE_GIC2_VOFFSET 0x00007000
#define PB11MPCORE_GIC3_VOFFSET 0x00008000
#define PB11MPCORE_SYSREGS_VBASE (IO_AREA0_VADDR + PB11MPCORE_SYSREGS_VOFFSET)
#define PB11MPCORE_SYSCTRL0_VBASE (IO_AREA0_VADDR + PB11MPCORE_SYSCTRL0_VOFFSET)
#define PB11MPCORE_SYSCTRL1_VBASE (IO_AREA0_VADDR + PB11MPCORE_SYSCTRL1_VOFFSET)
#define PB11MPCORE_UART0_VBASE (IO_AREA0_VADDR + PB11MPCORE_UART0_VOFFSET)
#define PB11MPCORE_TIMER01_VBASE (IO_AREA0_VADDR + PB11MPCORE_TIMER01_VOFFSET)
#define PB11MPCORE_GIC0_VBASE (IO_AREA0_VADDR + PB11MPCORE_GIC0_VOFFSET)
#define PB11MPCORE_GIC1_VBASE (IO_AREA0_VADDR + PB11MPCORE_GIC1_VOFFSET)
#define PB11MPCORE_GIC2_VBASE (IO_AREA0_VADDR + PB11MPCORE_GIC2_VOFFSET)
#define PB11MPCORE_GIC3_VBASE (IO_AREA0_VADDR + PB11MPCORE_GIC3_VOFFSET)
/* Add userspace devices here as they become necessary for irqs */
/* Add size of various user space devices, to be used in capability generation */
#endif /* __PLATFORM_PB11MPCORE_OFFSETS_H__ */

30
include/l4/platform/pb11mpcore/platform.h
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@@ -1,5 +1,5 @@
#ifndef __PB11MPCORE_PLATFORM_H__
#define __PB11MPCORE_PLATFORM_H__
#ifndef __PBA9_PLATFORM_H__
#define __PBA9_PLATFORM_H__
/*
* Platform specific ties between drivers and generic APIs used by the kernel.
* E.g. system timer and console.
@@ -7,28 +7,6 @@
* Copyright (C) Bahadir Balban 2007
*/
#include INC_PLAT(offsets.h)
#include INC_GLUE(memlayout.h)
#include <l4/platform/realview/platform.h>
#define PLATFORM_CONSOLE0_BASE PB11MPCORE_UART0_VBASE
#define PLATFORM_TIMER0_BASE PB11MPCORE_TIMER01_VBASE
/* Need to add syscntrl1 here */
#define PLATFORM_SP810_BASE PB11MPCORE_SYSCTRL0_VBASE
/* Total number of timers present in this platform */
#define TOTAL_TIMERS 8
#define PLATFORM_TIMER0 0
#define PLATFORM_TIMER1 1
#define PLATFORM_TIMER2 2
#define PLATFORM_TIMER3 3
#define PLATFORM_TIMER4 4
#define PLATFORM_TIMER5 5
#define PLATFORM_TIMER6 6
#define PLATFORM_TIMER7 7
void platform_irq_enable(int irq);
void platform_irq_disable(int irq);
void timer_start(void);
#endif /* __PB11MPCORE_PLATFORM_H__ */
#endif /* __PBA9_PLATFORM_H__ */

22
include/l4/platform/pb11mpcore/uart.h
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@@ -1,20 +1,6 @@
/*
* Platform specific ties to generic uart functions that putc expects.
*
* Copyright (C) 2007 Bahadir Balban
*
*/
#ifndef __PB11MPCORE_UART_H__
#define __PB11MPCORE_UART_H__
#ifndef __PLATFORM_PB11MPCORE_UART_H__
#define __PLATFORM_PB11MPCORE_UART_H__
#include <l4/platform/realview/uart.h>
#include INC_PLAT(offsets.h)
#include INC_GLUE(memlayout.h)
#define PLATFORM_CONSOLE_BASE PB11MPCORE_UART0_VBASE
#include <l4/drivers/uart/pl011/pl011_uart.h>
void uart_init(void);
void uart_putc(char c);
#endif /* __PLATFORM_PB11MPCORE_UART_H__ */
#endif /* __PB11MPCORE_UART_H__ */

10
include/l4/platform/pb926/irq.h
View File

@@ -22,12 +22,13 @@
#define IRQS_MAX VIC_IRQS_MAX + SIC_IRQS_MAX
/* Vectored Interrupt Controller local IRQ numbers */
#define VIC_IRQ_TIMER01 4
#define VIC_IRQ_TIMER23 5
#define VIC_IRQ_TIMER0 4
#define VIC_IRQ_TIMER1 5
#define VIC_IRQ_RTC 10
#define VIC_IRQ_UART0 12
#define VIC_IRQ_UART1 13
#define VIC_IRQ_UART2 14
#define VIC_IRQ_CLCD0 16
#define VIC_IRQ_SIC 31
/* Secondary Interrupt controller local IRQ numbers */
@@ -35,12 +36,13 @@
#define SIC_IRQ_UART3 6
/* Global irq numbers, note these should reflect global device names */
#define IRQ_TIMER0 (VIC_IRQ_TIMER01 + VIC_CHIP_OFFSET)
#define IRQ_TIMER1 (VIC_IRQ_TIMER23 + VIC_CHIP_OFFSET)
#define IRQ_TIMER0 (VIC_IRQ_TIMER0 + VIC_CHIP_OFFSET)
#define IRQ_TIMER1 (VIC_IRQ_TIMER1 + VIC_CHIP_OFFSET)
#define IRQ_RTC (VIC_IRQ_RTC + VIC_CHIP_OFFSET)
#define IRQ_UART0 (VIC_IRQ_UART0 + VIC_CHIP_OFFSET)
#define IRQ_UART1 (VIC_IRQ_UART1 + VIC_CHIP_OFFSET)
#define IRQ_UART2 (VIC_IRQ_UART2 + VIC_CHIP_OFFSET)
#define IRQ_CLCD0 (VIC_IRQ_CLCD0 + VIC_CHIP_OFFSET)
#define IRQ_SIC (VIC_IRQ_SIC + VIC_CHIP_OFFSET)
#define IRQ_SICSWI (SIC_IRQ_SWI + SIC_CHIP_OFFSET)

68
include/l4/platform/pb926/offsets.h
View File

@@ -8,51 +8,53 @@
#define __PLATFORM_PB926_OFFSETS_H__
/* Physical memory base */
#define PHYS_MEM_START 0x00000000 /* inclusive */
#define PHYS_MEM_END 0x08000000 /* 128 MB, exclusive */
/* Device offsets in physical memory */
#define PB926_SYSTEM_REGISTERS 0x10000000 /* System registers */
#define PB926_SYSCTRL_BASE 0x101E0000 /* System controller */
#define PB926_WATCHDOG_BASE 0x101E1000 /* Watchdog */
#define PB926_TIMER01_BASE 0x101E2000 /* Timers 0 and 1 */
#define PB926_TIMER23_BASE 0x101E3000 /* Timers 2 and 3 */
#define PB926_RTC_BASE 0x101E8000 /* Real Time Clock */
#define PB926_VIC_BASE 0x10140000 /* Primary Vectored IC */
#define PB926_SIC_BASE 0x10003000 /* Secondary IC */
#define PB926_UART0_BASE 0x101F1000 /* Console port (UART0) */
#define PB926_UART1_BASE 0x101F2000 /* Console port (UART1) */
#define PB926_UART2_BASE 0x101F3000 /* Console port (UART2) */
#define PB926_UART3_BASE 0x10009000 /* Console port (UART3) */
#define PB926_CLCD_BASE 0x10120000 /* Color LCD */
#define PLATFORM_PHYS_MEM_START 0x00000000 /* inclusive */
#define PLATFORM_PHYS_MEM_END 0x08000000 /* 128 MB, exclusive */
/*
* Uart virtual address until a file-based console access
* is available for userspace
* Device offsets in physical memory
* Naming of devices done starting with 0 subscript,
* as we use these names for device capability
*/
#define USERSPACE_CONSOLE_VIRTUAL 0x500000
#define PLATFORM_SYSTEM_REGISTERS 0x10000000 /* System registers */
#define PLATFORM_SYSCTRL_BASE 0x101E0000 /* System controller */
#define PLATFORM_WATCHDOG_BASE 0x101E1000 /* Watchdog */
#define PLATFORM_TIMER0_BASE 0x101E2000 /* Timers 0 and 1 */
#define PLATFORM_TIMER1_BASE 0x101E3000 /* Timers 2 and 3 */
#define PLATFORM_RTC_BASE 0x101E8000 /* Real Time Clock */
#define PLATFORM_VIC_BASE 0x10140000 /* Primary Vectored IC */
#define PLATFORM_SIC_BASE 0x10003000 /* Secondary IC */
#define PLATFORM_UART0_BASE 0x101F1000 /* Console port (UART0) */
#define PLATFORM_UART1_BASE 0x101F2000 /* Console port (UART1) */
#define PLATFORM_UART2_BASE 0x101F3000 /* Console port (UART2) */
#define PLATFORM_UART3_BASE 0x10009000 /* Console port (UART3) */
#define PLATFORM_CLCD0_BASE 0x10120000 /* Color LCD */
/*
* Device offsets in virtual memory. They offset to some virtual
* device base address. Each page on this virtual base is consecutively
* allocated to devices. Nice and smooth.
*/
#define PB926_TIMER01_VOFFSET 0x00000000
#define PB926_UART0_VOFFSET 0x00001000
#define PB926_VIC_VOFFSET 0x00002000
#define PB926_SIC_VOFFSET 0x00003000
#define PB926_SYSREGS_VOFFSET 0x00004000
#define PB926_SYSCTRL_VOFFSET 0x00005000
#define PB926_TIMER23_VOFFSET 0x00006000
#define DEVICE_PAGE 0x1000
#define PLATFORM_CONSOLE_VIRTUAL (IO_AREA0_VADDR + PB926_UART0_VOFFSET)
#define PLATFORM_TIMER0_VIRTUAL (IO_AREA0_VADDR + PB926_TIMER01_VOFFSET)
#define PLATFORM_SYSCTRL_VIRTUAL (IO_AREA0_VADDR + PB926_SYSCTRL_VOFFSET)
#define PLATFORM_IRQCTRL0_VIRTUAL (IO_AREA0_VADDR + PB926_VIC_VOFFSET)
#define PLATFORM_IRQCTRL1_VIRTUAL (IO_AREA0_VADDR + PB926_SIC_VOFFSET)
#define PLATFORM_TIMER0_VBASE (IO_AREA0_VADDR + (0 * DEVICE_PAGE))
#define PLATFORM_CONSOLE_VBASE (IO_AREA0_VADDR + (1 * DEVICE_PAGE))
#define PLATFORM_IRQCTRL0_VBASE (IO_AREA0_VADDR + (2 * DEVICE_PAGE))
#define PLATFORM_IRQCTRL1_VBASE (IO_AREA0_VADDR + (3 * DEVICE_PAGE))
#define PLATFORM_SYSCTRL_VBASE (IO_AREA0_VADDR + (4 * DEVICE_PAGE))
/* Add userspace devices here as they become necessary for irqs */
#define PLATFORM_TIMER1_VIRTUAL (IO_AREA0_VADDR + PB926_TIMER23_VOFFSET)
#define PLATFORM_TIMER1_VBASE (IO_AREA0_VADDR + (6 * DEVICE_PAGE))
/* The SP810 system controller offsets */
#define SP810_BASE PLATFORM_SYSCTRL_VBASE
#define SP810_SCCTRL (SP810_BASE + 0x0)
/* Add size of various user space devices, to be used in capability generation */
#define PLATFORM_UART1_SIZE 0x1000
#define PLATFORM_UART2_SIZE 0x1000
#define PLATFORM_UART3_SIZE 0x1000
#define PLATFORM_TIMER1_SIZE 0x1000
#endif /* __PLATFORM_PB926_OFFSETS_H__ */

42
include/l4/platform/pb926/platform.h
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@@ -7,46 +7,6 @@
* Copyright (C) Bahadir Balban 2007
*/
#include INC_PLAT(offsets.h)
#include INC_GLUE(memlayout.h)
#include <l4/generic/capability.h>
#include <l4/generic/cap-types.h>
#include <l4/generic/resource.h>
/* Default console used by kernel */
#define PLATFORM_CONSOLE_BASE PB926_UART0_BASE
/* SP804 timer has TIMER1 at TIMER0 + 0x20 address */
#define PLATFORM_TIMER0_BASE PB926_TIMER01_BASE
/* Total number of timers present in this platform */
#define TOTAL_TIMERS 4
#define PLATFORM_TIMER0 0
#define PLATFORM_TIMER1 1
#define PLATFORM_TIMER2 2
#define PLATFORM_TIMER3 3
#define PB926_UART_SIZE 0x1000
#define PB926_TIMER_SIZE 0x1000
#define PB926_CLCD_SIZE 0x1000
#define PLATFORM_UART1_BASE PB926_UART1_BASE
#define PLATFORM_UART2_BASE PB926_UART2_BASE
#define PLATFORM_UART3_BASE PB926_UART3_BASE
#define PLATFORM_UART1_SIZE PB926_UART_SIZE
#define PLATFORM_UART2_SIZE PB926_UART_SIZE
#define PLATFORM_UART3_SIZE PB926_UART_SIZE
#define PLATFORM_TIMER1_BASE PB926_TIMER23_BASE
#define PLATFORM_TIMER1_SIZE PB926_TIMER_SIZE
#define PLATFORM_CLCD0_BASE PB926_CLCD_BASE
#define PLATFORM_CLCD0_SIZE PB926_CLCD_SIZE
int platform_setup_device_caps(struct kernel_resources *kres);
void platform_irq_enable(int irq);
void platform_irq_disable(int irq);
void timer_start(void);
void platform_timer_start(void);
#endif /* __PB926_PLATFORM_H__ */

13
include/l4/platform/pb926/timer.h Normal file
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@@ -0,0 +1,13 @@
/*
* Platform encapsulation over timer driver.
*
* Copyright (C) 2007 Bahadir Balban
*
*/
#ifndef __PLATFORM_PB926_TIMER_H__
#define __PLATFORM_PB926_TIMER_H__
#include <l4/drivers/timer/sp804/timer.h>
#endif /* __PLATFORM_PB926_TIMER_H__ */

8
include/l4/platform/pb926/uart.h
View File

@@ -8,12 +8,6 @@
#ifndef __PLATFORM_PB926_UART_H__
#define __PLATFORM_PB926_UART_H__
#include INC_PLAT(offsets.h)
#include INC_GLUE(memlayout.h)
#include <l4/drivers/uart/pl011/pl011_uart.h>
void uart_init(void);
void uart_putc(char c);
#include <l4/drivers/uart/pl011/uart.h>
#endif /* __PLATFORM_PB926_UART_H__ */

28
include/l4/platform/pba8/irq.h Normal file
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@@ -0,0 +1,28 @@
#ifndef __PLATFORM_IRQ_H__
#define __PLATFORM_IRQ_H__
/*
* Support for generic irq handling using platform irq controller (GIC)
*
* Copyright (C) 2007 Bahadir Balban
*/
/* TODO: Not sure about this, need to check */
#define IRQ_CHIPS_MAX 4
#define IRQS_MAX 96
/* IRQ indices. */
#define IRQ_UART0 44
#define IRQ_UART1 45
#define IRQ_UART2 46
#define IRQ_UART3 47
/* General Purpose Timers */
#define IRQ_TIMER0 36
#define IRQ_TIMER1 37
#define IRQ_TIMER2 73
#define IRQ_TIMER3 74
#endif /* __PLATFORM_IRQ_H__ */

41
include/l4/platform/pba8/offsets.h Normal file
View File

@@ -0,0 +1,41 @@
/*
* Describes physical memory layout of EB platform.
*
* This only include physical and memory offsets that
* are not included in realview/offsets.h
*
* Copyright (C) 2009 B Labs Ltd.
*/
#ifndef __PLATFORM_PBA8_OFFSETS_H__
#define __PLATFORM_PBA8_OFFSETS_H__
#include <l4/platform/realview/offsets.h>
/*
* These bases taken from where kernel is `physically' linked at,
* also used to calculate virtual-to-physical translation offset.
* See the linker script for their sources. PHYS_ADDR_BASE can't
* use a linker variable because it's referred from assembler.
*/
#define PHYS_ADDR_BASE 0x100000
/* Device offsets in physical memory */
#define PLATFORM_TIMER2_BASE 0x10018000 /* Timers 4 and 5 */
#define PLATFORM_TIMER3_BASE 0x10019000 /* Timers 6 and 7 */
#define PLATFORM_SYSCTRL1_BASE 0x1001A000 /* System controller1 */
#define PLATFORM_GIC1_BASE 0x1E000000 /* GIC 1 */
#define PLATFORM_GIC2_BASE 0x1E010000 /* GIC 2 */
#define PLATFORM_GIC3_BASE 0x1E020000 /* GIC 3 */
#define PLATFORM_GIC4_BASE 0x1E030000 /* GIC 4 */
/*
* Device offsets in virtual memory. They offset to some virtual
* device base address. Each page on this virtual base is consecutively
* allocated to devices. Nice and smooth.
* Make sure the offsets used here are not conflicting with the ones
* present in <l4/platform/realview/offset.h>
*/
#endif /* __PLATFORM_PBA8_OFFSETS_H__ */

16
include/l4/platform/pba8/platform.h Normal file
View File

@@ -0,0 +1,16 @@
/*
* Platform specific ties between drivers and generic APIs used by the kernel.
* E.g. system timer and console.
*
* Copyright (C) 2009 B Labs Ltd.
*/
#ifndef __PBA8_PLATFORM_H__
#define __PBA8_PLATFORM_H__
#include <l4/drivers/irq/gic/gic.h>
#include <l4/platform/realview/platform.h>
void init_platform_irq_controller();
void init_platform_devices();
#endif /* __PBA8_PLATFORM_H__ */

6
include/l4/platform/pba8/uart.h Normal file
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@@ -0,0 +1,6 @@
#ifndef __PBA8_UART_H__
#define __PBA8_UART_H__
#include <l4/platform/realview/uart.h>
#endif /* __PBA8_UART_H__ */

34
include/l4/platform/pba9/irq.h Normal file
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@@ -0,0 +1,34 @@
/*
* Support for generic irq handling using platform irq controller (GIC)
*
* Copyright (C) 2007 B Labs Ltd.
*/
#ifndef __PLATFORM_IRQ_H__
#define __PLATFORM_IRQ_H__
/* TODO: Not sure about this, need to check */
#define IRQ_CHIPS_MAX 1
#define IRQS_MAX 96
#define IRQ_OFFSET 0
/* IRQ indices. */
#define IRQ_TIMER0 34
#define IRQ_TIMER1 35
#define IRQ_RTC 36
#define IRQ_UART0 37
#define IRQ_UART1 38
#define IRQ_UART2 39
#define IRQ_UART3 40
#define IRQ_CLCD0 46
/*
* Interrupt Distribution:
* 0-31: SI, provided by distributed interrupt controller
* 32-63: Externel peripheral interrupts
* 64-71: Tile site interrupt
* 72-95: Externel peripheral interrupts
*/
#endif /* __PLATFORM_IRQ_H__ */

35
include/l4/platform/pba9/offsets.h Normal file
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@@ -0,0 +1,35 @@
/*
* Describes physical memory layout of pb926 platform.
*
* This only include physical and memory offsets that
* are not included in realview/offsets.h
*
* Copyright (C) 2010 B Labs Ltd.
* Author: Bahadir Balban <bbalban@b-labs.co.uk>
*/
#ifndef __PLATFORM_PBA9_OFFSETS_H__
#define __PLATFORM_PBA9_OFFSETS_H__
#include <l4/platform/realview/offsets.h>
/*
* Device offsets in physical memory
* Naming of devices done starting with 0 subscript,
* as we use these names for device capability
*/
#define PLATFORM_TIMER2_BASE 0x10018000 /* Timers 2 and 3 */
#define PLATFORM_TIMER3_BASE 0x10019000 /* Timers 2 and 3 */
#define PLATFORM_SYSCTRL1_BASE 0x1001A000 /* System controller1 */
#define PLATFORM_GIC0_BASE 0x1E000000 /* GIC 0 */
#define MPCORE_PRIVATE_BASE 0x1E000000
#define MPCORE_PRIVATE_VBASE (IO_AREA0_VADDR + (13 * DEVICE_PAGE))
#define SCU_BASE MPCORE_PRIVATE_BASE
#define SCU_VBASE MPCORE_PRIVATE_VBASE
#define GIC0_CPU_VBASE (MPCORE_PRIVATE_VBASE + 0x100)
#define GIC0_DIST_VBASE (MPCORE_PRIVATE_VBASE + 0x1000)
#endif /* __PLATFORM_PBA9_OFFSETS_H__ */

12
include/l4/platform/pba9/platform.h Normal file
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@@ -0,0 +1,12 @@
#ifndef __PBA9_PLATFORM_H__
#define __PBA9_PLATFORM_H__
/*
* Platform specific ties between drivers and generic APIs used by the kernel.
* E.g. system timer and console.
*
* Copyright (C) Bahadir Balban 2007
*/
#include <l4/platform/realview/platform.h>
#endif /* __PBA9_PLATFORM_H__ */

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include/l4/platform/pba9/platsmp.h Normal file
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/*
* Copyright 2010 B Labs Ltd.
* Author: Prem Mallappa <prem.mallappa@b-labs.co.uk>
*/
#ifndef __VXA9_PLATSMP_H__
#define __VXA9_PLATSMP_H__
#include <l4/generic/irq.h>
#include <l4/generic/space.h>
#include <l4/drivers/irq/gic/gic.h>
#include <l4/generic/smp.h>
#include INC_GLUE(smp.h)
#include INC_PLAT(sysctrl.h)
void boot_secondary(int);
void platform_smp_init(int ncpus);
int platform_smp_start(int cpu, void (*start)(int));
void secondary_init_platform(void);
#endif /* VXA9_PLATSMP_H */

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include/l4/platform/pba9/sysctrl.h Normal file
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#ifndef __EB_SYSCTRL_H__
#define __EB_SYSCTRL_H__
/* TODO: Better to stick this file in a ARM specific folder as most realview boards
* tend to have this component
*/
#define SYS_ID 0x0000
#define SYS_SW 0x0004
#define SYS_LED 0x0008
#define SYS_OSC0 0x000C
#define SYS_OSC1 0x0010
#define SYS_OSC2 0x0014
#define SYS_OSC3 0x0018
#define SYS_OSC4 0x001C
#define SYS_LOCK 0x0020
#define SYS_100HZ 0x0024
#define SYS_CFGDATA0 0x0028
#define SYS_CFGDATA1 0x002C
#define SYS_FLAGS 0x0030
#define SYS_FLAGS_SET 0x0030
#define SYS_FLAGS_CLR 0x0034
#define SYS_NVFLAGS 0x0038
#define SYS_NVFLAGS_SET 0x0038
#define SYS_NVFLAGS_CLR 0x003C
#define SYS_PCICTL 0x0044
#define SYS_MCI 0x0048
#define SYS_FLASH 0x004C
#define SYS_CLCD 0x0050
#define SYS_CLCDSER 0x0054
#define SYS_BOOTCS 0x0058
#define SYS_24MHZ 0x005C
#define SYS_MISC 0x0060
#define SYS_DMAPSR0 0x0064
#define SYS_DMAPSR1 0x0068
#define SYS_DMAPSR2 0x006C
#define SYS_IOSEL 0x0070
#define SYS_PLDCTL1 0x0074
#define SYS_PLDCTL2 0x0078
#define SYS_BUSID 0x0080
#define SYS_PROCID1 0x0084
#define SYS_PROCID0 0x0088
#define SYS_OSCRESET0 0x008C
#define SYS_OSCRESET1 0x0090
#define SYS_OSCRESET2 0x0094
#define SYS_OSCRESET3 0x0098
#define SYS_OSCRESET4 0x009C
/* System Controller Lock/Unlock */
#define SYSCTRL_LOCK 0xFF
#define SYSCTRL_UNLOCK 0xA05F
#define ID_MASK_REV 0xF0000000
#define ID_MASK_HBI 0x0FFF0000
#define ID_MASK_BUILD 0x0000F000
#define ID_MASK_ARCH 0x00000F00
#define ID_MASK_FPGA 0x000000FF
#define SW_MASK_BOOTSEL 0x0000FF00
#define SW_MASK_GP 0x000000FF
#define LED_MASK_LED 0x000000FF
#define FLASH_WRITE_EN 0x1
#define FLASH_WRITE_DIS 0x0
#define CLCD_QVGA (0 << 8) /* 320x240 */
#define CLDE_VGA (1 << 8) /* 640x480 */
#define CLCD_SMALL (2 << 8) /* 220x176 */
#define CLCD_SSP_CS (1 << 7) /* SSP Chip Select */
#define CLCD_TS_EN (1 << 6) /* Touch Screen Enable */
/* Different Voltages */
#define CLCD_NEG_EN (1 << 5)
#define CLCD_3V5V_EN (1 << 4)
#define CLCD_POS_EN (1 << 3)
#define CLCD_IO_ON (1 << 2)
/* Normal without DCC, no FIQ, recommended for SMP */
#define PLD_CTRL1_INTMOD_WITHOUT_DCC (1 << 22)
/* Not Recommended */
#define PLD_CTRL1_INTMOD_WITH_DCC (2 << 22)
/* For single cpu such as 1136 */
#define PLD_CTRL1_INTMOD_LEGACY (4 << 22)
#endif /* __EB_SYSCTRL_H__ */

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#ifndef __PBA9_UART_H__
#define __PBA9_UART_H__
#include <l4/platform/realview/uart.h>
#endif /* __PBA9_UART_H__ */

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include/l4/platform/realview/offsets.h Normal file
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/*
* Describes physical memory layout of realview platform.
* Right now this contains common offsets for
* pb11mpcore, pba9 and eb.
*
* This is internally included by respective platform's offsets.h
*
* Copyright (C) 2007 Bahadir Balban
*/
#ifndef __PLATFORM_REALVIEW_OFFSETS_H__
#define __PLATFORM_REALVIEW_OFFSETS_H__
/* Physical memory base */
#define PLATFORM_PHYS_MEM_START 0x00000000 /* inclusive */
#define PLATFORM_PHYS_MEM_END 0x10000000 /* 256 MB, exclusive */
/*
* Device offsets in physical memory
* Naming of devices done starting with 0 subscript,
* as we use these names for device capability
*/
#define PLATFORM_SYSTEM_REGISTERS 0x10000000 /* System registers */
#define PLATFORM_SYSCTRL_BASE 0x10001000 /* System controller0 */
#define PLATFORM_UART0_BASE 0x10009000 /* Console port (UART0) */
#define PLATFORM_UART1_BASE 0x1000A000 /* Console port (UART1) */
#define PLATFORM_UART2_BASE 0x1000B000 /* Console port (UART2) */
#define PLATFORM_UART3_BASE 0x1000C000 /* Console port (UART3) */
#define PLATFORM_TIMER0_BASE 0x10011000 /* Timers 0 and 1 */
#define PLATFORM_TIMER1_BASE 0x10012000 /* Timers 2 and 3 */
/*
* Virtual Memory base address, where devices will be mapped.
* Each Device will take one page in virtual memory.
* Nice and smooth.
*/
#define DEVICE_PAGE 0x1000
#define PLATFORM_SYSREGS_VBASE (IO_AREA0_VADDR + (0 * DEVICE_PAGE))
#define PLATFORM_SYSCTRL_VBASE (IO_AREA0_VADDR + (1 * DEVICE_PAGE))
#define PLATFORM_SYSCTRL1_VBASE (IO_AREA0_VADDR + (2 * DEVICE_PAGE))
#define PLATFORM_CONSOLE_VBASE (IO_AREA0_VADDR + (3 * DEVICE_PAGE))
#define PLATFORM_TIMER0_VBASE (IO_AREA0_VADDR + (4 * DEVICE_PAGE))
#define PLATFORM_GIC0_VBASE (IO_AREA0_VADDR + (5 * DEVICE_PAGE))
#define PLATFORM_GIC1_VBASE (IO_AREA0_VADDR + (7 * DEVICE_PAGE))
#define PLATFORM_GIC2_VBASE (IO_AREA0_VADDR + (9 * DEVICE_PAGE))
#define PLATFORM_GIC3_VBASE (IO_AREA0_VADDR + (11 * DEVICE_PAGE))
/* Add userspace devices here as they become necessary for irqs */
/* Add size of various user space devices, to be used in capability generation */
/* The SP810 system controller offsets */
#define SP810_BASE PLATFORM_SYSCTRL_VBASE
#define SP810_SCCTRL (SP810_BASE + 0x0)
/* Add size of various user space devices, to be used in capability generation */
#define PLATFORM_UART1_SIZE DEVICE_PAGE
#define PLATFORM_UART2_SIZE DEVICE_PAGE
#define PLATFORM_UART3_SIZE DEVICE_PAGE
#define PLATFORM_TIMER1_SIZE DEVICE_PAGE
#endif /* __PLATFORM_REALVIEW_OFFSETS_H__ */

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include/l4/platform/realview/platform.h Normal file
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/*
* Platform specific ties between drivers and
* generic APIs used by the kernel.
* E.g. system timer and console.
*
* Copyright (C) Bahadir Balban 2007
*/
#ifndef __REALVIEW_PLATFORM_H__
#define __REALVIEW_PLATFORM_H__
void init_platform_irq_controller();
void init_platform_devices();
void platform_timer_start(void);
void platform_test_cpucycles();
void platform_timer_start(void);
void scu_init(void);
void scu_print_state(void);
#endif /* __REALVIEW_PLATFORM_H__ */

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include/l4/platform/realview/timer.h Normal file
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/*
* Platform encapsulation over timer driver.
*
* Copyright (C) 2007 Bahadir Balban
*
*/
#ifndef __PLATFORM_REALVIEW_TIMER_H__
#define __PLATFORM_REALVIEW_TIMER_H__
#include <l4/drivers/timer/sp804/timer.h>
#endif /* __PLATFORM_REALVIEW_TIMER_H__ */

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include/l4/platform/realview/uart.h Normal file
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/*
* Ties generic uart call to platform specific
* uart driver implementation
*
* Copyright (C) 2007 Bahadir Balban
*/
#ifndef __PLATFORM_REALVIEW_UART_H__
#define __PLATFORM_REALVIEW_UART_H__
/* Platform specific implementations are defined here */
#include <l4/drivers/uart/pl011/uart.h>
#endif /* __PLATFORM_REALVIEW_UART_H__ */

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