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Kernel updates since December 2009

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This commit is contained in:
Bahadir Balban
2010-03-25 01:12:40 +02:00
parent 16818191b3
commit 74b5963fcb
487 changed files with 22477 additions and 3857 deletions
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0
include/l4/arch/arm/v5/cache.h Normal file
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24
include/l4/arch/arm/v5/cpu.h Normal file
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@@ -0,0 +1,24 @@
/*
* Cpu specific features
* defined upon the base architecture.
*
* Copyright (C) 2010 B Labs Ltd.
* Written by Bahadir Balban
*/
#ifndef __V5_CPU_H__
#define __V5_CPU_H__
#include INC_SUBARCH(mmu_ops.h)
static inline void cpu_startup(void)
{
}
static inline int smp_get_cpuid()
{
return 0;
}
#endif /* __V5_CPU_H__ */

0
include/l4/arch/arm/v5/debug.h Normal file
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33
include/l4/arch/arm/v5/exception.h Normal file
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@@ -0,0 +1,33 @@
/*
* Definitions for exception support on ARMv5
*
* Copyright (C) 2007 Bahadir Balban
*/
#ifndef __ARCH_V5_EXCEPTION_H__
#define __ARCH_V5_EXCEPTION_H__
#include INC_ARCH(asm.h)
/*
* v5 Architecture-defined data abort values for FSR ordered
* in highest to lowest priority.
*/
#define DABT_TERMINAL 0x2
#define DABT_VECTOR 0x0 /* Obsolete */
#define DABT_ALIGN 0x1
#define DABT_EXT_XLATE_LEVEL1 0xC
#define DABT_EXT_XLATE_LEVEL2 0xE
#define DABT_XLATE_SECT 0x5
#define DABT_XLATE_PAGE 0x7
#define DABT_DOMAIN_SECT 0x9
#define DABT_DOMAIN_PAGE 0xB
#define DABT_PERM_SECT 0xD
#define DABT_PERM_PAGE 0xF
#define DABT_EXT_LFETCH_SECT 0x4
#define DABT_EXT_LFETCH_PAGE 0x6
#define DABT_EXT_NON_LFETCH_SECT 0x8
#define DABT_EXT_NON_LFETCH_PAGE 0xA
#define FSR_FS_MASK 0xF
#endif /* __ARCH_V5_EXCEPTION_H__ */

29
include/l4/arch/arm/v5/irq.h
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@@ -1,11 +1,28 @@
#ifndef __ARM_V5_IRQ_H__
#define __ARM_V5_IRQ_H__
/*
* Destructive atomic-read.
*
* Write 0 to byte at @location as its contents are read back.
*/
char l4_atomic_dest_readb(void *location);
static inline void enable_irqs()
{
__asm__ __volatile__(
"mrs r0, cpsr_fc\n"
"bic r0, r0, #0x80\n" /* ARM_IRQ_BIT */
"msr cpsr_fc, r0\n"
);
}
static inline void disable_irqs()
{
__asm__ __volatile__(
"mrs r0, cpsr_fc\n"
"orr r0, r0, #0x80\n" /* ARM_IRQ_BIT */
"msr cpsr_fc, r0\n"
);
}
/* Disable the irqs unconditionally, but also keep the previous state such that
* if it was already disabled before the call, the restore call would retain
* this state. */
void irq_local_disable_save(unsigned long *state);
void irq_local_restore(unsigned long state);
#endif

158
include/l4/arch/arm/v5/mm.h
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@@ -9,53 +9,65 @@
/* ARM specific definitions */
#define VIRT_MEM_START 0
#define VIRT_MEM_END 0xFFFFFFFF
#define ARM_SECTION_SIZE SZ_1MB
#define ARM_SECTION_MASK (ARM_SECTION_SIZE - 1)
#define ARM_SECTION_BITS 20
#define SECTION_SIZE SZ_1MB
#define SECTION_MASK (SECTION_SIZE - 1)
#define SECTION_ALIGN_MASK (~SECTION_MASK)
#define SECTION_BITS 20
#define ARM_PAGE_SIZE SZ_4K
#define ARM_PAGE_MASK 0xFFF
#define ARM_PAGE_BITS 12
#define PGD_SIZE SZ_4K * 4
#define PGD_ENTRY_TOTAL SZ_4K
#define PGD_TYPE_MASK 0x3
#define PGD_COARSE_ALIGN_MASK 0xFFFFFC00
#define PGD_SECTION_ALIGN_MASK 0xFFF00000
#define PGD_FINE_ALIGN_MASK 0xFFFFF000
#define PGD_TYPE_FAULT 0
#define PGD_TYPE_COARSE 1
#define PGD_TYPE_SECTION 2
#define PGD_TYPE_FINE 3
#define PMD_TYPE_MASK 0x3
#define PMD_TYPE_FAULT 0
#define PMD_TYPE_LARGE 1
#define PMD_TYPE_SMALL 2
#define PMD_TYPE_TINY 3
/* Permission field offsets */
#define SECTION_AP0 10
#define PMD_SIZE SZ_1K
#define PMD_ENTRY_TOTAL 256
#define PMD_MAP_SIZE SZ_1MB
#define PMD_ALIGN_MASK (~(PMD_SIZE - 1))
#define PMD_TYPE_MASK 0x3
#define PMD_TYPE_FAULT 0
#define PMD_TYPE_PMD 1
#define PMD_TYPE_SECTION 2
/* We need this as printascii.S is including this file */
#define PTE_TYPE_MASK 0x3
#define PTE_TYPE_FAULT 0
#define PTE_TYPE_LARGE 1
#define PTE_TYPE_SMALL 2
#define PTE_TYPE_TINY 3
/* Permission field offsets */
#define SECTION_AP0 10
/*
* These are indices into arrays with pgd_t or pmd_t sized elements,
* therefore the index must be divided by appropriate element size
*/
#define PGD_INDEX(x) (((((unsigned long)(x)) >> 18) \
& 0x3FFC) / sizeof(pmd_t))
/*
* Strip out the page offset in this
* megabyte from a total of 256 pages.
*/
#define PMD_INDEX(x) (((((unsigned long)(x)) >> 10) \
& 0x3FC) / sizeof (pte_t))
/* We need this as print-early.S is including this file */
#ifndef __ASSEMBLY__
/* Type-checkable page table elements */
typedef u32 pgd_t;
typedef u32 pmd_t;
typedef u32 pte_t;
/* Page global directory made up of pgd_t entries */
typedef struct pgd_table {
pgd_t entry[PGD_ENTRY_TOTAL];
pmd_t entry[PGD_ENTRY_TOTAL];
} pgd_table_t;
/* Page middle directory made up of pmd_t entries */
typedef struct pmd_table {
pmd_t entry[PMD_ENTRY_TOTAL];
pte_t entry[PMD_ENTRY_TOTAL];
} pmd_table_t;
/* Applies for both small and large pages */
@@ -79,86 +91,38 @@ typedef struct pmd_table {
#define unbufferable 0
/* Helper macros for common cases */
#define __MAP_USR_RW_FLAGS (cacheable | bufferable | (SVC_RW_USR_RW << PAGE_AP0) \
| (SVC_RW_USR_RW << PAGE_AP1) | (SVC_RW_USR_RW << PAGE_AP2) \
| (SVC_RW_USR_RW << PAGE_AP3))
#define __MAP_USR_RO_FLAGS (cacheable | bufferable | (SVC_RW_USR_RO << PAGE_AP0) \
| (SVC_RW_USR_RO << PAGE_AP1) | (SVC_RW_USR_RO << PAGE_AP2) \
| (SVC_RW_USR_RO << PAGE_AP3))
#define __MAP_SVC_RW_FLAGS (cacheable | bufferable | (SVC_RW_USR_NONE << PAGE_AP0) \
| (SVC_RW_USR_NONE << PAGE_AP1) | (SVC_RW_USR_NONE << PAGE_AP2) \
| (SVC_RW_USR_NONE << PAGE_AP3))
#define __MAP_SVC_IO_FLAGS (uncacheable | unbufferable | (SVC_RW_USR_NONE << PAGE_AP0) \
| (SVC_RW_USR_NONE << PAGE_AP1) | (SVC_RW_USR_NONE << PAGE_AP2) \
| (SVC_RW_USR_NONE << PAGE_AP3))
#define __MAP_USR_IO_FLAGS (uncacheable | unbufferable | (SVC_RW_USR_RW << PAGE_AP0) \
| (SVC_RW_USR_RW << PAGE_AP1) | (SVC_RW_USR_RW << PAGE_AP2) \
| (SVC_RW_USR_RW << PAGE_AP3))
#define __MAP_USR_RW (cacheable | bufferable | (SVC_RW_USR_RW << PAGE_AP0) \
| (SVC_RW_USR_RW << PAGE_AP1) | (SVC_RW_USR_RW << PAGE_AP2) \
| (SVC_RW_USR_RW << PAGE_AP3))
#define __MAP_USR_RO (cacheable | bufferable | (SVC_RW_USR_RO << PAGE_AP0) \
| (SVC_RW_USR_RO << PAGE_AP1) | (SVC_RW_USR_RO << PAGE_AP2) \
| (SVC_RW_USR_RO << PAGE_AP3))
#define __MAP_KERN_RW (cacheable | bufferable | (SVC_RW_USR_NONE << PAGE_AP0) \
| (SVC_RW_USR_NONE << PAGE_AP1) | (SVC_RW_USR_NONE << PAGE_AP2) \
| (SVC_RW_USR_NONE << PAGE_AP3))
#define __MAP_KERN_IO (uncacheable | unbufferable | (SVC_RW_USR_NONE << PAGE_AP0) \
| (SVC_RW_USR_NONE << PAGE_AP1) | (SVC_RW_USR_NONE << PAGE_AP2) \
| (SVC_RW_USR_NONE << PAGE_AP3))
#define __MAP_USR_IO (uncacheable | unbufferable | (SVC_RW_USR_RW << PAGE_AP0) \
| (SVC_RW_USR_RW << PAGE_AP1) | (SVC_RW_USR_RW << PAGE_AP2) \
| (SVC_RW_USR_RW << PAGE_AP3))
/* Abort information */
/* There is no execute bit in ARMv5, so we ignore it */
#define __MAP_USR_RWX __MAP_USR_RW
#define __MAP_USR_RX __MAP_USR_RO
#define __MAP_KERN_RWX __MAP_KERN_RW
#define __MAP_KERN_RX __MAP_KERN_RW /* We always have kernel RW */
#define __MAP_FAULT 0
/*FIXME: Carry all these definitions to an abort.h, Also carry all abort code to abort.c. Much neater!!! */
/* Abort type */
#define ARM_PABT 1
#define ARM_DABT 0
/* The kernel makes use of bit 8 (Always Zero) of FSR to define which type of abort */
#define set_abort_type(fsr, x) { fsr &= ~(1 << 8); fsr |= ((x & 1) << 8); }
#define ARM_FSR_MASK 0xF
#define is_prefetch_abort(fsr) ((fsr >> 8) & 0x1)
#define is_data_abort(fsr) (!is_prefetch_abort(fsr))
/*
* v5 Architecture-defined data abort values for FSR ordered
* in highest to lowest priority.
*/
#define DABT_TERMINAL 0x2
#define DABT_VECTOR 0x0 /* Obsolete */
#define DABT_ALIGN 0x1
#define DABT_EXT_XLATE_LEVEL1 0xC
#define DABT_EXT_XLATE_LEVEL2 0xE
#define DABT_XLATE_SECT 0x5
#define DABT_XLATE_PAGE 0x7
#define DABT_DOMAIN_SECT 0x9
#define DABT_DOMAIN_PAGE 0xB
#define DABT_PERM_SECT 0xD
#define DABT_PERM_PAGE 0xF
#define DABT_EXT_LFETCH_SECT 0x4
#define DABT_EXT_LFETCH_PAGE 0x6
#define DABT_EXT_NON_LFETCH_SECT 0x8
#define DABT_EXT_NON_LFETCH_PAGE 0xA
#define TASK_PGD(x) (x)->space->pgd
#define STACK_ALIGNMENT 8
/* Kernel's data about the fault */
typedef struct fault_kdata {
u32 faulty_pc;
u32 fsr;
u32 far;
pte_t pte;
} __attribute__ ((__packed__)) fault_kdata_t;
void arch_hardware_flush(pgd_table_t *pgd);
void add_section_mapping_init(unsigned int paddr, unsigned int vaddr,
unsigned int size, unsigned int flags);
void add_boot_mapping(unsigned int paddr, unsigned int vaddr,
unsigned int size, unsigned int flags);
struct address_space;
int delete_page_tables(struct address_space *space);
int copy_user_tables(struct address_space *new, struct address_space *orig);
pgd_table_t *copy_page_tables(pgd_table_t *from);
void remap_as_pages(void *vstart, void *vend);
int pgd_count_pmds(pgd_table_t *pgd);
pgd_table_t *realloc_page_tables(void);
void remove_section_mapping(unsigned long vaddr);
void copy_pgds_by_vrange(pgd_table_t *to, pgd_table_t *from,
unsigned long start, unsigned long end);
extern pgd_table_t init_pgd;
void arch_update_utcb(unsigned long utcb_address);
void system_identify(void);
#endif /* __ASSEMBLY__ */
#endif /* __V5_MM_H__ */

19
include/l4/arch/arm/v5/mmu_ops.h
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@@ -18,6 +18,7 @@ void arm_enable_high_vectors(void);
void arm_invalidate_cache(void);
void arm_invalidate_icache(void);
void arm_invalidate_dcache(void);
void arm_clean_dcache(void);
void arm_clean_invalidate_dcache(void);
void arm_clean_invalidate_cache(void);
void arm_drain_writebuffer(void);
@@ -31,4 +32,22 @@ static inline void arm_enable_caches(void)
arm_enable_dcache();
}
static inline void dmb(void)
{
/* This is the closest to its meaning */
arm_drain_writebuffer();
}
static inline void dsb(void)
{
/* No op */
}
static inline void isb(void)
{
/* No op */
}
#endif /* __MMU__OPS__H__ */

6
include/l4/arch/arm/v5/perfmon.h Normal file
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@@ -0,0 +1,6 @@
#ifndef __PERFMON_H__
#define __PERFMON_H__
static inline void perfmon_init(void) { }
#endif