Kernel updates since December 2009

2026-01-21 15:23:15 +01:00 · 2010-03-25 01:12:40 +02:00
parent 16818191b3
commit 74b5963fcb
487 changed files with 22477 additions and 3857 deletions
--- a/include/l4/drivers/irq/gic/gic.h
+++ b/include/l4/drivers/irq/gic/gic.h
@@ -1,35 +1,91 @@
 /*
 * Generic Interrupt Controller offsets
 *
- * Copyright (C) 2007 Bahadir Balban
+ * Copyright (C) 2009 B Labs Ltd.
 *
 */

 #ifndef __ARM_GIC_H__
 #define __ARM_GIC_H__

+#include <l4/types.h>
 #include INC_PLAT(platform.h)
+#include INC_PLAT(offsets.h)

-/* GIC CPU register offsets */
-#define ARM_GIC_CPU_IC		0x00 /* Interface Control */
-#define ARM_GIC_CPUPM		0x04 /* Interrupt Priority Mask */
-#define ARM_GIC_CPU_BP		0x08 /* Binary Point */
-#define ARM_GIC_CPU_IA		0x0c /* Interrupt Acknowledge */
-#define ARM_GIC_CPU_EOI		0x10 /* End of Interrupt */
-#define ARM_GIC_CPU_RPI		0x14 /* Running Priority */
-#define ARM_GIC_CPU_HPI		0x18 /* Highest Priority Interrupt*/
+/* CPU registers */
+struct gic_cpu
+{
+	u32	  control;		/* Control Register */
+	u32	  prio_mask;		/* Priority Mask */
+	u32	  bin_point;		/* Binary Point Register */
+	u32	  ack;			/* Interrupt */
+	u32	  eoi;			/* End of Interrupt */
+	u32	  running;		/* Running Priority register */
+	u32	  high_pending;		/* Highest Pending Register */
+};

-/* Distributor register map */
-#define ARM_GIC_DIST_CNTRL	0x000 /* Control Register */
-#define ARM_GIC_DIST_ICT	0x004 /* Interface Controller Type */
-#define ARM_GIC_DIST_ISE	0x100 /* Interrupt Set Enable */
-#define ARM_GIC_DIST_ICE	0x180 /* Interrupt Clear Enable */
-#define ARM_GIC_DIST_ISP	0x200 /* Interrupt Set Pending */
-#define ARM_GIC_DIST_ICP	0x280 /* Interrupt Clear Pending*/
-#define ARM_GIC_DIST_AB		0x300 /* Active Bit */
-#define ARM_GIC_DIST_IP		0x400 /* Interrupt Priority */
-#define ARM_GIC_DIST_IPT	0x800 /* Interrupt Processor Target */
-#define ARM_GIC_DIST_IC		0xc00 /* Interrupt Configuration */
-#define ARM_GIC_DIST_SGI	0xf00 /* Software Generated Interrupt */
+#define NIRQ				1024
+#define NREGS_1_BIT_PER_INT		32	/* when 1 bit per interrupt  */
+#define NREGS_4_BIT_PER_INT		256
+#define NREGS_4_BIT_PER_INT		256
+#define NREGS_2_BIT_PER_INT		64
+#define NID		4

-#endif /* __ARM_GIC_H__ */
+/* Distributor registers */
+/* -r- -- reserved */
+struct	gic_dist{
+	u32	  control;				/* Control Register */
+	u32	  const	  type;				/* Type Register */
+	u32	  dummy1[62];				/* -r- */
+	u32	  set_en[NREGS_1_BIT_PER_INT];		/* Enable Set */
+	u32	  clr_en[NREGS_1_BIT_PER_INT];		/* Enable Clear */
+	u32	  set_pending[NREGS_1_BIT_PER_INT];	/* Set Pending */
+	u32	  clr_pending[NREGS_1_BIT_PER_INT];	/* Clear Pending */
+	u32	  active[NREGS_1_BIT_PER_INT];		/* Active Bit registers */
+	u32	  dummy2[32];				/* -r- */
+	u32	  priority[NREGS_4_BIT_PER_INT];	/* Interrupt Priority */
+	u32	  target[NREGS_4_BIT_PER_INT];		/* CPU Target Registers */
+	u32	  config[NREGS_2_BIT_PER_INT];		/* Interrupt Config */
+	u32	  level[NREGS_2_BIT_PER_INT];		/* Interrupt Line Level */
+	u32	  dummy3[64];				/* -r- */
+	u32	  soft_int;				/* Software Interrupts */
+	u32	  dummy4[55];				/* -r- */
+	u32	  id[NID];				/* Primecell ID registers */
+};
+
+
+struct gic_data {
+	struct gic_cpu *cpu;
+	struct gic_dist *dist;
+};
+
+
+l4id_t gic_read_irq(void *data);
+
+void gic_mask_irq(l4id_t irq);
+
+void gic_unmask_irq(l4id_t irq);
+
+void gic_ack_irq(l4id_t irq);
+
+void gic_ack_and_mask(l4id_t irq);
+
+void gic_clear_pending(l4id_t irq);
+
+void gic_cpu_init(int idx, unsigned long base);
+
+void gic_dist_init(int idx, unsigned long base);
+
+void gic_send_ipi(int cpu, int ipi_cmd);
+
+void gic_set_target(u32 irq, u32 cpu);
+
+u32 gic_get_target(u32 irq);
+
+void gic_set_priority(u32 irq, u32 prio);
+
+u32 gic_get_priority(u32 irq);
+
+void gic_dummy_init(void);
+
+#endif /* __GIC_H__ */
--- a/include/l4/drivers/irq/omap3/omap3_intc.h
+++ b/include/l4/drivers/irq/omap3/omap3_intc.h
@@ -0,0 +1,73 @@
+/*
+ * OMAP3XXX Interrupt Controller Defines
+ *
+ * Copyright 2010 B Labs Ltd.
+ */
+#ifndef __OMAP3_INTC_H__
+#define __OMAP3_INTC_H__
+
+#include INC_ARCH(io.h)
+
+#define OMAP3_INTC_SYSCONFIG		(0x00000010) /* RW */
+#define OMAP3_INTC_SYSSTATUS		(0x00000014) /* RO */
+
+#define OMAP3_INTC_SIR_IRQ		(0x00000040) /* RO */
+#define OMAP3_INTC_SIR_FIQ		(0x00000044) /* RO */
+#define OMAP3_INTC_CONTROL		(0x00000048) /* RW */
+#define OMAP3_INTC_PROT			(0x0000004C) /* RW - Protection */
+#define OMAP3_INTC_IDLE			(0x00000050) /* RW */
+
+#define OMAP3_INTC_IRQ_PRIO		(0x00000060) /* RW - IRQ Priority */
+#define OMAP3_INTC_FIQ_PRIO		(0x00000064) /* RW - FIQ Priority */
+#define OMAP3_INTC_THREASHOLD		(0x00000068) /* RW */
+
+#define OMAP3_INTC_ITR			(0x00000080) /* RO - Raw Interrupt Status*/
+#define OMAP3_INTC_MIR			(0x00000084) /* RW - Masked Int Status */
+#define OMAP3_INTC_MIR_CLR		(0x00000088) /* WO - Clear Mask*/
+#define OMAP3_INTC_MIR_SET		(0x0000008C) /* WO - Set Mask*/
+#define OMAP3_INTC_ISR_SET		(0x00000090) /* RW - Software Int Set */
+#define OMAP3_INTC_ISR_CLR		(0x00000094) /* WO */
+#define OMAP3_INTC_IRQ_PEND		(0x00000098) /* RO */
+#define OMAP3_INTC_FIQ_PEND		(0x0000009C) /* RO */
+#define OMAP3_INTC_ILR			(0x00000100) /* RW */
+
+/* Reset Bits */
+#define OMAP_INTC_SOFTRESET     (1 << 1)
+
+static inline unsigned int omap3_intc_get_ilr(unsigned long base,
+					     unsigned int irq)
+{
+	return read((base + OMAP3_INTC_ILR + (irq * 4)));
+}
+
+static inline void  omap3_intc_set_ilr(unsigned long base, unsigned int irq,
+				       unsigned int val)
+{
+	write(val, (base + OMAP3_INTC_ILR + (irq * 4)));
+}
+
+/* Set clear Interrupt masks */
+static inline
+void omap3_intc_set_irq_status(unsigned long base, unsigned int reg,
+			       unsigned int irq)
+{
+	unsigned int val = 0;
+	unsigned int offset = (irq >> 5); /* Same as dividing by 32 */
+
+	irq -= (offset * 32);
+
+	val = read((base + reg + (0x20 * offset)));
+        val |= (1 << irq);
+	write(val, (base + reg + (0x20 * offset)));
+}
+
+void omap3_intc_reset(unsigned long base);
+void omap3_intc_init(void);
+void omap3_intc_eoi_irq(l4id_t irq);
+void omap3_intc_mask_irq(l4id_t irq);
+void omap3_intc_unmask_irq(l4id_t irq);
+void omap3_intc_ack_irq(l4id_t irq);
+void omap3_intc_ack_and_mask(l4id_t irq);
+l4id_t omap3_intc_read_irq(void *data);
+
+#endif	/* !__OMAP3_INTC_H__ */
--- a/include/l4/drivers/irq/pl190/pl190_vic.h
+++ b/include/l4/drivers/irq/pl190/pl190_vic.h
@@ -10,9 +10,10 @@

 #include INC_PLAT(platform.h)
 #include INC_ARCH(types.h)
+#include INC_ARCH(io.h)

-#define PL190_BASE				PLATFORM_IRQCTRL0_VIRTUAL
-#define PL190_SIC_BASE				PLATFORM_IRQCTRL1_VIRTUAL
+#define PL190_BASE				PLATFORM_IRQCTRL0_VBASE
+#define PL190_SIC_BASE				PLATFORM_IRQCTRL1_VBASE

 #define PL190_IRQS_MAX				32

@@ -49,9 +50,9 @@ void pl190_vic_init(void);
 void pl190_ack_irq(l4id_t irq);
 void pl190_mask_irq(l4id_t irq);
 void pl190_unmask_irq(l4id_t irq);
-l4id_t pl190_read_irq(void);
+l4id_t pl190_read_irq(void *irq_chip_data);

-l4id_t pl190_sic_read_irq(void);
+l4id_t pl190_sic_read_irq(void *irq_chip_data);
 void pl190_sic_mask_irq(l4id_t irq);
 void pl190_sic_mask_irq(l4id_t irq);
 void pl190_sic_ack_irq(l4id_t irq);
--- a/include/l4/drivers/timer/omap/timer.h
+++ b/include/l4/drivers/timer/omap/timer.h
@@ -0,0 +1,52 @@
+/*
+ * OMAP GP Timer offsets
+ *
+ * Copyright (C) 2007 Bahadir Balban
+ *
+ */
+#ifndef __OMAP_GPTIMER_H__
+#define __OMAP_GPTIMER_H__
+
+/* Register offsets */
+#define OMAP_TIMER_TIOCP		0x10
+#define OMAP_TIMER_TSTAT		0x14
+#define OMAP_TIMER_TISR                 0x18
+#define OMAP_TIMER_TIER			0x1C
+#define OMAP_TIMER_TCLR			0x24
+#define OMAP_TIMER_TCRR			0x28
+#define OMAP_TIMER_TLDR                 0x2C
+#define OMAP_TIMER_TMAR				0x38
+#define OMAP_TIMER_TPIR			0x48
+#define OMAP_TIMER_TNIR			0x4C
+#define OMAP_TIMER_TCVR			0x50
+
+/* Enable/Disable IRQ */
+#define OMAP_TIMER_IRQENABLE		1
+#define OMAP_TIMER_IRQDISABLE		0
+
+/* Timer modes supported */
+#define OMAP_TIMER_MODE_AUTORELAOD	1
+#define OMAP_TIMER_MODE_COMPARE		6
+#define OMAP_TIMER_MODE_CAPTURE		13
+
+/* Interrupt types */
+#define OMAP_TIMER_INTR_MATCH           0x0
+#define OMAP_TIMER_INTR_OVERFLOW        0x1
+#define OMAP_TIMER_INTR_CAPTURE         0x2
+
+/* Clock source for timer */
+#define OMAP_TIMER_CLKSRC_SYS_CLK	0x1
+#define OMAP_TIMER_CLKSRC_32KHZ_CLK	0x0
+
+void timer_init_oneshot(unsigned long timer_base);
+u32 timer_periodic_intr_status(unsigned long timer_base);
+void timer_reset(unsigned long timer_base);
+void timer_load(unsigned long timer_base, u32 value);
+u32 timer_read(unsigned long timer_base);
+void timer_start(unsigned long timer_base);
+void timer_stop(unsigned long timer_base);
+void timer_init_periodic(unsigned long timer_base);
+void timer_irq_clear(unsigned long timer_base);
+void timer_init(unsigned long timer_base);
+
+#endif /* __OMAP_GPTIMER_H__*/
--- a/include/l4/drivers/timer/sp804/timer.h
+++ b/include/l4/drivers/timer/sp804/timer.h
@@ -0,0 +1,46 @@
+/*
+ * SP804 Primecell Timer offsets
+ *
+ * Copyright (C) 2007 Bahadir Balban
+ *
+ */
+#ifndef __SP804_TIMER_H__
+#define __SP804_TIMER_H__
+
+#include INC_ARCH(io.h)
+
+/* Register offsets */
+#define SP804_LOAD			0x0
+#define SP804_VALUE			0x4
+#define SP804_CTRL			0x8
+#define SP804_INTCLR			0xC
+#define SP804_RIS			0x10
+#define SP804_MIS			0x14
+#define SP804_BGLOAD			0x18
+
+#define SP804_ENABLE			(1 << 7)
+#define SP804_PERIODIC			(1 << 6)
+#define SP804_IRQEN			(1 << 5)
+#define SP804_32BIT			(1 << 1)
+#define SP804_ONESHOT			(1 << 0)
+
+#define SP804_SECONDARY_OFFSET		0x20
+
+/* Timer prescaling */
+#define SP804_SCALE_SHIFT		2
+#define SP804_SCALE_DIV16		1
+#define SP804_SCALE_DIV256		2
+
+/* Wrapping = 0, Oneshot = 1 */
+#define SP804_ONESHOT			(1 << 0)
+
+unsigned long timer_secondary_base(unsigned long timer_base);
+void timer_irq_clear(unsigned long timer_base);
+void timer_start(unsigned long timer_base);
+void timer_load(u32 loadval, unsigned long timer_base);
+u32 timer_read(unsigned long timer_base);
+void timer_stop(unsigned long timer_base);
+void timer_init_periodic(unsigned long timer_base, unsigned int load_value);
+void timer_init_oneshot(unsigned long timer_base);
+void timer_init(unsigned long timer_base, unsigned int load_value);
+#endif /* __SP804_TIMER_H__ */
--- a/include/l4/drivers/uart/omap/uart.h
+++ b/include/l4/drivers/uart/omap/uart.h
@@ -0,0 +1,62 @@
+/*
+ * OMAP UART Generic driver implementation.
+ *
+ * Copyright (C) 2007 Bahadir Balban
+ *
+ * The particular intention of this code is that it has been carefully written
+ * as decoupled from os-specific code and in a verbose way such that it clearly
+ * demonstrates how the device operates, reducing the amount of time to be spent
+ * for understanding the operational model and implementing a driver from
+ * scratch. This is the very first to be such a driver so far, hopefully it will
+ * turn out to be useful.
+ */
+
+#ifndef __OMAP_UART_H__
+#define __OMAP_UART_H__
+
+#include INC_PLAT(uart.h)
+#include INC_ARCH(io.h)
+
+/* Register offsets */
+#define OMAP_UART_DLL		0x00
+#define OMAP_UART_THR		0x00
+#define OMAP_UART_RHR		0x00
+#define OMAP_UART_DLH		0x04
+#define OMAP_UART_IER		0x04
+#define OMAP_UART_FCR		0x08
+#define OMAP_UART_MCR		0x10
+#define OMAP_UART_LSR		0x14
+#define OMAP_UART_MDR1		0x20
+#define	OMAP_UART_LCR		0x0C
+
+/* Modes supported by OMAP UART/IRDA/CIR IP */
+#define OMAP_UART_MODE_UART16X               0x0
+#define OMAP_UART_MODE_SIR                   0x1
+#define OMAP_UART_MODE_UART16X_AUTO_BAUD     0x2
+#define OMAP_UART_MODE_UART13X               0x3
+#define OMAP_UART_MODE_MIR                   0x4
+#define OMAP_UART_MODE_FIR                   0x5
+#define OMAP_UART_MODE_CIR                   0x6
+#define OMAP_UART_MODE_DEFAULT               0x7 /* Disable */
+
+/* Number of data bits for UART */
+#define OMAP_UART_DATA_BITS_5           0x0
+#define OMAP_UART_DATA_BITS_6           0x1
+#define OMAP_UART_DATA_BITS_7           0x2
+#define OMAP_UART_DATA_BITS_8           0x3
+
+/* Stop bits to be used for UART data */
+#define OMAP_UART_STOP_BITS_1           0x0
+#define OMAP_UART_STOP_BITS_1_5         0x1
+
+/* Banked Register modes- ConfigA, ConfigB, Operational */
+#define OMAP_UART_BANKED_MODE_OPERATIONAL      0x00
+#define OMAP_UART_BANKED_MODE_CONFIG_A         0x80
+#define OMAP_UART_BANKED_MODE_CONFIG_B         0xBF
+
+void uart_tx_char(unsigned long base, char c);
+char uart_rx_char(unsigned long uart_base);
+void uart_set_baudrate(unsigned long uart_base, u32 baudrate, u32 clkrate);
+void uart_init(unsigned long uart_base);
+
+#endif /* __OMAP_UART_H__ */
--- a/include/l4/drivers/uart/pl011/uart.h
+++ b/include/l4/drivers/uart/pl011/uart.h
@@ -0,0 +1,35 @@
+/*
+ * PL011 UART Generic driver implementation.
+ * Copyright Bahadir Balban (C) 2009
+ */
+#ifndef __PL011_H__
+#define __PL011_H__
+
+#include INC_ARCH(io.h)
+#include INC_PLAT(offsets.h)
+
+/* Register offsets */
+#define PL011_UARTDR		0x00
+#define PL011_UARTRSR		0x04
+#define PL011_UARTECR		0x04
+#define PL011_UARTFR		0x18
+#define PL011_UARTILPR		0x20
+#define PL011_UARTIBRD		0x24
+#define PL011_UARTFBRD		0x28
+#define PL011_UARTLCR_H		0x2C
+#define PL011_UARTCR		0x30
+#define PL011_UARTIFLS		0x34
+#define PL011_UARTIMSC		0x38
+#define PL011_UARTRIS		0x3C
+#define PL011_UARTMIS		0x40
+#define PL011_UARTICR		0x44
+#define PL011_UARTDMACR		0x48
+
+
+void uart_tx_char(unsigned long uart_base, char c);
+char uart_rx_char(unsigned long uart_base);
+void uart_init(unsigned long base);
+
+
+#endif /* __PL011__UART__ */
+