mirror of
https://github.com/drasko/codezero.git
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Kernel updates since December 2009
This commit is contained in:
Bahadir Balban
25
include/l4/platform/beagle/cm.h
Normal file
25
include/l4/platform/beagle/cm.h
Normal file
@@ -0,0 +1,25 @@
|
||||
/*
|
||||
* Clock mangaer module of the beagleboard.
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||||
*
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||||
* Copyright (C) 2007 Bahadir Balban
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||||
*
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||||
*/
|
||||
|
||||
#ifndef __PLATFORM_BEAGLE_CM_H__
|
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#define __PLATFORM_BEAGLE_CM_H__
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||||
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/*
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||||
* Register offsets for Clock Manager(CM)
|
||||
* PER_CM, WKUP_CM etc all have same offsets
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* for registers
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*/
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#define CM_FCLKEN_OFFSET 0x00
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#define CM_ICLKEN_OFFSET 0x10
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#define CM_CLKSEL_OFFSET 0x40
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void omap_cm_enable_iclk(unsigned long cm_base, int bit);
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void omap_cm_enable_fclk(unsigned long cm_base, int bit);
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void omap_cm_clk_select(unsigned long cm_base, int bit, int src);
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|
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#endif /* __PLATFORM_BEAGLE_CM_H__ */
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|
||||
35
include/l4/platform/beagle/irq.h
Normal file
35
include/l4/platform/beagle/irq.h
Normal file
@@ -0,0 +1,35 @@
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#ifndef __PLATFORM_IRQ_H__
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#define __PLATFORM_IRQ_H__
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/*
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* Support for generic irq handling using platform irq controller (GIC)
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*
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* Copyright (C) 2007 Bahadir Balban
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||||
*/
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||||
|
||||
/* TODO: Not sure about this, need to check */
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#define IRQ_CHIPS_MAX 1
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#define IRQS_MAX 96
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/* IRQ indices. */
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#define IRQ_UART0 72
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#define IRQ_UART1 73
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#define IRQ_UART2 74
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|
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/* General Purpose Timers */
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#define IRQ_TIMER0 37
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#define IRQ_TIMER1 38
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#define IRQ_TIMER2 39
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#define IRQ_TIMER3 40
|
||||
#define IRQ_TIMER4 41
|
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#define IRQ_TIMER5 42
|
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#define IRQ_TIMER6 43
|
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#define IRQ_TIMER7 44
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#define IRQ_TIMER8 45
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#define IRQ_TIMER9 46
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#define IRQ_TIMER10 47
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#define IRQ_TIMER11 95
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#endif /* __PLATFORM_IRQ_H__ */
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66
include/l4/platform/beagle/offsets.h
Normal file
66
include/l4/platform/beagle/offsets.h
Normal file
@@ -0,0 +1,66 @@
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/*
|
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*
|
||||
* Describes physical memory layout of Beagle Boards.
|
||||
* We have rev3 boards.
|
||||
*
|
||||
* Copyright (C) 2007 Bahadir Balban
|
||||
*/
|
||||
|
||||
#ifndef __PLATFORM_BEAGLE_OFFSETS_H__
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||||
#define __PLATFORM_BEAGLE_OFFSETS_H__
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||||
|
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/*
|
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* Physical memory base
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* FIXME: Somewhere its written: Rev 1 and 2
|
||||
* of Beagleboard has 128MB SDRAM while Rev 3 has 256MB
|
||||
* SDRAM which is detected automatically on intiliazation,
|
||||
* we have Rev3 boards, so hardcoding this only.
|
||||
*/
|
||||
#define PLATFORM_PHYS_MEM_START 0x80000000 /* inclusive */
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||||
#define PLATFORM_PHYS_MEM_END 0x90000000 /* 256MB, exclusive */
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/*
|
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* Device offsets in physical memory
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* Naming of devices done starting with 0 subscript,
|
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* as we use these names for device capability
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*/
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#define PLATFORM_WKUP_CM_BASE 0x48004C00 /* Wake up clock manager */
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#define PLATFORM_PERCM_BASE 0x48005000 /* Peripheral Clock Manager */
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#define PLATFORM_UART0_BASE 0x4806A000 /* UART 0 */
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#define PLATFORM_UART1_BASE 0x4806C000 /* UART 1 */
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#define PLATFORM_UART2_BASE 0x49020000 /* UART 2 */
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||||
#define PLATFORM_TIMER0_BASE 0x48318000 /* GPTIMER1 */
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#define PLATFORM_TIMER1_BASE 0x49032000 /* GPTIMER2 */
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||||
#define PLATFORM_TIMER2_BASE 0x49034000 /* GPTIMER3 */
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#define PLATFORM_TIMER3_BASE 0x49036000 /* GPTIMER4 */
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#define PLATFORM_TIMER4_BASE 0x49038000 /* GPTIMER5 */
|
||||
#define PLATFORM_TIMER5_BASE 0x4903A000 /* GPTIMER6 */
|
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#define PLATFORM_TIMER6_BASE 0x4903C000 /* GPTIMER7 */
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||||
#define PLATFORM_TIMER7_BASE 0x4903E000 /* GPTIMER8 */
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#define PLATFORM_TIMER8_BASE 0x49040000 /* GPTIMER9 */
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||||
#define PLATFORM_TIMER9_BASE 0x48086000 /* GPTIMER10 */
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||||
#define PLATFORM_TIMER10_BASE 0x48088000 /* GPTIMER11 */
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||||
#define PLATFORM_TIMER11_BASE 0x48304000 /* GPTIMER12 */
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#define PLATFORM_INTC_BASE 0x48200000 /* Interrupt controller */
|
||||
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||||
/*
|
||||
* Virtual Memory base address, where devices will be mapped.
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* Each Device will take one page in virtual memory.
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* Nice and smooth.
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||||
*/
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#define DEVICE_PAGE 0x1000
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#define PLATFORM_WKUP_CM_VBASE (IO_AREA0_VADDR + (0 * DEVICE_PAGE))
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#define PLATFORM_CONSOLE_VBASE (IO_AREA0_VADDR + (1 * DEVICE_PAGE))
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||||
#define PLATFORM_TIMER0_VBASE (IO_AREA0_VADDR + (2 * DEVICE_PAGE))
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#define PLATFORM_INTC_VBASE (IO_AREA0_VADDR + (3 * DEVICE_PAGE))
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||||
#define PLATFORM_PERCM_VBASE (IO_AREA0_VADDR + (4 * DEVICE_PAGE))
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||||
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||||
/* Add userspace devices here as they become necessary for irqs */
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||||
#define PLATFORM_TIMER1_VBASE (IO_AREA0_VADDR + (5 * DEVICE_PAGE))
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||||
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||||
/* Add size of various user space devices, to be used in capability generation */
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#define PLATFORM_TIMER1_SIZE DEVICE_PAGE
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||||
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||||
#endif /* __PLATFORM_BEAGLE_OFFSETS_H__ */
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||||
|
||||
18
include/l4/platform/beagle/platform.h
Normal file
18
include/l4/platform/beagle/platform.h
Normal file
@@ -0,0 +1,18 @@
|
||||
#ifndef __BEAGLE_PLATFORM_H__
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#define __BEAGLE_PLATFORM_H__
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/*
|
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* Platform specific ties between drivers and generic APIs used by the kernel.
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* E.g. system timer and console.
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||||
*
|
||||
* Copyright (C) Bahadir Balban 2007
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*/
|
||||
|
||||
#include INC_PLAT(offsets.h)
|
||||
#include INC_GLUE(memlayout.h)
|
||||
#include <l4/generic/capability.h>
|
||||
#include <l4/generic/cap-types.h>
|
||||
|
||||
void platform_timer_start(void);
|
||||
|
||||
void platform_test_cpucycles(void);
|
||||
#endif /* __BEAGLE_PLATFORM_H__ */
|
||||
13
include/l4/platform/beagle/timer.h
Normal file
13
include/l4/platform/beagle/timer.h
Normal file
@@ -0,0 +1,13 @@
|
||||
/*
|
||||
* Platform encapsulation over timer driver.
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||||
*
|
||||
* Copyright (C) 2007 Bahadir Balban
|
||||
*
|
||||
*/
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||||
|
||||
#ifndef __PLATFORM_BEAGLE_TIMER_H__
|
||||
#define __PLATFORM_BEAGLE_TIMER_H__
|
||||
|
||||
#include <l4/drivers/timer/omap/timer.h>
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||||
#endif /* __PLATFORM_BEAGLE_TIMER_H__ */
|
||||
13
include/l4/platform/beagle/uart.h
Normal file
13
include/l4/platform/beagle/uart.h
Normal file
@@ -0,0 +1,13 @@
|
||||
/*
|
||||
* Platform specific ties to generic uart functions that putc expects.
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||||
*
|
||||
* Copyright (C) 2007 Bahadir Balban
|
||||
*
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||||
*/
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||||
|
||||
#ifndef __PLATFORM_BEAGLE_UART_H__
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||||
#define __PLATFORM_BEAGLE_UART_H__
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||||
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||||
#include <l4/drivers/uart/omap/uart.h>
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||||
|
||||
#endif /* __PLATFORM_BEAGLE_UART_H__ */
|
||||
@@ -1,26 +1,20 @@
|
||||
/*
|
||||
* Copyright (C) 2009 B Labs Ltd.
|
||||
*/
|
||||
|
||||
#ifndef __PLATFORM_IRQ_H__
|
||||
#define __PLATFORM_IRQ_H__
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||||
|
||||
/* TODO: Not sure about this, need to check */
|
||||
#define IRQ_CHIPS_MAX 4
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#define IRQS_MAX 96
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||||
/* Actually there are 4 GIC's on the EB, only 2 are used for tile site 1 */
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||||
#define IRQ_CHIPS_MAX 2
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#if defined(CONFIG_CPU_ARM11MPCORE) || defined (CONFIG_CPU_CORTEXA9)
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#define IRQS_MAX 64
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#else
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#define IRQS_MAX 96
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#endif
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/*
|
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* IRQ indices,
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* GIC 0 and 1 are for logic tile 1
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* GIC 2 and 3 are for logic tile 2
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||||
*/
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#define IRQ_TIMER01 4
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#define IRQ_TIMER23 5
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#define IRQ_RTC 10
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#define IRQ_UART0 12
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#define IRQ_UART1 13
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#define IRQ_UART2 14
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#define IRQ_UART3 15
|
||||
|
||||
/*
|
||||
* TODO: Seems like GIC0 and GIC1 are cascaded for logic tile1
|
||||
* and GIC2 and GIC3 are cascaded for logic tile 2.
|
||||
* Interrupt Distribution:
|
||||
* 0-31: Used as SI provided by distributed interrupt controller
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* 32-63: Externel Peripheral Interrupts
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@@ -28,4 +22,57 @@
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* 72-79: Interrupts from tile site 2
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* 80-95: PCI and reserved Interrupts
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||||
*/
|
||||
#define EB_GIC_IRQ_OFFSET 32
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#define EB_IRQ_WATCHDOG (EB_GIC_IRQ_OFFSET + 0)
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#define EB_IRQ_SOFTINT (EB_GIC_IRQ_OFFSET + 1)
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#define EB_IRQ_COMRX (EB_GIC_IRQ_OFFSET + 2)
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#define EB_IRQ_COMTX (EB_GIC_IRQ_OFFSET + 3)
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#define EB_IRQ_TIMER01 (EB_GIC_IRQ_OFFSET + 4)
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#define EB_IRQ_TIMER23 (EB_GIC_IRQ_OFFSET + 5)
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#define EB_IRQ_GPIO0 (EB_GIC_IRQ_OFFSET + 6)
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#define EB_IRQ_GPIO1 (EB_GIC_IRQ_OFFSET + 7)
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#define EB_IRQ_GPIO2 (EB_GIC_IRQ_OFFSET + 8)
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||||
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#define EB_IRQ_RTC (EB_GIC_IRQ_OFFSET + 10)
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||||
#define EB_IRQ_UART0 (EB_GIC_IRQ_OFFSET + 12)
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#define EB_IRQ_UART1 (EB_GIC_IRQ_OFFSET + 13)
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#define EB_IRQ_UART2 (EB_GIC_IRQ_OFFSET + 14)
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#define EB_IRQ_UART3 (EB_GIC_IRQ_OFFSET + 15)
|
||||
#define EB_IRQ_SCI (EB_GIC_IRQ_OFFSET + 16) /* Smart Card Interface */
|
||||
#define EB_IRQ_MCI0 (EB_GIC_IRQ_OFFSET + 17)
|
||||
#define EB_IRQ_MCI1 (EB_GIC_IRQ_OFFSET + 18)
|
||||
#define EB_IRQ_AACI (EB_GIC_IRQ_OFFSET + 19) /* Advanced Audio codec */
|
||||
#define EB_IRQ_KMI0 (EB_GIC_IRQ_OFFSET + 20) /* Keyboard */
|
||||
#define EB_IRQ_KMI1 (EB_GIC_IRQ_OFFSET + 21) /* Mouse */
|
||||
#define EB_IRQ_LCD (EB_GIC_IRQ_OFFSET + 20) /* Character LCD */
|
||||
#define EB_IRQ_DMAC (EB_GIC_IRQ_OFFSET + 20) /* DMA Controller */
|
||||
|
||||
|
||||
/* Interrupt Sources to ARM 11 MPCore or EB+A9 MPCore GIC */
|
||||
#define MPCORE_GIC_IRQ_AACI (EB_GIC_IRQ_OFFSET + 0)
|
||||
#define MPCORE_GIC_IRQ_TIMER01 (EB_GIC_IRQ_OFFSET + 1)
|
||||
#define MPCORE_GIC_IRQ_TIMER23 (EB_GIC_IRQ_OFFSET + 2)
|
||||
#define MPCORE_GIC_IRQ_USB (EB_GIC_IRQ_OFFSET + 3)
|
||||
#define MPCORE_GIC_IRQ_UART0 (EB_GIC_IRQ_OFFSET + 4)
|
||||
#define MPCORE_GIC_IRQ_UART1 (EB_GIC_IRQ_OFFSET + 5)
|
||||
#define MPCORE_GIC_IRQ_RTC (EB_GIC_IRQ_OFFSET + 6)
|
||||
#define MPCORE_GIC_IRQ_KMI0 (EB_GIC_IRQ_OFFSET + 7)
|
||||
#define MPCORE_GIC_IRQ_KMI1 (EB_GIC_IRQ_OFFSET + 8)
|
||||
#define MPCORE_GIC_IRQ_ETH (EB_GIC_IRQ_OFFSET + 9)
|
||||
|
||||
/* Interrupt from GIC1 on Base board */
|
||||
#define MPCORE_GIC_IRQ_EB_GIC1 (EB_GIC_IRQ_OFFSET + 10)
|
||||
#define MPCORE_GIC_IRQ_EB_GIC2 (EB_GIC_IRQ_OFFSET + 11)
|
||||
#define MPCORE_GIC_IRQ_EB_GIC3 (EB_GIC_IRQ_OFFSET + 12)
|
||||
#define MPCORE_GIC_IRQ_EB_GIC4 (EB_GIC_IRQ_OFFSET + 13)
|
||||
|
||||
#if defined (CONFIG_CPU_ARM11MPCORE) || defined (CONFIG_CPU_CORTEXA9)
|
||||
#define IRQ_TIMER0 MPCORE_GIC_IRQ_TIMER01
|
||||
#define IRQ_TIMER1 MPCORE_GIC_IRQ_TIMER23
|
||||
#else
|
||||
#define IRQ_TIMER0 EB_IRQ_TIMER01
|
||||
#define IRQ_TIMER1 EB_IRQ_TIMER23
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __PLATFORM_IRQ_H__ */
|
||||
|
||||
@@ -1,71 +1,61 @@
|
||||
/*
|
||||
* Describes physical memory layout of EB platform.
|
||||
*
|
||||
* Copyright (C) 2007 Bahadir Balban
|
||||
* This only include physical and memory offsets that
|
||||
* are not included in realview/offsets.h
|
||||
*
|
||||
* Copyright (C) 2009 B Labs Ltd.
|
||||
* Author: Prem Mallappa <prem.mallappa@b-labs.co.uk>
|
||||
*/
|
||||
|
||||
#ifndef __PLATFORM_EB_OFFSETS_H__
|
||||
#define __PLATFORM_EB_OFFSETS_H__
|
||||
|
||||
/* Physical memory base */
|
||||
#define PHYS_MEM_START 0x00000000 /* inclusive */
|
||||
#define PHYS_MEM_END 0x10000000 /* 256 MB, exclusive */
|
||||
|
||||
/*
|
||||
* These bases taken from where kernel is `physically' linked at,
|
||||
* also used to calculate virtual-to-physical translation offset.
|
||||
* See the linker script for their sources. PHYS_ADDR_BASE can't
|
||||
* use a linker variable because it's referred from assembler.
|
||||
*/
|
||||
#define PHYS_ADDR_BASE 0x100000
|
||||
|
||||
/* Device memory base */
|
||||
#define EB_DEV_PHYS 0x10000000
|
||||
#include <l4/platform/realview/offsets.h>
|
||||
|
||||
/* Device offsets in physical memory */
|
||||
#define EB_SYSTEM_REGISTERS 0x10000000 /* System registers */
|
||||
#define EB_SYSCTRL_BASE 0x10001000 /* System controller */
|
||||
#define EB_UART0_BASE 0x10009000 /* UART 0 */
|
||||
#define EB_UART1_BASE 0x1000A000 /* UART 1 */
|
||||
#define EB_UART2_BASE 0x1000B000 /* UART 2 */
|
||||
#define EB_UART3_BASE 0x1000C000 /* UART 3 */
|
||||
#define EB_WATCHDOG0_BASE 0x10010000 /* WATCHDOG */
|
||||
#define EB_TIMER01_BASE 0x10011000 /* TIMER 0-1 */
|
||||
#define EB_TIMER23_BASE 0x10012000 /* TIMER 2-3 */
|
||||
#define EB_RTC_BASE 0x10017000 /* RTC interface */
|
||||
#define EB_GIC0_BASE 0x10040000 /* GIC 0 */
|
||||
#define EB_GIC1_BASE 0x10050000 /* GIC 1 */
|
||||
#define EB_GIC2_BASE 0x10060000 /* GIC 2 */
|
||||
#define EB_GIC3_BASE 0x10070000 /* GIC 3 */
|
||||
#define PLATFORM_GIC1_BASE 0x10040000 /* GIC 1 */
|
||||
#define PLATFORM_GIC2_BASE 0x10050000 /* GIC 2 */
|
||||
#define PLATFORM_GIC3_BASE 0x10060000 /* GIC 3 */
|
||||
#define PLATFORM_GIC4_BASE 0x10070000 /* GIC 4 */
|
||||
|
||||
/*
|
||||
* Uart virtual address until a file-based console access
|
||||
* is available for userspace
|
||||
*/
|
||||
#define USERSPACE_UART_BASE 0x500000
|
||||
#define MPCORE_PRIVATE_VBASE (IO_AREA0_VADDR + (13 * DEVICE_PAGE))
|
||||
|
||||
/*
|
||||
* Device offsets in virtual memory. They offset to some virtual
|
||||
* device base address. Each page on this virtual base is consecutively
|
||||
* allocated to devices. Nice and smooth.
|
||||
*/
|
||||
#define EB_SYSREGS_VOFFSET 0x00000000
|
||||
#define EB_SYSCTRL_VOFFSET 0x00001000
|
||||
#define EB_UART0_VOFFSET 0x00002000
|
||||
#define EB_TIMER01_VOFFSET 0x00003000
|
||||
#define EB_GIC0_VOFFSET 0x00004000
|
||||
#define EB_GIC1_VOFFSET 0x00005000
|
||||
#define EB_GIC2_VOFFSET 0x00006000
|
||||
#define EB_GIC3_VOFFSET 0x00007000
|
||||
#if defined (CONFIG_CPU_CORTEXA9)
|
||||
#define MPCORE_PRIVATE_BASE 0x1F000000
|
||||
#endif /* End CORTEXA9 */
|
||||
|
||||
#define EB_SYSREGS_VBASE (IO_AREA0_VADDR + EB_SYSREGS_VOFFSET)
|
||||
#define EB_SYSCTRL_VBASE (IO_AREA0_VADDR + EB_SYSCTRL_VOFFSET)
|
||||
#define EB_UART0_VBASE (IO_AREA0_VADDR + EB_UART0_VOFFSET)
|
||||
#define EB_TIMER01_VBASE (IO_AREA0_VADDR + EB_TIMER01_VOFFSET)
|
||||
#define EB_GIC0_VBASE (IO_AREA0_VADDR + EB_GIC0_VOFFSET)
|
||||
#define EB_GIC1_VBASE (IO_AREA0_VADDR + EB_GIC1_VOFFSET)
|
||||
#define EB_GIC2_VBASE (IO_AREA0_VADDR + EB_GIC2_VOFFSET)
|
||||
#define EB_GIC3_VBASE (IO_AREA0_VADDR + EB_GIC3_VOFFSET)
|
||||
#if defined (CONFIG_CPU_ARM11MPCORE)
|
||||
#if defined REV_C || defined REV_D
|
||||
#define MPCORE_PRIVATE_BASE 0x1F000000
|
||||
#else /* REV_B and QEMU */
|
||||
#define MPCORE_PRIVATE_BASE 0x10100000
|
||||
#endif /* End REV_B and QEMU */
|
||||
#endif /* End ARM11MPCORE */
|
||||
|
||||
#if defined (CONFIG_CPU_CORTEXA9) || defined (CONFIG_CPU_ARM11MPCORE)
|
||||
/* MPCore private memory region */
|
||||
#define SCU_BASE MPCORE_PRIVATE_BASE
|
||||
#define SCU_VBASE MPCORE_PRIVATE_VBASE
|
||||
#define GIC0_CPU_VBASE (MPCORE_PRIVATE_VBASE + 0x100)
|
||||
#define GIC0_DIST_VBASE (MPCORE_PRIVATE_VBASE + 0x1000)
|
||||
#endif /* End CORTEXA9 || ARM11MPCORE */
|
||||
|
||||
#define GIC1_CPU_VBASE (PLATFORM_GIC1_VBASE + 0x0)
|
||||
#define GIC2_CPU_VBASE (PLATFORM_GIC2_VBASE + 0x0)
|
||||
#define GIC3_CPU_VBASE (PLATFORM_GIC3_VBASE + 0x0)
|
||||
#define GIC4_CPU_VBASE (PLATFORM_GIC4_VBASE + 0x0)
|
||||
|
||||
#define GIC1_DIST_VBASE (PLATFORM_GIC1_VBASE + 0x1000)
|
||||
#define GIC2_DIST_VBASE (PLATFORM_GIC2_VBASE + 0x1000)
|
||||
#define GIC3_DIST_VBASE (PLATFORM_GIC3_VBASE + 0x1000)
|
||||
#define GIC4_DIST_VBASE (PLATFORM_GIC4_VBASE + 0x1000)
|
||||
|
||||
#if defined (CONFIG_CPU_ARM11MPCORE) || defined (CONFIG_CPU_CORTEXA9)
|
||||
#define PLATFORM_IRQCTRL0_VIRTUAL EB_GIC0_VBASE
|
||||
#endif
|
||||
|
||||
#define PLATFORM_IRQCTRL1_VIRTUAL EB_GIC1_VBASE
|
||||
|
||||
#endif /* __PLATFORM_EB_OFFSETS_H__ */
|
||||
|
||||
|
||||
@@ -1,28 +1,18 @@
|
||||
#ifndef __EB_PLATFORM_H__
|
||||
#define __EB_PLATFORM_H__
|
||||
/*
|
||||
* Platform specific ties between drivers and generic APIs used by the kernel.
|
||||
* E.g. system timer and console.
|
||||
*
|
||||
* Copyright (C) Bahadir Balban 2007
|
||||
* Copyright (C) 2009 B Labs Ltd.
|
||||
*/
|
||||
#ifndef __EB_PLATFORM_H__
|
||||
#define __EB_PLATFORM_H__
|
||||
|
||||
#include INC_PLAT(offsets.h)
|
||||
#include INC_GLUE(memlayout.h)
|
||||
#include INC_PLAT(sysctrl.h)
|
||||
#include <l4/drivers/irq/gic/gic.h>
|
||||
#include <l4/platform/realview/platform.h>
|
||||
|
||||
#define PLATFORM_CONSOLE0_BASE EB_UART0_VBASE
|
||||
#define PLATFORM_TIMER0_BASE EB_TIMER01_VBASE
|
||||
#define PLATFORM_SP810_BASE EB_SYSCTRL_VBASE
|
||||
void cpu_extra_init(void);
|
||||
void init_platform_irq_controller();
|
||||
void init_platform_devices();
|
||||
|
||||
/* Total number of timers present in this platform */
|
||||
#define TOTAL_TIMERS 4
|
||||
|
||||
#define PLATFORM_TIMER0 0
|
||||
#define PLATFORM_TIMER1 1
|
||||
#define PLATFORM_TIMER2 2
|
||||
#define PLATFORM_TIMER3 3
|
||||
|
||||
void platform_irq_enable(int irq);
|
||||
void platform_irq_disable(int irq);
|
||||
void timer_start(void);
|
||||
#endif /* __EB_PLATFORM_H__ */
|
||||
|
||||
95
include/l4/platform/eb/sysctrl.h
Normal file
95
include/l4/platform/eb/sysctrl.h
Normal file
@@ -0,0 +1,95 @@
|
||||
#ifndef __EB_SYSCTRL_H__
|
||||
#define __EB_SYSCTRL_H__
|
||||
/* TODO: Better to stick this file in a ARM specific folder as most realview boards
|
||||
* tend to have this component
|
||||
*/
|
||||
#define SYS_ID 0x0000
|
||||
#define SYS_SW 0x0004
|
||||
#define SYS_LED 0x0008
|
||||
|
||||
#define SYS_OSC0 0x000C
|
||||
#define SYS_OSC1 0x0010
|
||||
#define SYS_OSC2 0x0014
|
||||
#define SYS_OSC3 0x0018
|
||||
#define SYS_OSC4 0x001C
|
||||
|
||||
#define SYS_LOCK 0x0020
|
||||
#define SYS_100HZ 0x0024
|
||||
|
||||
#define SYS_CFGDATA0 0x0028
|
||||
#define SYS_CFGDATA1 0x002C
|
||||
|
||||
#define SYS_FLAGS 0x0030
|
||||
#define SYS_FLAGS_SET 0x0030
|
||||
#define SYS_FLAGS_CLR 0x0034
|
||||
#define SYS_NVFLAGS 0x0038
|
||||
#define SYS_NVFLAGS_SET 0x0038
|
||||
#define SYS_NVFLAGS_CLR 0x003C
|
||||
|
||||
#define SYS_PCICTL 0x0044
|
||||
#define SYS_MCI 0x0048
|
||||
#define SYS_FLASH 0x004C
|
||||
#define SYS_CLCD 0x0050
|
||||
#define SYS_CLCDSER 0x0054
|
||||
#define SYS_BOOTCS 0x0058
|
||||
|
||||
#define SYS_24MHZ 0x005C
|
||||
#define SYS_MISC 0x0060
|
||||
#define SYS_DMAPSR0 0x0064
|
||||
#define SYS_DMAPSR1 0x0068
|
||||
#define SYS_DMAPSR2 0x006C
|
||||
#define SYS_IOSEL 0x0070
|
||||
#define SYS_PLDCTL1 0x0074
|
||||
#define SYS_PLDCTL2 0x0078
|
||||
|
||||
#define SYS_BUSID 0x0080
|
||||
#define SYS_PROCID1 0x0084
|
||||
#define SYS_PROCID0 0x0088
|
||||
|
||||
#define SYS_OSCRESET0 0x008C
|
||||
#define SYS_OSCRESET1 0x0090
|
||||
#define SYS_OSCRESET2 0x0094
|
||||
#define SYS_OSCRESET3 0x0098
|
||||
#define SYS_OSCRESET4 0x009C
|
||||
|
||||
|
||||
/* System Controller Lock/Unlock */
|
||||
#define SYSCTRL_LOCK 0xFF
|
||||
#define SYSCTRL_UNLOCK 0xA05F
|
||||
|
||||
|
||||
#define ID_MASK_REV 0xF0000000
|
||||
#define ID_MASK_HBI 0x0FFF0000
|
||||
#define ID_MASK_BUILD 0x0000F000
|
||||
#define ID_MASK_ARCH 0x00000F00
|
||||
#define ID_MASK_FPGA 0x000000FF
|
||||
|
||||
|
||||
#define SW_MASK_BOOTSEL 0x0000FF00
|
||||
#define SW_MASK_GP 0x000000FF
|
||||
|
||||
#define LED_MASK_LED 0x000000FF
|
||||
|
||||
#define FLASH_WRITE_EN 0x1
|
||||
#define FLASH_WRITE_DIS 0x0
|
||||
|
||||
#define CLCD_QVGA (0 << 8) /* 320x240 */
|
||||
#define CLDE_VGA (1 << 8) /* 640x480 */
|
||||
#define CLCD_SMALL (2 << 8) /* 220x176 */
|
||||
#define CLCD_SSP_CS (1 << 7) /* SSP Chip Select */
|
||||
#define CLCD_TS_EN (1 << 6) /* Touch Screen Enable */
|
||||
/* Different Voltages */
|
||||
#define CLCD_NEG_EN (1 << 5)
|
||||
#define CLCD_3V5V_EN (1 << 4)
|
||||
#define CLCD_POS_EN (1 << 3)
|
||||
#define CLCD_IO_ON (1 << 2)
|
||||
|
||||
|
||||
/* Normal without DCC, no FIQ, recommended for SMP */
|
||||
#define PLD_CTRL1_INTMOD_WITHOUT_DCC (1 << 22)
|
||||
/* Not Recommended */
|
||||
#define PLD_CTRL1_INTMOD_WITH_DCC (2 << 22)
|
||||
/* For single cpu such as 1136 */
|
||||
#define PLD_CTRL1_INTMOD_LEGACY (4 << 22)
|
||||
|
||||
#endif /* __EB_SYSCTRL_H__ */
|
||||
@@ -1,20 +1,6 @@
|
||||
/*
|
||||
* Platform specific ties to generic uart functions that putc expects.
|
||||
*
|
||||
* Copyright (C) 2007 Bahadir Balban
|
||||
*
|
||||
*/
|
||||
#ifndef __EB_UART_H__
|
||||
#define __EB_UART_H__
|
||||
|
||||
#ifndef __PLATFORM_EB_UART_H__
|
||||
#define __PLATFORM_EB_UART_H__
|
||||
#include <l4/platform/realview/uart.h>
|
||||
|
||||
#include INC_PLAT(offsets.h)
|
||||
#include INC_GLUE(memlayout.h)
|
||||
|
||||
#define PLATFORM_CONSOLE_BASE EB_UART0_VBASE
|
||||
#include <l4/drivers/uart/pl011/pl011_uart.h>
|
||||
|
||||
void uart_init(void);
|
||||
void uart_putc(char c);
|
||||
|
||||
#endif /* __PLATFORM_EB_UART_H__ */
|
||||
#endif /* __EB_UART_H__ */
|
||||
|
||||
@@ -6,10 +6,10 @@
|
||||
#define IRQS_MAX 96
|
||||
|
||||
/* IRQ indices. */
|
||||
#define IRQ_TIMER01 36
|
||||
#define IRQ_TIMER23 37
|
||||
#define IRQ_TIMER45 73
|
||||
#define IRQ_TIMER67 74
|
||||
#define IRQ_TIMER0 36
|
||||
#define IRQ_TIMER1 37
|
||||
#define IRQ_TIMER2 73
|
||||
#define IRQ_TIMER3 74
|
||||
#define IRQ_RTC 42
|
||||
#define IRQ_UART0 44
|
||||
#define IRQ_UART1 45
|
||||
|
||||
@@ -1,77 +1,35 @@
|
||||
/*
|
||||
* Describes physical memory layout of PB11MPCORE platform.
|
||||
*
|
||||
* This only include physical and memory offsets that
|
||||
* are not included in realview/offsets.h
|
||||
*
|
||||
* Copyright (C) 2007 Bahadir Balban
|
||||
*/
|
||||
|
||||
#ifndef __PLATFORM_PB11MPCORE_OFFSETS_H__
|
||||
#define __PLATFORM_PB11MPCORE_OFFSETS_H__
|
||||
|
||||
/* Physical memory base */
|
||||
#define PHYS_MEM_START 0x00000000 /* inclusive */
|
||||
#define PHYS_MEM_END 0x10000000 /* 256 MB, exclusive */
|
||||
|
||||
/*
|
||||
* These bases taken from where kernel is `physically' linked at,
|
||||
* also used to calculate virtual-to-physical translation offset.
|
||||
* See the linker script for their sources. PHYS_ADDR_BASE can't
|
||||
* use a linker variable because it's referred from assembler.
|
||||
*/
|
||||
#define PHYS_ADDR_BASE 0x100000
|
||||
|
||||
/* Device memory base */
|
||||
#define PB11MPCORE_DEV_PHYS 0x10000000
|
||||
#include <l4/platform/realview/offsets.h>
|
||||
|
||||
/* Device offsets in physical memory */
|
||||
#define PB11MPCORE_SYSTEM_REGISTERS 0x10000000 /* System registers */
|
||||
#define PB11MPCORE_SYSCTRL0_BASE 0x10001000 /* System controller 0 */
|
||||
#define PB11MPCORE_UART0_BASE 0x10009000 /* UART 0 */
|
||||
#define PB11MPCORE_UART1_BASE 0x1000A000 /* UART 1 */
|
||||
#define PB11MPCORE_UART2_BASE 0x1000B000 /* UART 2 */
|
||||
#define PB11MPCORE_UART3_BASE 0x1000C000 /* UART 3 */
|
||||
#define PB11MPCORE_WATCHDOG0_BASE 0x1000F000 /* WATCHDOG 0 */
|
||||
#define PB11MPCORE_WATCHDOG1_BASE 0x10010000 /* WATCHDOG 1 */
|
||||
#define PB11MPCORE_TIMER01_BASE 0x10011000 /* TIMER 0-1 */
|
||||
#define PB11MPCORE_TIMER23_BASE 0x10012000 /* TIMER 2-3 */
|
||||
#define PB11MPCORE_RTC_BASE 0x10017000 /* RTC interface */
|
||||
#define PB11MPCORE_TIMER45_BASE 0x10018000 /* TIMER 4-5 */
|
||||
#define PB11MPCORE_TIMER67_BASE 0x10019000 /* TIMER 6-7 */
|
||||
#define PB11MPCORE_SYSCTRL1_BASE 0x1001A000 /* System controller 1 */
|
||||
#define PB11MPCORE_GIC0_BASE 0x1E000000 /* GIC 0 */
|
||||
#define PB11MPCORE_GIC1_BASE 0x1E010000 /* GIC 1 */
|
||||
#define PB11MPCORE_GIC2_BASE 0x1E020000 /* GIC 2 */
|
||||
#define PB11MPCORE_GIC3_BASE 0x1E030000 /* GIC 3 */
|
||||
|
||||
/*
|
||||
* Uart virtual address until a file-based console access
|
||||
* is available for userspace
|
||||
*/
|
||||
#define USERSPACE_UART_BASE 0x500000
|
||||
#define PLATFORM_TIMER2_BASE 0x10018000 /* TIMER 4-5 */
|
||||
#define PLATFORM_TIMER3_BASE 0x10019000 /* TIMER 6-7 */
|
||||
#define PLATFORM_SYSCTRL1_BASE 0x1001A000 /* System controller 1 */
|
||||
#define PLATFORM_GIC0_BASE 0x1E000000 /* GIC 0 */
|
||||
#define PLATFORM_GIC1_BASE 0x1E010000 /* GIC 1 */
|
||||
#define PLATFORM_GIC2_BASE 0x1E020000 /* GIC 2 */
|
||||
#define PLATFORM_GIC3_BASE 0x1E030000 /* GIC 3 */
|
||||
|
||||
/*
|
||||
* Device offsets in virtual memory. They offset to some virtual
|
||||
* device base address. Each page on this virtual base is consecutively
|
||||
* allocated to devices. Nice and smooth.
|
||||
*/
|
||||
#define PB11MPCORE_SYSREGS_VOFFSET 0x00000000
|
||||
#define PB11MPCORE_SYSCTRL0_VOFFSET 0x00001000
|
||||
#define PB11MPCORE_SYSCTRL1_VOFFSET 0x00002000
|
||||
#define PB11MPCORE_UART0_VOFFSET 0x00003000
|
||||
#define PB11MPCORE_TIMER01_VOFFSET 0x00004000
|
||||
|
||||
#define PB11MPCORE_GIC0_VOFFSET 0x00005000
|
||||
#define PB11MPCORE_GIC1_VOFFSET 0x00006000
|
||||
#define PB11MPCORE_GIC2_VOFFSET 0x00007000
|
||||
#define PB11MPCORE_GIC3_VOFFSET 0x00008000
|
||||
#define PB11MPCORE_SYSREGS_VBASE (IO_AREA0_VADDR + PB11MPCORE_SYSREGS_VOFFSET)
|
||||
#define PB11MPCORE_SYSCTRL0_VBASE (IO_AREA0_VADDR + PB11MPCORE_SYSCTRL0_VOFFSET)
|
||||
#define PB11MPCORE_SYSCTRL1_VBASE (IO_AREA0_VADDR + PB11MPCORE_SYSCTRL1_VOFFSET)
|
||||
#define PB11MPCORE_UART0_VBASE (IO_AREA0_VADDR + PB11MPCORE_UART0_VOFFSET)
|
||||
#define PB11MPCORE_TIMER01_VBASE (IO_AREA0_VADDR + PB11MPCORE_TIMER01_VOFFSET)
|
||||
#define PB11MPCORE_GIC0_VBASE (IO_AREA0_VADDR + PB11MPCORE_GIC0_VOFFSET)
|
||||
#define PB11MPCORE_GIC1_VBASE (IO_AREA0_VADDR + PB11MPCORE_GIC1_VOFFSET)
|
||||
#define PB11MPCORE_GIC2_VBASE (IO_AREA0_VADDR + PB11MPCORE_GIC2_VOFFSET)
|
||||
#define PB11MPCORE_GIC3_VBASE (IO_AREA0_VADDR + PB11MPCORE_GIC3_VOFFSET)
|
||||
/* Add userspace devices here as they become necessary for irqs */
|
||||
|
||||
/* Add size of various user space devices, to be used in capability generation */
|
||||
|
||||
#endif /* __PLATFORM_PB11MPCORE_OFFSETS_H__ */
|
||||
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
#ifndef __PB11MPCORE_PLATFORM_H__
|
||||
#define __PB11MPCORE_PLATFORM_H__
|
||||
#ifndef __PBA9_PLATFORM_H__
|
||||
#define __PBA9_PLATFORM_H__
|
||||
/*
|
||||
* Platform specific ties between drivers and generic APIs used by the kernel.
|
||||
* E.g. system timer and console.
|
||||
@@ -7,28 +7,6 @@
|
||||
* Copyright (C) Bahadir Balban 2007
|
||||
*/
|
||||
|
||||
#include INC_PLAT(offsets.h)
|
||||
#include INC_GLUE(memlayout.h)
|
||||
#include <l4/platform/realview/platform.h>
|
||||
|
||||
#define PLATFORM_CONSOLE0_BASE PB11MPCORE_UART0_VBASE
|
||||
#define PLATFORM_TIMER0_BASE PB11MPCORE_TIMER01_VBASE
|
||||
/* Need to add syscntrl1 here */
|
||||
#define PLATFORM_SP810_BASE PB11MPCORE_SYSCTRL0_VBASE
|
||||
|
||||
/* Total number of timers present in this platform */
|
||||
#define TOTAL_TIMERS 8
|
||||
|
||||
#define PLATFORM_TIMER0 0
|
||||
#define PLATFORM_TIMER1 1
|
||||
#define PLATFORM_TIMER2 2
|
||||
#define PLATFORM_TIMER3 3
|
||||
#define PLATFORM_TIMER4 4
|
||||
#define PLATFORM_TIMER5 5
|
||||
#define PLATFORM_TIMER6 6
|
||||
#define PLATFORM_TIMER7 7
|
||||
|
||||
void platform_irq_enable(int irq);
|
||||
void platform_irq_disable(int irq);
|
||||
void timer_start(void);
|
||||
|
||||
#endif /* __PB11MPCORE_PLATFORM_H__ */
|
||||
#endif /* __PBA9_PLATFORM_H__ */
|
||||
|
||||
@@ -1,20 +1,6 @@
|
||||
/*
|
||||
* Platform specific ties to generic uart functions that putc expects.
|
||||
*
|
||||
* Copyright (C) 2007 Bahadir Balban
|
||||
*
|
||||
*/
|
||||
#ifndef __PB11MPCORE_UART_H__
|
||||
#define __PB11MPCORE_UART_H__
|
||||
|
||||
#ifndef __PLATFORM_PB11MPCORE_UART_H__
|
||||
#define __PLATFORM_PB11MPCORE_UART_H__
|
||||
#include <l4/platform/realview/uart.h>
|
||||
|
||||
#include INC_PLAT(offsets.h)
|
||||
#include INC_GLUE(memlayout.h)
|
||||
|
||||
#define PLATFORM_CONSOLE_BASE PB11MPCORE_UART0_VBASE
|
||||
#include <l4/drivers/uart/pl011/pl011_uart.h>
|
||||
|
||||
void uart_init(void);
|
||||
void uart_putc(char c);
|
||||
|
||||
#endif /* __PLATFORM_PB11MPCORE_UART_H__ */
|
||||
#endif /* __PB11MPCORE_UART_H__ */
|
||||
|
||||
@@ -22,12 +22,13 @@
|
||||
#define IRQS_MAX VIC_IRQS_MAX + SIC_IRQS_MAX
|
||||
|
||||
/* Vectored Interrupt Controller local IRQ numbers */
|
||||
#define VIC_IRQ_TIMER01 4
|
||||
#define VIC_IRQ_TIMER23 5
|
||||
#define VIC_IRQ_TIMER0 4
|
||||
#define VIC_IRQ_TIMER1 5
|
||||
#define VIC_IRQ_RTC 10
|
||||
#define VIC_IRQ_UART0 12
|
||||
#define VIC_IRQ_UART1 13
|
||||
#define VIC_IRQ_UART2 14
|
||||
#define VIC_IRQ_CLCD0 16
|
||||
#define VIC_IRQ_SIC 31
|
||||
|
||||
/* Secondary Interrupt controller local IRQ numbers */
|
||||
@@ -35,12 +36,13 @@
|
||||
#define SIC_IRQ_UART3 6
|
||||
|
||||
/* Global irq numbers, note these should reflect global device names */
|
||||
#define IRQ_TIMER0 (VIC_IRQ_TIMER01 + VIC_CHIP_OFFSET)
|
||||
#define IRQ_TIMER1 (VIC_IRQ_TIMER23 + VIC_CHIP_OFFSET)
|
||||
#define IRQ_TIMER0 (VIC_IRQ_TIMER0 + VIC_CHIP_OFFSET)
|
||||
#define IRQ_TIMER1 (VIC_IRQ_TIMER1 + VIC_CHIP_OFFSET)
|
||||
#define IRQ_RTC (VIC_IRQ_RTC + VIC_CHIP_OFFSET)
|
||||
#define IRQ_UART0 (VIC_IRQ_UART0 + VIC_CHIP_OFFSET)
|
||||
#define IRQ_UART1 (VIC_IRQ_UART1 + VIC_CHIP_OFFSET)
|
||||
#define IRQ_UART2 (VIC_IRQ_UART2 + VIC_CHIP_OFFSET)
|
||||
#define IRQ_CLCD0 (VIC_IRQ_CLCD0 + VIC_CHIP_OFFSET)
|
||||
#define IRQ_SIC (VIC_IRQ_SIC + VIC_CHIP_OFFSET)
|
||||
|
||||
#define IRQ_SICSWI (SIC_IRQ_SWI + SIC_CHIP_OFFSET)
|
||||
|
||||
@@ -8,51 +8,53 @@
|
||||
#define __PLATFORM_PB926_OFFSETS_H__
|
||||
|
||||
/* Physical memory base */
|
||||
#define PHYS_MEM_START 0x00000000 /* inclusive */
|
||||
#define PHYS_MEM_END 0x08000000 /* 128 MB, exclusive */
|
||||
|
||||
/* Device offsets in physical memory */
|
||||
#define PB926_SYSTEM_REGISTERS 0x10000000 /* System registers */
|
||||
#define PB926_SYSCTRL_BASE 0x101E0000 /* System controller */
|
||||
#define PB926_WATCHDOG_BASE 0x101E1000 /* Watchdog */
|
||||
#define PB926_TIMER01_BASE 0x101E2000 /* Timers 0 and 1 */
|
||||
#define PB926_TIMER23_BASE 0x101E3000 /* Timers 2 and 3 */
|
||||
#define PB926_RTC_BASE 0x101E8000 /* Real Time Clock */
|
||||
#define PB926_VIC_BASE 0x10140000 /* Primary Vectored IC */
|
||||
#define PB926_SIC_BASE 0x10003000 /* Secondary IC */
|
||||
#define PB926_UART0_BASE 0x101F1000 /* Console port (UART0) */
|
||||
#define PB926_UART1_BASE 0x101F2000 /* Console port (UART1) */
|
||||
#define PB926_UART2_BASE 0x101F3000 /* Console port (UART2) */
|
||||
#define PB926_UART3_BASE 0x10009000 /* Console port (UART3) */
|
||||
#define PB926_CLCD_BASE 0x10120000 /* Color LCD */
|
||||
#define PLATFORM_PHYS_MEM_START 0x00000000 /* inclusive */
|
||||
#define PLATFORM_PHYS_MEM_END 0x08000000 /* 128 MB, exclusive */
|
||||
|
||||
/*
|
||||
* Uart virtual address until a file-based console access
|
||||
* is available for userspace
|
||||
* Device offsets in physical memory
|
||||
* Naming of devices done starting with 0 subscript,
|
||||
* as we use these names for device capability
|
||||
*/
|
||||
#define USERSPACE_CONSOLE_VIRTUAL 0x500000
|
||||
#define PLATFORM_SYSTEM_REGISTERS 0x10000000 /* System registers */
|
||||
#define PLATFORM_SYSCTRL_BASE 0x101E0000 /* System controller */
|
||||
#define PLATFORM_WATCHDOG_BASE 0x101E1000 /* Watchdog */
|
||||
#define PLATFORM_TIMER0_BASE 0x101E2000 /* Timers 0 and 1 */
|
||||
#define PLATFORM_TIMER1_BASE 0x101E3000 /* Timers 2 and 3 */
|
||||
#define PLATFORM_RTC_BASE 0x101E8000 /* Real Time Clock */
|
||||
#define PLATFORM_VIC_BASE 0x10140000 /* Primary Vectored IC */
|
||||
#define PLATFORM_SIC_BASE 0x10003000 /* Secondary IC */
|
||||
#define PLATFORM_UART0_BASE 0x101F1000 /* Console port (UART0) */
|
||||
#define PLATFORM_UART1_BASE 0x101F2000 /* Console port (UART1) */
|
||||
#define PLATFORM_UART2_BASE 0x101F3000 /* Console port (UART2) */
|
||||
#define PLATFORM_UART3_BASE 0x10009000 /* Console port (UART3) */
|
||||
#define PLATFORM_CLCD0_BASE 0x10120000 /* Color LCD */
|
||||
|
||||
/*
|
||||
* Device offsets in virtual memory. They offset to some virtual
|
||||
* device base address. Each page on this virtual base is consecutively
|
||||
* allocated to devices. Nice and smooth.
|
||||
*/
|
||||
#define PB926_TIMER01_VOFFSET 0x00000000
|
||||
#define PB926_UART0_VOFFSET 0x00001000
|
||||
#define PB926_VIC_VOFFSET 0x00002000
|
||||
#define PB926_SIC_VOFFSET 0x00003000
|
||||
#define PB926_SYSREGS_VOFFSET 0x00004000
|
||||
#define PB926_SYSCTRL_VOFFSET 0x00005000
|
||||
#define PB926_TIMER23_VOFFSET 0x00006000
|
||||
#define DEVICE_PAGE 0x1000
|
||||
|
||||
#define PLATFORM_CONSOLE_VIRTUAL (IO_AREA0_VADDR + PB926_UART0_VOFFSET)
|
||||
#define PLATFORM_TIMER0_VIRTUAL (IO_AREA0_VADDR + PB926_TIMER01_VOFFSET)
|
||||
#define PLATFORM_SYSCTRL_VIRTUAL (IO_AREA0_VADDR + PB926_SYSCTRL_VOFFSET)
|
||||
#define PLATFORM_IRQCTRL0_VIRTUAL (IO_AREA0_VADDR + PB926_VIC_VOFFSET)
|
||||
#define PLATFORM_IRQCTRL1_VIRTUAL (IO_AREA0_VADDR + PB926_SIC_VOFFSET)
|
||||
#define PLATFORM_TIMER0_VBASE (IO_AREA0_VADDR + (0 * DEVICE_PAGE))
|
||||
#define PLATFORM_CONSOLE_VBASE (IO_AREA0_VADDR + (1 * DEVICE_PAGE))
|
||||
#define PLATFORM_IRQCTRL0_VBASE (IO_AREA0_VADDR + (2 * DEVICE_PAGE))
|
||||
#define PLATFORM_IRQCTRL1_VBASE (IO_AREA0_VADDR + (3 * DEVICE_PAGE))
|
||||
#define PLATFORM_SYSCTRL_VBASE (IO_AREA0_VADDR + (4 * DEVICE_PAGE))
|
||||
|
||||
/* Add userspace devices here as they become necessary for irqs */
|
||||
#define PLATFORM_TIMER1_VIRTUAL (IO_AREA0_VADDR + PB926_TIMER23_VOFFSET)
|
||||
#define PLATFORM_TIMER1_VBASE (IO_AREA0_VADDR + (6 * DEVICE_PAGE))
|
||||
|
||||
/* The SP810 system controller offsets */
|
||||
#define SP810_BASE PLATFORM_SYSCTRL_VBASE
|
||||
#define SP810_SCCTRL (SP810_BASE + 0x0)
|
||||
|
||||
/* Add size of various user space devices, to be used in capability generation */
|
||||
#define PLATFORM_UART1_SIZE 0x1000
|
||||
#define PLATFORM_UART2_SIZE 0x1000
|
||||
#define PLATFORM_UART3_SIZE 0x1000
|
||||
#define PLATFORM_TIMER1_SIZE 0x1000
|
||||
|
||||
#endif /* __PLATFORM_PB926_OFFSETS_H__ */
|
||||
|
||||
|
||||
@@ -7,46 +7,6 @@
|
||||
* Copyright (C) Bahadir Balban 2007
|
||||
*/
|
||||
|
||||
#include INC_PLAT(offsets.h)
|
||||
#include INC_GLUE(memlayout.h)
|
||||
#include <l4/generic/capability.h>
|
||||
#include <l4/generic/cap-types.h>
|
||||
#include <l4/generic/resource.h>
|
||||
|
||||
/* Default console used by kernel */
|
||||
#define PLATFORM_CONSOLE_BASE PB926_UART0_BASE
|
||||
|
||||
/* SP804 timer has TIMER1 at TIMER0 + 0x20 address */
|
||||
#define PLATFORM_TIMER0_BASE PB926_TIMER01_BASE
|
||||
|
||||
/* Total number of timers present in this platform */
|
||||
#define TOTAL_TIMERS 4
|
||||
|
||||
#define PLATFORM_TIMER0 0
|
||||
#define PLATFORM_TIMER1 1
|
||||
#define PLATFORM_TIMER2 2
|
||||
#define PLATFORM_TIMER3 3
|
||||
|
||||
#define PB926_UART_SIZE 0x1000
|
||||
#define PB926_TIMER_SIZE 0x1000
|
||||
#define PB926_CLCD_SIZE 0x1000
|
||||
|
||||
#define PLATFORM_UART1_BASE PB926_UART1_BASE
|
||||
#define PLATFORM_UART2_BASE PB926_UART2_BASE
|
||||
#define PLATFORM_UART3_BASE PB926_UART3_BASE
|
||||
#define PLATFORM_UART1_SIZE PB926_UART_SIZE
|
||||
#define PLATFORM_UART2_SIZE PB926_UART_SIZE
|
||||
#define PLATFORM_UART3_SIZE PB926_UART_SIZE
|
||||
|
||||
#define PLATFORM_TIMER1_BASE PB926_TIMER23_BASE
|
||||
#define PLATFORM_TIMER1_SIZE PB926_TIMER_SIZE
|
||||
|
||||
#define PLATFORM_CLCD0_BASE PB926_CLCD_BASE
|
||||
#define PLATFORM_CLCD0_SIZE PB926_CLCD_SIZE
|
||||
|
||||
int platform_setup_device_caps(struct kernel_resources *kres);
|
||||
void platform_irq_enable(int irq);
|
||||
void platform_irq_disable(int irq);
|
||||
void timer_start(void);
|
||||
void platform_timer_start(void);
|
||||
|
||||
#endif /* __PB926_PLATFORM_H__ */
|
||||
|
||||
13
include/l4/platform/pb926/timer.h
Normal file
13
include/l4/platform/pb926/timer.h
Normal file
@@ -0,0 +1,13 @@
|
||||
/*
|
||||
* Platform encapsulation over timer driver.
|
||||
*
|
||||
* Copyright (C) 2007 Bahadir Balban
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __PLATFORM_PB926_TIMER_H__
|
||||
#define __PLATFORM_PB926_TIMER_H__
|
||||
|
||||
#include <l4/drivers/timer/sp804/timer.h>
|
||||
|
||||
#endif /* __PLATFORM_PB926_TIMER_H__ */
|
||||
@@ -8,12 +8,6 @@
|
||||
#ifndef __PLATFORM_PB926_UART_H__
|
||||
#define __PLATFORM_PB926_UART_H__
|
||||
|
||||
#include INC_PLAT(offsets.h)
|
||||
#include INC_GLUE(memlayout.h)
|
||||
|
||||
#include <l4/drivers/uart/pl011/pl011_uart.h>
|
||||
|
||||
void uart_init(void);
|
||||
void uart_putc(char c);
|
||||
#include <l4/drivers/uart/pl011/uart.h>
|
||||
|
||||
#endif /* __PLATFORM_PB926_UART_H__ */
|
||||
|
||||
28
include/l4/platform/pba8/irq.h
Normal file
28
include/l4/platform/pba8/irq.h
Normal file
@@ -0,0 +1,28 @@
|
||||
|
||||
#ifndef __PLATFORM_IRQ_H__
|
||||
#define __PLATFORM_IRQ_H__
|
||||
|
||||
/*
|
||||
* Support for generic irq handling using platform irq controller (GIC)
|
||||
*
|
||||
* Copyright (C) 2007 Bahadir Balban
|
||||
*/
|
||||
|
||||
/* TODO: Not sure about this, need to check */
|
||||
#define IRQ_CHIPS_MAX 4
|
||||
#define IRQS_MAX 96
|
||||
|
||||
/* IRQ indices. */
|
||||
#define IRQ_UART0 44
|
||||
#define IRQ_UART1 45
|
||||
#define IRQ_UART2 46
|
||||
#define IRQ_UART3 47
|
||||
|
||||
/* General Purpose Timers */
|
||||
#define IRQ_TIMER0 36
|
||||
#define IRQ_TIMER1 37
|
||||
#define IRQ_TIMER2 73
|
||||
#define IRQ_TIMER3 74
|
||||
|
||||
#endif /* __PLATFORM_IRQ_H__ */
|
||||
|
||||
41
include/l4/platform/pba8/offsets.h
Normal file
41
include/l4/platform/pba8/offsets.h
Normal file
@@ -0,0 +1,41 @@
|
||||
/*
|
||||
* Describes physical memory layout of EB platform.
|
||||
*
|
||||
* This only include physical and memory offsets that
|
||||
* are not included in realview/offsets.h
|
||||
*
|
||||
* Copyright (C) 2009 B Labs Ltd.
|
||||
*/
|
||||
|
||||
#ifndef __PLATFORM_PBA8_OFFSETS_H__
|
||||
#define __PLATFORM_PBA8_OFFSETS_H__
|
||||
|
||||
#include <l4/platform/realview/offsets.h>
|
||||
|
||||
/*
|
||||
* These bases taken from where kernel is `physically' linked at,
|
||||
* also used to calculate virtual-to-physical translation offset.
|
||||
* See the linker script for their sources. PHYS_ADDR_BASE can't
|
||||
* use a linker variable because it's referred from assembler.
|
||||
*/
|
||||
#define PHYS_ADDR_BASE 0x100000
|
||||
|
||||
/* Device offsets in physical memory */
|
||||
#define PLATFORM_TIMER2_BASE 0x10018000 /* Timers 4 and 5 */
|
||||
#define PLATFORM_TIMER3_BASE 0x10019000 /* Timers 6 and 7 */
|
||||
#define PLATFORM_SYSCTRL1_BASE 0x1001A000 /* System controller1 */
|
||||
#define PLATFORM_GIC1_BASE 0x1E000000 /* GIC 1 */
|
||||
#define PLATFORM_GIC2_BASE 0x1E010000 /* GIC 2 */
|
||||
#define PLATFORM_GIC3_BASE 0x1E020000 /* GIC 3 */
|
||||
#define PLATFORM_GIC4_BASE 0x1E030000 /* GIC 4 */
|
||||
|
||||
/*
|
||||
* Device offsets in virtual memory. They offset to some virtual
|
||||
* device base address. Each page on this virtual base is consecutively
|
||||
* allocated to devices. Nice and smooth.
|
||||
* Make sure the offsets used here are not conflicting with the ones
|
||||
* present in <l4/platform/realview/offset.h>
|
||||
*/
|
||||
|
||||
#endif /* __PLATFORM_PBA8_OFFSETS_H__ */
|
||||
|
||||
16
include/l4/platform/pba8/platform.h
Normal file
16
include/l4/platform/pba8/platform.h
Normal file
@@ -0,0 +1,16 @@
|
||||
/*
|
||||
* Platform specific ties between drivers and generic APIs used by the kernel.
|
||||
* E.g. system timer and console.
|
||||
*
|
||||
* Copyright (C) 2009 B Labs Ltd.
|
||||
*/
|
||||
#ifndef __PBA8_PLATFORM_H__
|
||||
#define __PBA8_PLATFORM_H__
|
||||
|
||||
#include <l4/drivers/irq/gic/gic.h>
|
||||
#include <l4/platform/realview/platform.h>
|
||||
|
||||
void init_platform_irq_controller();
|
||||
void init_platform_devices();
|
||||
|
||||
#endif /* __PBA8_PLATFORM_H__ */
|
||||
6
include/l4/platform/pba8/uart.h
Normal file
6
include/l4/platform/pba8/uart.h
Normal file
@@ -0,0 +1,6 @@
|
||||
#ifndef __PBA8_UART_H__
|
||||
#define __PBA8_UART_H__
|
||||
|
||||
#include <l4/platform/realview/uart.h>
|
||||
|
||||
#endif /* __PBA8_UART_H__ */
|
||||
34
include/l4/platform/pba9/irq.h
Normal file
34
include/l4/platform/pba9/irq.h
Normal file
@@ -0,0 +1,34 @@
|
||||
/*
|
||||
* Support for generic irq handling using platform irq controller (GIC)
|
||||
*
|
||||
* Copyright (C) 2007 B Labs Ltd.
|
||||
*/
|
||||
#ifndef __PLATFORM_IRQ_H__
|
||||
#define __PLATFORM_IRQ_H__
|
||||
|
||||
|
||||
/* TODO: Not sure about this, need to check */
|
||||
#define IRQ_CHIPS_MAX 1
|
||||
#define IRQS_MAX 96
|
||||
#define IRQ_OFFSET 0
|
||||
|
||||
/* IRQ indices. */
|
||||
#define IRQ_TIMER0 34
|
||||
#define IRQ_TIMER1 35
|
||||
#define IRQ_RTC 36
|
||||
#define IRQ_UART0 37
|
||||
#define IRQ_UART1 38
|
||||
#define IRQ_UART2 39
|
||||
#define IRQ_UART3 40
|
||||
#define IRQ_CLCD0 46
|
||||
|
||||
/*
|
||||
* Interrupt Distribution:
|
||||
* 0-31: SI, provided by distributed interrupt controller
|
||||
* 32-63: Externel peripheral interrupts
|
||||
* 64-71: Tile site interrupt
|
||||
* 72-95: Externel peripheral interrupts
|
||||
*/
|
||||
|
||||
#endif /* __PLATFORM_IRQ_H__ */
|
||||
|
||||
35
include/l4/platform/pba9/offsets.h
Normal file
35
include/l4/platform/pba9/offsets.h
Normal file
@@ -0,0 +1,35 @@
|
||||
/*
|
||||
* Describes physical memory layout of pb926 platform.
|
||||
*
|
||||
* This only include physical and memory offsets that
|
||||
* are not included in realview/offsets.h
|
||||
*
|
||||
* Copyright (C) 2010 B Labs Ltd.
|
||||
* Author: Bahadir Balban <bbalban@b-labs.co.uk>
|
||||
*/
|
||||
|
||||
#ifndef __PLATFORM_PBA9_OFFSETS_H__
|
||||
#define __PLATFORM_PBA9_OFFSETS_H__
|
||||
|
||||
#include <l4/platform/realview/offsets.h>
|
||||
|
||||
/*
|
||||
* Device offsets in physical memory
|
||||
* Naming of devices done starting with 0 subscript,
|
||||
* as we use these names for device capability
|
||||
*/
|
||||
#define PLATFORM_TIMER2_BASE 0x10018000 /* Timers 2 and 3 */
|
||||
#define PLATFORM_TIMER3_BASE 0x10019000 /* Timers 2 and 3 */
|
||||
#define PLATFORM_SYSCTRL1_BASE 0x1001A000 /* System controller1 */
|
||||
|
||||
#define PLATFORM_GIC0_BASE 0x1E000000 /* GIC 0 */
|
||||
|
||||
#define MPCORE_PRIVATE_BASE 0x1E000000
|
||||
#define MPCORE_PRIVATE_VBASE (IO_AREA0_VADDR + (13 * DEVICE_PAGE))
|
||||
|
||||
#define SCU_BASE MPCORE_PRIVATE_BASE
|
||||
#define SCU_VBASE MPCORE_PRIVATE_VBASE
|
||||
#define GIC0_CPU_VBASE (MPCORE_PRIVATE_VBASE + 0x100)
|
||||
#define GIC0_DIST_VBASE (MPCORE_PRIVATE_VBASE + 0x1000)
|
||||
|
||||
#endif /* __PLATFORM_PBA9_OFFSETS_H__ */
|
||||
12
include/l4/platform/pba9/platform.h
Normal file
12
include/l4/platform/pba9/platform.h
Normal file
@@ -0,0 +1,12 @@
|
||||
#ifndef __PBA9_PLATFORM_H__
|
||||
#define __PBA9_PLATFORM_H__
|
||||
/*
|
||||
* Platform specific ties between drivers and generic APIs used by the kernel.
|
||||
* E.g. system timer and console.
|
||||
*
|
||||
* Copyright (C) Bahadir Balban 2007
|
||||
*/
|
||||
|
||||
#include <l4/platform/realview/platform.h>
|
||||
|
||||
#endif /* __PBA9_PLATFORM_H__ */
|
||||
21
include/l4/platform/pba9/platsmp.h
Normal file
21
include/l4/platform/pba9/platsmp.h
Normal file
@@ -0,0 +1,21 @@
|
||||
/*
|
||||
* Copyright 2010 B Labs Ltd.
|
||||
* Author: Prem Mallappa <prem.mallappa@b-labs.co.uk>
|
||||
*/
|
||||
|
||||
#ifndef __VXA9_PLATSMP_H__
|
||||
#define __VXA9_PLATSMP_H__
|
||||
|
||||
#include <l4/generic/irq.h>
|
||||
#include <l4/generic/space.h>
|
||||
#include <l4/drivers/irq/gic/gic.h>
|
||||
#include <l4/generic/smp.h>
|
||||
#include INC_GLUE(smp.h)
|
||||
#include INC_PLAT(sysctrl.h)
|
||||
|
||||
void boot_secondary(int);
|
||||
void platform_smp_init(int ncpus);
|
||||
int platform_smp_start(int cpu, void (*start)(int));
|
||||
void secondary_init_platform(void);
|
||||
|
||||
#endif /* VXA9_PLATSMP_H */
|
||||
95
include/l4/platform/pba9/sysctrl.h
Normal file
95
include/l4/platform/pba9/sysctrl.h
Normal file
@@ -0,0 +1,95 @@
|
||||
#ifndef __EB_SYSCTRL_H__
|
||||
#define __EB_SYSCTRL_H__
|
||||
/* TODO: Better to stick this file in a ARM specific folder as most realview boards
|
||||
* tend to have this component
|
||||
*/
|
||||
#define SYS_ID 0x0000
|
||||
#define SYS_SW 0x0004
|
||||
#define SYS_LED 0x0008
|
||||
|
||||
#define SYS_OSC0 0x000C
|
||||
#define SYS_OSC1 0x0010
|
||||
#define SYS_OSC2 0x0014
|
||||
#define SYS_OSC3 0x0018
|
||||
#define SYS_OSC4 0x001C
|
||||
|
||||
#define SYS_LOCK 0x0020
|
||||
#define SYS_100HZ 0x0024
|
||||
|
||||
#define SYS_CFGDATA0 0x0028
|
||||
#define SYS_CFGDATA1 0x002C
|
||||
|
||||
#define SYS_FLAGS 0x0030
|
||||
#define SYS_FLAGS_SET 0x0030
|
||||
#define SYS_FLAGS_CLR 0x0034
|
||||
#define SYS_NVFLAGS 0x0038
|
||||
#define SYS_NVFLAGS_SET 0x0038
|
||||
#define SYS_NVFLAGS_CLR 0x003C
|
||||
|
||||
#define SYS_PCICTL 0x0044
|
||||
#define SYS_MCI 0x0048
|
||||
#define SYS_FLASH 0x004C
|
||||
#define SYS_CLCD 0x0050
|
||||
#define SYS_CLCDSER 0x0054
|
||||
#define SYS_BOOTCS 0x0058
|
||||
|
||||
#define SYS_24MHZ 0x005C
|
||||
#define SYS_MISC 0x0060
|
||||
#define SYS_DMAPSR0 0x0064
|
||||
#define SYS_DMAPSR1 0x0068
|
||||
#define SYS_DMAPSR2 0x006C
|
||||
#define SYS_IOSEL 0x0070
|
||||
#define SYS_PLDCTL1 0x0074
|
||||
#define SYS_PLDCTL2 0x0078
|
||||
|
||||
#define SYS_BUSID 0x0080
|
||||
#define SYS_PROCID1 0x0084
|
||||
#define SYS_PROCID0 0x0088
|
||||
|
||||
#define SYS_OSCRESET0 0x008C
|
||||
#define SYS_OSCRESET1 0x0090
|
||||
#define SYS_OSCRESET2 0x0094
|
||||
#define SYS_OSCRESET3 0x0098
|
||||
#define SYS_OSCRESET4 0x009C
|
||||
|
||||
|
||||
/* System Controller Lock/Unlock */
|
||||
#define SYSCTRL_LOCK 0xFF
|
||||
#define SYSCTRL_UNLOCK 0xA05F
|
||||
|
||||
|
||||
#define ID_MASK_REV 0xF0000000
|
||||
#define ID_MASK_HBI 0x0FFF0000
|
||||
#define ID_MASK_BUILD 0x0000F000
|
||||
#define ID_MASK_ARCH 0x00000F00
|
||||
#define ID_MASK_FPGA 0x000000FF
|
||||
|
||||
|
||||
#define SW_MASK_BOOTSEL 0x0000FF00
|
||||
#define SW_MASK_GP 0x000000FF
|
||||
|
||||
#define LED_MASK_LED 0x000000FF
|
||||
|
||||
#define FLASH_WRITE_EN 0x1
|
||||
#define FLASH_WRITE_DIS 0x0
|
||||
|
||||
#define CLCD_QVGA (0 << 8) /* 320x240 */
|
||||
#define CLDE_VGA (1 << 8) /* 640x480 */
|
||||
#define CLCD_SMALL (2 << 8) /* 220x176 */
|
||||
#define CLCD_SSP_CS (1 << 7) /* SSP Chip Select */
|
||||
#define CLCD_TS_EN (1 << 6) /* Touch Screen Enable */
|
||||
/* Different Voltages */
|
||||
#define CLCD_NEG_EN (1 << 5)
|
||||
#define CLCD_3V5V_EN (1 << 4)
|
||||
#define CLCD_POS_EN (1 << 3)
|
||||
#define CLCD_IO_ON (1 << 2)
|
||||
|
||||
|
||||
/* Normal without DCC, no FIQ, recommended for SMP */
|
||||
#define PLD_CTRL1_INTMOD_WITHOUT_DCC (1 << 22)
|
||||
/* Not Recommended */
|
||||
#define PLD_CTRL1_INTMOD_WITH_DCC (2 << 22)
|
||||
/* For single cpu such as 1136 */
|
||||
#define PLD_CTRL1_INTMOD_LEGACY (4 << 22)
|
||||
|
||||
#endif /* __EB_SYSCTRL_H__ */
|
||||
6
include/l4/platform/pba9/uart.h
Normal file
6
include/l4/platform/pba9/uart.h
Normal file
@@ -0,0 +1,6 @@
|
||||
#ifndef __PBA9_UART_H__
|
||||
#define __PBA9_UART_H__
|
||||
|
||||
#include <l4/platform/realview/uart.h>
|
||||
|
||||
#endif /* __PBA9_UART_H__ */
|
||||
64
include/l4/platform/realview/offsets.h
Normal file
64
include/l4/platform/realview/offsets.h
Normal file
@@ -0,0 +1,64 @@
|
||||
/*
|
||||
* Describes physical memory layout of realview platform.
|
||||
* Right now this contains common offsets for
|
||||
* pb11mpcore, pba9 and eb.
|
||||
*
|
||||
* This is internally included by respective platform's offsets.h
|
||||
*
|
||||
* Copyright (C) 2007 Bahadir Balban
|
||||
*/
|
||||
|
||||
#ifndef __PLATFORM_REALVIEW_OFFSETS_H__
|
||||
#define __PLATFORM_REALVIEW_OFFSETS_H__
|
||||
|
||||
/* Physical memory base */
|
||||
#define PLATFORM_PHYS_MEM_START 0x00000000 /* inclusive */
|
||||
#define PLATFORM_PHYS_MEM_END 0x10000000 /* 256 MB, exclusive */
|
||||
|
||||
/*
|
||||
* Device offsets in physical memory
|
||||
* Naming of devices done starting with 0 subscript,
|
||||
* as we use these names for device capability
|
||||
*/
|
||||
#define PLATFORM_SYSTEM_REGISTERS 0x10000000 /* System registers */
|
||||
#define PLATFORM_SYSCTRL_BASE 0x10001000 /* System controller0 */
|
||||
#define PLATFORM_UART0_BASE 0x10009000 /* Console port (UART0) */
|
||||
#define PLATFORM_UART1_BASE 0x1000A000 /* Console port (UART1) */
|
||||
#define PLATFORM_UART2_BASE 0x1000B000 /* Console port (UART2) */
|
||||
#define PLATFORM_UART3_BASE 0x1000C000 /* Console port (UART3) */
|
||||
#define PLATFORM_TIMER0_BASE 0x10011000 /* Timers 0 and 1 */
|
||||
#define PLATFORM_TIMER1_BASE 0x10012000 /* Timers 2 and 3 */
|
||||
|
||||
/*
|
||||
* Virtual Memory base address, where devices will be mapped.
|
||||
* Each Device will take one page in virtual memory.
|
||||
* Nice and smooth.
|
||||
*/
|
||||
#define DEVICE_PAGE 0x1000
|
||||
|
||||
#define PLATFORM_SYSREGS_VBASE (IO_AREA0_VADDR + (0 * DEVICE_PAGE))
|
||||
#define PLATFORM_SYSCTRL_VBASE (IO_AREA0_VADDR + (1 * DEVICE_PAGE))
|
||||
#define PLATFORM_SYSCTRL1_VBASE (IO_AREA0_VADDR + (2 * DEVICE_PAGE))
|
||||
#define PLATFORM_CONSOLE_VBASE (IO_AREA0_VADDR + (3 * DEVICE_PAGE))
|
||||
#define PLATFORM_TIMER0_VBASE (IO_AREA0_VADDR + (4 * DEVICE_PAGE))
|
||||
#define PLATFORM_GIC0_VBASE (IO_AREA0_VADDR + (5 * DEVICE_PAGE))
|
||||
#define PLATFORM_GIC1_VBASE (IO_AREA0_VADDR + (7 * DEVICE_PAGE))
|
||||
#define PLATFORM_GIC2_VBASE (IO_AREA0_VADDR + (9 * DEVICE_PAGE))
|
||||
#define PLATFORM_GIC3_VBASE (IO_AREA0_VADDR + (11 * DEVICE_PAGE))
|
||||
|
||||
/* Add userspace devices here as they become necessary for irqs */
|
||||
|
||||
/* Add size of various user space devices, to be used in capability generation */
|
||||
|
||||
/* The SP810 system controller offsets */
|
||||
#define SP810_BASE PLATFORM_SYSCTRL_VBASE
|
||||
#define SP810_SCCTRL (SP810_BASE + 0x0)
|
||||
|
||||
/* Add size of various user space devices, to be used in capability generation */
|
||||
#define PLATFORM_UART1_SIZE DEVICE_PAGE
|
||||
#define PLATFORM_UART2_SIZE DEVICE_PAGE
|
||||
#define PLATFORM_UART3_SIZE DEVICE_PAGE
|
||||
#define PLATFORM_TIMER1_SIZE DEVICE_PAGE
|
||||
|
||||
#endif /* __PLATFORM_REALVIEW_OFFSETS_H__ */
|
||||
|
||||
24
include/l4/platform/realview/platform.h
Normal file
24
include/l4/platform/realview/platform.h
Normal file
@@ -0,0 +1,24 @@
|
||||
/*
|
||||
* Platform specific ties between drivers and
|
||||
* generic APIs used by the kernel.
|
||||
* E.g. system timer and console.
|
||||
*
|
||||
* Copyright (C) Bahadir Balban 2007
|
||||
*/
|
||||
|
||||
#ifndef __REALVIEW_PLATFORM_H__
|
||||
#define __REALVIEW_PLATFORM_H__
|
||||
|
||||
void init_platform_irq_controller();
|
||||
void init_platform_devices();
|
||||
|
||||
void platform_timer_start(void);
|
||||
void platform_test_cpucycles();
|
||||
|
||||
void platform_timer_start(void);
|
||||
|
||||
void scu_init(void);
|
||||
|
||||
void scu_print_state(void);
|
||||
|
||||
#endif /* __REALVIEW_PLATFORM_H__ */
|
||||
13
include/l4/platform/realview/timer.h
Normal file
13
include/l4/platform/realview/timer.h
Normal file
@@ -0,0 +1,13 @@
|
||||
/*
|
||||
* Platform encapsulation over timer driver.
|
||||
*
|
||||
* Copyright (C) 2007 Bahadir Balban
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __PLATFORM_REALVIEW_TIMER_H__
|
||||
#define __PLATFORM_REALVIEW_TIMER_H__
|
||||
|
||||
#include <l4/drivers/timer/sp804/timer.h>
|
||||
|
||||
#endif /* __PLATFORM_REALVIEW_TIMER_H__ */
|
||||
14
include/l4/platform/realview/uart.h
Normal file
14
include/l4/platform/realview/uart.h
Normal file
@@ -0,0 +1,14 @@
|
||||
/*
|
||||
* Ties generic uart call to platform specific
|
||||
* uart driver implementation
|
||||
*
|
||||
* Copyright (C) 2007 Bahadir Balban
|
||||
*/
|
||||
|
||||
#ifndef __PLATFORM_REALVIEW_UART_H__
|
||||
#define __PLATFORM_REALVIEW_UART_H__
|
||||
|
||||
/* Platform specific implementations are defined here */
|
||||
#include <l4/drivers/uart/pl011/uart.h>
|
||||
|
||||
#endif /* __PLATFORM_REALVIEW_UART_H__ */
|
||||
Reference in New Issue
Block a user