Kernel updates since December 2009

include/l4/platform/beagle/cm.h

@@ -0,0 +1,25 @@
+/*
+ * Clock mangaer module of the beagleboard.
+ *
+ * Copyright (C) 2007 Bahadir Balban
+ *
+ */
+
+#ifndef __PLATFORM_BEAGLE_CM_H__
+#define __PLATFORM_BEAGLE_CM_H__
+
+/*
+ * Register offsets for Clock Manager(CM)
+ * PER_CM, WKUP_CM etc all have same offsets
+ * for registers
+ */
+#define CM_FCLKEN_OFFSET    0x00
+#define CM_ICLKEN_OFFSET    0x10
+#define CM_CLKSEL_OFFSET    0x40
+
+void omap_cm_enable_iclk(unsigned long cm_base, int bit);
+void omap_cm_enable_fclk(unsigned long cm_base, int bit);
+void omap_cm_clk_select(unsigned long cm_base, int bit, int src);
+
+#endif /* __PLATFORM_BEAGLE_CM_H__ */
+

include/l4/platform/beagle/irq.h

@@ -0,0 +1,35 @@
+
+#ifndef __PLATFORM_IRQ_H__
+#define __PLATFORM_IRQ_H__
+
+/*
+ * Support for generic irq handling using platform irq controller (GIC)
+ *
+ * Copyright (C) 2007 Bahadir Balban
+ */
+
+/* TODO: Not sure about this, need to check */
+#define IRQ_CHIPS_MAX		1
+#define IRQS_MAX		96
+
+/* IRQ indices. */
+#define IRQ_UART0	72
+#define IRQ_UART1	73
+#define IRQ_UART2	74
+
+/* General Purpose Timers */
+#define IRQ_TIMER0	37
+#define IRQ_TIMER1	38
+#define IRQ_TIMER2	39
+#define IRQ_TIMER3	40
+#define IRQ_TIMER4	41
+#define IRQ_TIMER5	42
+#define IRQ_TIMER6	43
+#define IRQ_TIMER7	44
+#define IRQ_TIMER8	45
+#define IRQ_TIMER9	46
+#define IRQ_TIMER10	47
+#define IRQ_TIMER11	95
+
+#endif /* __PLATFORM_IRQ_H__ */
+

include/l4/platform/beagle/offsets.h

@@ -0,0 +1,66 @@
+/*
+ *
+ * Describes physical memory layout of Beagle Boards.
+ * We have rev3 boards.
+ *
+ * Copyright (C) 2007 Bahadir Balban
+ */
+
+#ifndef __PLATFORM_BEAGLE_OFFSETS_H__
+#define __PLATFORM_BEAGLE_OFFSETS_H__
+
+/*
+ * Physical memory base
+ * FIXME: Somewhere its written: Rev 1 and 2
+ * of Beagleboard has 128MB SDRAM while Rev 3 has 256MB
+ * SDRAM which is detected automatically on intiliazation,
+ * we have Rev3 boards, so hardcoding this only.
+ */
+#define PLATFORM_PHYS_MEM_START	0x80000000 /* inclusive */
+#define PLATFORM_PHYS_MEM_END	0x90000000 /* 256MB, exclusive */
+
+/*
+ * Device offsets in physical memory
+ * Naming of devices done starting with 0 subscript,
+ * as we use these names for device capability
+ */
+#define PLATFORM_WKUP_CM_BASE		0x48004C00 /* Wake up clock manager */
+#define PLATFORM_PERCM_BASE		0x48005000 /* Peripheral Clock Manager */
+#define PLATFORM_UART0_BASE		0x4806A000 /* UART 0 */
+#define PLATFORM_UART1_BASE		0x4806C000 /* UART 1 */
+#define PLATFORM_UART2_BASE		0x49020000 /* UART 2 */
+#define PLATFORM_TIMER0_BASE		0x48318000 /* GPTIMER1 */
+#define PLATFORM_TIMER1_BASE		0x49032000 /* GPTIMER2 */
+#define PLATFORM_TIMER2_BASE            0x49034000 /* GPTIMER3 */
+#define PLATFORM_TIMER3_BASE            0x49036000 /* GPTIMER4 */
+#define PLATFORM_TIMER4_BASE            0x49038000 /* GPTIMER5 */
+#define PLATFORM_TIMER5_BASE            0x4903A000 /* GPTIMER6 */
+#define PLATFORM_TIMER6_BASE            0x4903C000 /* GPTIMER7 */
+#define PLATFORM_TIMER7_BASE            0x4903E000 /* GPTIMER8 */
+#define PLATFORM_TIMER8_BASE            0x49040000 /* GPTIMER9 */
+#define PLATFORM_TIMER9_BASE            0x48086000 /* GPTIMER10 */
+#define PLATFORM_TIMER10_BASE		0x48088000 /* GPTIMER11 */
+#define PLATFORM_TIMER11_BASE		0x48304000 /* GPTIMER12 */
+#define PLATFORM_INTC_BASE		0x48200000 /* Interrupt controller */
+
+/*
+ * Virtual Memory base address, where devices will be mapped.
+ * Each Device will take one page in virtual memory.
+ * Nice and smooth.
+ */
+#define DEVICE_PAGE		0x1000
+
+#define PLATFORM_WKUP_CM_VBASE		(IO_AREA0_VADDR + (0 * DEVICE_PAGE))
+#define PLATFORM_CONSOLE_VBASE		(IO_AREA0_VADDR + (1 * DEVICE_PAGE))
+#define PLATFORM_TIMER0_VBASE		(IO_AREA0_VADDR + (2 * DEVICE_PAGE))
+#define PLATFORM_INTC_VBASE		(IO_AREA0_VADDR + (3 * DEVICE_PAGE))
+#define PLATFORM_PERCM_VBASE          	(IO_AREA0_VADDR + (4 * DEVICE_PAGE))
+
+/* Add userspace devices here as they become necessary for irqs */
+#define PLATFORM_TIMER1_VBASE           (IO_AREA0_VADDR + (5 * DEVICE_PAGE))
+
+/* Add size of various user space devices, to be used in capability generation */
+#define PLATFORM_TIMER1_SIZE		DEVICE_PAGE
+
+#endif /* __PLATFORM_BEAGLE_OFFSETS_H__ */
+

include/l4/platform/beagle/platform.h

@@ -0,0 +1,18 @@
+#ifndef __BEAGLE_PLATFORM_H__
+#define __BEAGLE_PLATFORM_H__
+/*
+ * Platform specific ties between drivers and generic APIs used by the kernel.
+ * E.g. system timer and console.
+ *
+ * Copyright (C) Bahadir Balban 2007
+ */
+
+#include INC_PLAT(offsets.h)
+#include INC_GLUE(memlayout.h)
+#include <l4/generic/capability.h>
+#include <l4/generic/cap-types.h>
+
+void platform_timer_start(void);
+
+void platform_test_cpucycles(void);
+#endif /* __BEAGLE_PLATFORM_H__ */

include/l4/platform/beagle/timer.h

@@ -0,0 +1,13 @@
+/*
+ * Platform encapsulation over timer driver.
+ *
+ * Copyright (C) 2007 Bahadir Balban
+ *
+ */
+
+#ifndef __PLATFORM_BEAGLE_TIMER_H__
+#define __PLATFORM_BEAGLE_TIMER_H__
+
+#include <l4/drivers/timer/omap/timer.h>
+
+#endif /* __PLATFORM_BEAGLE_TIMER_H__ */

include/l4/platform/beagle/uart.h

@@ -0,0 +1,13 @@
+/*
+ * Platform specific ties to generic uart functions that putc expects.
+ *
+ * Copyright (C) 2007 Bahadir Balban
+ *
+ */
+
+#ifndef __PLATFORM_BEAGLE_UART_H__
+#define __PLATFORM_BEAGLE_UART_H__
+
+#include <l4/drivers/uart/omap/uart.h>
+
+#endif /* __PLATFORM_BEAGLE_UART_H__ */