mirror of
https://github.com/drasko/codezero.git
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Kernel updates since December 2009
This commit is contained in:
Bahadir Balban
@@ -1,26 +1,20 @@
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/*
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* Copyright (C) 2009 B Labs Ltd.
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*/
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#ifndef __PLATFORM_IRQ_H__
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#define __PLATFORM_IRQ_H__
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/* TODO: Not sure about this, need to check */
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#define IRQ_CHIPS_MAX 4
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#define IRQS_MAX 96
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/* Actually there are 4 GIC's on the EB, only 2 are used for tile site 1 */
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#define IRQ_CHIPS_MAX 2
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#if defined(CONFIG_CPU_ARM11MPCORE) || defined (CONFIG_CPU_CORTEXA9)
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#define IRQS_MAX 64
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#else
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#define IRQS_MAX 96
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#endif
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/*
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* IRQ indices,
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* GIC 0 and 1 are for logic tile 1
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* GIC 2 and 3 are for logic tile 2
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*/
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#define IRQ_TIMER01 4
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#define IRQ_TIMER23 5
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#define IRQ_RTC 10
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#define IRQ_UART0 12
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#define IRQ_UART1 13
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#define IRQ_UART2 14
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#define IRQ_UART3 15
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/*
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* TODO: Seems like GIC0 and GIC1 are cascaded for logic tile1
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* and GIC2 and GIC3 are cascaded for logic tile 2.
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* Interrupt Distribution:
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* 0-31: Used as SI provided by distributed interrupt controller
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* 32-63: Externel Peripheral Interrupts
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@@ -28,4 +22,57 @@
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* 72-79: Interrupts from tile site 2
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* 80-95: PCI and reserved Interrupts
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*/
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#define EB_GIC_IRQ_OFFSET 32
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#define EB_IRQ_WATCHDOG (EB_GIC_IRQ_OFFSET + 0)
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#define EB_IRQ_SOFTINT (EB_GIC_IRQ_OFFSET + 1)
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#define EB_IRQ_COMRX (EB_GIC_IRQ_OFFSET + 2)
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#define EB_IRQ_COMTX (EB_GIC_IRQ_OFFSET + 3)
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#define EB_IRQ_TIMER01 (EB_GIC_IRQ_OFFSET + 4)
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#define EB_IRQ_TIMER23 (EB_GIC_IRQ_OFFSET + 5)
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#define EB_IRQ_GPIO0 (EB_GIC_IRQ_OFFSET + 6)
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#define EB_IRQ_GPIO1 (EB_GIC_IRQ_OFFSET + 7)
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#define EB_IRQ_GPIO2 (EB_GIC_IRQ_OFFSET + 8)
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#define EB_IRQ_RTC (EB_GIC_IRQ_OFFSET + 10)
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#define EB_IRQ_UART0 (EB_GIC_IRQ_OFFSET + 12)
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#define EB_IRQ_UART1 (EB_GIC_IRQ_OFFSET + 13)
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#define EB_IRQ_UART2 (EB_GIC_IRQ_OFFSET + 14)
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#define EB_IRQ_UART3 (EB_GIC_IRQ_OFFSET + 15)
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#define EB_IRQ_SCI (EB_GIC_IRQ_OFFSET + 16) /* Smart Card Interface */
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#define EB_IRQ_MCI0 (EB_GIC_IRQ_OFFSET + 17)
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#define EB_IRQ_MCI1 (EB_GIC_IRQ_OFFSET + 18)
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#define EB_IRQ_AACI (EB_GIC_IRQ_OFFSET + 19) /* Advanced Audio codec */
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#define EB_IRQ_KMI0 (EB_GIC_IRQ_OFFSET + 20) /* Keyboard */
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#define EB_IRQ_KMI1 (EB_GIC_IRQ_OFFSET + 21) /* Mouse */
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#define EB_IRQ_LCD (EB_GIC_IRQ_OFFSET + 20) /* Character LCD */
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#define EB_IRQ_DMAC (EB_GIC_IRQ_OFFSET + 20) /* DMA Controller */
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/* Interrupt Sources to ARM 11 MPCore or EB+A9 MPCore GIC */
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#define MPCORE_GIC_IRQ_AACI (EB_GIC_IRQ_OFFSET + 0)
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#define MPCORE_GIC_IRQ_TIMER01 (EB_GIC_IRQ_OFFSET + 1)
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#define MPCORE_GIC_IRQ_TIMER23 (EB_GIC_IRQ_OFFSET + 2)
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#define MPCORE_GIC_IRQ_USB (EB_GIC_IRQ_OFFSET + 3)
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#define MPCORE_GIC_IRQ_UART0 (EB_GIC_IRQ_OFFSET + 4)
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#define MPCORE_GIC_IRQ_UART1 (EB_GIC_IRQ_OFFSET + 5)
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#define MPCORE_GIC_IRQ_RTC (EB_GIC_IRQ_OFFSET + 6)
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#define MPCORE_GIC_IRQ_KMI0 (EB_GIC_IRQ_OFFSET + 7)
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#define MPCORE_GIC_IRQ_KMI1 (EB_GIC_IRQ_OFFSET + 8)
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#define MPCORE_GIC_IRQ_ETH (EB_GIC_IRQ_OFFSET + 9)
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/* Interrupt from GIC1 on Base board */
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#define MPCORE_GIC_IRQ_EB_GIC1 (EB_GIC_IRQ_OFFSET + 10)
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#define MPCORE_GIC_IRQ_EB_GIC2 (EB_GIC_IRQ_OFFSET + 11)
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#define MPCORE_GIC_IRQ_EB_GIC3 (EB_GIC_IRQ_OFFSET + 12)
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#define MPCORE_GIC_IRQ_EB_GIC4 (EB_GIC_IRQ_OFFSET + 13)
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#if defined (CONFIG_CPU_ARM11MPCORE) || defined (CONFIG_CPU_CORTEXA9)
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#define IRQ_TIMER0 MPCORE_GIC_IRQ_TIMER01
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#define IRQ_TIMER1 MPCORE_GIC_IRQ_TIMER23
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#else
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#define IRQ_TIMER0 EB_IRQ_TIMER01
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#define IRQ_TIMER1 EB_IRQ_TIMER23
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#endif
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#endif /* __PLATFORM_IRQ_H__ */
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@@ -1,71 +1,61 @@
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/*
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* Describes physical memory layout of EB platform.
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*
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* Copyright (C) 2007 Bahadir Balban
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* This only include physical and memory offsets that
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* are not included in realview/offsets.h
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*
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* Copyright (C) 2009 B Labs Ltd.
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* Author: Prem Mallappa <prem.mallappa@b-labs.co.uk>
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*/
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#ifndef __PLATFORM_EB_OFFSETS_H__
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#define __PLATFORM_EB_OFFSETS_H__
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/* Physical memory base */
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#define PHYS_MEM_START 0x00000000 /* inclusive */
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#define PHYS_MEM_END 0x10000000 /* 256 MB, exclusive */
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/*
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* These bases taken from where kernel is `physically' linked at,
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* also used to calculate virtual-to-physical translation offset.
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* See the linker script for their sources. PHYS_ADDR_BASE can't
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* use a linker variable because it's referred from assembler.
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*/
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#define PHYS_ADDR_BASE 0x100000
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/* Device memory base */
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#define EB_DEV_PHYS 0x10000000
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#include <l4/platform/realview/offsets.h>
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/* Device offsets in physical memory */
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#define EB_SYSTEM_REGISTERS 0x10000000 /* System registers */
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#define EB_SYSCTRL_BASE 0x10001000 /* System controller */
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#define EB_UART0_BASE 0x10009000 /* UART 0 */
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#define EB_UART1_BASE 0x1000A000 /* UART 1 */
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#define EB_UART2_BASE 0x1000B000 /* UART 2 */
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#define EB_UART3_BASE 0x1000C000 /* UART 3 */
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#define EB_WATCHDOG0_BASE 0x10010000 /* WATCHDOG */
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#define EB_TIMER01_BASE 0x10011000 /* TIMER 0-1 */
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#define EB_TIMER23_BASE 0x10012000 /* TIMER 2-3 */
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#define EB_RTC_BASE 0x10017000 /* RTC interface */
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#define EB_GIC0_BASE 0x10040000 /* GIC 0 */
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#define EB_GIC1_BASE 0x10050000 /* GIC 1 */
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#define EB_GIC2_BASE 0x10060000 /* GIC 2 */
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#define EB_GIC3_BASE 0x10070000 /* GIC 3 */
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#define PLATFORM_GIC1_BASE 0x10040000 /* GIC 1 */
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#define PLATFORM_GIC2_BASE 0x10050000 /* GIC 2 */
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#define PLATFORM_GIC3_BASE 0x10060000 /* GIC 3 */
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#define PLATFORM_GIC4_BASE 0x10070000 /* GIC 4 */
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/*
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* Uart virtual address until a file-based console access
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* is available for userspace
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*/
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#define USERSPACE_UART_BASE 0x500000
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#define MPCORE_PRIVATE_VBASE (IO_AREA0_VADDR + (13 * DEVICE_PAGE))
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/*
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* Device offsets in virtual memory. They offset to some virtual
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* device base address. Each page on this virtual base is consecutively
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* allocated to devices. Nice and smooth.
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*/
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#define EB_SYSREGS_VOFFSET 0x00000000
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#define EB_SYSCTRL_VOFFSET 0x00001000
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#define EB_UART0_VOFFSET 0x00002000
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#define EB_TIMER01_VOFFSET 0x00003000
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#define EB_GIC0_VOFFSET 0x00004000
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#define EB_GIC1_VOFFSET 0x00005000
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#define EB_GIC2_VOFFSET 0x00006000
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#define EB_GIC3_VOFFSET 0x00007000
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#if defined (CONFIG_CPU_CORTEXA9)
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#define MPCORE_PRIVATE_BASE 0x1F000000
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#endif /* End CORTEXA9 */
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#define EB_SYSREGS_VBASE (IO_AREA0_VADDR + EB_SYSREGS_VOFFSET)
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#define EB_SYSCTRL_VBASE (IO_AREA0_VADDR + EB_SYSCTRL_VOFFSET)
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#define EB_UART0_VBASE (IO_AREA0_VADDR + EB_UART0_VOFFSET)
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#define EB_TIMER01_VBASE (IO_AREA0_VADDR + EB_TIMER01_VOFFSET)
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#define EB_GIC0_VBASE (IO_AREA0_VADDR + EB_GIC0_VOFFSET)
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#define EB_GIC1_VBASE (IO_AREA0_VADDR + EB_GIC1_VOFFSET)
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#define EB_GIC2_VBASE (IO_AREA0_VADDR + EB_GIC2_VOFFSET)
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#define EB_GIC3_VBASE (IO_AREA0_VADDR + EB_GIC3_VOFFSET)
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#if defined (CONFIG_CPU_ARM11MPCORE)
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#if defined REV_C || defined REV_D
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#define MPCORE_PRIVATE_BASE 0x1F000000
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#else /* REV_B and QEMU */
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#define MPCORE_PRIVATE_BASE 0x10100000
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#endif /* End REV_B and QEMU */
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#endif /* End ARM11MPCORE */
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#if defined (CONFIG_CPU_CORTEXA9) || defined (CONFIG_CPU_ARM11MPCORE)
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/* MPCore private memory region */
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#define SCU_BASE MPCORE_PRIVATE_BASE
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#define SCU_VBASE MPCORE_PRIVATE_VBASE
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#define GIC0_CPU_VBASE (MPCORE_PRIVATE_VBASE + 0x100)
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#define GIC0_DIST_VBASE (MPCORE_PRIVATE_VBASE + 0x1000)
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#endif /* End CORTEXA9 || ARM11MPCORE */
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#define GIC1_CPU_VBASE (PLATFORM_GIC1_VBASE + 0x0)
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#define GIC2_CPU_VBASE (PLATFORM_GIC2_VBASE + 0x0)
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#define GIC3_CPU_VBASE (PLATFORM_GIC3_VBASE + 0x0)
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#define GIC4_CPU_VBASE (PLATFORM_GIC4_VBASE + 0x0)
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#define GIC1_DIST_VBASE (PLATFORM_GIC1_VBASE + 0x1000)
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#define GIC2_DIST_VBASE (PLATFORM_GIC2_VBASE + 0x1000)
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#define GIC3_DIST_VBASE (PLATFORM_GIC3_VBASE + 0x1000)
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#define GIC4_DIST_VBASE (PLATFORM_GIC4_VBASE + 0x1000)
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#if defined (CONFIG_CPU_ARM11MPCORE) || defined (CONFIG_CPU_CORTEXA9)
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#define PLATFORM_IRQCTRL0_VIRTUAL EB_GIC0_VBASE
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#endif
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#define PLATFORM_IRQCTRL1_VIRTUAL EB_GIC1_VBASE
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#endif /* __PLATFORM_EB_OFFSETS_H__ */
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@@ -1,28 +1,18 @@
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#ifndef __EB_PLATFORM_H__
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#define __EB_PLATFORM_H__
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/*
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* Platform specific ties between drivers and generic APIs used by the kernel.
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* E.g. system timer and console.
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*
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* Copyright (C) Bahadir Balban 2007
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* Copyright (C) 2009 B Labs Ltd.
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*/
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#ifndef __EB_PLATFORM_H__
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#define __EB_PLATFORM_H__
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#include INC_PLAT(offsets.h)
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#include INC_GLUE(memlayout.h)
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#include INC_PLAT(sysctrl.h)
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#include <l4/drivers/irq/gic/gic.h>
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#include <l4/platform/realview/platform.h>
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#define PLATFORM_CONSOLE0_BASE EB_UART0_VBASE
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#define PLATFORM_TIMER0_BASE EB_TIMER01_VBASE
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#define PLATFORM_SP810_BASE EB_SYSCTRL_VBASE
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void cpu_extra_init(void);
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void init_platform_irq_controller();
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void init_platform_devices();
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/* Total number of timers present in this platform */
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#define TOTAL_TIMERS 4
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#define PLATFORM_TIMER0 0
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#define PLATFORM_TIMER1 1
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#define PLATFORM_TIMER2 2
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#define PLATFORM_TIMER3 3
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void platform_irq_enable(int irq);
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void platform_irq_disable(int irq);
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void timer_start(void);
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#endif /* __EB_PLATFORM_H__ */
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95
include/l4/platform/eb/sysctrl.h
Normal file
95
include/l4/platform/eb/sysctrl.h
Normal file
@@ -0,0 +1,95 @@
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#ifndef __EB_SYSCTRL_H__
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#define __EB_SYSCTRL_H__
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/* TODO: Better to stick this file in a ARM specific folder as most realview boards
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* tend to have this component
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*/
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#define SYS_ID 0x0000
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#define SYS_SW 0x0004
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#define SYS_LED 0x0008
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#define SYS_OSC0 0x000C
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#define SYS_OSC1 0x0010
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#define SYS_OSC2 0x0014
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#define SYS_OSC3 0x0018
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#define SYS_OSC4 0x001C
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#define SYS_LOCK 0x0020
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#define SYS_100HZ 0x0024
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#define SYS_CFGDATA0 0x0028
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#define SYS_CFGDATA1 0x002C
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#define SYS_FLAGS 0x0030
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#define SYS_FLAGS_SET 0x0030
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#define SYS_FLAGS_CLR 0x0034
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#define SYS_NVFLAGS 0x0038
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#define SYS_NVFLAGS_SET 0x0038
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#define SYS_NVFLAGS_CLR 0x003C
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#define SYS_PCICTL 0x0044
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#define SYS_MCI 0x0048
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#define SYS_FLASH 0x004C
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#define SYS_CLCD 0x0050
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#define SYS_CLCDSER 0x0054
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#define SYS_BOOTCS 0x0058
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#define SYS_24MHZ 0x005C
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#define SYS_MISC 0x0060
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#define SYS_DMAPSR0 0x0064
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#define SYS_DMAPSR1 0x0068
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#define SYS_DMAPSR2 0x006C
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#define SYS_IOSEL 0x0070
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#define SYS_PLDCTL1 0x0074
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#define SYS_PLDCTL2 0x0078
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#define SYS_BUSID 0x0080
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#define SYS_PROCID1 0x0084
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#define SYS_PROCID0 0x0088
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#define SYS_OSCRESET0 0x008C
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#define SYS_OSCRESET1 0x0090
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#define SYS_OSCRESET2 0x0094
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#define SYS_OSCRESET3 0x0098
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#define SYS_OSCRESET4 0x009C
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/* System Controller Lock/Unlock */
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#define SYSCTRL_LOCK 0xFF
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#define SYSCTRL_UNLOCK 0xA05F
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#define ID_MASK_REV 0xF0000000
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#define ID_MASK_HBI 0x0FFF0000
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#define ID_MASK_BUILD 0x0000F000
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#define ID_MASK_ARCH 0x00000F00
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#define ID_MASK_FPGA 0x000000FF
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#define SW_MASK_BOOTSEL 0x0000FF00
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#define SW_MASK_GP 0x000000FF
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#define LED_MASK_LED 0x000000FF
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#define FLASH_WRITE_EN 0x1
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#define FLASH_WRITE_DIS 0x0
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#define CLCD_QVGA (0 << 8) /* 320x240 */
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#define CLDE_VGA (1 << 8) /* 640x480 */
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#define CLCD_SMALL (2 << 8) /* 220x176 */
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#define CLCD_SSP_CS (1 << 7) /* SSP Chip Select */
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#define CLCD_TS_EN (1 << 6) /* Touch Screen Enable */
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/* Different Voltages */
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#define CLCD_NEG_EN (1 << 5)
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#define CLCD_3V5V_EN (1 << 4)
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#define CLCD_POS_EN (1 << 3)
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#define CLCD_IO_ON (1 << 2)
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/* Normal without DCC, no FIQ, recommended for SMP */
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#define PLD_CTRL1_INTMOD_WITHOUT_DCC (1 << 22)
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/* Not Recommended */
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#define PLD_CTRL1_INTMOD_WITH_DCC (2 << 22)
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/* For single cpu such as 1136 */
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#define PLD_CTRL1_INTMOD_LEGACY (4 << 22)
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#endif /* __EB_SYSCTRL_H__ */
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@@ -1,20 +1,6 @@
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/*
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* Platform specific ties to generic uart functions that putc expects.
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*
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* Copyright (C) 2007 Bahadir Balban
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*
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*/
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#ifndef __EB_UART_H__
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#define __EB_UART_H__
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#ifndef __PLATFORM_EB_UART_H__
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#define __PLATFORM_EB_UART_H__
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#include <l4/platform/realview/uart.h>
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#include INC_PLAT(offsets.h)
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#include INC_GLUE(memlayout.h)
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#define PLATFORM_CONSOLE_BASE EB_UART0_VBASE
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#include <l4/drivers/uart/pl011/pl011_uart.h>
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void uart_init(void);
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void uart_putc(char c);
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#endif /* __PLATFORM_EB_UART_H__ */
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#endif /* __EB_UART_H__ */
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