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Kernel updates since December 2009

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This commit is contained in:
Bahadir Balban
2010-03-25 01:12:40 +02:00
parent 16818191b3
commit 74b5963fcb
487 changed files with 22477 additions and 3857 deletions
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8
include/l4/platform/pb11mpcore/irq.h
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@@ -6,10 +6,10 @@
#define IRQS_MAX 96
/* IRQ indices. */
#define IRQ_TIMER01 36
#define IRQ_TIMER23 37
#define IRQ_TIMER45 73
#define IRQ_TIMER67 74
#define IRQ_TIMER0 36
#define IRQ_TIMER1 37
#define IRQ_TIMER2 73
#define IRQ_TIMER3 74
#define IRQ_RTC 42
#define IRQ_UART0 44
#define IRQ_UART1 45

70
include/l4/platform/pb11mpcore/offsets.h
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@@ -1,77 +1,35 @@
/*
* Describes physical memory layout of PB11MPCORE platform.
*
* This only include physical and memory offsets that
* are not included in realview/offsets.h
*
* Copyright (C) 2007 Bahadir Balban
*/
#ifndef __PLATFORM_PB11MPCORE_OFFSETS_H__
#define __PLATFORM_PB11MPCORE_OFFSETS_H__
/* Physical memory base */
#define PHYS_MEM_START 0x00000000 /* inclusive */
#define PHYS_MEM_END 0x10000000 /* 256 MB, exclusive */
/*
* These bases taken from where kernel is `physically' linked at,
* also used to calculate virtual-to-physical translation offset.
* See the linker script for their sources. PHYS_ADDR_BASE can't
* use a linker variable because it's referred from assembler.
*/
#define PHYS_ADDR_BASE 0x100000
/* Device memory base */
#define PB11MPCORE_DEV_PHYS 0x10000000
#include <l4/platform/realview/offsets.h>
/* Device offsets in physical memory */
#define PB11MPCORE_SYSTEM_REGISTERS 0x10000000 /* System registers */
#define PB11MPCORE_SYSCTRL0_BASE 0x10001000 /* System controller 0 */
#define PB11MPCORE_UART0_BASE 0x10009000 /* UART 0 */
#define PB11MPCORE_UART1_BASE 0x1000A000 /* UART 1 */
#define PB11MPCORE_UART2_BASE 0x1000B000 /* UART 2 */
#define PB11MPCORE_UART3_BASE 0x1000C000 /* UART 3 */
#define PB11MPCORE_WATCHDOG0_BASE 0x1000F000 /* WATCHDOG 0 */
#define PB11MPCORE_WATCHDOG1_BASE 0x10010000 /* WATCHDOG 1 */
#define PB11MPCORE_TIMER01_BASE 0x10011000 /* TIMER 0-1 */
#define PB11MPCORE_TIMER23_BASE 0x10012000 /* TIMER 2-3 */
#define PB11MPCORE_RTC_BASE 0x10017000 /* RTC interface */
#define PB11MPCORE_TIMER45_BASE 0x10018000 /* TIMER 4-5 */
#define PB11MPCORE_TIMER67_BASE 0x10019000 /* TIMER 6-7 */
#define PB11MPCORE_SYSCTRL1_BASE 0x1001A000 /* System controller 1 */
#define PB11MPCORE_GIC0_BASE 0x1E000000 /* GIC 0 */
#define PB11MPCORE_GIC1_BASE 0x1E010000 /* GIC 1 */
#define PB11MPCORE_GIC2_BASE 0x1E020000 /* GIC 2 */
#define PB11MPCORE_GIC3_BASE 0x1E030000 /* GIC 3 */
/*
* Uart virtual address until a file-based console access
* is available for userspace
*/
#define USERSPACE_UART_BASE 0x500000
#define PLATFORM_TIMER2_BASE 0x10018000 /* TIMER 4-5 */
#define PLATFORM_TIMER3_BASE 0x10019000 /* TIMER 6-7 */
#define PLATFORM_SYSCTRL1_BASE 0x1001A000 /* System controller 1 */
#define PLATFORM_GIC0_BASE 0x1E000000 /* GIC 0 */
#define PLATFORM_GIC1_BASE 0x1E010000 /* GIC 1 */
#define PLATFORM_GIC2_BASE 0x1E020000 /* GIC 2 */
#define PLATFORM_GIC3_BASE 0x1E030000 /* GIC 3 */
/*
* Device offsets in virtual memory. They offset to some virtual
* device base address. Each page on this virtual base is consecutively
* allocated to devices. Nice and smooth.
*/
#define PB11MPCORE_SYSREGS_VOFFSET 0x00000000
#define PB11MPCORE_SYSCTRL0_VOFFSET 0x00001000
#define PB11MPCORE_SYSCTRL1_VOFFSET 0x00002000
#define PB11MPCORE_UART0_VOFFSET 0x00003000
#define PB11MPCORE_TIMER01_VOFFSET 0x00004000
#define PB11MPCORE_GIC0_VOFFSET 0x00005000
#define PB11MPCORE_GIC1_VOFFSET 0x00006000
#define PB11MPCORE_GIC2_VOFFSET 0x00007000
#define PB11MPCORE_GIC3_VOFFSET 0x00008000
#define PB11MPCORE_SYSREGS_VBASE (IO_AREA0_VADDR + PB11MPCORE_SYSREGS_VOFFSET)
#define PB11MPCORE_SYSCTRL0_VBASE (IO_AREA0_VADDR + PB11MPCORE_SYSCTRL0_VOFFSET)
#define PB11MPCORE_SYSCTRL1_VBASE (IO_AREA0_VADDR + PB11MPCORE_SYSCTRL1_VOFFSET)
#define PB11MPCORE_UART0_VBASE (IO_AREA0_VADDR + PB11MPCORE_UART0_VOFFSET)
#define PB11MPCORE_TIMER01_VBASE (IO_AREA0_VADDR + PB11MPCORE_TIMER01_VOFFSET)
#define PB11MPCORE_GIC0_VBASE (IO_AREA0_VADDR + PB11MPCORE_GIC0_VOFFSET)
#define PB11MPCORE_GIC1_VBASE (IO_AREA0_VADDR + PB11MPCORE_GIC1_VOFFSET)
#define PB11MPCORE_GIC2_VBASE (IO_AREA0_VADDR + PB11MPCORE_GIC2_VOFFSET)
#define PB11MPCORE_GIC3_VBASE (IO_AREA0_VADDR + PB11MPCORE_GIC3_VOFFSET)
/* Add userspace devices here as they become necessary for irqs */
/* Add size of various user space devices, to be used in capability generation */
#endif /* __PLATFORM_PB11MPCORE_OFFSETS_H__ */

30
include/l4/platform/pb11mpcore/platform.h
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@@ -1,5 +1,5 @@
#ifndef __PB11MPCORE_PLATFORM_H__
#define __PB11MPCORE_PLATFORM_H__
#ifndef __PBA9_PLATFORM_H__
#define __PBA9_PLATFORM_H__
/*
* Platform specific ties between drivers and generic APIs used by the kernel.
* E.g. system timer and console.
@@ -7,28 +7,6 @@
* Copyright (C) Bahadir Balban 2007
*/
#include INC_PLAT(offsets.h)
#include INC_GLUE(memlayout.h)
#include <l4/platform/realview/platform.h>
#define PLATFORM_CONSOLE0_BASE PB11MPCORE_UART0_VBASE
#define PLATFORM_TIMER0_BASE PB11MPCORE_TIMER01_VBASE
/* Need to add syscntrl1 here */
#define PLATFORM_SP810_BASE PB11MPCORE_SYSCTRL0_VBASE
/* Total number of timers present in this platform */
#define TOTAL_TIMERS 8
#define PLATFORM_TIMER0 0
#define PLATFORM_TIMER1 1
#define PLATFORM_TIMER2 2
#define PLATFORM_TIMER3 3
#define PLATFORM_TIMER4 4
#define PLATFORM_TIMER5 5
#define PLATFORM_TIMER6 6
#define PLATFORM_TIMER7 7
void platform_irq_enable(int irq);
void platform_irq_disable(int irq);
void timer_start(void);
#endif /* __PB11MPCORE_PLATFORM_H__ */
#endif /* __PBA9_PLATFORM_H__ */

22
include/l4/platform/pb11mpcore/uart.h
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@@ -1,20 +1,6 @@
/*
* Platform specific ties to generic uart functions that putc expects.
*
* Copyright (C) 2007 Bahadir Balban
*
*/
#ifndef __PB11MPCORE_UART_H__
#define __PB11MPCORE_UART_H__
#ifndef __PLATFORM_PB11MPCORE_UART_H__
#define __PLATFORM_PB11MPCORE_UART_H__
#include <l4/platform/realview/uart.h>
#include INC_PLAT(offsets.h)
#include INC_GLUE(memlayout.h)
#define PLATFORM_CONSOLE_BASE PB11MPCORE_UART0_VBASE
#include <l4/drivers/uart/pl011/pl011_uart.h>
void uart_init(void);
void uart_putc(char c);
#endif /* __PLATFORM_PB11MPCORE_UART_H__ */
#endif /* __PB11MPCORE_UART_H__ */