mirror of
https://github.com/drasko/codezero.git
synced 2026-03-10 14:23:33 +01:00
Kernel updates since December 2009
This commit is contained in:
Bahadir Balban
@@ -22,12 +22,13 @@
|
||||
#define IRQS_MAX VIC_IRQS_MAX + SIC_IRQS_MAX
|
||||
|
||||
/* Vectored Interrupt Controller local IRQ numbers */
|
||||
#define VIC_IRQ_TIMER01 4
|
||||
#define VIC_IRQ_TIMER23 5
|
||||
#define VIC_IRQ_TIMER0 4
|
||||
#define VIC_IRQ_TIMER1 5
|
||||
#define VIC_IRQ_RTC 10
|
||||
#define VIC_IRQ_UART0 12
|
||||
#define VIC_IRQ_UART1 13
|
||||
#define VIC_IRQ_UART2 14
|
||||
#define VIC_IRQ_CLCD0 16
|
||||
#define VIC_IRQ_SIC 31
|
||||
|
||||
/* Secondary Interrupt controller local IRQ numbers */
|
||||
@@ -35,12 +36,13 @@
|
||||
#define SIC_IRQ_UART3 6
|
||||
|
||||
/* Global irq numbers, note these should reflect global device names */
|
||||
#define IRQ_TIMER0 (VIC_IRQ_TIMER01 + VIC_CHIP_OFFSET)
|
||||
#define IRQ_TIMER1 (VIC_IRQ_TIMER23 + VIC_CHIP_OFFSET)
|
||||
#define IRQ_TIMER0 (VIC_IRQ_TIMER0 + VIC_CHIP_OFFSET)
|
||||
#define IRQ_TIMER1 (VIC_IRQ_TIMER1 + VIC_CHIP_OFFSET)
|
||||
#define IRQ_RTC (VIC_IRQ_RTC + VIC_CHIP_OFFSET)
|
||||
#define IRQ_UART0 (VIC_IRQ_UART0 + VIC_CHIP_OFFSET)
|
||||
#define IRQ_UART1 (VIC_IRQ_UART1 + VIC_CHIP_OFFSET)
|
||||
#define IRQ_UART2 (VIC_IRQ_UART2 + VIC_CHIP_OFFSET)
|
||||
#define IRQ_CLCD0 (VIC_IRQ_CLCD0 + VIC_CHIP_OFFSET)
|
||||
#define IRQ_SIC (VIC_IRQ_SIC + VIC_CHIP_OFFSET)
|
||||
|
||||
#define IRQ_SICSWI (SIC_IRQ_SWI + SIC_CHIP_OFFSET)
|
||||
|
||||
@@ -8,51 +8,53 @@
|
||||
#define __PLATFORM_PB926_OFFSETS_H__
|
||||
|
||||
/* Physical memory base */
|
||||
#define PHYS_MEM_START 0x00000000 /* inclusive */
|
||||
#define PHYS_MEM_END 0x08000000 /* 128 MB, exclusive */
|
||||
|
||||
/* Device offsets in physical memory */
|
||||
#define PB926_SYSTEM_REGISTERS 0x10000000 /* System registers */
|
||||
#define PB926_SYSCTRL_BASE 0x101E0000 /* System controller */
|
||||
#define PB926_WATCHDOG_BASE 0x101E1000 /* Watchdog */
|
||||
#define PB926_TIMER01_BASE 0x101E2000 /* Timers 0 and 1 */
|
||||
#define PB926_TIMER23_BASE 0x101E3000 /* Timers 2 and 3 */
|
||||
#define PB926_RTC_BASE 0x101E8000 /* Real Time Clock */
|
||||
#define PB926_VIC_BASE 0x10140000 /* Primary Vectored IC */
|
||||
#define PB926_SIC_BASE 0x10003000 /* Secondary IC */
|
||||
#define PB926_UART0_BASE 0x101F1000 /* Console port (UART0) */
|
||||
#define PB926_UART1_BASE 0x101F2000 /* Console port (UART1) */
|
||||
#define PB926_UART2_BASE 0x101F3000 /* Console port (UART2) */
|
||||
#define PB926_UART3_BASE 0x10009000 /* Console port (UART3) */
|
||||
#define PB926_CLCD_BASE 0x10120000 /* Color LCD */
|
||||
#define PLATFORM_PHYS_MEM_START 0x00000000 /* inclusive */
|
||||
#define PLATFORM_PHYS_MEM_END 0x08000000 /* 128 MB, exclusive */
|
||||
|
||||
/*
|
||||
* Uart virtual address until a file-based console access
|
||||
* is available for userspace
|
||||
* Device offsets in physical memory
|
||||
* Naming of devices done starting with 0 subscript,
|
||||
* as we use these names for device capability
|
||||
*/
|
||||
#define USERSPACE_CONSOLE_VIRTUAL 0x500000
|
||||
#define PLATFORM_SYSTEM_REGISTERS 0x10000000 /* System registers */
|
||||
#define PLATFORM_SYSCTRL_BASE 0x101E0000 /* System controller */
|
||||
#define PLATFORM_WATCHDOG_BASE 0x101E1000 /* Watchdog */
|
||||
#define PLATFORM_TIMER0_BASE 0x101E2000 /* Timers 0 and 1 */
|
||||
#define PLATFORM_TIMER1_BASE 0x101E3000 /* Timers 2 and 3 */
|
||||
#define PLATFORM_RTC_BASE 0x101E8000 /* Real Time Clock */
|
||||
#define PLATFORM_VIC_BASE 0x10140000 /* Primary Vectored IC */
|
||||
#define PLATFORM_SIC_BASE 0x10003000 /* Secondary IC */
|
||||
#define PLATFORM_UART0_BASE 0x101F1000 /* Console port (UART0) */
|
||||
#define PLATFORM_UART1_BASE 0x101F2000 /* Console port (UART1) */
|
||||
#define PLATFORM_UART2_BASE 0x101F3000 /* Console port (UART2) */
|
||||
#define PLATFORM_UART3_BASE 0x10009000 /* Console port (UART3) */
|
||||
#define PLATFORM_CLCD0_BASE 0x10120000 /* Color LCD */
|
||||
|
||||
/*
|
||||
* Device offsets in virtual memory. They offset to some virtual
|
||||
* device base address. Each page on this virtual base is consecutively
|
||||
* allocated to devices. Nice and smooth.
|
||||
*/
|
||||
#define PB926_TIMER01_VOFFSET 0x00000000
|
||||
#define PB926_UART0_VOFFSET 0x00001000
|
||||
#define PB926_VIC_VOFFSET 0x00002000
|
||||
#define PB926_SIC_VOFFSET 0x00003000
|
||||
#define PB926_SYSREGS_VOFFSET 0x00004000
|
||||
#define PB926_SYSCTRL_VOFFSET 0x00005000
|
||||
#define PB926_TIMER23_VOFFSET 0x00006000
|
||||
#define DEVICE_PAGE 0x1000
|
||||
|
||||
#define PLATFORM_CONSOLE_VIRTUAL (IO_AREA0_VADDR + PB926_UART0_VOFFSET)
|
||||
#define PLATFORM_TIMER0_VIRTUAL (IO_AREA0_VADDR + PB926_TIMER01_VOFFSET)
|
||||
#define PLATFORM_SYSCTRL_VIRTUAL (IO_AREA0_VADDR + PB926_SYSCTRL_VOFFSET)
|
||||
#define PLATFORM_IRQCTRL0_VIRTUAL (IO_AREA0_VADDR + PB926_VIC_VOFFSET)
|
||||
#define PLATFORM_IRQCTRL1_VIRTUAL (IO_AREA0_VADDR + PB926_SIC_VOFFSET)
|
||||
#define PLATFORM_TIMER0_VBASE (IO_AREA0_VADDR + (0 * DEVICE_PAGE))
|
||||
#define PLATFORM_CONSOLE_VBASE (IO_AREA0_VADDR + (1 * DEVICE_PAGE))
|
||||
#define PLATFORM_IRQCTRL0_VBASE (IO_AREA0_VADDR + (2 * DEVICE_PAGE))
|
||||
#define PLATFORM_IRQCTRL1_VBASE (IO_AREA0_VADDR + (3 * DEVICE_PAGE))
|
||||
#define PLATFORM_SYSCTRL_VBASE (IO_AREA0_VADDR + (4 * DEVICE_PAGE))
|
||||
|
||||
/* Add userspace devices here as they become necessary for irqs */
|
||||
#define PLATFORM_TIMER1_VIRTUAL (IO_AREA0_VADDR + PB926_TIMER23_VOFFSET)
|
||||
#define PLATFORM_TIMER1_VBASE (IO_AREA0_VADDR + (6 * DEVICE_PAGE))
|
||||
|
||||
/* The SP810 system controller offsets */
|
||||
#define SP810_BASE PLATFORM_SYSCTRL_VBASE
|
||||
#define SP810_SCCTRL (SP810_BASE + 0x0)
|
||||
|
||||
/* Add size of various user space devices, to be used in capability generation */
|
||||
#define PLATFORM_UART1_SIZE 0x1000
|
||||
#define PLATFORM_UART2_SIZE 0x1000
|
||||
#define PLATFORM_UART3_SIZE 0x1000
|
||||
#define PLATFORM_TIMER1_SIZE 0x1000
|
||||
|
||||
#endif /* __PLATFORM_PB926_OFFSETS_H__ */
|
||||
|
||||
|
||||
@@ -7,46 +7,6 @@
|
||||
* Copyright (C) Bahadir Balban 2007
|
||||
*/
|
||||
|
||||
#include INC_PLAT(offsets.h)
|
||||
#include INC_GLUE(memlayout.h)
|
||||
#include <l4/generic/capability.h>
|
||||
#include <l4/generic/cap-types.h>
|
||||
#include <l4/generic/resource.h>
|
||||
|
||||
/* Default console used by kernel */
|
||||
#define PLATFORM_CONSOLE_BASE PB926_UART0_BASE
|
||||
|
||||
/* SP804 timer has TIMER1 at TIMER0 + 0x20 address */
|
||||
#define PLATFORM_TIMER0_BASE PB926_TIMER01_BASE
|
||||
|
||||
/* Total number of timers present in this platform */
|
||||
#define TOTAL_TIMERS 4
|
||||
|
||||
#define PLATFORM_TIMER0 0
|
||||
#define PLATFORM_TIMER1 1
|
||||
#define PLATFORM_TIMER2 2
|
||||
#define PLATFORM_TIMER3 3
|
||||
|
||||
#define PB926_UART_SIZE 0x1000
|
||||
#define PB926_TIMER_SIZE 0x1000
|
||||
#define PB926_CLCD_SIZE 0x1000
|
||||
|
||||
#define PLATFORM_UART1_BASE PB926_UART1_BASE
|
||||
#define PLATFORM_UART2_BASE PB926_UART2_BASE
|
||||
#define PLATFORM_UART3_BASE PB926_UART3_BASE
|
||||
#define PLATFORM_UART1_SIZE PB926_UART_SIZE
|
||||
#define PLATFORM_UART2_SIZE PB926_UART_SIZE
|
||||
#define PLATFORM_UART3_SIZE PB926_UART_SIZE
|
||||
|
||||
#define PLATFORM_TIMER1_BASE PB926_TIMER23_BASE
|
||||
#define PLATFORM_TIMER1_SIZE PB926_TIMER_SIZE
|
||||
|
||||
#define PLATFORM_CLCD0_BASE PB926_CLCD_BASE
|
||||
#define PLATFORM_CLCD0_SIZE PB926_CLCD_SIZE
|
||||
|
||||
int platform_setup_device_caps(struct kernel_resources *kres);
|
||||
void platform_irq_enable(int irq);
|
||||
void platform_irq_disable(int irq);
|
||||
void timer_start(void);
|
||||
void platform_timer_start(void);
|
||||
|
||||
#endif /* __PB926_PLATFORM_H__ */
|
||||
|
||||
13
include/l4/platform/pb926/timer.h
Normal file
13
include/l4/platform/pb926/timer.h
Normal file
@@ -0,0 +1,13 @@
|
||||
/*
|
||||
* Platform encapsulation over timer driver.
|
||||
*
|
||||
* Copyright (C) 2007 Bahadir Balban
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __PLATFORM_PB926_TIMER_H__
|
||||
#define __PLATFORM_PB926_TIMER_H__
|
||||
|
||||
#include <l4/drivers/timer/sp804/timer.h>
|
||||
|
||||
#endif /* __PLATFORM_PB926_TIMER_H__ */
|
||||
@@ -8,12 +8,6 @@
|
||||
#ifndef __PLATFORM_PB926_UART_H__
|
||||
#define __PLATFORM_PB926_UART_H__
|
||||
|
||||
#include INC_PLAT(offsets.h)
|
||||
#include INC_GLUE(memlayout.h)
|
||||
|
||||
#include <l4/drivers/uart/pl011/pl011_uart.h>
|
||||
|
||||
void uart_init(void);
|
||||
void uart_putc(char c);
|
||||
#include <l4/drivers/uart/pl011/uart.h>
|
||||
|
||||
#endif /* __PLATFORM_PB926_UART_H__ */
|
||||
|
||||
Reference in New Issue
Block a user